Storage apparatus, control method, control apparatus, and chip

Abstract

Disclosed are a storage apparatus, a control method, a control apparatus, and a chip. The storage apparatus comprises: a first memory cell, comprising first and second transistors, wherein a gate terminal of the first transistor is connected to a first terminal of the second transistor, a second terminal of the first transistor is used for receiving an input voltage, the first memory cell outputs an output current of the first memory cell at a first terminal of the first transistor in response to the input of the input voltage, a gate terminal of the second transistor is used for receiving a turn-on signal, and a second terminal of the second transistor is used for receiving a write signal; and a write control circuit, used for controlling the first memory cell and configured to control, in response to the first memory cell being in a write state and the output current of the first memory cell satisfying a threshold condition, to stop applying the write signal to the second terminal of the second transistor or stop applying the turn-on signal to the second transistor, wherein the threshold condition is determined on the basis of a value to be written of the first memory cell.

Description

Storage device, control method, control device and chip Technical Field

[0001] This disclosure relates to data processing, and more particularly to a storage device, a control method, a control device, and a chip. Background Technology

[0002] In the traditional von Neumann computing architecture, memory and processor are physically separated and connected by a data bus. When performing related calculations, the vector and matrix data to be processed must first be read from memory, transferred to the processor for calculation, and then the calculation results are stored back in memory. This consumes a lot of data bus bandwidth and transmission power.

[0003] The methods described in this section are not necessarily methods that had been previously conceived or adopted. Unless otherwise specified, no method described in this section should be assumed to be prior art simply because it is included in this section. Similarly, unless otherwise specified, the issues mentioned in this section should not be considered to be accepted in any prior art. Summary of the Invention

[0004] According to a first aspect of this disclosure, a storage device is provided, comprising: a first memory cell including a first transistor and a second transistor, wherein the gate terminal of the first transistor is connected to a first terminal of the second transistor, wherein the second terminal of the first transistor is configured to receive an input voltage, the first memory cell outputs an output current of the first memory cell in response to the input voltage, the gate terminal of the second transistor is configured to receive an on signal, and the second terminal of the second transistor is configured to receive a write signal; and a write control circuit configured to control the first memory cell to stop applying a write signal to the second terminal of the second transistor in the first memory cell or to stop applying an on signal to the second transistor in the first memory cell in response to the first memory cell being in a write state and the output current of the first memory cell satisfying a threshold condition, wherein the threshold condition is determined based on the value to be written to the first memory cell.

[0005] According to a second aspect of this disclosure, a control method is provided, comprising: in response to a first memory cell being in a write state, applying a write signal corresponding to the first memory cell to a second terminal of a second transistor of the first memory cell, and applying an on signal to the gate terminal of the second transistor of the first memory cell; and in response to an output current of the first memory cell satisfying a threshold condition, controlling a write control circuit to control the application of a write signal to the second terminal of the second transistor in the first memory cell to stop or to stop applying an on signal to the second transistor in the first memory cell, wherein the threshold condition is determined based on the value to be written in the first memory cell.

[0006] According to a third aspect of this disclosure, a control device is provided, comprising: an interface circuit for signal connection to a storage device; and at least one processing circuit for executing any of the control methods of the second aspect.

[0007] According to a fourth aspect of this disclosure, a chip is provided, comprising any of the storage devices of the first aspect and / or any of the control devices of the third aspect. Attached Figure Description

[0008] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0009] Figure 1 shows a schematic diagram of a memory computing circuit according to an exemplary embodiment of the present disclosure;

[0010] Figures 2A-2D show schematic diagrams of memory cells according to exemplary embodiments of the present disclosure;

[0011] Figure 3 shows a circuit schematic diagram of controlled writing according to an exemplary embodiment of the present disclosure;

[0012] Figure 4 shows a schematic diagram of a write control circuit according to an exemplary embodiment of the present disclosure;

[0013] Figure 5 shows a circuit schematic diagram of controlled writing according to an exemplary embodiment of the present disclosure;

[0014] Figure 6 shows a schematic diagram of a write control circuit according to an exemplary embodiment of the present disclosure;

[0015] Figure 7 shows a flowchart of a method for controlling a memory circuit according to an exemplary embodiment of the present disclosure;

[0016] Figure 8 shows a schematic diagram of a chip according to an exemplary embodiment of the present disclosure;

[0017] Figure 9 shows a schematic diagram of a memory computing circuit according to an exemplary embodiment of the present disclosure;

[0018] Figure 10 shows a schematic diagram of a memory computing circuit according to an exemplary embodiment of the present disclosure;

[0019] Figure 11 shows a circuit schematic diagram of control writing according to an exemplary embodiment of the present disclosure;

[0020] Figure 12 shows a circuit schematic diagram of control writing according to an exemplary embodiment of the present disclosure;

[0021] Figure 13 shows a flowchart of a method for controlling a memory circuit according to an exemplary embodiment of the present disclosure;

[0022] Figure 14 shows a schematic diagram of a memory computing circuit according to an exemplary embodiment of the present disclosure;

[0023] Figure 15 shows a circuit schematic diagram of control writing according to an exemplary embodiment of the present disclosure;

[0024] Figure 16 shows a flowchart of a method for controlling a memory circuit according to an exemplary embodiment of the present disclosure;

[0025] Figure 17 shows a schematic diagram of a storage device according to an exemplary embodiment of the present disclosure;

[0026] Figure 18 shows a schematic diagram of another storage device according to an exemplary embodiment of the present disclosure;

[0027] Figure 19 shows a schematic diagram of yet another storage device according to an exemplary embodiment of the present disclosure;

[0028] Figure 20 shows a schematic diagram of a control method according to an exemplary embodiment of the present disclosure;

[0029] Figure 21 shows a schematic diagram of a control device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0030] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0031] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof.

[0032] As mentioned above, in the traditional von Neumann computing architecture, due to the separation of memory and processor, a large amount of data bus bandwidth and transmission power consumption are required to perform related calculations.

[0033] To address the aforementioned problems, this disclosure provides a memory computing circuit, comprising: a memory array including: a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each memory cell includes a first transistor and a second transistor, the gate terminal of the first transistor in each memory cell is connected to a first terminal of the second transistor, the output current of each memory cell is the output current of the first terminal of the first transistor in that memory cell, and each memory cell is configured to store a weight corresponding to that memory cell, wherein the first terminal of the first transistor in the memory cells in the same row is connected to a row output terminal corresponding to that row, and the second terminal of the first transistor in the memory cells in the same column is connected to a column input terminal corresponding to that column; and one or more write control circuits, wherein each write control circuit is used to control the storage One or more memory cells in a memory array, and each write control circuit is configured to: for any memory cell controlled by the write control circuit, in response to any memory cell being in a write state and the output current of any memory cell satisfying a threshold condition, control to stop applying a write signal to the second terminal of the second transistor in any memory cell, wherein the threshold condition is determined based on the value to be written to any memory cell, wherein the first terminal of the first transistor is the source terminal and the second terminal of the first transistor is the drain terminal, or, the first terminal of the first transistor is the drain terminal and the second terminal of the first transistor is the source terminal, and the first terminal of the second transistor is the source terminal and the second terminal of the second transistor is the drain terminal, or, the first terminal of the second transistor is the drain terminal and the second terminal of the second transistor is the source terminal.

[0034] To address the aforementioned problems, this disclosure provides a memory computing circuit, comprising: a memory array including: a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each memory cell includes a first transistor, a second transistor, and a write control switch; in each memory cell, the gate terminal of the first transistor is connected to a first terminal of the second transistor, the first terminal of the write control switch is connected to the gate terminal of the second transistor, and the second terminal of the write control switch is connected to a write word line corresponding to the memory cell; the output current of each memory cell is the output current of the first terminal of the first transistor in the memory cell; and each memory cell is configured to store a weight corresponding to the memory cell; wherein the first terminal of the first transistor in the memory cells in the same row is connected to the row output terminal corresponding to the row, and the second terminal of the first transistor in the memory cells in the same column is connected to the column output terminal corresponding to the column. The array includes column input terminals; and one or more write control circuits, wherein each write control circuit controls one or more memory cells in the memory array, and each write control circuit is configured to: for any memory cell controlled by the write control circuit, in response to any memory cell being in a write state and the output current of any memory cell satisfying a threshold condition, control the write control switch in any memory cell to be turned off, the threshold condition being determined based on the value to be written to any memory cell, wherein the first terminal of the first transistor is the source terminal and the second terminal of the first transistor is the drain terminal, or the first terminal of the first transistor is the drain terminal and the second terminal of the first transistor is the source terminal and the first terminal of the second transistor is the source terminal and the second terminal of the second transistor is the drain terminal, or the first terminal of the second transistor is the drain terminal and the second terminal of the second transistor is the source terminal.

[0035] According to the embodiments described herein, by storing computation-related weights in a memory array within the memory circuit, computations (e.g., multiplication) between the input and the stored weights can be performed, thereby reducing overhead from analog-to-digital conversion, digital-to-analog conversion, data transmission, etc., improving processing performance, simplifying circuit structure, increasing response speed, and reducing power consumption. Furthermore, by controlling the writing of a memory cell to stop when the memory cell is in a writing state via a write control circuit, the accuracy of the values ​​written into the memory cell is ensured.

[0036] To address the aforementioned problems, this disclosure provides a memory computing circuit, comprising: a memory array including: a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each memory cell includes a first transistor and a second transistor, the gate terminal of the first transistor in each memory cell is connected to a first terminal of the second transistor, the output current of each memory cell is the output current of the first terminal of the first transistor in that memory cell, and each memory cell is configured to store a weight corresponding to that memory cell, wherein the first terminal of the first transistor in the memory cells in the same row is connected to a row output terminal corresponding to that row, and the second terminal of the first transistor in the memory cells in the same column is connected to a column input terminal corresponding to that column; and one or more write control circuits, wherein each write control circuit is configured to control one or more memory cells in the memory array, and each write control circuit is configured to store a weight corresponding to that weight. The setting is as follows: For any memory cell controlled by the write control circuit, in response to any memory cell being in a write state and the output current of any memory cell satisfying a threshold condition, the control stops applying a write signal to the second terminal of the second transistor in any memory cell, wherein the threshold condition is determined based on the value to be written in any memory cell, wherein for each write control circuit, the gate terminals of the second transistors in different memory cells controlled by the write control circuit are connected to different write word lines, and wherein the first terminal of the first transistor is the source terminal and the second terminal of the first transistor is the drain terminal, or, the first terminal of the first transistor is the drain terminal and the second terminal of the first transistor is the source terminal and the first terminal of the second transistor is the source terminal and the second terminal of the second transistor is the drain terminal, or, the first terminal of the second transistor is the drain terminal and the second terminal of the second transistor is the source terminal.

[0037] According to the embodiments described herein, by storing computation-related weights in a memory array within the memory circuit, computations (e.g., multiplication) between the input and the stored weights can be performed, thereby reducing overhead from analog-to-digital conversion, digital-to-analog conversion, data transmission, etc., improving processing performance, simplifying circuit structure, increasing response speed, and reducing power consumption. Through the write control circuit, the writing of a memory cell is stopped based on its output current when the memory cell is in a write state, ensuring the accuracy of the values ​​written into the memory cell. Furthermore, since the gate terminals of the second write transistors (i.e., the transistors performing write control) in different memory cells controlled by each write control circuit are connected to different write word lines, independent control of the writing process of different memory cells controlled by each write control circuit can be achieved, ensuring that memory cells in a write state controlled by each write control circuit do not interfere with memory cells not in a write state.

[0038] In the embodiments described in this disclosure, a row in the memory array comprises a set of memory cells at the same vertical position in the horizontal direction of the memory array, and a column in the memory array comprises a set of memory cells at the same horizontal position in the vertical direction of the memory array; or, a column in the memory array comprises a set of memory cells at the same vertical position in the horizontal direction of the memory array, and a row in the memory array comprises a set of memory cells at the same horizontal position in the vertical direction of the memory array.

[0039] Figure 1 shows a schematic diagram of a memory computing circuit 100 according to an exemplary embodiment of the present disclosure.

[0040] According to some embodiments, as shown in FIG1, the in-memory computing circuit 100 includes a memory array 110 and one or more write control circuits 121-12N, wherein each write control circuit is used to control one or more memory cells in the memory array 110. It should be understood that although multiple write control circuits 121-12N are shown in FIG1, FIG1 is only schematic, and the in-memory computing circuit 100 may include only one write control circuit.

[0041] Figure 9 shows a schematic diagram of a memory computing circuit 900 according to an exemplary embodiment of the present disclosure.

[0042] According to some embodiments, as shown in FIG9, the in-memory computing circuit 900 includes a memory array 910 and one or more write control circuits 921-92N, wherein each write control circuit is used to control one or more memory cells in the memory array 910. It should be understood that although multiple write control circuits 921-92N are shown in FIG9, FIG9 is only schematic, and the in-memory computing circuit 900 may include only one write control circuit.

[0043] According to some embodiments, a memory cell includes a first transistor and a second transistor, the gate terminal of the first transistor is connected to a first terminal of the second transistor, and the memory cell is configured to store weights corresponding to the memory cell. According to some embodiments, the output current of each memory cell is the output current of the first terminal of the first transistor in the memory cell.

[0044] Figure 14 shows a schematic diagram of a memory computing circuit 1400 according to an exemplary embodiment of the present disclosure.

[0045] According to some embodiments, as shown in FIG14, the in-memory computing circuit 1400 includes a memory array 1410 and one or more write control circuits 1421-142N, wherein each write control circuit is used to control one or more memory cells in the memory array 1410. It should be understood that although multiple write control circuits 1421-142N are shown in FIG14, FIG14 is only schematic, and the in-memory computing circuit 1400 may include only one write control circuit.

[0046] According to some embodiments, each memory cell includes a first transistor, a second transistor, and a write control switch. In each memory cell, the gate terminal of the first transistor is connected to a first terminal of the second transistor, the first terminal of the write control switch is connected to the gate terminal of the second transistor, and the second terminal of the write control switch is connected to a write word line (WWL) corresponding to the memory cell. The memory cell is configured to store weights corresponding to that memory cell. According to some embodiments, the output current of each memory cell is the output current of the first terminal of the first transistor in that memory cell.

[0047] According to some embodiments, in memory arrays 110, 910, or 1410, the first terminal of a first transistor in a memory cell within the same row is connected to the row output terminal corresponding to that row, and the second terminal of a first transistor in a memory cell within the same column is connected to the column input terminal corresponding to that column; however, the embodiments are not limited thereto. According to some embodiments, in memory arrays 110, 910, or 1410, the first terminal of a first transistor in a memory cell within the same row is connected to the row input terminal corresponding to that row, and the second terminal of a first transistor in a memory cell within the same column is connected to the column output terminal corresponding to that column. According to some embodiments, in memory arrays 110, 910, or 1410, the first terminal of a first transistor in a memory cell within the same column is connected to the column input terminal corresponding to that column, and the second terminal of a first transistor in a memory cell within the same row is connected to the row output terminal corresponding to that row. According to some embodiments, in memory arrays 110, 910, or 1410, the first terminal of a first transistor in a memory cell within the same column is connected to the column output terminal corresponding to that column, and the second terminal of a first transistor in a memory cell within the same row is connected to the row input terminal corresponding to that row.

[0048] According to some embodiments, in each memory cell, a write operation is performed on the memory cell via a second transistor to change the weight stored in the memory cell.

[0049] Figures 2A-2D show schematic diagrams of memory cells according to exemplary embodiments of the present disclosure.

[0050] According to some embodiments, as shown in FIG2A or FIG2C, in memory cell 200, there is a parasitic capacitance 203 between the gate terminal 201g of the first transistor 201 and the ground point, and the weight stored in memory cell 200 is determined based on the charge stored in the parasitic capacitance 203 in memory cell 200.

[0051] According to some embodiments, as shown in FIG2B or FIG2D, the memory cell 200 further includes a storage capacitor 203, a first terminal of the storage capacitor 203 being connected to the gate terminal 201g of the first transistor 201 of the memory cell 200, and a second terminal of the storage capacitor 203 being connected to a ground point, wherein the weight stored in the memory cell 200 is determined based on the charge stored in the storage capacitor 203 in the memory cell 200.

[0052] According to some embodiments, in the memory cell 200 shown in Figures 2A-2D, by applying a conduction signal (e.g., conduction voltage) to the gate terminal 202g of the second transistor 202 and applying a write signal (e.g., write voltage) to the second terminal 202b of the second transistor 202, the charge stored in the storage capacitor 203 or parasitic capacitor 203 in the memory cell 200 can be controlled, thereby controlling the weight value stored in the memory cell.

[0053] According to some embodiments, for each write control circuit, each write control circuit is used to control one or more memory cells in the memory array. For example, as shown in FIG1, FIG9 or FIG14, write control circuit 121, 921 or 1421 is used to control memory cells in the first column and the second column of the memory array.

[0054] According to some embodiments, each write control circuit is configured to: for any memory cell controlled by the write control circuit, in response to any memory cell being in a write state and the output current of any memory cell satisfying a threshold condition, control to stop applying a write signal to the second terminal of the second transistor in any memory cell, wherein the threshold condition is determined based on the value to be written of any memory cell.

[0055] According to some embodiments, as shown in Figures 1 and 9, each of the write control circuits 121-12N and 921-92N can be reused to control the writing of multiple memory cells. For each write control circuit, when any memory cell under its control is in a write state, the output current of that memory cell is detected to determine whether it is necessary to stop applying a write signal to the second terminal of the second transistor in that memory cell, thereby ending the writing to that memory cell. It should be understood that, as described above, the memory computing circuits 100 and 900 may include only one write control circuit. In this case, the write control circuit can be reused to control the writing of memory cells in the memory computing circuits 100 and 900. In this implementation, the circuit structure for write control is simplified, saving the area of ​​the write control circuit on the chip. However, compared to embodiments using multiple write control circuits, the efficiency of writing to the memory computing circuit is reduced.

[0056] According to some embodiments, each write control circuit is configured to: for any memory cell controlled by the write control circuit, in response to the memory cell being in a write state and the output current of the memory cell satisfying a threshold condition, control the write control switch in the memory cell to be turned off, the threshold condition being determined based on the value to be written in the memory cell.

[0057] According to some embodiments, as shown in FIG14, each write control circuit in the write control circuits 1421-142N can be reused to control the writing of multiple memory cells. For each write control circuit, when any memory cell under its control is in a write state, the output current of that memory cell is detected to determine whether it is necessary to control the write control switch in that memory cell to be turned off, thereby ending the writing to that memory cell. It should be understood that, as described above, the memory computing circuit 1400 may include only one write control circuit. In this case, the write control circuit can be reused to control the writing of memory cells in the memory computing circuit 1400. In this implementation, the circuit structure for write control is simplified, saving the area of ​​the write control circuit on the chip. However, compared to embodiments using multiple write control circuits, the efficiency of writing to the memory computing circuit is reduced.

[0058] According to some embodiments, for any column of memory cells in memory array 110, 910 or 1410, the memory cells in the column are "activated" in response to receiving an input voltage corresponding to the column at the second terminal of their respective first transistor, so as to output a corresponding output current at the first terminal of their respective first transistor. According to some embodiments, the output current at the first terminal of the first transistor of a memory cell depends on the weight stored in the memory cell and the input voltage at the second terminal of the first transistor of the memory cell.

[0059] According to some embodiments, the output current at the first terminal of the first transistor of a memory cell in memory array 110, 910 or 1410 is the product of the weight stored in the memory cell and the input voltage at the second terminal of the first transistor of the memory cell, that is, I OUT = V IN × W, where I OUT is the output current at the first terminal of the first transistor of the memory cell, V IN is the input voltage at the second terminal of the first transistor of the memory cell, and W is the stored value of the first transistor of the memory cell.

[0060] According to some embodiments, vector-matrix multiplication can be implemented by memory array 110, 910 or 1410, where the input voltages received by each column of memory array 110, 910 or 1410 correspond to the respective components of the input vector of the vector-matrix multiplication, the weights of each memory cell in memory array 110, 910 or 1410 correspond to the respective weight values of the matrix of the vector-matrix multiplication, and the output currents of each row of memory array 110, 910 or 1410 correspond to the respective components of the output vector of the vector-matrix multiplication.

[0061] According to some embodiments, for any row of memory cells in memory array 110, 910 or 1410, since the first terminals of the first transistors of the memory cells in the row are connected, the output currents of the first transistors of the memory cells in the row are summed to form the output current of the row.

[0062] For example, if the weight stored in the memory cell located in the k-th row and the j-th column is W k,j , the output current is I k,j , and the input voltage is V INj , where 0 < k ≤ M, 0 < j ≤ N, then the relationship between the output current, the stored weight and the input voltage of the memory cell located in the k-th row and the j-th column can be expressed as I k,j = V INj W k,jFurthermore, for the memory cell in the k-th row, according to Kirchhoff's laws, the current I at the output terminal of the k-th row is... OUTk It is the sum of the output currents of all memory cells in that row, that is, For example, if a memory array can be viewed as a storage matrix Furthermore, the input voltages of multiple columns in the memory array can be considered as vectors. Based on the above analysis, the output current of multiple rows of the memory array can be considered as a vector.

[0063] According to some embodiments, for each write control circuit, the gate terminals of the second transistors in different memory cells controlled by the write control circuit are connected to different write word lines, thereby allowing independent write control of the different memory cells controlled by the write control circuit. For example, when a memory cell controlled by the write control circuit is in a write state, an on control signal is applied to the write word line to which the memory cell in the write state is connected, and an off control signal is applied to the write word lines to which other memory cells controlled by the write control circuit are connected, so that the second transistors in the other memory cells are turned off and are not in a write state. Since the off control signal is applied to the write word line to which the other memory cells are connected, the second transistors in the other memory cells are turned off, thereby avoiding interference caused by the floating voltage that may still exist on the second terminal of the second transistor when the control stops applying the write signal to the second terminal of the second transistor in the memory cell as described above, and minimizing interference between memory cells in the write state and memory cells not in the write state.

[0064] According to some embodiments, for each of the one or more write control circuits, the gate terminal of the second transistor in any memory cell controlled by the write control circuit is connected to the same write word line as the gate terminals of the second transistors in the corresponding memory cells controlled by other write control circuits. According to some embodiments, any memory cell controlled by the write control circuit is located in the same row of the memory array and is not adjacent to the corresponding memory cells controlled by other write control circuits.

[0065] For example, the gate terminals of the second transistors in memory cells with the same row number and the same column number controlled by the write control circuits 921 to 92N shown in FIG9 are connected to the same write word line. For example, the memory cells in the first row and the first column of the memory cells controlled by the write control circuit 921, the memory cells in the first row and the first column of the memory cells controlled by the write control circuit 922, ... the memory cells in the first row and the first column of the memory cells controlled by the write control circuit 92N are connected to the same write word line.

[0066] According to embodiments of the present disclosure, parallel writing of corresponding memory cells controlled by different write control circuits can be achieved by connecting the gate terminals of the second transistors in the corresponding memory cells controlled by different write control circuits to the same write word line. Furthermore, since the corresponding memory cells controlled by different write control circuits are usually spaced a certain distance apart (e.g., at least not adjacent memory cells), the possibility of mutual interference between them is extremely small.

[0067] According to some embodiments, for each of one or more write control circuits, the memory cell controlled by the write control circuit is a memory cell in a corresponding column group of a memory array, wherein the corresponding column group of the memory array includes memory cells in multiple consecutive columns of the memory array. For example, as shown in FIG9, the write control circuit 921 controls memory cells in the first column and the second column.

[0068] According to some embodiments, in each memory cell, the first terminal of the first transistor is the source terminal and the second terminal of the first transistor is the drain terminal, or the first terminal of the first transistor is the drain terminal and the second terminal of the first transistor is the source terminal.

[0069] According to some embodiments, in each memory cell, the first terminal of the second transistor is the source terminal and the second terminal of the second transistor is the drain terminal, or the first terminal of the second transistor is the drain terminal and the second terminal of the second transistor is the source terminal.

[0070] According to some embodiments, each write control circuit includes a write detection circuit configured to generate a stop write signal corresponding to any memory cell controlled by the write control circuit in response to the memory cell being in a write state and the output current of the memory cell satisfying a threshold condition. Each memory cell also includes a write control switch, one end of which is connected to the second terminal of the second transistor in the memory cell, and the other end of which receives the write signal corresponding to the memory cell. The write control switch in each memory cell is configured to disconnect the write control switch in response to receiving the stop write signal corresponding to the memory cell at the control terminal of the write control switch.

[0071] According to some embodiments, the write control switch in each memory cell is further configured to close the write control switch in response to the memory cell being in a write state and not receiving a stop write signal corresponding to the memory cell at the control terminal of the write control switch.

[0072] It should be understood that the accompanying drawings only schematically show the signal transmission, but the actual circuit connection can be adjusted according to actual needs. For example, in Figures 1, 9 or 14, memory cells in the same column can share a bus for transmitting write control signals, and each memory cell in the same column has a signal sub-line connected to the bus to transmit write control signals to the memory cell.

[0073] According to some embodiments, each write control circuit is further configured to: for any memory cell controlled by the write control circuit, in response to any memory cell being in a write state and the output current of any memory cell not meeting a threshold condition, control the write control switch in any memory cell to close.

[0074] According to some embodiments, in each memory cell, the write control switch is a transistor, and the gate terminal of the write control switch is connected to the write control circuit that controls the memory cell. The first terminal of the write control switch is the source terminal, and the second terminal of the write control switch is the drain terminal, or the first terminal of the write control switch is the drain terminal, and the second terminal of the write control switch is the source terminal.

[0075] Figure 3 shows a circuit schematic of controlled writing according to an exemplary embodiment of the present disclosure. For simplicity, only one write control circuit and a memory cell controlled by it in a write state are shown in Figure 3 to illustrate the write control of the memory cell by the write control circuit, while other parts of the memory circuit are omitted.

[0076] According to some embodiments, the memory cell 300 shown in FIG3 may be the same as or similar to the memory cell in the memory circuit 100 described with reference to FIG1 and the memory cell 200 described with reference to FIG2A or 2B. Therefore, the characteristics and technical effects of the memory cell in the memory circuit 100 described with reference to FIG1 and the memory cell 200 described with reference to FIG2A or 2B can also be applied to the memory cell 300 in FIG3, and are omitted here.

[0077] According to some embodiments, the write control circuit 310 shown in FIG3 may be the same as or similar to the write control circuits 121 to 12N described with reference to FIG1. ​​Therefore, the characteristics and technical effects of the write control circuits 121 to 12N in the memory-based circuit 100 described above with reference to FIG1 can also be applied to the write control circuit 310 in FIG3, and are omitted here.

[0078] According to some embodiments, the write control circuit 310 includes a write detection circuit 311, which is configured to generate a stop write signal corresponding to any memory cell (e.g., memory cell 300 shown in FIG3) for any memory cell controlled by the write control circuit (e.g., memory cell 300 shown in FIG3) in response to any memory cell (e.g., memory cell 300 shown in FIG3) being in a write state and the output current of any memory cell (e.g., memory cell 300 shown in FIG3) satisfying a threshold condition.

[0079] According to some embodiments, the memory cell 300 further includes a write control switch 304, one end of which is connected to the second terminal 302b of the second transistor 302 in the memory cell 300, and the other end of which receives a write signal corresponding to the memory cell 300. The write control switch 304 in each memory cell is configured to disconnect the write control switch in response to receiving a stop write signal corresponding to the memory cell at the control terminal of the write control switch 304.

[0080] According to some embodiments, although FIG. 3 shows that the write control circuit 310 directly receives the output current of the memory cell 300, as will be described in further detail below with reference to FIG. 4-5, the write control circuit 310 can also be connected to multiple memory cells it controls for writing via a multiplexer to achieve its multiplexing. In particular, when the write control circuit 310 is used to control any memory cell in the write state, the write control circuit 310 is connected to the memory cell in the write state via a multiplexer to receive its output current.

[0081] According to some embodiments, a write control switch in memory cell 300 is connected to a write bit line (WBL) corresponding to that memory cell 300 to receive a write signal. According to some embodiments, as shown in FIG1, the second terminals of second transistors in memory cells of the same column in the memory array are connected (e.g., connected to the write bit line corresponding to that column), and the gate terminals of second transistors in memory cells of the same row in the memory array are connected (e.g., connected to the write word line corresponding to that row). According to other embodiments, the second terminals of second transistors in memory cells of the same row in the memory array are connected (e.g., connected to the write bit line corresponding to that column), and the gate terminals of second transistors in memory cells of the same column in the memory array are connected (e.g., connected to the write word line corresponding to that row).

[0082] According to some embodiments, when a write operation is performed on memory cell 300, an input voltage is applied to the second terminal 301a of the first transistor 301 in memory cell 300. The input voltage can be a preset value to determine a threshold condition for judging the output current. According to some embodiments, since, as analyzed above, the output current of the first terminal 301b of the first transistor 301 of memory cell 300 is the product of the weight stored in memory cell 300 and the input voltage at the second terminal 301a of the first transistor 301 of memory cell 300, the threshold condition for the output current can be set as follows: the output current is greater than or equal to an upper current limit value, where the upper current limit value is set based on the weight value written to memory cell 300 and the input voltage of memory cell 300 (e.g., equal to the product of the weight value written to memory cell 300 and the input voltage of memory cell 300).

[0083] According to some embodiments, although FIG. 3 shows the write control circuit 310 directly sending a stop write signal to the memory cell 300, as will be described in further detail below with reference to FIG. 4-5, the write control circuit 310 can also be connected to multiple memory cells it controls for writing via a multiplexer to achieve its multiplexing. In particular, when the write control circuit 310 is used to control any memory cell in the write state, the write control circuit 310 is connected to the memory cell in the write state via a multiplexer to send a stop write signal to the write control switch therein.

[0084] According to some embodiments, the write control switch 304 in the memory cell 300 is further configured to: close the write control switch 304 in response to the memory cell 300 being in a write state and not receiving a stop write signal corresponding to the memory cell at the control terminal of the write control switch 304. According to some embodiments, the write detection circuit 311 is further configured to: generate an enable write signal corresponding to any memory cell (e.g., the memory cell 300 shown in FIG. 3) controlled by the write control circuit in response to any memory cell (e.g., the memory cell 300 shown in FIG. 3) being in a write state and the output current of any memory cell (e.g., the memory cell 300 shown in FIG. 3) not meeting a threshold condition; and the write control switch 304 in the memory cell 300 is further configured to: close the write control switch 304 in response to the memory cell 300 being in a write state and receiving an enable write signal corresponding to the memory cell at the control terminal of the write control switch 304.

[0085] Figure 10 shows a schematic diagram of a memory computing circuit 1000 according to an exemplary embodiment of the present disclosure. According to some embodiments, the memory array 1010 and write control circuits 1021-102N in Figure 10 can be similar to the memory 910 and write control circuits 921-92N in Figure 9, respectively. Therefore, the features and / or effects of the memory 910 and write control circuits 921-92N described above with reference to Figure 9 can also be applied to the memory array 1010 and write control circuits 1021-102N in Figure 10, and are omitted here.

[0086] According to some embodiments, the in-memory computing circuit 1000 further includes a first encoding circuit 1031, wherein the first encoding circuit 1031 is configured to generate signals corresponding to write word lines of the memory array 1010 in the in-memory computing circuit 1000. According to some embodiments, the first encoding circuit 1000 is configured to: apply an on control signal to the write word line connected to any memory cell in the memory array 1010 in response to any memory cell in the memory array being in a write state; and apply an off control signal to the write word line connected to any memory cell in response to any memory cell in the memory array ending a write state.

[0087] It should be understood that although Figure 10 shows multiple write control circuits, the memory computing circuit 1000 may include only one write control circuit. In this case, the write control circuit can be reused to control the write to the memory cells in the memory computing circuit 1000.

[0088] Figure 11 shows a circuit schematic of controlled writing according to an exemplary embodiment of the present disclosure. For simplicity, only one write control circuit and a memory cell controlled by it in a write state are shown in Figure 11 to illustrate the write control of the memory cell by the write control circuit and the write word line, while other parts of the memory circuit are omitted.

[0089] According to some embodiments, the memory cell 1100 shown in FIG11 may be the same as or similar to the memory cell in the memory circuit 900 described with reference to FIG9 and the memory cell 200 described with reference to FIG2A or 2B. Therefore, the characteristics and technical effects of the memory array 910 described with reference to FIG9, the memory cell in the memory array 1110 described with reference to FIG11, and the memory cell 200 described with reference to FIG2A or 2B can also be applied to the memory cell 1100 in FIG11, and are omitted here.

[0090] According to some embodiments, the write control circuit 1110 shown in FIG11 may be the same as or similar to the write control circuits 921-92N described with reference to FIG9 and the write control circuits 1021-102N described with reference to FIG10. Therefore, the characteristics and technical effects of the write control circuits 921-92N in the memory-based circuit 900 described with reference to FIG9 and the write control circuits 1021-102N described with reference to FIG10 can also be applied to the write control circuit 1110 in FIG11, and are omitted here.

[0091] According to some embodiments, the write control circuit 1110 includes a write detection circuit 1111, which is configured to generate a stop write signal corresponding to any memory cell (e.g., memory cell 1100 shown in FIG. 11) for any memory cell (e.g., memory cell 1100 shown in FIG. 11) controlled by the write control circuit, in response to any memory cell (e.g., memory cell 1100 shown in FIG. 11) being in a write state and the output current of any memory cell (e.g., memory cell 1100 shown in FIG. 11) satisfying a threshold condition.

[0092] According to some embodiments, the memory cell 1100 further includes a write control switch 1104, one end of which is connected to the second terminal 1102b of the second transistor 1102 in the memory cell 1100, and the other end of which receives a write signal corresponding to the memory cell 1100. The write control switch 1104 in each memory cell is configured to disconnect the write control switch in response to receiving a stop write signal corresponding to the memory cell at the control terminal of the write control switch 1104.

[0093] According to some embodiments, although the write control circuit 1110 is shown in FIG11 directly receiving the output current of the memory cell 1100, as will be described in further detail below with reference to FIG4 and 12, the write control circuit 1110 may also be connected to multiple memory cells under its control via a multiplexer to achieve its multiplexing. In particular, when the write control circuit 1110 is used to control any memory cell in the write state, the write control circuit 1110 is connected to the memory cell in the write state via a multiplexer to receive its output current.

[0094] According to some embodiments, a write control switch in memory cell 1100 is connected to the write bit line (WBL) corresponding to memory cell 1100 to receive write signals.

[0095] According to some embodiments, when a write operation is performed on memory cell 1100, an input voltage is applied to the second terminal 1101a of the first transistor 1101 in memory cell 1100. The input voltage can be a preset value to determine a threshold condition for judging the output current. According to some embodiments, since, as analyzed above, the output current of the first terminal 1101b of the first transistor 1101 in memory cell 1100 is the product of the weight stored in memory cell 1100 and the input voltage at the second terminal 1101a of the first transistor 1101 in memory cell 1100, the threshold condition for the output current can be set as follows: the output current is greater than or equal to an upper current limit value, where the upper current limit value is set based on the weight value written to memory cell 1100 and the input voltage of memory cell 1100 (e.g., equal to the product of the weight value written to memory cell 1100 and the input voltage of memory cell 1100).

[0096] According to some embodiments, although FIG11 shows the write control circuit 1110 directly sending a stop write signal to the memory cell 1100, as will be described in further detail below with reference to FIG4 and 12, the write control circuit 1110 can also be connected to multiple memory cells it controls for writing via a multiplexer to achieve its multiplexing. In particular, when the write control circuit 1110 is used to control any memory cell in the write state, the write control circuit 1110 is connected to the memory cell in the write state via a multiplexer to send a stop write signal to the write control switch therein.

[0097] According to some embodiments, the write control switch 1104 in the memory cell 1100 is further configured to: close the write control switch 1104 in response to the memory cell 1100 being in a write state and not receiving a stop write signal corresponding to the memory cell at the control terminal of the write control switch 1104. According to some embodiments, the write detection circuit 1111 is further configured to: generate an enable write signal corresponding to any memory cell (e.g., the memory cell 1100 shown in FIG. 11) for any memory cell (e.g., the memory cell 1100 shown in FIG. 11) controlled by the write control circuit in response to any memory cell (e.g., the memory cell 1100 shown in FIG. 11) being in a write state and the output current of any memory cell (e.g., the memory cell 1100 shown in FIG. 11) not meeting a threshold condition; and the write control switch 1104 in the memory cell 1100 is further configured to: close the write control switch 1104 in response to the memory cell 1100 being in a write state and receiving an enable write signal corresponding to the memory cell at the control terminal of the write control switch 1104.

[0098] According to some embodiments, the gate terminal 1102g of the second transistor 1102 in the memory cell 1100 is connected to the write word line (WWL) 1120 corresponding to the memory cell 1100 to control the second transistor 1102 to be turned on or off.

[0099] Figure 15 shows a circuit schematic of controlled writing according to an exemplary embodiment of the present disclosure. For simplicity, only one write control circuit and a memory cell in a write state controlled by it are shown in Figure 15 to illustrate the write control of the memory cell by the write control circuit, while other parts of the memory circuit are omitted.

[0100] According to some embodiments, the memory cell 1500 shown in FIG15 may be the same as or similar to the memory cell in the memory array 1400 described with reference to FIG14 and the memory cell 200 described with reference to FIG2A, 2B, 2C or 2D. Therefore, the characteristics and technical effects of the memory cell in the memory array 1400 described with reference to FIG14 and the memory cell 200 described with reference to FIG2A, 2B or 2C or 2D can also be applied to the memory cell 1500 in FIG15, and are omitted here.

[0101] According to some embodiments, the write control circuit 1510 shown in FIG15 may be the same as or similar to the write control circuits 1421-142N described with reference to FIG14. Therefore, the characteristics and technical effects of the write control circuits 1421-142N in the memory array 1400 described above with reference to FIG14 can also be applied to the write control circuit 1510 in FIG15, and are omitted here.

[0102] According to some embodiments, the write control circuit 1510 is configured to generate a stop write signal corresponding to any memory cell (e.g., memory cell 1500 shown in FIG. 15) for any memory cell controlled by the write control circuit (e.g., memory cell 1500 shown in FIG. 15) in a write state and the output current of any memory cell (e.g., memory cell 1500 shown in FIG. 15) satisfies a threshold condition.

[0103] According to some embodiments, the memory cell 1500 further includes a write control switch 1504, one end of which is connected to the gate terminal 1502g of the second transistor 1502 in the memory cell 1500, and the other end of which receives a write control signal corresponding to the memory cell 1500. The write control switch 1504 in each memory cell is configured to disconnect the write control switch 1504 in response to receiving a stop write signal corresponding to the memory cell at the control terminal of the write control switch 1504.

[0104] According to some embodiments, the write control switch 1504 is a transistor, and the control terminal of the write control switch 1504 is a gate terminal, wherein the write control switch is turned off in response to receiving a stop write signal corresponding to the memory cell at the control terminal of the write control switch 1504.

[0105] According to some embodiments, when the write control switch 1504 is turned off in response to a stop write signal, the second transistor 1502 is disconnected from the word line WWL 1520, and the second transistor 1502 is turned off accordingly, thereby stopping the write process to the memory cell 1500.

[0106] According to some embodiments, in response to the memory cell 1500 being in a write state and the output current of the memory cell 1500 not meeting the threshold condition, the write control circuit 1510 controls the write control switch 1504 in the memory cell 1500 to close. For example, it sends an enable write signal to the control terminal of the write control switch 1504 in the memory cell 1500, so that the second transistor 1502 can accept the write control signal from the word line WWL 1520 and be turned on, and further receives the write signal from the write bit line (WBL) 1530 from the second terminal 1502b of the second transistor 1502 to perform a write operation on the memory cell 1500.

[0107] According to some embodiments, although the write control circuit 1510 is shown in FIG15 directly receiving the output current of the memory cell 1500, as will be described in further detail below with reference to FIG4-5, the write control circuit 1510 may also be connected to multiple memory cells under its control via a multiplexer to achieve its multiplexing. In particular, when the write control circuit 1510 is used to control any memory cell in the write state, the write control circuit 1510 is connected to the memory cell in the write state via a multiplexer to receive its output current.

[0108] According to some embodiments, as shown in FIG1, the second terminals of the second transistors in the memory cells of the same column in the memory array are connected (e.g., connected to the write bit line corresponding to that column), and the gate terminals of the second transistors in the memory cells of the same row in the memory array are connected (e.g., connected to the write word line corresponding to that row). According to some embodiments, the second terminal of the write control switch in the memory cells of the same row is connected to the write word line corresponding to that row.

[0109] According to some embodiments, when a write operation is performed on memory cell 1500, an input voltage is applied to the second terminal 1501a of the first transistor 1501 in memory cell 1500. The input voltage can be a preset value to determine a threshold condition for judging the output current. According to some embodiments, since, as analyzed above, the output current of the first terminal 1501b of the first transistor 1501 of memory cell 1500 is the product of the weight stored in memory cell 1500 and the input voltage at the second terminal 1501a of the first transistor 1501 of memory cell 1500, the threshold condition for the output current can be set as follows: the output current is greater than or equal to an upper current limit value, where the upper current limit value is set based on the weight value written to memory cell 1500 and the input voltage of memory cell 1500 (e.g., equal to the product of the weight value written to memory cell 1500 and the input voltage of memory cell 1500).

[0110] According to some embodiments, although FIG15 shows the write control circuit 1510 directly sending a stop write signal to the memory cell 1500, as will be described in further detail below with reference to FIG4-5, the write control circuit 1510 can also be connected to multiple memory cells it controls for writing via a multiplexer to achieve its multiplexing. In particular, when the write control circuit 1510 is used to control any memory cell in the write state, the write control circuit 1510 is connected to the memory cell in the write state via a multiplexer to send a stop write signal to the write control switch therein.

[0111] According to some embodiments, each write control circuit includes a first multiplexer, and the first multiplexer in each write control circuit is configured to: in response to any memory cell controlled by the write control circuit corresponding to the first multiplexer being in a write state, connect the write control circuit corresponding to the first multiplexer to a second terminal of a first transistor in any memory cell in the write state to receive the output current of any memory cell in the write state.

[0112] According to some embodiments, each write control circuit includes a second multiplexer, and the second multiplexer in each write control circuit is configured to: in response to any memory cell controlled by the write control circuit corresponding to the second multiplexer being in a write state, connect the write control circuit corresponding to the second multiplexer to a write control switch in any memory cell in the write state, so as to provide a stop write signal corresponding to any memory cell to any memory cell when the write control circuit corresponding to the second multiplexer generates a stop write signal corresponding to any memory cell.

[0113] According to some embodiments, each write control circuit includes a second multiplexer, and the second multiplexer in each write control circuit is configured to connect the write control circuit corresponding to the second multiplexer to a write control switch in any memory cell in the write state in response to the write control circuit corresponding to the second multiplexer being in a write state.

[0114] Figure 4 shows a schematic diagram of a write control circuit 400 according to an exemplary embodiment of the present disclosure. According to some embodiments, the write control circuit 400 may be the same as or similar to the write control circuits 121-12N, 921-92N, or 1421-142N described with reference to Figures 1, 9, or 14, or the write control circuits 310, 1010, or 1510 described with reference to Figures 3, 10, or 15. Therefore, features and / or technical effects of the write control circuits 121-12N described with reference to Figure 1, the write control circuit 310 in Figure 3, the write control circuits 921-92N described with reference to Figure 9, the write control circuit 1010 in Figure 10, the write control circuits 1421-142N described with reference to Figure 14, and the write control circuit 1510 in Figure 15 can be applied to the write control circuit 400 and are therefore omitted.

[0115] According to some embodiments, the write control circuit 400 includes a first multiplexer 401, which is configured to connect the write control circuit 400 corresponding to the first multiplexer 401 to a first terminal of a first transistor in any memory cell in the write state in response to any memory cell controlled by the write control circuit 400 being in a write state, so as to receive the output current of any memory cell in the write state.

[0116] According to some embodiments, the write control circuit 400 includes a write detection circuit 403, wherein the write detection circuit 403 is based on the output current of a first transistor in any memory cell in a write state received by a first multiplexer 401, and the first multiplexer 401 may optionally connect any memory cell in a write state to the write detection circuit 403 to perform write control on the memory cell.

[0117] According to some embodiments, the write control circuit 400 includes a write detection circuit 403, wherein the write detection circuit 403 may be the same as or similar to the write detection circuits 311 and 1111 described with reference to FIG3 and FIG11. The first multiplexer 401 may optionally connect any memory cell in the write state to the write detection circuit 403 to perform write control on the memory cell.

[0118] According to some embodiments, the write control circuit 400 includes a second multiplexer 402, and the second multiplexer 402 is configured to connect the write control circuit 400 to a write control switch in any memory cell in the write state in response to any memory cell controlled by the write control circuit 400 being in a write state.

[0119] According to some embodiments, the write control circuit 400 includes a second multiplexer 402, and the second multiplexer 402 is configured to connect the write control circuit 400 to a write control switch in any memory cell in the write state in response to any memory cell being in a write state, so as to provide a stop write signal corresponding to any memory cell to the write control unit in any memory cell when the write control circuit 400 generates a stop write signal corresponding to any memory cell.

[0120] According to some embodiments, the second multiplexer 402 may optionally connect the write control switch in any memory cell in the write state to the write detection circuit 403 to perform write control on that memory cell.

[0121] According to some embodiments, the write detection circuit 403 determines whether to generate a stop write signal based on the output current of the first transistor in any memory cell in the write state received by the first multiplexer 401. The second multiplexer 402 may optionally connect the write control switch in any memory cell in the write state to the write detection circuit 410 to perform write control on the memory cell. For example, when the write detection circuit 403 generates a write control signal, the write control signal may optionally be transmitted to the write control switch in any memory cell in the write state through the second multiplexer 402.

[0122] Figure 5 shows a circuit schematic of controlled writing according to an exemplary embodiment of the present disclosure. For simplicity, only a write control circuit 500 and memory cells 511-51N in a row of memory cells controlled by it are shown in Figure 5 to illustrate the write control of the memory cells by the write control circuit, while other parts of the memory circuit are omitted.

[0123] According to some embodiments, when performing a write operation on memory cells in the memory array, the memory cells are written row by row. Therefore, it can be equivalent to only one memory cell in a row being connected to the write control circuit 500 at any given time. According to some embodiments, memory cells 511-51N are connected to the same write word line 520.

[0124] According to some embodiments, the write control circuit 500 is optionally connected to the memory cells 511-51N via a first multiplexer 501 and a second multiplexer 502. The first multiplexer 501 optionally connects the memory cells 511-51N in the write state to the write control circuit 500 (e.g., the write detection circuit 503 in the write control circuit 500) to receive the output current from the memory cells in the write state. The second multiplexer 502 optionally connects the memory cells 511-51N in the write state to the write control circuit 500 (e.g., the write detection circuit 503 in the write control circuit 500) to transmit a stop write signal to the memory cell in the write state when the output current of the memory cell in the write state meets a threshold condition.

[0125] Figure 12 shows a circuit schematic of controlled writing according to an exemplary embodiment of the present disclosure. For simplicity, only the two write control circuits 1221-1222 and the memory cells 12111-1211N and 12121-1212N in a row controlled by them are shown in Figure 12 to illustrate the write control of the memory cells by the write control circuit, while other parts of the memory computing circuit are omitted.

[0126] According to some embodiments, when writing to memory cells in a memory array, the memory cells are written row by row. Therefore, it can be equivalent to only one memory cell in a row being connected to the write control circuits 1221 and 1222 at the same write time.

[0127] According to some embodiments, for each write control circuit, each memory cell controlled by the write control circuit corresponds to the same write word line as the memory cells corresponding to that memory cell controlled by other write control circuits. For example, the memory cell 12111 in the first column of the memory cells 12111-1211N controlled by the first write control circuit 1221 and the memory cell 12121 in the first column of the memory cells 12121-1212N in the same row controlled by the second write control circuit 1222 are connected to the same write word line 1241. The memory cells 12112 in the second column of the memory cells 12111-1211N controlled by the first write control circuit 1221 and the memory cell 12112 in the second column of the memory cells 12111-1211N controlled by the first write control circuit 1222 are connected to the same write word line 1241. The memory cell 12122 in the second column of the memory cells 12121-1212N in the same row controlled by the first write control circuit 1221 is connected to the same write word line 1242, ... The memory cell 1211N in the Nth column of the memory cells 12111-1211N in the same row controlled by the first write control circuit 1221 and the memory cell 1212N in the Nth column of the memory cells 12121-1212N in the same row controlled by the second write control circuit 1222 is connected to the same write word line 124N.

[0128] According to some embodiments, the write control circuit 1221 is optionally connected to memory cells 12111-1211N via a first multiplexer 12211 and a second multiplexer 12213. The first multiplexer 12211 optionally connects memory cells in the write state of memory cells 12111-1211N to the write control circuit 1221 (e.g., the write detection circuit 12212 in the write control circuit 1221) to receive the output current from the memory cells in the write state. The second multiplexer 12213 optionally connects memory cells in the write state of memory cells 12111-1211N to the write control circuit 1221 (e.g., the write detection circuit 12212 in the write control circuit 1221) to transmit a stop write signal to the memory cell in the write state when the output current of the memory cell in the write state meets a threshold condition.

[0129] According to some embodiments, the write control circuit 1222 is optionally connected to memory cells 12121-1212N via a first multiplexer 12221 and a second multiplexer 12223. The first multiplexer 12221 optionally connects memory cells in the write state of memory cells 12121-1212N to the write control circuit 1222 (e.g., the write detection circuit 12222 in the write control circuit 1222) to receive the output current from the memory cells in the write state. The second multiplexer 12223 optionally connects memory cells in the write state of memory cells 12121-1212N to the write control circuit 1222 (e.g., the write detection circuit 12222 in the write control circuit 1222) to transmit a stop write signal to the memory cell in the write state when the output current of the memory cell in the write state meets a threshold condition.

[0130] According to some embodiments, the first encoding circuit 1231 is connected to the write word lines 1241-124N corresponding to the memory cells 12111-1211N and 12121-1212N to generate corresponding signals for each write word line 1241-124N.

[0131] According to some embodiments, each of the one or more write control circuits includes: a conversion circuit configured to receive an output current of any memory cell controlled by the write control circuit and convert the received output current of the memory cell into a detection voltage; and a comparison circuit configured to control a write control switch in any memory cell to open in response to the detection voltage being greater than or equal to a threshold voltage, wherein the threshold voltage is determined based on the value to be written to the memory cell.

[0132] According to some embodiments, each of the one or more write control circuits includes: a conversion circuit configured to: receive an output current of any memory cell controlled by the write control circuit, and convert the received output current of any memory cell into a detection voltage; and a comparison circuit configured to: control a halt to applying a write signal to a second terminal of a second transistor in any memory cell in response to the detection voltage being greater than or equal to a threshold voltage, wherein the threshold voltage is determined based on the value to be written to any memory cell.

[0133] Figure 6 shows a schematic diagram of a write control circuit 600 according to an exemplary embodiment of the present disclosure. It should be understood that, for simplicity, only a write control circuit 600 and signals received from and sent to memory cells in a write state are shown, while other components and connections in the memory array are omitted.

[0134] According to some embodiments, as shown in FIG6, the write control circuit 600 includes a conversion circuit 601 configured to receive the output current I of any memory cell controlled by the write control circuit 600. out Furthermore, the output current I of any received memory cell will be... out Converted to detection voltage V dec ; and comparator circuit 602, configured to: respond to detection voltage V dec Greater than or equal to the threshold voltage V ref The control stops applying a write signal to the second terminal of the second transistor in any memory cell, wherein the threshold voltage V ref It is determined based on the value to be written to any memory cell.

[0135] According to some embodiments, in response to the detected voltage V dec Greater than or equal to the threshold voltage V ref The comparator circuit 602 outputs a stop writing signal.

[0136] According to some embodiments, the write control circuit 600 may further include a first multiplexer and / or a second multiplexer as shown in FIG4, FIG5 or FIG12, to optionally connect the write control circuit 600 to a memory cell in a write state among the memory cells it controls.

[0137] According to some embodiments, one or more write control circuits include write control circuitry corresponding to each column group of the memory array, wherein each column group of the memory array includes memory cells in one or more columns of the memory array. According to some embodiments, each column group of the memory array may include memory cells in four columns of the memory array.

[0138] According to some embodiments, in each memory cell, there exists a parasitic capacitance between the gate terminal of the first transistor and the ground point. According to some embodiments, the weight stored in each memory cell is determined based on the charge stored in the parasitic capacitance of that memory cell. According to some embodiments, as shown in FIG2A or FIG2C, in memory cell 200, there exists a parasitic capacitance 203 between the gate terminal 201g of the first transistor 201 and the ground point, and the charge stored in this parasitic capacitance can be changed during the writing process of memory cell 200.

[0139] According to some embodiments, each memory cell further includes a storage capacitor, a first terminal of which is connected to the gate terminal of a first transistor of the memory cell, and a second terminal of which is connected to a ground point. The weight stored in each memory cell is determined based on the charge stored in the storage capacitor within that memory cell. According to some embodiments, as shown in FIG2B or FIG2D, the charge stored in the storage capacitor 203 can be changed during the writing process of the memory cell 200. According to the embodiments described in this disclosure, the weight value stored in the memory cell can be accurately set by manually configuring the storage capacitor.

[0140] According to some embodiments, the in-memory computing circuit further includes a digital-to-analog converter for converting the digital input signal into an analog signal for input to the in-memory computing circuit. According to some embodiments, the in-memory computing circuit further includes an analog-to-digital converter for converting the analog output signal of the memory array into a digital signal output.

[0141] According to some embodiments, the first transistor is a silicon transistor (e.g., a complementary metal-oxide-semiconductor (CMOS) transistor), and the second transistor is an indium gallium zinc oxide (IGZO) transistor. According to the embodiments described in this disclosure, since IGZO transistors have good leakage current performance, using IGZO transistors as write transistors can better prevent memory cell leakage (e.g., leakage of storage capacitance or parasitic capacitance connected to the source or drain terminals of the IGZO transistor). Furthermore, since the gate of a silicon transistor is typically oxide, there is not much leakage current, and using a silicon transistor as a read transistor will not cause more memory cell leakage (e.g., leakage of storage capacitance or parasitic capacitance) than with IGZO transistors.

[0142] According to other embodiments, the first transistor may also be configured as an IGZO transistor to improve write speed.

[0143] According to some embodiments, the in-memory computing circuit may also include programming circuitry to control the process of writing to the memory array in the in-memory computing circuit.

[0144] Figure 7 shows a flowchart of a method 700 for controlling a memory-based computing circuit (e.g., memory-based computing circuit 100 described with reference to Figure 1, memory-based computing circuit 900 described with reference to Figure 9, and memory-based computing circuit 1000 described with reference to Figure 10) according to exemplary embodiments of the present disclosure. According to some embodiments, features and / or technical effects of the memory-based computing circuits and their components described above with reference to Figures 1-12 can be applied accordingly to method 700, and are therefore omitted here. As shown in Figure 7, method 700 includes:

[0145] Step S701: In response to any memory cell in the memory array being in a write state, a write signal corresponding to any memory cell is applied to the second terminal of the second transistor of any memory cell, and a turn-on control signal is applied to the gate terminal of the second transistor of any memory cell; and

[0146] Step S702: In response to the output current of any memory cell in the write state satisfying a threshold condition, control stops applying the write signal corresponding to any memory cell to the second terminal of the second transistor in any memory cell, wherein the threshold condition is determined based on the value to be written of any memory cell.

[0147] Figure 13 shows a flowchart of a method 1300 for controlling a memory-based circuit (e.g., memory-based circuit 900 described with reference to Figure 9, memory-based circuit 1000 described with reference to Figure 10) according to an exemplary embodiment of the present disclosure. According to some embodiments, features and / or technical effects of the memory-based circuit and its components described above with reference to Figures 1-12 can be applied accordingly to method 1300, and are therefore omitted here. As shown in Figure 13, method 1300 includes:

[0148] Step S1301: In response to any memory cell in the memory array being in a write state, a write signal corresponding to any memory cell is applied to the second terminal of the second transistor of any memory cell, and a turn-on control signal is applied to the write word line connected to any memory cell.

[0149] Step S1302: In response to the output current of any memory cell in the write state satisfying a threshold condition, control stops applying the write signal corresponding to any memory cell to the second terminal of the second transistor in any memory cell, wherein the threshold condition is determined based on the value to be written to any memory cell; and

[0150] Step S1303: In response to the end of the write state of any memory cell in the memory array, a shutdown control signal is applied to the write word line connected to any memory cell.

[0151] According to some embodiments, each memory cell further includes a write control switch, one end of which is connected to a second terminal of a second transistor in the memory cell, and the other end of which receives a write signal corresponding to the memory cell. The control to stop applying the write signal corresponding to any memory cell to the second terminal of the second transistor in any memory cell in response to the output current of any memory cell in the write state satisfying a threshold condition includes: disconnecting the write control switch in any memory cell in response to the output current of any memory cell in the write state satisfying the threshold condition.

[0152] According to some embodiments, the method described in this disclosure further includes: closing a write control switch in any memory cell in response to the output current of any memory cell in a write state not meeting a threshold condition.

[0153] According to some embodiments, each write control circuit includes a first multiplexer, and the method as described in this disclosure further includes: for each first multiplexer, in response to any memory cell controlled by the write control circuit corresponding to the first multiplexer being in a write state, connecting the write control circuit corresponding to the first multiplexer to a first terminal of a first transistor in any memory cell in the write state to receive the output current of any memory cell in the write state.

[0154] According to some embodiments, each write control circuit includes a second multiplexer, and the method as described in this disclosure further includes: for each second multiplexer, in response to any memory cell controlled by the write control circuit corresponding to the second multiplexer being in a write state, connecting the write control circuit corresponding to the second multiplexer to any memory cell in the write state, so as to provide a stop write signal corresponding to any memory cell to any memory cell when the write control circuit corresponding to the second multiplexer generates a stop write signal corresponding to any memory cell.

[0155] According to some embodiments, each of the one or more write control circuits includes a switching circuit and a comparator circuit, and controlling the cessation of applying a write signal corresponding to any memory cell to the second terminal of the second transistor in any memory cell in response to the output current of any memory cell in a write state satisfying a threshold condition includes: receiving the output current of any memory cell via the switching circuit in the write control circuit corresponding to any memory cell, and converting the received output current of any memory cell into a detection voltage; and controlling the cessation of applying a write signal to the second terminal of the second transistor in any memory cell via the comparator circuit in the write control circuit corresponding to any memory cell in response to the detection voltage being greater than or equal to a threshold voltage, wherein the threshold voltage is determined based on the value to be written of any memory cell.

[0156] Figure 16 shows a flowchart of a method 1600 for controlling a memory-based circuit (e.g., memory-based circuit 1400 described with reference to Figure 14) according to an exemplary embodiment of the present disclosure. According to some embodiments, features and / or technical effects of the memory-based circuit and its components described above with reference to Figures 1-15 can be applied accordingly to method 1600, and are therefore omitted here. As shown in Figure 16, method 1600 includes:

[0157] Step S1601: In response to any memory cell in the memory array being in a write state, a write signal corresponding to any memory cell is applied to the write word line corresponding to any memory cell, and a turn-on control signal is applied to the gate terminal of the second transistor of any memory cell; and

[0158] Step S1602: In response to the output current of any memory cell in the write state satisfying a threshold condition, the write control switch in any memory cell is turned off, wherein the threshold condition is determined based on the value to be written in any memory cell.

[0159] According to some embodiments, the method described in this disclosure further includes: controlling a write control switch in any memory cell to close in response to the output current of any memory cell in the write state not meeting a threshold condition.

[0160] According to some embodiments, in each memory cell, the write control switch is a transistor, the gate terminal of the write control switch is connected to a write control circuit that controls the memory cell, and controlling the write control switch in any memory cell to turn off in response to the output current of any memory cell in the write state satisfying a threshold condition includes: generating a stop write signal corresponding to any memory cell in response to the output current of any memory cell in the write state satisfying the threshold condition; and applying the stop write signal corresponding to any memory cell to the gate terminal of the write control switch in any memory cell to control the write control switch in any memory cell to turn off.

[0161] According to some embodiments, each write control circuit includes a first multiplexer, and the method as described in this disclosure further includes: for each first multiplexer, in response to any memory cell controlled by the write control circuit corresponding to the first multiplexer being in the write state, connecting the write control circuit corresponding to the first multiplexer to a first terminal of a first transistor in any memory cell in the write state to receive the output current of any memory cell in the write state.

[0162] According to some embodiments, each write control circuit includes a second multiplexer, and the method as described in this disclosure further includes: for each second multiplexer, in response to any memory cell controlled by the write control circuit corresponding to the second multiplexer being in the write state, connecting the write control circuit corresponding to the second multiplexer to a write control switch in any memory cell in the write state.

[0163] According to some embodiments, each of the one or more write control circuits includes a conversion circuit and a comparison circuit, and controlling the write control switch in any memory cell to open in response to the output current of any memory cell in the write state satisfying a threshold condition includes: receiving the output current of any memory cell via the conversion circuit in the write control circuit corresponding to any memory cell, and converting the received output current of any memory cell into a detection voltage; and controlling the write control switch in any memory cell to open via the comparison circuit in the write control circuit corresponding to any memory cell in response to the detection voltage being greater than or equal to a threshold voltage, wherein the threshold voltage is determined based on the value to be written in any memory cell.

[0164] Figure 17 shows a schematic diagram of a storage device according to an exemplary embodiment of the present disclosure.

[0165] According to some embodiments, as shown in FIG17, the storage device 1700 includes a memory array 1710 and write control circuits 1721-172N. The memory array 1710 may include, for example, M×N memory cells. The write control circuits 172n are used to control one or more memory cells in the memory array 1710, where n∈[1,N]. A first memory cell may include any memory cell corresponding to the write control circuit 172n. A description of the memory cells may be given with reference to other figures and / or embodiments.

[0166] According to some embodiments, the first terminal of a first transistor in a memory cell in the same row of the memory array 1710 is connected, for example, via an input line to a row input terminal corresponding to that row, and the second terminal of a first transistor in a memory cell in the same column is connected, for example, via an output line to a column output terminal corresponding to that column; however, the embodiments are not limited thereto. According to some embodiments, the first terminal of a first transistor in a memory cell in the same row of the memory array 1710 is connected to a row output terminal corresponding to that row, and the second terminal of a first transistor in a memory cell in the same column is connected to a column input terminal corresponding to that column. According to some embodiments, the first terminal of a first transistor in a memory cell in the same column of the memory array 1710 is connected to a column input terminal corresponding to that column, and the second terminal of a first transistor in a memory cell in the same row is connected to a row output terminal corresponding to that row. According to some embodiments, the first terminal of a first transistor in a memory cell in the same column of the memory array 1710 is connected to a column output terminal corresponding to that column, and the second terminal of a first transistor in a memory cell in the same row is connected to a row input terminal corresponding to that row.

[0167] In the following description, the example is that the first terminal of the first transistor is connected to the row input terminal and the second terminal of the first transistor is connected to the column output terminal; or the case where the first terminal of the first transistor is connected to the row output terminal and the second terminal of the first transistor is connected to the column input terminal; or the case where the first terminal of the first transistor is connected to the column input terminal and the second terminal of the first transistor is connected to the row output terminal; or the case where the first terminal of the first transistor is connected to the column output terminal and the second terminal of the first transistor is connected to the row input terminal can be referred to the description where the first terminal of the first transistor is connected to the row input terminal and the second terminal of the first transistor is connected to the column output terminal.

[0168] According to some embodiments, write control circuit 172n is used to control one or more memory cells in a memory array. For example, as shown in FIG17, write control circuit 1721 is used to control multiple memory cells in a first column of a memory array.

[0169] According to some embodiments, a write control circuit 172n is used to control a first memory cell in a write state and is configured to control the stopping of programming operations on the first memory cell in response to the output current of the first memory cell meeting a threshold condition. According to some embodiments, the write control circuit 172n may include a write detection circuit configured to control the stopping of programming operations on the first memory cell in response to the output current of the first memory cell meeting a threshold condition. The first memory cell may be any one of a plurality of memory cells controlled by the write control circuit. The threshold condition may be determined based on the value to be written to the first memory cell. As shown in FIG17, the write control circuit 172n may control the second transistor of the first memory cell to stop current flow. For example, the write control circuit 172n may control the stopping of applying a write signal to the second terminal of the second transistor of the first memory cell, or stop applying an on signal to the gate terminal of the second transistor of the first memory cell, or stop applying an off signal to the gate terminal of the second transistor of the first memory cell.

[0170] Figure 18 shows a schematic diagram of another storage device according to an exemplary embodiment of the present disclosure.

[0171] According to some embodiments, as shown in FIG18, the storage device 1800 includes a memory array 1810 and write control circuits 1821-182N. The memory array 1810 may include, for example, M×N memory cells. The write control circuits 182n are used to control one or more memory cells in the memory array 1810, where n∈[1,N]. A first memory cell may include any memory cell corresponding to the write control circuit 182n. The description of the memory cells may be referred to in other figures and / or embodiments.

[0172] As shown in Figure 18, the gate terminal of the second transistor of a memory cell in the same row of the memory array 1810 is connected to a first control line corresponding to that row, such as WWL, and the second terminal of the second transistor of a memory cell in the same column is connected to a second control line corresponding to that column, such as WBL. The second control line is used to couple a write signal. The second control line can be connected to a switch (also referred to as a first write control switch) for turning the write signal on or off, such as a write control switch. The switch connected to the second control line can also be referred to as the memory cell corresponding to the second control line.

[0173] According to some embodiments, the memory cell may include a write control switch (also referred to as a first write control switch), which is used to turn on or off the connection between the second terminal of the second transistor of the memory cell and the corresponding second control line.

[0174] According to some embodiments, the write control circuit 182n may include a write detection circuit configured to generate a first stop write signal in response to a first memory cell being in a write state and the output current of the first memory cell satisfying the threshold condition. The first stop write signal is used to disconnect the first write control switch.

[0175] According to some embodiments, the write control circuit can be shared by multiple outputs of the memory array, such as multiple column outputs or multiple row outputs. The write control circuit can control one of the multiple outputs, thus avoiding confusion in write control. For example, at the same time, one of the memory cells corresponding to the multiple outputs can be in a write state. This reduces the number of write control circuits and lowers circuit overhead. For example, write control circuit 1821 can be shared by the column outputs of the first to fourth columns of the memory array 1810. This eliminates the need for write control circuits 1822, 1823, and 1824.

[0176] According to some embodiments, the write control circuitry, shared by multiple column outputs or multiple row outputs of the memory array, can be implemented using a multiplexer, such as a first multiplexer and / or a second multiplexer. A description of the multiplexer can be found in other embodiments, such as the one in Figure 4. For example, a first control line can control the conduction of a second transistor in a memory cell of a corresponding row, thereby allowing the memory cell in that row to be used for writing. The write control circuitry utilizes the multiplexer to select a memory cell from the memory cells of the corresponding row for write control.

[0177] According to some embodiments, the write control circuit being shared by multiple column outputs or multiple row outputs of the memory array can be achieved by providing multiple first control lines and / or multiple input lines for each row of memory cells. Memory cells sharing the write control circuit in a row are controlled by different first control lines and / or different input lines. For example, multiple outputs can be connected to each other and to the write control circuit, which can control the first write control switches corresponding to the multiple outputs. During writing, the second transistor of one memory cell (e.g., the first memory cell) sharing the write control circuit is turned on by the signal of the first control line, while the second transistors of other memory cells are turned off by the signal of the first control line; and / or, the first transistor of one memory cell (e.g., the first memory cell) sharing the write control circuit is controlled to output by the signal of the input line, while the first transistors of other memory cells are controlled not to output by the signal of the input line. In this way, the write control circuit can perform write control on, for example, the first memory cell while reducing the impact on other memory cells.

[0178] According to some embodiments, the write control circuitry being shared by multiple column outputs or multiple row outputs of the memory array can be implemented using a multiplexer and by providing multiple first control lines and / or multiple input lines for each row of memory cells. Related descriptions can be found in other embodiments, such as those shown in Figures 10 and 12.

[0179] Figure 19 shows a schematic diagram of yet another storage device according to an exemplary embodiment of the present disclosure.

[0180] According to some embodiments, as shown in FIG19, the storage device 1900 includes a memory array 1910 and write control circuits 1921-192N. The memory array 1910 may include, for example, M×N memory cells. The write control circuits 192n are used to control one or more memory cells in the memory array 1910, where n∈[1,N]. A first memory cell may include any memory cell corresponding to the write control circuit 192n. A description of the memory cells may be given with reference to other figures and / or embodiments.

[0181] According to some embodiments, the write control circuit 192n may include a write detection circuit configured to generate a second stop write signal in response to the first memory cell being in a write state and the output current of the first memory cell satisfying a threshold condition. The second stop write signal is used to control the shutdown of a second transistor of the first memory cell.

[0182] According to some embodiments, the second stop write signal may include a signal that turns off the second transistor. Write control circuitry 192n may be connected to the second transistor of the first memory cell, and the second stop write signal may be applied to the gate terminal of the second transistor of the first memory cell to turn off the second transistor of the first memory cell.

[0183] According to some embodiments, the storage device 1900 may further include drivers 1931 to 193N. A second stop write signal generated by the write detection circuit of the write control circuit 192n can be used to control the driver 193n to generate a third stop write signal. The third stop write signal can be applied to the gate terminal of the second transistor of the first memory cell through the third transistor to turn off the second transistor of the first memory cell.

[0184] According to some embodiments, the memory cells of the memory array 1910 further include a second write control switch, which is used to turn on or off the connection of an on signal to the gate terminal of a second transistor of the memory cell; or to control the connection of an on signal or an off signal to the gate terminal of a second transistor of the memory cell, wherein the off signal is used to turn off the second transistor of the first memory cell. For example, the off signal may include a third stop write signal.

[0185] According to some embodiments, the second write control switch may include a third transistor, the first terminal of which is connected to the gate terminal of the second transistor. The gate terminals of the third transistors in the same row or column are connected to each other, and the second terminals of the third transistors in the same column or row are connected to each other and connected to the write control circuit of the corresponding column or row, or connected to the write control circuit of the corresponding column or row via a driver of the corresponding column or row.

[0186] Figure 20 shows a schematic diagram of a control method according to an exemplary embodiment of the present disclosure.

[0187] Control methods 2000 include:

[0188] S2010, in response to the first memory cell being in a write state, a write signal corresponding to the first memory cell is applied to the second terminal of the second transistor of the first memory cell, and an on signal is applied to the gate terminal of the second transistor of the first memory cell.

[0189] S2020, in response to the output current of the first memory cell satisfying the threshold condition, the write control circuit controls to stop applying a write signal to the second terminal of the second transistor in the first memory cell or to stop applying a conduction signal to the second transistor in the first memory cell, wherein the threshold condition is determined based on the value to be written in the first memory cell.

[0190] The embodiments of the storage device and control method disclosed herein can be combined with any other embodiment.

[0191] Embodiments of this disclosure also provide a control device, as shown in FIG21. FIG21 illustrates a schematic diagram of a control device according to an exemplary embodiment of this disclosure. As shown in FIG21, the control device 2100 includes: at least one processing circuit 2110 and an interface circuit 2120, the interface circuit 2120 being used for signal connection with a storage device, and the at least one processing circuit 2110 being used for executing any of the control methods provided in the above embodiments.

[0192] Figure 8 shows a schematic diagram of a chip 800 according to an exemplary embodiment of the present disclosure. According to some embodiments, the chip 800 includes a memory computing circuit 801 or a storage device as described in the present disclosure.

[0193] The memory computing circuit and its control method described in this disclosure, as well as the chip, can be used in terminals such as computers, mobile phones, and tablet computers to perform related calculations. Other essential components of the memory computing circuit are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present invention.

[0194] By adjusting the voltage at the gate terminal of the first transistor in the memory cell, each memory cell is regarded as a variable equivalent analog weight, which is equivalent to analog matrix data. Furthermore, by applying analog voltage to the memory cell, matrix multiplication is achieved. The circuit structure is simple, the number of components is small, the response speed is fast, and the power consumption is low, which greatly reduces the overhead caused by analog-to-digital conversion, digital-to-analog conversion, and data transmission, and effectively improves the processing performance of the memory computing circuit.

[0195] Furthermore, the memory array provided by the present invention can be used as a dynamic random access memory (DRAM) when the memory array is in an idle state, thereby enabling the reuse of electrical components, improving component utilization efficiency, and saving hardware costs of integrated circuits.

[0196] The storage device provided by this invention integrates in-memory computing circuitry, enabling calculations to be performed directly within the storage device. This achieves in-memory computing integration, eliminating the need for data transfer between the memory and the processor, thereby improving processing performance and reducing power consumption and cost.

[0197] While embodiments or examples of this disclosure have been described with reference to the accompanying drawings, it should be understood that the methods, systems, and devices described above are merely exemplary embodiments or examples, and the scope of the invention is not limited by these embodiments or examples, but only by the granted claims and their equivalents. Various elements in the embodiments or examples may be omitted or replaced by their equivalents. Furthermore, the steps may be performed in a different order than that described in this disclosure. Further, various elements in the embodiments or examples may be combined in various ways. Importantly, as the technology evolves, many elements described herein can be replaced by equivalents that appear after this disclosure.

Claims

1. A storage apparatus, comprising: a first memory cell comprising a first transistor and a second transistor, a gate terminal of the first transistor being connected with a first terminal of the second transistor, wherein a second terminal of the first transistor is configured to receive an input voltage, the first memory cell being configured to output an output current of the first memory cell at a first terminal of the first transistor in response to an input of the input voltage, a gate terminal of the second transistor being configured to receive a pass signal, and a second terminal of the second transistor being configured to receive a write signal; and a write control circuit configured to control the first memory cell, and configured to control, in response to the first memory cell being in a write state and the output current of the first memory cell satisfying a threshold condition, stopping applying the write signal to the second terminal of the second transistor in the first memory cell or stopping applying the pass signal to the second transistor in the first memory cell, wherein the threshold condition is determined based on a value to be written into the first memory cell. 2.The storage apparatus of claim 1, wherein the first terminal of the first transistor is a source terminal and the second terminal of the first transistor is a drain terminal, or the first terminal of the first transistor is a drain terminal and the second terminal of the first transistor is a source terminal, and wherein the first terminal of the second transistor is a source terminal and the second terminal of the second transistor is a drain terminal, or the first terminal of the second transistor is a drain terminal and the second terminal of the second transistor is a source terminal. The first memory cell further comprises a first write control switch configured to turn on or turn off the connection of the write signal to the second terminal of the second transistor in the first memory cell.

3. The memory device of claim 1 or 2, wherein, The write control circuit comprises a write detection circuit configured to generate a first stop write signal for disconnecting the first write control switch in response to the first memory cell being in the write state and the output current of the first memory cell satisfying the threshold condition.

4. The memory device of claim 3, wherein, The write control circuit is configured to control a plurality of memory cells, the plurality of memory cells comprising the first memory cell, and gate terminals of the second transistors of the plurality of memory cells sharing a pass signal or independently receiving pass signals.

5. The memory device of claim 4, wherein, The gate terminals of the second transistors of the plurality of memory cells are connected to different write word lines through which the pass signals are independently received.

6. The memory device of claim 5, wherein, The write control circuit comprises a first multiplexer configured to select the connection of the first terminal of the first transistor of the first memory cell to the write detection circuit in response to the first memory cell being in the write state.

7. The memory device of claim 5 or 6, wherein, ​ 8. The memory device of claim 7, wherein, The write control circuit further includes a second multiplexer, wherein the second multiplexer is configured to select, in response to the first memory cell being in the write state, a connection of a write control switch of the first memory cell to the write detection circuit to provide the first stop write signal to the first memory cell when the write detection circuit generates the first stop write signal.

9. The memory device of any one of claims 5-8, wherein, The storage device includes a memory array, and the plurality of memory cells are located in a same row or a same column of the memory array.

10. The memory device of claim 9, wherein, In the memory array, a first terminal of the first transistor in a memory cell in a same row is connected to a row input terminal of the row, and a second terminal of the first transistor in a memory cell in a same column is connected to a column output terminal of the column; or In the memory array, a first terminal of the first transistor in a memory cell in a same column is connected to a column input terminal of the column, and a second terminal of the first transistor in a memory cell in a same row is connected to a row output terminal of the row.

11. The memory device of claim 1 or 2, wherein, The write control circuit includes a write detection circuit configured to generate, in response to the first memory cell being in a write state and an output current of the first memory cell satisfying the threshold condition, a second stop write signal for controlling to turn off a second transistor of the first memory cell.

12. The memory device of claim 11, wherein, The second stop write signal is for being applied to a gate terminal of the second transistor of the first memory cell and turning off the second transistor of the first memory cell.

13. The memory device of claim 11, wherein, The storage device further includes a driver, and the second stop write signal is for controlling the driver to generate a third stop write signal for being applied to the gate terminal of the second transistor of the first memory cell and turning off the second transistor of the first memory cell.

14. The memory device of any one of claims 11-13, wherein, The first memory cell further includes a second write control switch for connecting or disconnecting the pass signal to a gate terminal of the second transistor of the first memory cell; or The second write control switch is for connecting the pass signal or disconnecting the signal to the gate terminal of the second transistor of the first memory cell.

15. The memory device of any one of claims 11-14, wherein, The write control circuit is for controlling a plurality of memory cells including the first memory cell, and the write control circuit includes a first multiplexer, wherein the first multiplexer is configured to select, in response to the first memory cell being in the write state, a connection of a first terminal of the first transistor of the first memory cell to the write detection circuit.

16. The memory device of any one of claims 11-15, wherein, The write control circuit further includes a second multiplexer, wherein the second multiplexer is configured to select, in response to the first memory cell being in the write state, a connection of the write detection circuit to the first memory cell to provide the second stop write signal or a third stop write signal generated by a driver controlled by the second stop write signal to the first memory cell when the write detection circuit generates the second stop write signal.

17. The memory device of claim 15 or 16, wherein, The storage device includes a memory array, and the plurality of memory cells are located in a same row or a same column of the memory array.

18. The memory device of claim 17, wherein, In the memory array, a first terminal of the first transistor in the memory cell in the same row is connected to a row input terminal of the row, and a second terminal of the first transistor in the memory cell in the same column is connected to a column output terminal of the column; or In the memory array, a first terminal of the first transistor in the memory cell in the same column is connected to a column input terminal of the column, and a second terminal of the first transistor in the memory cell in the same row is connected to a row output terminal of the row.

19. The storage device of any one of claims 1-18, wherein, The write control circuit includes: a conversion circuit configured to, in response to the first memory cell being in a write state, receive an output current of the first memory cell, and convert the received output current of the first memory cell into a detection voltage; and a comparison circuit configured to, in response to the detection voltage being greater than or equal to a threshold voltage, control to stop applying a write signal to a second terminal of the second transistor in the first memory cell or stop applying a conduction signal to a gate terminal of the second transistor in the first memory cell, wherein the threshold voltage is determined based on a to-be-written value of the first memory cell.

20. The storage device of any one of claims 1-19, wherein, The storage device includes a memory array, and the write control circuit corresponds to memory cells in one or more columns of the memory array, or the write control circuit corresponds to memory cells in one or more rows of the memory array.

21. The storage device of any one of claims 1-20, wherein, The first memory cell further includes a storage capacitor, a first terminal of the storage capacitor is connected to a gate terminal of the first transistor of the first memory cell, and a second terminal of the storage capacitor is connected to a ground point, wherein the weight stored by the first memory cell is determined based on a charge stored by the storage capacitor in the first memory cell.

22. The memory device of any one of claims 1-20, wherein, In the first memory cell, there is a parasitic capacitor between the gate terminal of the first transistor and the ground point, and the weight stored by the first memory cell is determined based on a charge stored by the parasitic capacitor in the first memory cell.

23. The storage device of any one of claims 1-22, wherein, The first transistor is a silicon transistor, and the second transistor is an indium gallium zinc oxide transistor.

24. A control method, the control method comprising: in response to a first memory cell being in a write state, applying a write signal corresponding to the first memory cell to a second terminal of a second transistor of the first memory cell, and applying a conduction signal to a gate terminal of the second transistor of the first memory cell; and in response to an output current of the first memory cell satisfying a threshold condition, controlling a write control circuit to control to stop applying the write signal to the second terminal of the second transistor in the first memory cell or stop applying the conduction signal to the second transistor in the first memory cell, wherein the threshold condition is determined based on a to-be-written value of the first memory cell.

25. The control method of claim 24, further comprising: A write detection circuit controlling the write control circuit generates a first stop write signal for turning off a second transistor of the first memory cell in response to the first memory cell being in a write state and an output current of the first memory cell satisfying the threshold condition.

26. The control method according to claim 25, wherein The write control circuit is configured to control a plurality of memory cells including the first memory cell, Gate terminals of the second transistors of the plurality of memory cells share a pass signal, or gate terminals of the second transistors of the plurality of memory cells independently receive pass signals and are connected to different write word lines through which the pass signals are independently received.

27. The control method according to claim 25 or 26, further comprising: A first multiplexer controlling the write control circuit selects a connection of a first terminal of a first transistor of the first memory cell to the write detection circuit in response to the first memory cell being in the write state.

28. The control method of claim 27, further comprising: A second multiplexer controlling the write control circuit selects a connection of a write control switch of the first memory cell to the write detection circuit in response to the first memory cell being in the write state, so as to provide the first stop write signal to the first memory cell when the write detection circuit generates the first stop write signal.

29. The control method according to any one of claims 26 to 28, wherein, The storage device includes a memory array in which the plurality of memory cells are located in a same row or a same column.

30. The control method according to claim 29, wherein In the memory array, first terminals of the first transistors in the memory cells in a same row are connected to a row input terminal of the row, and second terminals of the first transistors in the memory cells in a same column are connected to a column output terminal of the column; or In the memory array, first terminals of the first transistors in the memory cells in a same column are connected to a column input terminal of the column, and second terminals of the first transistors in the memory cells in a same row are connected to a row output terminal of the row.

31. The control method of claim 24, further comprising: A write detection circuit controlling the write control circuit generates a second stop write signal for controlling turning off the second transistor of the first memory cell in response to the first memory cell being in a write state and an output current of the first memory cell satisfying the threshold condition.

32. The control method according to claim 31, wherein The second stop write signal is for being applied to a gate terminal of the second transistor of the first memory cell and turning off the second transistor of the first memory cell.

33. The control method according to claim 31, wherein The storage device further includes a driver, and the second stop write signal is for controlling the driver to generate a third stop write signal for being applied to the gate terminal of the second transistor of the first memory cell and turning off the second transistor of the first memory cell.

34. The control method according to any one of claims 31 to 33, wherein, The first memory cell further comprises a second write control switch for turning on or off the connection of the pass signal to a gate terminal of the second transistor of the first memory cell; or The second write control switch is for turning on the pass signal or turning off the signal to the gate terminal of the second transistor of the first memory cell.

35. The control method according to any one of claims 31 to 34, wherein, The write control circuit is for controlling a plurality of memory cells, the plurality of memory cells comprising the first memory cell, and the control method further comprises: controlling a first multiplexer of the write control circuit to select the connection of the first terminal of the first transistor of the first memory cell to the write detection circuit in response to the first memory cell being in the write state.

36. The control method according to any one of claims 31 to 35, further comprising: controlling a second multiplexer of the write control circuit to select the connection of the write detection circuit and the first memory cell in response to the first memory cell being in the write state, so as to provide the second stop write signal or a third stop write signal generated by a second stop write signal control driver to the first memory cell when the write detection circuit generates the second stop write signal.

37. The control method according to claim 35 or 36, wherein The storage device comprises a memory array, and the plurality of memory cells are located in a same row or a same column of the memory array.

38. The control method according to claim 37, wherein In the memory array, the first terminal of the first transistor in the memory cell in the same row is connected to a row input terminal of the row, and the second terminal of the first transistor in the memory cell in the same column is connected to a column output terminal of the column; or In the memory array, the first terminal of the first transistor in the memory cell in the same column is connected to a column input terminal of the column, and the second terminal of the first transistor in the memory cell in the same row is connected to a row output terminal of the row.

39. The control method according to any one of claims 24-38, further comprising: controlling a conversion circuit of the write control circuit to receive the output current of the first memory cell in response to the first memory cell being in the write state, and convert the received output current of the first memory cell into a detection voltage; and controlling a comparison circuit of the write control circuit to control stopping applying the write signal to the second terminal of the second transistor in the first memory cell or stopping applying the pass signal to the gate terminal of the second transistor in the first memory cell in response to the detection voltage being greater than or equal to a threshold voltage, wherein the threshold voltage is determined based on a to-be-written value of the first memory cell.

40. The control method according to any one of claims 24-39, wherein, The storage device comprises a memory array, and the write control circuit corresponds to memory cells in one or more columns of the memory array, or the write control circuit corresponds to memory cells in one or more rows of the memory array.

41. A control device, comprising: an interface circuit for signal connection with a storage device; and at least one processing circuit for performing the control method according to any one of claims 24-40.

42. A chip comprising the storage device according to any one of claims 1-20 and / or the control device according to claim 41.

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