Semiconductor structure

Abstract

According to the invention, a semiconductor structure (1) comprises : - a substrate (2) comprising -a first surface (4), -a second surface (6), opposite to the first surface (4), - at least one through-substrate via (8) in a cavity (10) in the first surface (4), the cavity (10) being defined by the first surface (4), two lateral surfaces (10a) and a bottom surface (10b), wherein the through-substrate via (8) lines the cavity (10), and - a plug (12) for partly plugging the through-substrate via (8), wherein the plug (12) has two lateral surfaces (12a), which contact the lateral surfaces (8a) of the at least one through-substrate via (8), and wherein the plug (12) is separating the at least one through-substrate via (8) in two zones (14a, 14b), wherein one zone (14a) is plugged by the plug (12) and an other zone (14b) is devoid of the plug (12). Furthermore, a corresponding method for manufacturing a semiconductor structure is disclosed.

Description

[0001] SEMICONDUCTOR STRUCTURE

[0002] DESCRIPTION

[0003] TECHNICAL FIELD

[0004] The present invention relates to a semiconductor structure and a method for manufacturing the same .

[0005] BACKGROUND o ■© o ■©

[0006] Through-substrate vias , often abbreviated as TSVs , are vertical electrical connections that pass entirely through e . g . a silicon wafer or die . With this , stacking circuits can be build on top of each other in 3D for a broad range of applications and performance improvements .

[0007] By allowing connections to pass through the substrate , rather than j ust on the surface , through-substrate vias enable a more increased bandwith, reduced signal delay, improved power management , and smaller form- factors .

[0008] Through-substrate vias can be protected during manufacturing and afterwards using various methods and materials . This is needed to e . g . protect the through-substrate via from filling with compression mold, as this could cause damage to the through-substrate vias - i . e . cracks at the through-substrate via membrane and could cause therefore reliability issues .

[0009] Further the through-substrate via protection is needed to safeguard the through-substrate via from process chemistry and cross contamination as residuals could remain in the open through-substrate vias . One such method is covering a through-substrate via with a thin membrane , metaphorically referred to as a "tent" and involves the application of a protective layer over the through-substrate via . The "tent" or thin membrane serves as a protective layer, safeguarding the through-substrate via from environmental factors and potential damage during the manufacturing process and afterwards .

[0010] Yet , it has some disadvantages . The application of the "tent" can be a complex and delicate process that requires precise control to ensure the protective layer is evenly applied over the through-substrate via . This can be time-consuming and require speciali zed equipment and can damage the through- substrate via and its sidewalls .

[0011] The materials used for the "tent" can be expensive , potentially increasing the overall cost of manufacturing the through-substrate vias .

[0012] Despite its protective role , the "tent" may not provide complete protection against all environmental factors or potential damage during the manufacturing process . For example , it may not fully prevent moisture ingress or protect against physical damage during subsequent processing steps .

[0013] Furthermore , the "tenting" process may not be suitable for all types of through-substrate vias or semiconductor devices , limiting its applicability . The speci fic materials and methods used for the protective layer can vary based on the requirements of the speci fic semiconductor device , adding another layer of complexity to the process .

[0014] The tenting solution can also not withstand higher pressures , which is a maj or drawback . SUMMARY

[0015] The obj ect of the present invention is therefore to provide a semiconductor structure and a method to manufacture the same , which solve the above addressed problems and present a solution which is more robust , can withstand higher pressures and does not damage the through-substrate via and its sidewalls .

[0016] According to the invention, the obj ect is met by a device speci fied in claim 1 and by a method with the steps speci fied in claim 11 .

[0017] Therefore , a semiconductor structure is proposed by the invention, comprising :

[0018] - a substrate comprising

[0019] - a first surface ( 4 ) , - a second surface , opposite to the first surface

[0020] ( 4 ) ,

[0021] - at least one through-substrate via in a cavity in the first surface ( 4 ) , the cavity being defined by the first surface ( 4 ) , two lateral surfaces and a bottom surface , wherein the through-substrate via lines the cavity, and

[0022] - a plug for partly plugging the through-substrate via, wherein the plug has two lateral surfaces , which contact the lateral surfaces of the at least one through-substrate via, and wherein the plug is separating the at least one through-substrate via in two zones , wherein one zone is plugged by the plug and an other zone is devoid of the plug .

[0023] A plugged through-substrate via is more robust than a tented one . The achievable thickness of the plug is higher than that of a simple tent . The height of the tent is limited by various processes , including solder ball dimensions and the general dimensions of the package . Plugged vias can also resist higher pressures .

[0024] Moreover, the remaining empty space reduces the ef fective path length for signals . As a result , signal propagation through the through-substrate via becomes faster, minimi zing delay .

[0025] Furthermore , the gap between the plug and the through- substrate via bottom surface reduces the capacitance between the plug and the surrounding silicon substrate . Lower capacitance means less energy is required to charge or discharge the through-substrate via during signal transitions , improving overall power ef ficiency .

[0026] The empty space below the plug acts as thermal insulation . Heat generated by active components in the semiconductor structure is less likely to trans fer through the through- substrate via, helping manage temperature and preventing locali zed hotspots .

[0027] Also , i f the plug were to touch the through-substrate via bottom surface , it could potentially cause a short circuit . By leaving a gap, the risk of unintended electrical connections is minimi zed .

[0028] Through-substrate via plugging is further implemented for the safeguarding of through-substrate vias . This involves the encapsulation and shielding of through-substrate vias to prevent any potential harm during the processing sequence . This is because the filling could lead to damage in the through-substrate vias due to discrepancies in the Coef ficient of Thermal Expansion ( CTE ) .

[0029] Also , the formed plug is more robust compared to the e . g . a tent for protecting the through-substrate via . Thereby, a sturdy protective layer is established .

[0030] The through-substrate via may furthermore be a through-silicon via . In an embodiment of the invention, the other zone , which is devoid of the plug, may be bordered by the bottom surface of the through-substrate via .

[0031] The absence of a plug in the other zone ensures that there is no electrical connection between the through-substrate via and the surrounding material .

[0032] Also , without a plug, heat generated within the through- substrate via can dissipate more ef fectively through the bottom surface . This helps maintain optimal operating temperatures and prevents overheating .

[0033] Furthermore , the absence of a plug reduces stress concentration points within the through-substrate via structure . Stress concentration can lead to mechanical failure or reliability issues .

[0034] In a further embodiment of the invention the proportion of the other zone , which is devoid of the plug, may be at least 10% of the total volume of the through-substrate via .

[0035] The advantages named above can be ensured when having a predetermined proportion of the zones i f the zone devoid of the plug has a certain volume compared to the overall volume of the through-substrate via, in order to guarantee that the zone is big enough - and therefore has enough volume - to be able to ful fill these .

[0036] In an even further embodiment of the invention, the other zone of the at least one through-substrate via may be filled with gas .

[0037] By incorporating a cavity filled with gas at the through- substrate via' s bottom, tension in the through-substrate via membrane is ef fectively reduced . This design choice prevents structural strain and ensures the through-substrate via remains intact during operation . The gas-filled cavity acts as a buffer, absorbing mechanical stress and shocks, enhancing the through-substrate via's reliability, especially in dynamic environments or temperature variations. It also redistributes forces, contributing to the through-substrate via's long-term stability.

[0038] Furthermore, the gas may be air.

[0039] Using air as the gas in the other zone of the through- substrate via offers several advantages. Air acts as an insulator, reducing heat transfer between the plug and the through-substrate via floor. This helps manage temperature and prevents localized hotspots. Additionally, using air is environmentally safe, and it doesn't require specialized handling or containment methods.

[0040] In a further embodiment of the invention, the pressure in the other zone of the at least one through-substrate via may be lower than atmospheric pressure.

[0041] Lower pressure within the through-substrate via reduces mechanical stress, which in turn improves the overall reliability of the semiconductor structure during thermal cycling or strain. Additionally, the gap between the plug and the floor shortens the signal path, minimizing delay for highspeed communication between different layers of the semiconductor device. Less contact area between the plug and the substrate also reduces capacitance, enhancing power efficiency during signal transitions.

[0042] Moreover, the plug may extend at least partly over the first surface .

[0043] A semiconductor structure, where the plug partially or fully overlaps the first surface, offers multiple benefits. This design enhances the control over the device's electrical characteristics. The extended plug aids in establishing a more consistent electric field throughout the semiconductor structure , thereby boosting the device ' s performance .

[0044] Furthermore , the extended plug lends additional structural reinforcement to the semiconductor structure , thereby enhancing its mechanical robustness . This feature proves especially advantageous in scenarios where the device is exposed to physical strain or elevated temperatures .

[0045] Partly overlapping can mean in this context e . g . that the plug overlaps partly the first surface adj oining the through- substrate via and forming a rim on that .

[0046] In another embodiment of the invention, the plug may comprise a polymer and / or an epoxide and / or a polyimide and / or a lactate and / or a siloxane .

[0047] All of polymers and / or epoxides and / or polyimides and / or lactates and / or siloxanes are known for their good electrical insulation properties , which can help to prevent unwanted current leakages .

[0048] Furthermore , all those materials have good thermal stability, which means they can withstand high temperatures without degrading and are generally lightweight and flexible , which can contribute to the mechanical stability of the device without adding unnecessary weight .

[0049] Lastly, polymers , epoxides , polyimides , lactates , and siloxanes are often used in the miniaturi zation of semiconductor structures due to their ability to form thin, uni form layers . This can enable the production of smaller, more compact devices that are suitable for integration into various electronic systems .

[0050] Furthermore , the plug may be at least partly patterned .

[0051] A patterned plug in a semiconductor device provides numerous advantages . One of these is the ability to manipulate the device ' s electrical characteristics more accurately . By tailoring the design of the patterns , the electric field distribution within the device can be optimi zed, which in turn enhances its performance .

[0052] Another advantage is the enhancement of the semiconductor structure ' s mechanical resilience through the process of patterning . By strategically designing the patterns , they can provide additional structural reinforcement , which increases the device ' s resistance to physical stress .

[0053] The plug might be patterned on its top .

[0054] Moreover, the invention proposes a semiconductor chip with a semiconductor structure as disclosed .

[0055] Moreover, the invention proposes a method for manufacturing a semiconductor structure comprising the steps of :

[0056] - providing a substrate comprising a first surface and a second surface , opposite to the first surface , with at least one through-substrate via in a cavity in the first surface , wherein the cavity is defined by the first surface , two lateral surfaces and a bottom surface , and wherein the through-substrate via lines the cavity, and

[0057] - providing a plug for partly plugging the through- substrate via, which has two lateral surfaces ,

[0058] - bringing the two lateral surfaces of the plug into contact with the lateral surfaces of the at least one through-substrate via, thus separating the at least one through-substrate via in two zones , wherein one zone is plugged by the plug and an other zone is devoid of the plug .

[0059] What has been said with respect to the device may analogously be applied to the method and therefore need not be repeated there . Method embodiments and details have a counterpart in the device and vice versa .

[0060] It shall be noted that the steps given above do not necessarily have to be carried out in the given order . The provided steps may be carried out in any other suitable order or even some or all of them at the same time .

[0061] In an embodiment of the invention, the plug may be provided and brought into contact with the lateral surfaces of the at least one through-substrate via by dry film vacuum lamination .

[0062] With dry film vacuum lamination, the vacuum environment ensures precise control over the material deposition and reduces contamination from air molecules .

[0063] Furthermore , dry vacuum lamination prevents water vapor back- streaming, which helps maintain the purity of specialty steels and reduces the risk of contamination .

[0064] Furthermore , dry vacuum lamination is more energy-ef ficient and produces less waste compared to traditional wet processes .

[0065] In an alternative embodiment of the invention, the plug may be provided and brought into contact with the lateral surfaces of the at least one through-substrate via by vacuum assisted spin coating .

[0066] Spin coating is a method, which reduces material waste by ef ficiently covering the substrate . It enhances adhesion between the film and the substrate , leading to better film quality and stability . With this , the film thickness can also be precisely controlled by adj usting spin speed and vacuum pressure .

[0067] In a further alternative embodiment of the invention, the plug may be provided and brought into contact with the lateral surfaces of the at least one through-substrate via by dry screen printing . Dry screen printing ensures a reliable seal that protects the delicate internal structures by precisely depositing materials .

[0068] It furthermore creates precise electrical pathways through the substrate . These pathways allow electrical signals to pass between di f ferent layers or components within the semiconductor device .

[0069] In an even further alternative embodiment of the invention, the plug may be provided and brought into contact with the lateral surfaces of the at least one through-substrate via by curtain coating .

[0070] With curtain coating thin liquid layers can be applied even on irregular surfaces and it operates at very high speeds , making it ef ficient for large-scale production .

[0071] BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In the following, the invention will be described in further detail with reference to the accompanying drawings , wherein :

[0073] FIG . 1 depicts an embodiment of the semiconductor structure in a sectional view, and

[0074] FIG . 2 depicts a detail of a through-substrate via, and

[0075] FIG . 3a depicts the semiconductor structure in a sectional view with the plugs overlapping a surface of the substrate , and

[0076] FIG . 3b depicts the semiconductor structure in a sectional view with the plugs covering a surface of the substrate .

[0077] Identical parts are labelled by the same reference signs . DETAILED DESCRIPTION

[0078] In FIG. 1 an embodiment of the present invention is shown. In this embodiment, a semiconductor structure is depicted generally with the reference sign 1.

[0079] This semiconductor structure 1 comprises a substrate 2 having a first surface 4 and a second surface 6.

[0080] The substrate 2 can be composed of various materials depending on the specific application and requirements. The substrate 2 can e.g. be made of a semiconductor material like silicon (Si) , germanium (Ge) , or gallium arsenide (GaAs) . Silicon is the most commonly used material due to its semiconductor properties and abundance. However, other materials like gallium arsenide are used for specialized applications where higher electron mobility or direct bandgap are required.

[0081] In some cases, the substrate 2 may be composed of a compound semiconductor material or a silicon-on-insulator (SOI) structure for specific device applications.

[0082] Furthermore, the substrate 2 comprises at least one through- substrate via 8, which is arranged in the first surface 4.

[0083] The through-substrate via 8 is a vertical electrical connection that passes through the substrate 2. The use of through-substrate vias allows for three-dimensional integration of components, thereby reducing the footprint of the device and improving performance by shortening the interconnect lengths.

[0084] This through-substrate via 8 is arranged in a cavity 10 in the first surface 4. The cavity 10 is defined by the first surface 4, two lateral surfaces 10a and a bottom surface 10b. The through-substrate via 8 lines the cavity 10 and is thus defined by two lateral surfaces 8a and a bottom surface 8b as well .

[0085] Moreover, the semiconductor structure 1 comprises a plug 12 , which is partly plugging the through-substrate via 8 . The plug 12 has two lateral surfaces 12a, which contact the lateral surfaces 8a of the at least one through-substrate via 8 , and a bottom surface 12b, which is positioned with a distance from the bottom surface of the through-substrate via 8 .

[0086] Thus , the plug 12 separates the at least one through-substrate via 8 in two zones 14a and 14b, wherein one zone 14a is filled with the plug and the other zone 14b is devoid of the plug .

[0087] In the context of a given, like a certain pressure to be applied on the through-substrate via 8 , the proportion between the two distinct zones 14a, 14b might be predetermined or established in advance . By defining this proportion ahead of time , a desired outcome can be achieved . This proportion can e . g . be that the other zone 14b is 10% of the overall volume of the through-substrate via 8 and the zone 14a is 90% .

[0088] The other zone 14b might be filled with gas , wherein the gas could be air or any other suitable gas .

[0089] Furthermore , the pressure within the other zone 14b of this through-substrate via 8 might be maintained below atmospheric pressure . This pressure can prevent damage to the through- substrate via membrane 22 and edge due to di f ferences in coef ficient of thermal expansion ( GTE ) . By controlling the pressure di f ferential , the performance and reliability of the semiconductor structure 1 can be optimi zed .

[0090] The through-substrate via 8 is shown in more detail in FIG . 2 .

[0091] The via of the through-substrate via 8 is formed by the cavity 10 that is etched through the e . g . silicon wafer or die 2 and the plug 12 material . Furthermore , there are several layers , e . g . three layers in this embodiment :

[0092] A passivation layer 16 , which is a protective coating, is applied on the first surface 4 , the two lateral surfaces 10a and the bottom surface 10b of the cavity 10 . It can be made of silicon nitride or silicon dioxide .

[0093] The second layer is a conducting layer 18 of conductive material , usually metal , that is deposited over the passivation layer 16 . It provides a surface for connecting the through-substrate via 8 to other components .

[0094] A further passivation layer 20 is applied over the conducting layer 18 for additional protection . This layer 20 isolates the plug 12 from the surrounding to prevent electrical leakage and corrosion .

[0095] On the second surface 6 , a through-substrate via membrane 22 is applied at the bottom of the through-substrate via 8 on the passivation layer 16 . The through-substrate via membrane 22 separating the through-substrate via 8 from Complementary Metal-Oxide-Semiconductor ( CMOS ) devices .

[0096] Moreover, the plug 12 might be made of and / or might comprise a polymer and / or an epoxide and / or a polyimide and / or a lactate and / or a siloxane .

[0097] All of polymers and / or epoxides and / or polyimides and / or lactates and / or siloxanes are known for their good electrical insulation properties , which can help to prevent unwanted current leakages .

[0098] Furthermore , all of those materials have good thermal stability, which means they can withstand high temperatures without degrading and are generally lightweight and flexible , which can contribute to the mechanical stability of the device without adding unnecessary weight . Lastly, polymers, epoxides, polyimides, lactates, and siloxanes are often used in the miniaturization of semiconductor structures due to their ability to form thin, uniform layers. This can enable the production of smaller, more compact devices that are suitable for integration into various electronic systems.

[0099] The plug 12 should have sufficient thickness to withstand the intended pressure, but it should not completely fill the through-substrate via 8. To prevent tension at the through- substrate via membrane 22 on the bottom 8b of the through- substrate via 8, a empty zone 14b must be formed. This is to avoid damage, such as cracks, to the through-substrate via membrane 22 and the through-substrate via edge due to differences in coefficient of thermal expansion (GTE) .

[0100] This plug 12 might extend partly, as it can be seen in FIG. 3a or completely, as it can be seen in FIG. 3b, over the first surface 4, which might have functional implications, such as connecting different layers or enhancing performance and performance implications, which may enhance electrical conductivity, optimize charge transport, or improve thermal dissipation .

[0101] The through-substrate via 8 can be a through-silicon via. The use of a through-silicon via allows for vertical interconnections between different layers of silicon of the semiconductor structure 1. This can significantly enhance the device's performance by reducing the length of interconnections, thereby minimizing signal delay and power consumption .

[0102] The plug 12 might be at least partly patterned, which gives it the advantage to manipulate the device's electrical characteristics more accurately. By tailoring the design of the patterns, the electric field distribution within the device can be optimized, which in turn enhances its performance . Furthermore , the semiconductor structure 1 can be a part of a semiconductor chip .

[0103] Lastly, to manufacture a semiconductor structure 1 , the following steps should be performed :

[0104] A substrate 2 that has two surfaces , a first surface 4 and a second surface 6 , is provided . On the first surface 4 , there is at least one through-via substrate 8 . This through- substrate via 8 is defined by two lateral surfaces 8a and a bottom surface 8b .

[0105] Next , a plug 12 designed to partially fill the through- substrate via 8 is provided and brought into contact with the lateral surfaces 8a of the at least one through-substrate via 8 . The plug 12 itsel f has two lateral surfaces 12a . Its purpose is to separate the through-substrate via 8 into distinct zones 14a, 14b . Furthermore , the lateral surfaces 12a of the plug 12 are aligned with the lateral surfaces 8a of the through-substrate via 8 .

[0106] As a result of this arrangement , one zone 14a of the through- substrate via 8 is plugged by the inserted plug 12 . The other zone 14b remains free from the plug 12 .

[0107] To provide and bring said plug 12 into contact with the lateral surfaces 8a of the through-substrate via 8 , there are several methods :

[0108] With vacuum-assisted spin coating a uni form polymer liner coverage is ensured . The process involves applying a polymer solution ( such as polyimide ) onto the respective surface , here the lateral surfaces 8a and the first surface 4 . The substrate 2 is then spun to spread the polymer evenly . Finally, patterning the plug 12 and curing is a last step .

[0109] Dry film lamination involves using a photosensitive dry film dielectric . The dry film is applied to the respective surface , here the lateral surfaces 8a and the first surface 4 . Vacuum lamination or a roll laminator applies pressure and heat , ensuring material flow into the through-substrate via 8 .

[0110] In dry screen printing, a conductive paste or dielectric material is deposited into the through-substrate via 8 . A screen with a pattern matching the through-substrate via 8 layout guides the material deposition . After drying and curing, a plug 12 is formed within the through-substrate via 8 .

[0111] Curtain coating is a liquid deposition technique . A liquid (polymer, dielectric, or conductive material ) is dispensed from a moving curtain onto the respective surface , here the lateral surfaces 8a and the first surface 4 . The curtain ensures uni form material distribution, resulting in a plug 12 within the through-substrate via 8 .

[0112] List of abbreviations : LIST OF REFERENCE SIGNS

[0113] Semiconductor structure 1

[0114] Substrate 2

[0115] First surface 4

[0116] Second surface 6

[0117] Through-substrate via / through-silicon via 8

[0118] Lateral surface 8a

[0119] Bottom surface 8b

[0120] Cavity 10

[0121] Lateral surface 10a

[0122] Bottom surface 10b

[0123] Plug 12

[0124] Lateral surface 12a

[0125] Zone 14a

[0126] Zone 14b

[0127] Passivation layer 16

[0128] Conducting layer 18

[0129] Passivation layer 20

[0130] Through-substrate via membrane 22

Claims

CLAIMS1. A semiconductor structure (1) , comprising- a substrate (2) comprising-a first surface (4) , -a second surface (6) , opposite to the first surface ( 4 ) ,- at least one through-substrate via (8) in a cavity (10) in the first surface (4) , the cavity (10) being defined by the first surface (4) , two lateral surfaces (10a) and a bottom surface (10b) , wherein the through-substrate via (8) lines the cavity (10) , and- a plug (12) for partly plugging the through-substrate via ( 8 ) , wherein the plug (12) has two lateral surfaces 12a, which contact the lateral surfaces (8a) of the at least one through-substrate via (8) , and wherein the plug (12) is separating the at least one through-substrate via (8) in two zones (14a, 14b) , wherein one zone (14a) is plugged by the plug (12) and an other zone (14b) is devoid of the plug (12) .

2. A semiconductor structure (1) according to claim 1, wherein the other zone (14b) , which is devoid of the plug (12) , is bordered by a bottom surface (8b) of the through- substrate via (8) .

3. A semiconductor structure (1) according to claim 1 or 2, wherein the proportion of the other zone (14b) , which is devoid of the plug (12) , is at least 10% of the total volume of the through-substrate via (8) .

4. A semiconductor structure (1) according to any one of the preceding claims, wherein the other zone (14b) of the at least one through-substrate via (8) is filled with gas.

5. A semiconductor structure (1) according to claim 4, wherein the gas is air.

6. A semiconductor structure (1) according any one of the preceding claims, wherein the pressure in the other zone (14b) of the at least one through-substrate via (8) is lower than atmospheric pressure.

7. A semiconductor structure (1) according to any one of the preceding claims, wherein the plug (12) extends at least partly over the first surface (4) .

8. A semiconductor structure (1) according to any one of the preceding claims, wherein the plug (12) comprises a polymer and / or an epoxide and / or a polyimide and / or a lactate and / or a siloxane.

9. A semiconductor structure (1) according to any one of the preceding claims, wherein the plug (12) is at least partly patterned .

10. Semiconductor chip with a semiconductor structure (1) according to any one of claims 1 to 9.

11. A method for manufacturing a semiconductor structure (1) according to any one of claims 1 to 9, comprising the steps of :- providing a substrate (2) comprising a first surface (4) and a second surface (6) , opposite to the first surface (4) , with at least one through-substrate via (8) in a cavity (10) in the first surface (4) , wherein the cavity (10) is defined by the first surface (4) , two lateral surfaces (10a) and a bottom surface (10b) , and wherein the through-substrate via (8) lines the cavity (10) , and- providing a plug (12) for partly plugging the through- substrate via (8) , which has two lateral surfaces(8a) ,- bringing the two lateral surfaces (12a) of the plug (12) into contact with the lateral surfaces (8a) of the at least one through-substrate via (8) , thus separating the at least one through-substrate via (8) in two zones (14a, 14b) , wherein one zone (14a) is plugged by the plug (12) and an other zone (14b) is devoid of the plug (12) .

12. A method for manufacturing a semiconductor structure (1) according to claim 11, wherein the plug (12) is provided and brought into contact with the lateral surfaces (8a) of the at least one through-substrate via (8) by dry film vacuum lamination.

13. A method for manufacturing a semiconductor structure (1) according to claim 11, wherein the plug (12) is provided and brought into contact with the lateral surfaces (8a) of the at least one through-substrate via (8) by vacuum assisted spin coating.

14. A method for manufacturing a semiconductor structure (1) according to claim 11, wherein the plug (12) is provided and brought into contact with the lateral surfaces (8a) of the at least one through-substrate via (8) by dry screen printing .

15. A method for manufacturing a semiconductor structure (1) according to claim 11, wherein the plug (12) is provided and brought into contact with the lateral surfaces (8a) of the at least one through-substrate via (8) by curtain coating .

Images