Planar photonic integrated circuit with single photon photodetector and method for the realization of an planar photonic integrated circuit

Abstract

A planar photonic integrated circuit (100), comprising: a layer (10) of a semiconductor material having along its longitudinal development (X) an inert portion (10a) and a contiguous sensitive portion (10b) on which at least one solid-state photodetector (11 ) is defined; a waveguide (60) having a first section (60a, 60b) defined above the inert portion (10a) and a contiguous second section (60c) defined above the sensitive portion (10b), the waveguide (60) being configured to convey photons from the first section (60a, 60b) to the second section (60c) towards the sensitive portion (10b). This circuit (100) comprises a first containment layer (30) interposed between the first section (60a, 60b) and the inert portion (10a); the first containment layer (30) is configured to prevent the crossing of photons towards the layer (10).

Description

[0001] PLANAR PHOTONIC INTEGRATED CIRCUIT WITH SINGLE PHOTON PHOTODETECTOR AND METHOD FOR THE REALIZATION OF AN PLANAR PHOTONIC INTEGRATED CIRCUIT.

[0002] DESCRIPTION

[0003] The invention concerns a planar photonic integrated circuit.

[0004] Furthermore, the present invention also concerns a method for the realization of a planar photonic integrated circuit.

[0005] Photonic circuits are known today that comprise:

[0006] - a layer of semiconductor material having along its longitudinal development an inert portion and a contiguous sensitive portion on which at least one photodetector is defined;

[0007] - a waveguide having a first section defined above said inert portion and a contiguous second section defined above said sensitive portion, wherein this waveguide is configured to convey photons from the first section to the second section towards said sensitive portion.

[0008] Such a circuit, although well known and appreciated, has an important limit.

[0009] In particular, with this circuit of the known art, it is necessary to place the photodetector at a temperature much lower than the ambient temperature, in order to minimize the energy dispersions of the photons in the passage between the waveguide and the aforesaid photodetector.

[0010] The task of the present invention is to develop a planar photonic integrated circuit capable of obviating the aforesaid drawbacks and limitations of the prior art.

[0011] In particular, it is an object of the invention to develop a planar photonic integrated circuit where the photodetector can operate at ambient temperature obtaining lower energy dispersions of the photons in the passage between the waveguide and the aforesaid photodetector compared to a similar circuit of known type.

[0012] The above task and purposes are achieved by a planar photonic integrated circuit according to claim 1 .

[0013] Further characteristics of the planar photonic integrated circuit according to claim 1 are described in the dependent claims.

[0014] The aforesaid task and objects, together with the advantages that will be mentioned hereinafter, are highlighted by the description of an embodiment of the invention, which is given by way of non-limiting example with reference to the attached drawings, where:

[0015] - figure 1 a represents a first step of a method for the realization of a planar photonic integrated circuit according to the invention;

[0016] - figure 1 b represents a second step of this method;

[0017] - figure 1 c represents a third step of this method;

[0018] - figure 1 d represents a fourth step of this method;

[0019] - figure 1 e represents a fifth step of this method;

[0020] - figure 1f represents a sixth step of this method;

[0021] - figure 1 g represents a seventh step of this method;

[0022] - figure 1 h represents an eighth step of this method;

[0023] - figure 1 i represents a ninth step of this method;

[0024] - figure 11 represents a tenth step of this method;

[0025] - figure 1 m represents an eleventh step of this method;

[0026] - figure 1 n represents a planar photonic integrated circuit made according to the aforesaid method.

[0027] With reference to the cited figures, a planar photonic integrated circuit according to the invention is indicated as a whole with the number 100 and is schematically represented in figures 1 m and 1 n.

[0028] This circuit 100 comprises:

[0029] - a layer 10 of a semiconductor material, preferably silicon, clearly visible in each of the aforesaid figures, which has along its longitudinal development X an inert portion 10a and a contiguous sensitive portion 10b in which at least one solid-state photodetector 11 is defined, as schematically represented in figure 1 a;

[0030] - a waveguide 60, clearly visible in figures 11, 1 m and 1 n, which has a first section 60a and 60b defined above the inert portion 10a and a contiguous second section 60c defined above the sensitive portion 10b; in particular, this waveguide 60 is configured to convey photons from the first section 60a and 60b to the second section 60c towards the sensitive portion 10b.

[0031] It is pointed out that the photodetector 11 is integrated directly into the sensitive portion 10b of the layer 10, and that the circuit 100 also comprises a first containment layer 30, clearly visible in figures 1 c, 1d, 1 e, 1f, 1 g, 1 h, 1 i, 11, 1 m and 1 n, interposed between the first section 60a and 60b and the inert portion 10a, where this first containment layer 30 is configured to prevent the crossing of photons towards the layer 10 and their absorption in the same layer 10. It is important to underline how the photodetector 11 is manufactured directly in the layer 10, at the aforesaid sensitive portion 10b.

[0032] Considering that the photon absorption index of the first containment layer 30 is much lower than that of the underlying layer, this first containment layer 30 clearly allows to prevent the absorption in the layer 10 of the photons channeled along the waveguide 60 before they can reach the sensitive portion 10b.

[0033] Furthermore, since the photodetector 11 is directly integrated in the sensitive portion 10b of the layer 10, it is possible to operate this photodetector 11 at ambient temperature obtaining lower energy dispersions of the photons in the passage between the waveguide 60 and the aforesaid photodetector 11 compared to a similar circuit of known type.

[0034] In the present embodiment of the invention, the first containment layer 30 has a thickness comprised between 1.6 pm and 1.8 pm.

[0035] This advantageously allows to optimize the passage of photons between the waveguide 60 and the photodetector 11 when the radiation transmitted by this waveguide 60 is infrared radiation.

[0036] Still with reference to the present embodiment of the invention, the aforesaid first containment layer 30 is made of a material comprising silicon dioxide.

[0037] However, it is not excluded that a different material configured to prevent the crossing of photons can be used to realize this first containment layer 30.

[0038] In the present embodiment of the invention, the waveguide 60 is made of a material comprising silicon nitride and has a thickness comprised between 100 and 200 nm.

[0039] It is not excluded, however, that the material and thickness of the waveguide 60 are different from what has just been described.

[0040] Still in the present embodiment of the invention, the first section 60a and 60b of the waveguide 60 has at least one section inclined 60b towards the sensitive portion 10b with an angle 0 with respect to the aforesaid longitudinal development X of the layer 10.

[0041] More precisely, the first section 60a and 60b has a flat section 60a that develops parallel to the longitudinal development X of the layer 10 and the aforesaid inclined section 60b contiguous to this flat section 60a and that develops up to the second section 60c at the sensitive portion 10b.

[0042] The configuration of the waveguide 60 just described advantageously allows to obtain even lower photon dispersions in the passage between the waveguide 60 and the aforesaid photodetector 11 compared to a similar circuit of known type thanks to a transition between the first section 60a, 60b and the second section 60c with this angle 0 of less than 90°.

[0043] Even more precisely, in the present embodiment of the invention, the angle 0 is equal to 7°.

[0044] However, it is not excluded that this angle 0 is different from what has just been described, preferably comprised between 5° and 10°.

[0045] In the present embodiment of the invention, the circuit 100 comprises a second containment layer 70, clearly visible in figures 1 m and 1 n, defined above the waveguide 60, where this second containment layer 70 is configured to prevent the crossing of photons.

[0046] The presence of this second containment layer 70 advantageously allows to isolate the aforesaid waveguide 60 during the crossing of photons, further minimizing the energy dispersion of the photons crossing the waveguide 60.

[0047] Even more precisely, this second containment layer 70 is made of a material comprising silicon dioxide.

[0048] It is not excluded, however, that this second containment layer 70 is made of a material different from what has just been described or that it is completely absent.

[0049] As indicated above, the present invention also concerns a method for the realization of a planar photonic integrated circuit 100 whose steps are schematically represented in sequence in figures 1a, 1 b, 1 c, 1 d, 1 e, 1f, 1 g, 1 h, 1 i, 11 and 1 m.

[0050] This method comprises the following sequential steps: a) arranging a layer 10 of a semiconductor material, as represented in figure 1 a, which has along its longitudinal development X an inert portion 10a and a contiguous sensitive portion 10b in which at least one solid-state photodetector 11 is defined; b) depositing a masking layer 20 on the inert portion 10a and the sensitive portion 10b, as represented in figure 1 b, where this masking layer 20 is configured to allow the crossing of photons and is configured to resist dissolution when immersed in an acid solution AS; c) depositing a first containment layer 30 on the masking layer 20, as can be seen from figure 1 c, where this first containment layer 30 is configured to prevent the crossing of photons and is configured to dissolve at a first speed vi when immersed in the acid solution AS; moreover, this first containment layer 30 has a thickness equal to the first speed vi for a dissolution time td; d) depositing a first sacrificial layer 40 on the first containment layer 30 at least at the inert portion 10a, as represented in figure 1 d, where this first sacrificial layer 40 is configured to completely dissolve at a second speed V2 when immersed in the aforesaid acid solution AS for the dissolution time td; f) immersing the first containment layer 30 and the first sacrificial layer 40 in the acid solution AS for the dissolution time td, as represented in figures 1 g and 1 h, in such a way as to expose the masking layer 20 at the sensitive portion 10b, as can be seen in figure 1 i; g) depositing a waveguide 60 as represented in figure 11, with a first section 60a and 60b arranged on the first containment layer 30 at the inert portion 10a and a contiguous second section 60c arranged on the masking layer 20 at the sensitive portion 10b; where the waveguide 60 is configured to convey photons from the first section 60a and 60b to the second section 60c towards the sensitive portion 10b.

[0051] It should be noted that “dissolution” in acid solution AS means the isotropic removal of material by means of this acid solution AS.

[0052] The method just described allows, with reference to a planar photonic integrated circuit 100 obtained by this method, to obtain even lower photon energy dispersions in the passage between the waveguide 60 and the aforesaid photodetector 11.

[0053] In particular, during the aforesaid step f) of immersing the first containment layer 30 and the first sacrificial layer 40 in the acid solution AS for the dissolution time td, the containment layer 30 is subject to dissolution in a direction substantially orthogonal to the longitudinal development X towards the aforesaid layer 10, while the first sacrificial layer 40 is subject to dissolution in a direction parallel to the longitudinal development X in the opposite direction to the sensitive portion 10b.

[0054] This dissolution dynamic leads to a change in the thickness of the first containment layer 30 which will result, at the end of the dissolution time td, in an inclination of the first containment layer 30 towards the sensitive portion 10b with an angle 0 with respect to the longitudinal development X and in complete dissolution at the sensitive portion 10b. In the present embodiment of the invention, the aforesaid step d) comprises depositing the sacrificial layer 40 on the first containment layer 30 at the inert portion 10a and the sensitive portion 10b.

[0055] In addition, the method presented here comprises the following step between step d) and step f): e) obtaining an opening through the first sacrificial layer 40, as represented in figure 1 f, in such a way as to expose the first containment layer 30 at the sensitive portion 10b.

[0056] Even more precisely, the aforesaid angle 0 is directly proportional to the ratio between the first speed vi and the second speed V2 according to the formula:

[0057] / Vl\

[0058] 0 = arcsin — v2J

[0059] In particular, in the present embodiment of the method, the second speed V2 is higher than the first speed vi.

[0060] Furthermore, the ratio between said first speed vi and said second speed V2 is less than 0.13 with an angle 0 equal to 7°.

[0061] However, it is not excluded that the first speed vi and the second speed V2 are different from what has just been described.

[0062] With reference to the present embodiment of the invention, the masking layer 20 comprises silicon nitride with a thickness substantially equal to 30 nm.

[0063] In addition, the first sacrificial layer 40 comprises amorphous silicon or doped oxide (BPSG, borophosphosilicate glass), with a thickness substantially equal to 300 nm.

[0064] However, it is not excluded that the masking layer 20 and the first sacrificial layer 40 are different from what has just been described.

[0065] Still with reference to the present embodiment of the invention, the first sacrificial layer 40 has a length along the longitudinal development X equal to the second speed V2 for the dissolution time td starting from the sensitive portion 10b towards the inert portion 10a.

[0066] This advantageously allows to obtain the total dissolution of the first sacrificial layer 40 in the acid solution AS in the dissolution time td.

[0067] However, it is not excluded that this length is different from what has just been described.

[0068] Furthermore, the method described herein comprises the following step between step d) and step e): d’) depositing a second sacrificial layer 50 on the first sacrificial layer 40 as represented in figure 1f, where the second sacrificial layer 50 is configured to dissolve at a third speed vs when immersed in the acid solution AS and this second sacrificial layer 50 has a thickness equal to the third speed vs for the dissolution time td.

[0069] More precisely, step e) comprises the creation of the aforesaid opening through the first sacrificial layer 40 and the second sacrificial layer 50 at the sensitive portion 10b, as can be seen from figure 1f, and where step f) comprises the immersion of the second sacrificial layer 50 in the acid solution AS for the dissolution time td.

[0070] This makes it possible to protect the upper surface of the first sacrificial layer 40 by limiting its dissolution in a direction parallel to the longitudinal development X in the opposite direction to the sensitive portion 10b.

[0071] In particular, the second sacrificial layer 50 is made of a material comprising silicon dioxide.

[0072] However, it is not excluded that this second sacrificial layer 50 is absent in other embodiments of the present invention.

[0073] Still with reference to the present embodiment of the invention, the method comprises the following step following step g): h) depositing a second containment layer 70 on the waveguide 60, as represented in figures 1 m and 1 n, where this second containment layer 70 is configured to prevent the crossing of photons.

[0074] In particular, this second containment layer 70 is made of a material comprising silicon dioxide.

[0075] However, it is not excluded that this containment layer 70 is different from what has just been described.

[0076] Practically, it has been established that the invention achieves the intended task and objects.

[0077] In particular, with the invention, a planar photonic integrated circuit has been developed that prevents the absorption of the photons channelled along the waveguide before they reach the sensitive portion.

[0078] In addition, a planar photonic integrated circuit has been developed where the photodetector can operate at ambient temperature obtaining lower energy dispersions of the photons in the passage between the waveguide and the aforesaid photodetector compared to a similar circuit of known type.

Claims

1.CLAIMS1 ) Planar photonic integrated circuit (100), comprising:- a layer (10) of a semiconductor material having along its longitudinal development (X) an inert portion (10a) and a contiguous sensitive portion (10b) on which at least one solid-state photodetector (11 ) is defined;- a waveguide (60) having a first section (60a, 60b) defined above said inert portion (10a) and a contiguous second section (60c) defined above said sensitive portion (10b), said waveguide (60) being configured to convey photons from said first section (60a, 60b) to said second section (60c) towards said sensitive portion (10b); characterized in that said photodetector (11 ) is directly integrated in said sensitive portion (10b) of said layer (10), said circuit (100) comprising a first containment layer (30) interposed between said first section (60a, 60b) and said inert portion (10a), said first containment layer (30) being configured to prevent the crossing of photons towards said layer (10).2) Circuit (100) according to claim 1 , characterized in that said first containment layer (30) has a maximum thickness comprised between 1.4 and 1 .8 pm.3) Circuit (100) according to claim 1 or 2, characterized in that said first section (60a, 60b) has at least one section inclined (60b) towards said sensitive portion (10b) with an angle (9) with respect to said longitudinal development (X).4) Circuit (100) according to any one of the preceding claims, characterized in that it comprises a second containment layer (70) defined above said waveguide (60), said second containment layer (70) being configured to prevent the crossing of photons.5) Method for the realization of a planar photonic integrated circuit (100), characterized by comprising the following steps in sequence: a) arranging a layer (10) of a semiconductor material having along its longitudinal development (X) an inert portion (10a) and a contiguous sensitive portion (10b) in which at least one solid-state photodetector (11 ) is defined; b) depositing a masking layer (20) on said inert portion (10a) and said sensitive portion (10b), said masking layer (20) being configured to allow the crossing of photons and being configured to resist dissolution when immersed in an acid solution (AS);c) depositing a first containment layer (30) on said masking layer (20), said first containment layer (30) being configured to prevent the crossing of photons and being configured to dissolve at a first speed (vi) when immersed in said acid solution (AS), said first containment layer (30) having a thickness equal to said first speed (vi) for a dissolution time (td); d) depositing a first sacrificial layer (40) on said first containment layer (30) at least at said inert portion (10a), said first sacrificial layer (40) being configured to completely dissolve at a second speed (V2) when immersed in said acid solution (AS) for said dissolution time (td); f) immersing said first containment layer (30) and said first sacrificial layer (40) in said acid solution (AS) for said dissolution time (td) in such a way as to expose the masking layer (20) at said sensitive portion (10b); g) depositing a waveguide (60) with a first section (60a, 60b) arranged on said first containment layer (30) at said inert portion (10a) and a contiguous second section (60c) arranged on said masking layer (20) at said sensitive portion (10b), said waveguide (60) being configured to convey photons from said first section (60a, 60b) to said second section (60c) towards said sensitive portion (10b).6) Method according to claim 5, characterized in that said step d) comprises depositing said sacrificial layer (40) on said first containment layer (30) at said inert portion (10a) and said sensitive portion (10b), said method comprising the following step between said step d) and said step f): e) obtaining an opening through said first sacrificial layer (40) in such a way as to expose said first containment layer (30) at said sensitive portion (10b).7) Method according to claim 5 or 6, characterized in that said second speed (V2) is higher than said first speed (vi).8) Method according to claim 7, characterized in that the ratio between said first speed (vi) and said second speed (V2) is less than 0.13.9) Method according to any one of claims 5 to 8, characterized in that said first sacrificial layer (40) has a length along said longitudinal development (X) equal to said second speed (V2) for said dissolution time (td) starting from said sensitive portion (10b) towards said inert portion (10a).10) Method according to any one of claims 5 to 9, characterized in that it comprises the following step between said step d) and said step e): d’) depositing a second sacrificial layer (50) on said first sacrificial layer (40),said second sacrificial layer (50) being configured to dissolve at a third speed (vs) when immersed in said acid solution (AS), said second sacrificial layer (50) having a thickness equal to said third speed (vs) for said dissolution time (td); said step e) comprising creating said opening through said first sacrificial layer (40) and said second sacrificial layer (50) at said sensitive portion (10b), said step f) comprising immersing said second sacrificial layer (50) in said acid solution (AS) for said dissolution time (td).11 ) Method according to any one of claims 5 to 10, characterized in that it comprises the following step following said step g): h) depositing a second containment layer (70) on said waveguide (60), said second containment layer (70) being configured to prevent the crossing of photons.

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