Power conversion device

Abstract

The purpose of the present invention is to reduce noise in a power conversion device. Each of a plurality of gate drive circuits (5) has a gate driver (50), a first gate resistance circuit (51), and a second gate resistance circuit (52). The first gate resistance circuit (51) is connected between a gate terminal of a corresponding switching element (8) among a plurality of switching elements (8) and the gate driver (50). The first gate resistance circuit (51) includes a first gate resistor (511) and a first diode (512) through which a current flows when the corresponding switching element (8) is turned on. The second gate resistance circuit (52) is connected in parallel to the first gate resistance circuit (51). The second gate resistance circuit (52) includes a second gate resistor (521) and a second diode (522) through which a current flows when the corresponding switching element (8) is turned off. A resistance value Rg1 of the first gate resistor (511) is greater than a resistance value Rg2 of the second gate resistor (521).

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device, and more particularly to a power conversion device including a three-phase inverter circuit.

[0002] Patent Document 1 discloses a power conversion device including a three-phase inverter circuit.

[0003] The power conversion device disclosed in Patent Document 1 includes a noise reduction circuit for reducing common-mode noise.

[0004] Japanese Patent Application Laid-Open No. 2001-245477

[0005] In a power conversion device, there are cases where it is desired to reduce noise without adding a noise reduction circuit.

[0006] An object of the present disclosure is to provide a power conversion device capable of reducing noise.

[0007] A power conversion device according to one aspect of the present disclosure includes a three-phase inverter circuit, multiple gate drive circuits, and a control device. The three-phase inverter circuit includes multiple switching elements. Each of the multiple switching elements has a gate terminal. The multiple gate drive circuits correspond one-to-one to the multiple switching elements. The control device outputs multiple control signals to the multiple gate drive circuits. Each of the multiple gate drive circuits includes a gate driver, a first gate resistor circuit, and a second gate resistor circuit. The first gate resistor circuit is connected between the gate driver and a gate terminal of a corresponding switching element among the multiple switching elements. The first gate resistor circuit includes a first gate resistor and a first diode through which a current flows when the corresponding switching element is turned on. The second gate resistor circuit is connected in parallel to the first gate resistor circuit. The second gate resistor circuit includes a second gate resistor and a second diode through which a current flows when the corresponding switching element is turned off. The resistance value of the first gate resistor is greater than the resistance value of the second gate resistor.

[0008] The power conversion device of the present disclosure has the effect of being able to reduce noise.

[0009] FIG. 1 is a circuit diagram of a power conversion device according to the first embodiment. FIG. 2 is a circuit diagram of a first gate drive circuit in the power conversion device according to the first embodiment. FIG. 3 is a circuit diagram of a second gate drive circuit in the power conversion device according to the first embodiment. FIG. 4 is an explanatory diagram of the relationship between a control signal output from a control device and a waveform of a gate voltage applied to a switching element from a gate drive circuit in the power conversion device according to the first embodiment. FIG. 5 is an explanatory diagram of the operation of the power conversion device according to the first embodiment. FIG. 6 is an explanatory diagram of the operation of the power conversion device according to the first embodiment. FIG. 7 is an explanatory diagram of the operation of the power conversion device according to the first embodiment. FIG. 8 is an explanatory diagram of the operation of the power conversion device according to the first embodiment. FIG. 9 is an explanatory diagram of the operation of the power conversion device according to the first embodiment. FIG. 10 is an explanatory diagram of the operation of the power conversion device according to the first embodiment. FIG. 11 is an explanatory diagram of the operation of the power conversion device according to the first embodiment. FIG. 12 is an explanatory diagram of the operation of the power conversion device according to the first embodiment. FIG. 13 is an explanatory diagram of the operation of the power conversion device according to the first embodiment. FIG. 14 is an explanatory diagram of the operation of the power conversion device according to the first embodiment. FIG. 15 is a graph showing the relationship between dv / dt and Rg1 / Rg2 in the power conversion device according to the first embodiment. FIG. 16 is a graph showing the frequency characteristics of the noise voltage level when the value of Rg1 / Rg2 is changed in the power conversion device according to the first embodiment. FIG. 17 is a waveform diagram of the gate voltage when the control device performs voltage vector control in the power conversion device according to the first embodiment. FIG. 18 is a waveform diagram of the gate voltage when the control device performs PWM control in the power conversion device according to the first embodiment. FIG. 19 is a circuit diagram of a first gate drive circuit in the power conversion device according to the first modification of the first embodiment. FIG. 20 is a circuit diagram of a second gate drive circuit in the power conversion device according to the first modification of the first embodiment. FIG. 21 is an explanatory diagram of the operation of the power conversion device according to the first modification of the first embodiment. FIG. 22 is an explanatory diagram of the operation of the power conversion device according to the first modification of the first embodiment. FIG. 23 is an explanatory diagram of the operation of the power conversion device according to the second modification of the first embodiment. FIG. 24 is an explanatory diagram of the operation of the power conversion device according to the second modification of the first embodiment. Fig. 25 is a circuit diagram of a power conversion device according to embodiment 2. Fig. 26 is a circuit diagram of a power conversion device according to embodiment 3.FIG. 27 is a graph showing the relationship between dv / dt and Rg1 / Rg2 in the power conversion device according to the third embodiment.

[0010] First Embodiment A power conversion device 100 according to a first embodiment will be described below with reference to FIGS.

[0011] (1) Overall Configuration of the Power Conversion Device FIG. 1 is a circuit diagram of a power conversion device 100 according to a first embodiment. As shown in FIG. 1 , the power conversion device 100 includes, for example, a three-phase inverter circuit 2, a plurality of (12 in the example of FIG. 1 ) gate drive circuits 5, and a control device 4. The three-phase inverter circuit 2 includes a plurality of (12 in the example of FIG. 1 ) switching elements 8 (three first switching elements Q1, three second switching elements Q2, three third switching elements Q3, and three fourth switching elements Q4). Each of the switching elements 8 has a gate terminal, a first main terminal, and a second main terminal. In this embodiment, each of the switching elements 8 is an insulated gate bipolar transistor (IGBT). The first main terminal and the second main terminal of each of the switching elements 8 are a collector terminal and an emitter terminal, respectively. The gate drive circuits 5 correspond one-to-one to the switching elements 8. The control device 4 outputs a plurality of control signals US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, and WS4 (12 in the example of FIG. 1 ) to the plurality of gate drive circuits 5, respectively. Each of the plurality of gate drive circuits 5 includes a gate driver 50, a first gate resistance circuit 51, and a second gate resistance circuit 52, as shown in, for example, FIG. 2 or 3 . The first gate resistance circuit 51 is connected between the gate driver 50 and a gate terminal of a corresponding one of the plurality of switching elements 8. The first gate resistance circuit 51 includes a first gate resistor 511 and a first diode 512 through which a current flows when the corresponding switching element 8 is turned on. The second gate resistance circuit 52 is connected in parallel with the first gate resistance circuit 51. The second gate resistor circuit 52 includes a second gate resistor 521 and a second diode 522 through which a current flows when the corresponding switching element 8 is turned off.

[0012] 1, the power conversion device 100 further includes a DC power supply unit 3. The power conversion device 100 further includes a DC-DC converter 6.

[0013] In the power conversion device 100, the three-phase inverter circuit 2 is a diode-clamped three-level three-phase inverter circuit. In the power conversion device 100, the three-phase inverter circuit 2 includes three inverter circuits 1U, 1V, and 1W, each of which has an output terminal 9. In the power conversion device 100, AC loads are connected to the three output terminals 9.

[0014] The AC load is, for example, a three-phase servo motor. In the power conversion device 100, one inverter circuit 1U of the three inverter circuits 1U, 1V, and 1W is an inverter circuit that outputs a U-phase voltage, another inverter circuit 1V is an inverter circuit that outputs a V-phase voltage, and the remaining inverter circuit 1W is an inverter circuit that outputs a W-phase voltage. In each of the three inverter circuits 1U, 1V, and 1W, the potential level of the output voltage changes in three levels depending on the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4. Note that the output voltage of the inverter circuit 1U, the output voltage of the inverter circuit 1V, and the output voltage of the inverter circuit 1W are out of phase with each other.

[0015] (2) Details of the Power Conversion Device As shown in FIG. 1 , the power conversion device 100 includes, for example, a DC power supply unit 3, a three-phase inverter circuit 2, a plurality of gate drive circuits 5, and a control device 4.

[0016] The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The "intermediate potential point M1" is a point at an intermediate potential between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3. The DC power supply unit 3 has a first capacitor C11 and a second capacitor C12. In the DC power supply unit 3, the first capacitor C11 and the second capacitor C12 are connected in series. The DC power supply unit 3 further has a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1. In the DC power supply unit 3, a first end of the first capacitor C11 is connected to the first DC terminal 31, a second end of the first capacitor C11 is connected to a first end of the second capacitor C12, and a second end of the second capacitor C12 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection point between the first capacitor C11 and the second capacitor C12 is an intermediate potential point M1. For example, an external power supply outputting a DC output voltage is connected between the first DC terminal 31 and the second DC terminal 32. In this case, the output voltage of the external power supply is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The series circuit of the first capacitor C11 and the second capacitor C12 forms a voltage divider circuit. The capacitance of the second capacitor C12 is the same as the capacitance of the first capacitor C11. The phrase "the capacitance of the second capacitor C12 is the same as the capacitance of the first capacitor C11" does not necessarily mean that the capacitance of the second capacitor C12 exactly matches the capacitance of the first capacitor C11, but may mean that the capacitance of the second capacitor C12 is within a range of 90% to 110% of the capacitance of the first capacitor C11.

[0017] Each of the three inverter circuits 1U, 1V, and 1W has a first switching element Q1, a second switching element Q2, a third switching element Q3, a fourth switching element Q4, a first clamp diode D5, and a second clamp diode D6. In the power conversion device 100, the potential of the intermediate potential point M1 is clamped by the first clamp diode D5 and the second clamp diode D6 of each of the inverter circuits 1U, 1V, and 1W.

[0018] In each of the three inverter circuits 1U, 1V, 1W, the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series from the positive electrode P1 side to the negative electrode N1 side of the DC power supply unit 3 in the order of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4.

[0019] In each of the three inverter circuits 1U, 1V, and 1W, a first main terminal of a first switching element Q1 is connected to a positive electrode P1 of the DC power supply unit 3, and a second main terminal of the first switching element Q1 is connected to a first main terminal of a second switching element Q2. In each of the three inverter circuits 1U, 1V, and 1W, a second main terminal of the second switching element Q2 is connected to a first main terminal of a third switching element Q3. In each of the three inverter circuits 1U, 1V, and 1W, a second main terminal of the third switching element Q3 is connected to a first main terminal of a fourth switching element Q4, and a second main terminal of the fourth switching element Q4 is connected to a negative electrode N1 of the DC power supply unit 3.

[0020] In each of the three inverter circuits 1U, 1V, and 1W, an output point 13 between the second switching element Q2 and the third switching element Q3 is connected to the output terminal 9. In each of the three inverter circuits 1U, 1V, and 1W, the output point 13 is the connection point between the second switching element Q2 and the third switching element Q3. The output point 13 is not limited to the connection point between the second switching element Q2 and the third switching element Q3, but may also be a node between the second main terminal of the second switching element Q2 and the first main terminal of the third switching element Q3. The output terminal 9 of the inverter circuit 1U is connected to the U-phase terminal of a three-phase servo motor. The output terminal 9 of the inverter circuit 1V is connected to the V-phase terminal of a three-phase servo motor. The output terminal 9 of the inverter circuit 1W is connected to the W-phase terminal of a three-phase servo motor.

[0021] Each of the three inverter circuits 1U, 1V, and 1W further includes four diodes D1 to D4. In each of the three inverter circuits 1U, 1V, and 1W, the diode D1 is connected in anti-parallel to the first switching element Q1. In each of the three inverter circuits 1U, 1V, and 1W, the diode D2 is connected in anti-parallel to the second switching element Q2. In each of the three inverter circuits 1U, 1V, and 1W, the diode D3 is connected in anti-parallel to the third switching element Q3. In each of the three inverter circuits 1U, 1V, and 1W, the diode D4 is connected in anti-parallel to the fourth switching element Q4.

[0022] In each of the three inverter circuits 1U, 1V, and 1W, the diode D1 may be substituted with a parasitic diode of the IGBT that constitutes the first switching element Q1. In each of the three inverter circuits 1U, 1V, and 1W, the diode D2 may be substituted with a parasitic diode of the IGBT that constitutes the second switching element Q2. In each of the three inverter circuits 1U, 1V, and 1W, the diode D3 may be substituted with a parasitic diode of the IGBT that constitutes the third switching element Q3. In each of the three inverter circuits 1U, 1V, and 1W, the diode D4 may be substituted with a parasitic diode of the IGBT that constitutes the fourth switching element Q4.

[0023] In each of the three inverter circuits 1U, 1V, and 1W, the first clamp diode D5 is connected between a first connection point 11 between the first switching element Q1 and the second switching element Q2 and the intermediate potential point M1. More specifically, in each of the three inverter circuits 1U, 1V, and 1W, the cathode of the first clamp diode D5 is connected to the first connection point 11 between the first switching element Q1 and the second switching element Q2, and the anode of the first clamp diode D5 is connected to the intermediate potential point M1 of the DC power supply unit 3.

[0024] In each of the three inverter circuits 1U, 1V, and 1W, a second clamp diode D6 is connected between a second connection point 12 between the third switching element Q3 and the fourth switching element Q4 and the intermediate potential point M1. More specifically, the cathode of the second clamp diode D6 is connected to the intermediate potential point M1. The anode of the second clamp diode D6 is connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4.

[0025] In the first embodiment, when the voltage between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3 is Vdc, the potential difference between the positive electrode P1 and the intermediate potential point M1 is approximately Vdc / 2, and the potential difference between the negative electrode N1 and the intermediate potential point M1 is approximately Vdc / 2.

[0026] A corresponding one of the plurality of gate drive circuits 5 is connected between the gate terminal of each of the plurality of switching elements 8 and the second main terminal. Each of the plurality of switching elements 8 is driven (turned on and off) by a corresponding one of the plurality of gate drive circuits 5.

[0027] The plurality of gate drive circuits 5 are connected to the control device 4. Each of the plurality of gate drive circuits 5 is connected between the gate terminal of a corresponding one of the plurality of switching elements 8 and the second main terminal.

[0028] In FIG. 1, the plurality of gate drive circuits 5 include three gate drive circuits 5 (hereinafter also referred to as first gate drive circuits 5A) that correspond one-to-one to the three fourth switching elements Q4, and nine gate drive circuits 5 (hereinafter also referred to as second gate drive circuits 5B) that correspond one-to-one to the three first switching elements Q1, three second switching elements Q2, and three third switching elements Q3.

[0029] Each of the multiple gate drive circuits 5 controls the on / off state of the switching element 8 based on a control signal provided thereto. More specifically, the gate drive circuit 5 connected to the first switching element Q1 of the inverter circuit 1U controls the on / off state of the switching element 8 based on a control signal US1. The gate drive circuit 5 connected to the second switching element Q2 of the inverter circuit 1U controls the on / off state of the switching element 8 based on a control signal US2. The gate drive circuit 5 connected to the third switching element Q3 of the inverter circuit 1U controls the on / off state of the switching element 8 based on a control signal US3. The gate drive circuit 5 connected to the fourth switching element Q4 of the inverter circuit 1U controls the on / off state of the switching element 8 based on a control signal US4. The gate drive circuit 5 connected to the first switching element Q1 of the inverter circuit 1V controls the on / off state of the switching element 8 based on a control signal VS1. The gate drive circuit 5 connected to the second switching element Q2 of the inverter circuit 1V controls the on / off state of the switching element 8 based on a control signal VS2. The gate drive circuit 5 connected to the third switching element Q3 of the inverter circuit 1V controls the on / off state of the switching element 8 based on a control signal VS3. The gate drive circuit 5 connected to the fourth switching element Q4 of the inverter circuit 1V controls the on / off state of the switching element 8 based on a control signal VS4. The gate drive circuit 5 connected to the first switching element Q1 of the inverter circuit 1W controls the on / off state of the switching element 8 based on a control signal WS1. The gate drive circuit 5 connected to the second switching element Q2 of the inverter circuit 1W controls the on / off state of the switching element 8 based on a control signal WS2. The gate drive circuit 5 connected to the third switching element Q3 of the inverter circuit 1W controls the on / off state of the switching element 8 based on a control signal WS3. The gate drive circuit 5 connected to the fourth switching element Q4 of the inverter circuit 1W controls the on / off state of the switching element 8 based on a control signal WS4.

[0030] As shown in FIG. 2 or 3 , each of the plurality of gate drive circuits 5 includes a gate driver 50 , a first gate resistance circuit 51 , and a second gate resistance circuit 52 .

[0031] The gate driver 50 has a first input terminal 501, a second input terminal 502, an output terminal 503, a positive power supply terminal 504, and a negative power supply terminal 505. The gate driver 50 has an input-stage diode (not shown) whose anode is connected to the first input terminal 501 and whose cathode is connected to the second input terminal 502. The input-stage diode is conductive when a control signal provided by the control device 4 is at a high level and is non-conductive when the control signal is at a low level. The gate driver 50 also has a series circuit formed by connecting a pair of transistors (not shown) in reverse series. This series circuit is connected between the positive power supply terminal 504 and the negative power supply terminal 505. The gate driver 50 outputs a voltage that turns on the switching element 8 when the input-stage diode is conductive, and outputs a voltage that turns off the switching element 8 when the input-stage diode is non-conductive.

[0032] The first gate resistance circuit 51 is connected between the gate terminal of a corresponding one of the multiple switching elements 8 and the gate driver 50. The first gate resistance circuit 51 includes a first gate resistor 511 and a first diode 512 through which a current flows when the corresponding switching element 8 is turned on. In the first gate resistance circuit 51 of this embodiment, a first end of the first gate resistor 511 is connected to the output terminal 503 of the gate driver 50, a second end of the first gate resistor 511 is connected to the anode of the first diode 512, and a cathode of the first diode 512 is connected to the gate terminal of the switching element 8.

[0033] The second gate resistance circuit 52 is connected in parallel to the first gate resistance circuit 51. The second gate resistance circuit 52 includes a second gate resistance 521 and a second diode 522 through which a current flows when the corresponding switching element 8 is turned off. In the second gate resistance circuit 52 of this embodiment, a first end of the second gate resistance 521 is connected to the output terminal 503 of the gate driver 50, a second end of the second gate resistance 521 is connected to the cathode of the second diode 522, and an anode of the second diode 522 is connected to the gate terminal of the switching element 8.

[0034] In each of the plurality of gate drive circuits 5, the resistance value Rg1 of the first gate resistor 511 is greater than the resistance value Rg2 of the second gate resistor 521.

[0035] 2 is a circuit diagram of a first gate drive circuit 5A in the power conversion device 100 according to the first embodiment. Each of the three first gate drive circuits 5A is configured to switch the output voltage of the gate driver 50 between a positive voltage (e.g., 15 V) and a negative voltage (e.g., −9 V) greater than the gate threshold voltage of the IGBT based on a corresponding one of the control signals US4, VS4, and WS4. Each of the three first gate drive circuits 5A is configured to apply a positive voltage between the gate terminal of a corresponding one of the multiple switching elements 8 and the second main terminal, and to apply a negative voltage between the gate terminal of the corresponding one of the switching elements 8 and the second main terminal, as shown in FIG. 2 . Each of the three first gate drive circuits 5A includes a gate driver 50, a first gate resistor circuit 51, a second gate resistor circuit 52, and a bipolar power supply circuit (positive / negative power supply circuit) 53 that outputs a positive voltage and a negative voltage. The bipolar power supply circuit 53 has, for example, a positive input terminal 531, a negative input terminal 532, a reference output terminal 533, a high-potential output terminal 534, and a low-potential output terminal 535. The bipolar power supply circuit 53 also has a smoothing capacitor C53, a resistor 556, two smoothing capacitors C54 and C55 connected in series, a Zener diode 557, a resistor 558, and two capacitors C56 and C57 connected in series. The positive input terminal 531 and the negative input terminal 532 of the bipolar power supply circuit 53 are connected to the positive output terminal and the negative output terminal of the DC-DC converter 6, respectively. In the bipolar power supply circuit 53, a positive voltage of 15 V is output between the high-potential output terminal 534 and the reference output terminal 533, with the potential of the reference output terminal 533 serving as a reference potential. In addition, in the bipolar power supply circuit 53, a negative voltage of -9V is output between the low potential side output terminal 535 and the reference output terminal 533, with the potential of the reference output terminal 533 being used as the reference potential.

[0036] 2 , in each of the three first gate drive circuits 5A, the high-potential output terminal 534 of the bipolar power supply circuit 53 is connected to the positive power supply terminal 504 of the gate driver 50, and the low-potential output terminal 535 is connected to the negative power supply terminal 505 of the gate driver 50. The reference output terminal 533 is connected to the second main terminal of the switching element 8.

[0037] 3 is a circuit diagram of a second gate drive circuit 5B in the power conversion device 100 according to the first embodiment. Each of the nine second gate drive circuits 5B is configured to switch the output voltage of the gate driver 50 between a voltage higher than the gate threshold voltage of the IGBT (e.g., 15 V) and 0 V based on a corresponding control signal from among control signals US1, US2, US3, VS1, VS2, VS3, WS1, WS2, and WS3. More specifically, each of the nine second gate drive circuits 5B includes a gate driver 50, a first gate resistor circuit 51, and a second gate resistor circuit 52, as shown in FIG. 3 . A first end of a capacitor C1 in the bootstrap circuit 7 is connected to a positive power supply terminal 504 of the gate driver 50, and a second end of the capacitor C1 is connected to a negative power supply terminal 505 of the gate driver 50.

[0038] The DC-DC converter 6 is, for example, an isolated DC-DC converter that boosts a first voltage (for example, 5 V) and outputs a second voltage (for example, 24 V). The first voltage is, for example, a voltage input to the DC-DC converter 6 from a DC power supply (not shown) connected between the positive and negative input terminals of the DC-DC converter 6.

[0039] The DC-DC converter 6 supplies voltage to the nine bootstrap circuits 7 and the three first gate drive circuits 5A.

[0040] Each of the nine bootstrap circuits 7 corresponds one-to-one to the nine second gate drive circuits 5B. Each of the nine bootstrap circuits 7 supplies a voltage to a corresponding one of the nine second gate drive circuits 5B. Each of the nine bootstrap circuits 7 includes a diode D1, a resistor R1, and a capacitor C1. As shown in FIG. 3 , in each of the nine bootstrap circuits 7, a first end of the capacitor C1 is connected to the positive power supply terminal 504 of the gate driver 50 in the corresponding gate drive circuit 5, and a second end of the capacitor C1 is connected to the negative power supply terminal 505 of the gate driver 50. The bootstrap circuit 7 supplies the gate driver 50 with a voltage required to turn on the switching element 8 in the gate driver 50.

[0041] In the bootstrap circuit 7 connected to the first gate drive circuit 5A corresponding to the first switching element Q1, the anode of the diode D1 is connected to the positive terminal of the DC-DC converter 6 via the diode D1 of the bootstrap circuit 7 connected to the first gate drive circuit 5A corresponding to the second switching element Q2 and the diode D1 of the bootstrap circuit 7 connected to the first gate drive circuit 5A corresponding to the third switching element Q3.

[0042] In the bootstrap circuit 7 connected to the first gate drive circuit 5A corresponding to the second switching element Q2, the anode of the diode D1 is connected to the positive terminal of the DC-DC converter 6 via the diode D1 of the bootstrap circuit 7 connected to the first gate drive circuit 5A corresponding to the third switching element Q3.

[0043] In the bootstrap circuit 7 connected to the first gate drive circuit 5A corresponding to the third switching element Q3, the anode of the diode D1 is connected to the positive terminal of the DC-DC converter 6.

[0044] The control device 4 generates, for example, control signals US1 to US4 for the first switching element Q1 to the fourth switching element Q4 of the inverter circuit 1U, control signals VS1 to VS4 for the first switching element Q1 to the fourth switching element Q4 of the inverter circuit 1V, and control signals WS1 to WS4 for the first switching element Q1 to the fourth switching element Q4 of the inverter circuit 1W based on a U-phase voltage command, a V-phase voltage command, and a W-phase voltage command relating to the output voltages of the inverter circuits 1U, 1V, and 1W, respectively.

[0045] The U-phase voltage command, the V-phase voltage command, and the W-phase voltage command are, for example, sinusoidal signals whose phases are different from each other by 120°, and whose values ​​(voltage command values) change over time. The U-phase voltage command, the V-phase voltage command, and the W-phase voltage command have the same cycle length. The control device 4 may perform proportional integral (PI) control of the U-phase voltage command, the V-phase voltage command, and the W-phase voltage command based on information output from a detection unit (not shown) that detects the state of the AC load. When the AC load is a three-phase servo motor, the information output from the detection unit includes, for example, at least one of information on the detection results of multiple current sensors that detect output currents flowing through the U-phase terminals, the V-phase terminals, and the W-phase terminals of the three-phase servo motor, and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase servo motor.

[0046] The control device 4 outputs a plurality of control signals US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, and WS4. The control signals US1, US2, US3, and US4 are provided to gate drive circuits 5 connected to the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the inverter circuit 1U, respectively. The control signals VS1, VS2, VS3, and VS4 are provided to gate drive circuits 5 connected to the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the inverter circuit 1V, respectively. The control signals WS1, WS2, WS3, and WS4 are provided to gate drive circuits 5 connected to the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the inverter circuit 1W, respectively.

[0047] Each of the multiple control signals US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, and WS4 is a signal whose potential level changes between, for example, a first potential level V1 (see FIG. 4) and a second potential level V2 (see FIG. 4) that is higher than the first potential level V1.

[0048] The first potential level V1 is, for example, 0 V, and the second potential level V2 is, for example, a potential level that can make conductive an input stage diode included in the gate driver 50 of the gate drive circuit 5. The input stage diode is, for example, a light-emitting diode of a photocoupler, but is not limited to a light-emitting diode.

[0049] The control device 4 controls the plurality of gate drive circuits 5 by performing voltage vector control.

[0050] In this embodiment, when performing voltage vector control, the control device 4 generates control signals US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, and WS4 using space vector modulation. The control device 4 also charges multiple bootstrap circuits 7 using space vector modulation. The voltage vector control using space vector modulation in this embodiment will be described in more detail below.

[0051] The control device 4 selects, for example, a plurality of voltage vectors adjacent to the command voltage vector from a group (27 voltage vectors). Each of the group of voltage vectors is determined by a combination of the potential levels of the three output points 13 of the three inverter circuits 1U, 1V, and 1W. The group of voltage vectors includes 12 voltage vectors each having a reference magnitude, 6 voltage vectors each having a magnitude twice the reference magnitude, and 12 voltage vectors each having a magnitude three times the reference magnitude. １／２ The control device 4 replaces one of two first voltage vectors, which have a reference magnitude and are closest to the command voltage vector, with a zero vector (third zero vector) of a combination in which the potential levels of the three output points 13 in the three inverter circuits 1U, 1V, and 1W are the potential of the negative pole N1, and six voltage vectors each having a magnitude twice that of the first voltage vector, a zero vector (first zero vector) of a combination in which the potential levels of all three output points 13 are the potential of the positive pole P1, a zero vector (second zero vector) of a combination in which the potential levels of all three output points 13 are the potential of the intermediate potential point M1, and a zero vector (third zero vector) of a combination in which the potential levels of all three output points 13 are the potential of the negative pole N1, and a second voltage vector having the same direction as the first voltage vector but twice the magnitude of the first voltage vector. The control device 4 controls the multiple (12) gate drive circuits 5 within a predetermined control period so that the composite vector of the voltage vectors other than the first voltage vector, the third zero vector, and the second voltage vector among the multiple voltage vectors matches the command voltage vector.

[0052] The executing entity of the control device 4 includes a computer system. The computer system has one or more computers. The computer system is mainly composed of a processor and memory as hardware. The processor executes a program recorded in the memory of the computer system, thereby realizing the function of the executing entity of the control device 4 in the present disclosure. The program may be pre-recorded in the memory of the computer system, provided via a telecommunications line, or recorded and provided on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The multiple electronic circuits may be integrated into a single chip or distributed across multiple chips. The multiple chips may be integrated into a single device or distributed across multiple devices.

[0053] (3) Characteristics Figure 4 is an explanatory diagram of the relationship between the control signal output from the control device 4 in the power conversion device 100 according to the first embodiment and the waveform of the gate voltage applied to the switching element 8 from the gate drive circuit 5. Figure 4 schematically shows the relationship between each of the plurality of control signals US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, and WS4 and the waveform of the gate voltage (in this embodiment, the gate-emitter voltage) of each of the plurality of switching elements 8. That is, Figure 4 shows the relationship between any one control signal among the plurality of control signals US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, and WS4 and the waveform of the gate voltage applied between the gate terminal and the second main terminal (emitter terminal) of the switching element 8 from the gate drive circuit 5 to which this one control signal is input. In this embodiment, each of the multiple control signals US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, and WS4 output from the control device 4 is a rectangular-wave voltage signal. Furthermore, in this embodiment, the resistance value Rg1 of the first gate resistor 511 is greater than the resistance value Rg2 of the second gate resistor 521, and the resistance value of the first gate resistor circuit 51 is greater than the resistance value of the second gate resistor circuit 52. Therefore, in this embodiment, with regard to the waveform of the gate voltage, the absolute value of the voltage change rate (dv / dt) when the gate voltage increases from the low-potential-level voltage value V3 to the high-potential-level voltage value V4 is smaller than the absolute value of the voltage change rate (dv / dt) when the gate voltage decreases from the high-potential-level voltage value V4 to the low-potential-level voltage value V3. The waveform of the gate voltage shown in FIG. 4 is drawn omitting the portion where the gate voltage becomes constant at the gate threshold voltage (plateau voltage) due to the Miller effect.

[0054] Fig. 5 is a diagram illustrating the operation of the power conversion device 100 according to the first embodiment. Fig. 5 shows the waveforms of the gate voltage when the first switching element Q1 of the inverter circuit 1U is turned on, the voltage between the first main terminal and the second main terminal of the switching element 8 (collector-emitter voltage Vce), and the U-phase load current. The horizontal axis of Fig. 5 is 500 ns / div.

[0055] FIG. 6 is an explanatory diagram of the operation of the power conversion device 100 according to the first embodiment. FIG. 6 shows the waveforms of the gate voltage, the collector-emitter voltage Vce, and the U-phase load current when the first switching element Q1 of the inverter circuit 1U is turned off. The horizontal axis of FIG. 6 is 500 ns / div. In FIG. 6, noise occurs in the collector-emitter voltage Vce of the first switching element Q1 and in the load current, starting from the point when the third switching element Q3 is turned on after the dead time period has elapsed after the first switching element Q1 is turned off.

[0056] Fig. 7 is a diagram illustrating the operation of the power conversion device 100 according to the first embodiment. Fig. 7 shows the waveforms of the gate voltage, the collector-emitter voltage Vce, and the U-phase load current when the third switching element Q3 of the inverter circuit 1U is turned on. The horizontal axis in Fig. 7 is 500 ns / div.

[0057] 8 is a diagram illustrating the operation of the power conversion device 100 according to the first embodiment. Fig. 8 shows the waveforms of the gate voltage, the collector-emitter voltage Vce, and the U-phase load current when the third switching element Q3 of the inverter circuit 1U is turned off. In Fig. 8, noise occurs in the collector-emitter voltage Vce of the third switching element Q3 and the load current, starting from the moment the first switching element Q1 is turned on after the dead time period has elapsed after the third switching element Q3 is turned off.

[0058] 9 is a diagram illustrating the operation of the power conversion device 100 according to the first embodiment. The three waveforms in the upper part of FIG. 9 represent the gate voltage (Vge_Q1) of the first switching element Q1 of the inverter circuit 1U, the gate voltage (Vge_Q2) of the second switching element Q2 of the inverter circuit 1U, and the common-mode current I flowing from the power conversion device 100 to the ground conductor. ＣＭ 9 shows the waveforms of the respective voltages. The three waveforms in the lower part of FIG. 9 are enlarged waveform diagrams of an area A1 including the three waveforms in the upper part of FIG. 9. Regarding the waveforms in the lower part of FIG. 9, the scale of Vge_Q1 on the vertical axis is 25 V / div, the scale of Vge_Q2 on the vertical axis is 25 V / div, and the scale of the common mode current I ＣＭThe scale of the horizontal axis is 2 A / div. In the lower part of FIG. 9, the scale of the horizontal axis is 2 μs / div. FIG. 10 is a diagram illustrating the operation of the power conversion device 100 according to the first embodiment. FIG. 10 shows the gate voltage Vge_Q1, the gate voltage Vge_Q2, and the common mode current I when the range of the horizontal axis of FIG. 9 is changed from 2 μs / div to 200 ns / div. ＣＭ 11 is a diagram illustrating the operation of the power conversion device 100 according to the first embodiment. ＣＭ When the scale is changed from 2 A / div to 10 mA / div, the gate voltage Vge_Q1, gate voltage Vge_Q2, and common mode current I ＣＭ The respective waveforms are shown.

[0059] 9 to 11, in the power conversion device 100, the common mode current I ＣＭ It can be seen that the gate voltage of the third switching element Q3 falls during the dead time period (2 μs) before the gate voltage Vge_Q1 of the first switching element Q1 starts to rise, but the common mode current I ＣＭ It can be seen that the absolute value of is small.

[0060] 12 is a diagram illustrating the operation of the power conversion device 100 according to the first embodiment. The three waveforms in the upper part of FIG. 12 are the gate voltage (Vge_Q1) of the first switching element Q1 of the inverter circuit 1U, the gate voltage (Vge_Q2) of the second switching element Q2 of the inverter circuit 1U, and the common mode current I flowing from the power conversion device 100 to the ground conductor. ＣＭ 12. The three waveforms in the lower part of FIG. 12 are enlarged waveform diagrams of an area A2 including the three waveforms in the upper part of FIG. 12. For the waveforms in the lower part of FIG. 12, the scale of Vge_Q1 on the vertical axis is 25 V / div, the scale of Vge_Q2 on the vertical axis is 25 V / div, and the scale of the common mode current I ＣＭThe scale of the horizontal axis is 2 A / div. In the lower part of FIG. 12, the scale of the horizontal axis is 2 μs / div. FIG. 13 is a diagram illustrating the operation of the power conversion device 100 according to the first embodiment. FIG. 13 shows the gate voltage Vge_Q1, the gate voltage Vge_Q2, and the common mode current I when the range of the horizontal axis of FIG. 12 is changed from 2 μs / div to 200 ns / div. ＣＭ 14 is a diagram illustrating the operation of the power conversion device 100 according to the first embodiment. ＣＭ When the scale is changed from 2 A / div to 10 mA / div, the gate voltage Vge_Q1, gate voltage Vge_Q2, and common mode current I ＣＭ The respective waveforms are shown.

[0061] 12 to 14, in the power conversion device 100, the common mode current I ＣＭ The gate voltage of the fourth switching element Q4 falls during the dead time (2 μs) before the gate voltage Vge_Q2 of the second switching element Q2 starts to rise. However, the common mode current I ＣＭ It can be seen that the absolute value of is small.

[0062] FIG. 15 is a graph showing the relationship between dv / dt and Rg1 / Rg2 in the power conversion device 100 according to the first embodiment. FIG. 15 is a graph showing the relationship between Rg1 / Rg2 and the voltage change rate (dv / dt) when the value of Rg1 / Rg2, which is the ratio of the resistance value Rg1 of the first gate resistor 511 to the resistance value Rg2 of the second gate resistor 521 in the gate drive circuit 5, is changed. In FIG. 15 , "B1" indicates the dv / dt of the collector-emitter voltage Vce of the first switching element Q1, and "B2" indicates the dv / dt of the collector-emitter voltage Vce of the second switching element Q2. In the power conversion device 100, dv / dt can be reduced by increasing Rg1 / Rg2 to a value greater than 1. Furthermore, in the power conversion device 100, it is preferable to set the value of Rg1 / Rg2 to three or more times the value in order to reduce dv / dt. It can be seen from FIG. 15 that in the power conversion device 100, the larger the value of Rg1 / Rg2, the more dv / dt can be reduced.

[0063] Fig. 16 is a graph showing the frequency characteristics of the noise level when the value of Rg1 / Rg2 is changed in the power conversion device 100 according to embodiment 1. Fig. 16 shows that in the power conversion device 100, the noise level (noise voltage level) can be reduced by increasing the value of Rg1 / Rg2.

[0064] FIG. 17 is a waveform diagram of the gate voltage when the control device 4 performs voltage vector control in the power conversion device 100 according to the first embodiment. FIG. 17 shows the waveform of the gate voltage when the control device 4 performs voltage vector control with the carrier signal frequency set to 12 kHz. FIG. 18 is a waveform diagram of the gate voltage when the control device 4 performs PWM control in the power conversion device 100 according to the first embodiment. FIG. 18 shows the waveform of the gate voltage when the control device 4 performs PWM control instead of voltage vector control. As can be seen from FIGS. 17 and 18 , in the power conversion device 100, the control device 4 is configured to perform voltage vector control. This allows for a wider pulse width than when the control device 4 is configured to perform PWM control, thereby ensuring a larger width for generating the slope of the gate voltage waveform. This allows for a gate voltage that significantly exceeds the limit of PWM control when generating a gradual gate voltage change such as that shown in FIG. 4 . This demonstrates that noise can be reduced.

[0065] (4) Advantages In the power conversion device 100 according to the first embodiment, each of the multiple gate drive circuits 5 includes a gate driver 50, a first gate resistance circuit 51, and a second gate resistance circuit 52. The first gate resistance circuit 51 is connected between the gate driver 50 and a gate terminal of a corresponding one of the multiple switching elements 8. The first gate resistance circuit 51 includes a first gate resistor 511 and a first diode 512 through which a current flows when the corresponding switching element 8 is turned on. The second gate resistance circuit 52 is connected in parallel with the first gate resistance circuit 51. The second gate resistance circuit 52 includes a second gate resistor 521 and a second diode 522 through which a current flows when the corresponding switching element 8 is turned off. The resistance value Rg1 of the first gate resistor 511 is greater than the resistance value Rg2 of the second gate resistor 521.

[0066] The above configuration makes it possible to reduce noise. More specifically, the above configuration makes it possible to reduce noise (common mode noise) that occurs when the switching element 8 is turned on, and to reduce noise without adding a noise reduction circuit.

[0067] The power conversion device 100 according to the first embodiment further includes a plurality of (nine) bootstrap circuits 7 that supply power supply voltages to corresponding nine gate drive circuits 5 (second gate drive circuits 5B) among the plurality of (twelve) gate drive circuits 5. The control device 4 charges the plurality of bootstrap circuits 7 by space vector modulation.

[0068] According to the above configuration, it is possible to reduce noise while miniaturizing the power conversion device 100 .

[0069] (5) Modifications (5.1) Modification 1 The overall configuration of a power conversion device 100 according to Modification 1 of Embodiment 1 is the same as that shown in FIG. 1 , and therefore will not be illustrated or described again. FIG. 19 is a circuit diagram of a first gate drive circuit 5A in a power conversion device 100 according to Modification 1 of Embodiment 1. In Modification 1, as shown in FIG. 19 , the circuit configuration of the first gate resistance circuit 51 in the first gate drive circuit 5A differs from the circuit configuration of the first gate resistance circuit 51 in the first gate drive circuit 5A (see FIG. 2 ) of Embodiment 1. FIG. 20 is a circuit diagram of a second gate drive circuit 5B in a power conversion device 100 according to Modification 1 of Embodiment 1. In Modification 1, as shown in FIG. 20 , the circuit configuration of the first gate resistance circuit 51 in the second gate drive circuit 5B differs from the circuit configuration of the first gate resistance circuit 51 in the second gate drive circuit 5B (see FIG. 3 ) of Embodiment 1.

[0070] In each of the plurality of gate drive circuits 5 of Modification 1, the first gate resistor circuit 51 is a variable resistance circuit that can change the resistance value of the first gate resistor circuit 51. More specifically, the first gate resistor circuit 51 further includes an impedance adjustment element 513 connected in parallel to the first gate resistor 511, and the impedance of the impedance adjustment element 513 is controlled by the control device 4. The impedance adjustment element 513 is, for example, a normally-off n-channel metal oxide semiconductor field effect transistor (MOSFET).

[0071] The control device 4 controls the first gate resistance circuit 51 for each of the plurality of gate drive circuits 5 so that the resistance value of the first gate resistance circuit 51 becomes smaller than the resistance value Rg1 of the first gate resistance 511 after the voltage value of the gate voltage reaches the gate threshold voltage Vth (see FIGS. 21 and 22 ) of the corresponding switching element 8 among the plurality of switching elements 8. The gate threshold voltage Vth is a plateau voltage.

[0072] FIG. 21 is an explanatory diagram illustrating the operation of the power conversion device 100 according to Modification 1 of Embodiment 1. For each of the multiple gate drive circuits 5, as shown in FIG. 21 , the control device 4 controls the impedance adjustment element 513 to increase the resistance of the first gate resistor circuit 51, thereby reducing the gate current and the dv / dt of the gate voltage waveform, until the gate voltage starts to rise from a voltage value V3 of the third potential level and reaches the gate threshold voltage Vth, thereby generating a Miller effect. In FIG. 21 , the gate voltage starts to increase from time t0, and when it reaches the gate threshold voltage Vth at time t1, the Miller effect occurs, causing the gate voltage to become substantially constant. As soon as the Miller effect period begins, the control device 4 controls the impedance adjustment element 513 to decrease the resistance of the first gate resistor circuit 51 at time t2, thereby increasing the gate current and sharpening the rising edge of the gate voltage waveform. Furthermore, at time t4 after time t2, the control device 4 controls the impedance adjustment element 513 to increase the resistance of the first gate resistor circuit 51, thereby reducing the gate current and decreasing the dv / dt of the gate voltage waveform. In the example of FIG. 21 , the gate voltage reaches a high potential level voltage value V4 at time t5 and becomes substantially constant. The gate voltage waveform falls during the period from time t6 to time t8. In the example of FIG. 21 , focusing on dv / dt, the absolute value of (V4 - V3) / (time t5 - time t0) is smaller than the absolute value of (V3 - V4) / (time t8 - time t6).

[0073] FIG. 22 is an explanatory diagram of the operation of the power conversion device 100 according to Modification 1 of Embodiment 1. FIG. 21 illustrates a case in which the control device 4 controls the impedance adjustment element 513 so as not to change the duty of the gate voltage waveform from that shown in FIG. 4 . However, the control device 4 may also control the impedance adjustment element 513 so as to change the duty of the gate voltage waveform. In this case, the gate voltage waveform may have, for example, a waveform as shown in FIG. 22 . In FIGS. 21 and 22 , the duty is a value defined by T2 / T1. T1 is one period of the gate voltage waveform. T2 is the length between time t3, at which the voltage value becomes (V3+V4) / 2 when the gate voltage waveform rises, and time t7, at which the voltage value becomes (V3+V4) / 2 when the gate voltage waveform falls. In the example of FIG. 21 , one period of the gate voltage waveform is, for example, the length of the period between time t3 and time t9.

[0074] The power conversion device 100 according to the first modification can reduce noise, similarly to the power conversion device 100 according to the first embodiment.

[0075] (5.2) Modification 2 The configuration of the power conversion device 100 according to Modification 2 is the same as the configuration of the power conversion device 100 according to Modification 1, and the circuit configuration of the gate of the first gate resistor circuit 51 by the control device 4 is the same as the circuit configuration of Modification 1, so illustration and description thereof will be omitted.

[0076] The control device 4 controls the first gate resistance circuit 51 for each of the plurality of gate drive circuits 5 so that the resistance value of the first gate resistance circuit 51 becomes smaller than the resistance value Rg1 of the first gate resistance 511 before the voltage value of the gate voltage reaches the gate threshold voltage Vth (see FIGS. 23 and 24 ) of the corresponding switching element 8 among the plurality of switching elements 8. The gate threshold voltage Vth is a plateau voltage.

[0077] FIG. 23 is an explanatory diagram illustrating the operation of the power conversion device 100 according to Modification 2 of Embodiment 1. In Modification 2, for each of the multiple gate drive circuits 5, for example, as shown in FIG. 23 , when the gate voltage starts to rise from a voltage value V3 of the third potential level at time t0, the control device 4 controls the impedance adjustment element 513 to increase the gate current and increase the dv / dt of the gate voltage waveform. At time t1, before the gate voltage reaches the gate threshold voltage Vth (plateau voltage), the control device 4 controls the impedance adjustment element 513 to decrease the gate current and decrease the dv / dt of the gate voltage waveform. At time t2, the gate voltage reaches the gate threshold voltage Vth, generating the Miller effect. The gate voltage begins to increase from time t3, and at time t5, the control device 4 controls the impedance adjustment element 513 to increase the gate current and increase the dv / dt of the gate voltage waveform. In the example of FIG. 23 , the gate voltage reaches a voltage value V4 of the high potential level at time t6 and becomes substantially constant. The waveform of the gate voltage falls during the period from time t7 to time t9. In the example of Figure 23, when focusing on dv / dt, the absolute value of (V4 - V3) / (time t6 - time t0) is smaller than the absolute value of (V3 - V4) / (time t9 - time t7).

[0078] FIG. 24 is an explanatory diagram of the operation of the power conversion device 100 according to Modification 2 of Embodiment 1. FIG. 23 illustrates a case in which the control device 4 controls the impedance adjustment element 513 so as not to change the duty of the gate voltage waveform from that shown in FIG. 4 . However, the control device 4 may also control the impedance adjustment element 513 so as to change the duty of the gate voltage waveform. In this case, the gate voltage waveform may be, for example, as shown in FIG. 24 . In FIGS. 23 and 24 , the duty is a value defined by T2 / T1. T1 is one period of the gate voltage waveform. T2 is the length between time t4, at which the voltage value becomes (V3+V4) / 2 when the gate voltage waveform rises, and time t8, at which the voltage value becomes (V3+V4) / 2 when the gate voltage waveform falls.

[0079] The power conversion device 100 according to the second modification can reduce noise, similarly to the power conversion device 100 according to the first embodiment.

[0080] (5.3) Modification 3 The overall configuration of the power conversion device 100 according to Modification 3 of the first embodiment is the same as that shown in Fig. 1, and therefore will not be illustrated or described again. In Modification 3, the operation of the space vector modulation of the control device 4 differs from the operation of the space vector modulation of the control device 4 according to the first embodiment.

[0081] The control device 4 selects, from the voltage vectors in the first group, a first voltage vector, a second voltage vector, and a third voltage vector adjacent to the command voltage vector. Each of the voltage vectors in the first group is determined in a first vector space by a combination of the potential levels of the output points 13 of the three inverter circuits 1U, 1V, and 1W. The control device 4 changes the first voltage vector, the second voltage vector, and the third voltage vector to a combination of a zero vector and a fourth voltage vector and a fifth voltage vector adjacent to the command voltage vector in a second vector space different from the first vector space. Each of the voltage vectors in the second group is determined by a combination of the potential levels of the output points of the three inverter circuits 1U, 1V, and 1W. The zero vector is a voltage vector from the voltage vectors in the second group that is a combination of the potential levels of the output points of the three inverter circuits 1U, 1V, and 1W that is the potential of the negative pole N1 and the potential of the positive pole P1. The control device 4 controls the multiple (12) gate drive circuits 5 within a predetermined control period so that the composite vector of the zero vector, the fourth voltage vector, and the fifth voltage vector in the second vector space coincides with the command voltage vector.

[0082] The power conversion device 100 according to the third modification can reduce noise, similarly to the power conversion device 100 according to the first embodiment.

[0083] (5.4) Modification 4 The overall configuration of the power conversion device 100 according to Modification 4 of Embodiment 1 is the same as that shown in Fig. 1, and therefore will not be illustrated or described again. Modification 4 differs from the power conversion device 100 according to Embodiment 1 in that the control device 4 performs PWM control instead of voltage vector control.

[0084] The power conversion device 100 according to the fourth modification can reduce noise, similarly to the power conversion device 100 according to the first embodiment.

[0085] (Embodiment 2) A power conversion device 100A according to embodiment 2 will be described below with reference to Fig. 25. Note that, with respect to the power conversion device 100A according to embodiment 2, components similar to those of the power conversion device 100 according to embodiment 1 are denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0086] (1) Overall Configuration of the Power Conversion Device FIG. 25 is a circuit diagram of a power conversion device 100A according to the second embodiment. As shown in FIG. 25 , the power conversion device 100A includes, for example, a three-phase inverter circuit 2A, a plurality of (12 in the example of FIG. 25 ) gate drive circuits 5, and a control device 4. The three-phase inverter circuit 2A includes a plurality of (12 in the example of FIG. 25 ) switching elements 8 (three first switching elements Q1, three second switching elements Q2, three third switching elements Q3, and three fourth switching elements Q4). Each of the switching elements 8 has a gate terminal, a first main terminal, and a second main terminal. In this embodiment, each of the switching elements 8 is an insulated gate bipolar transistor (IGBT). The first main terminal and the second main terminal of each of the switching elements 8 are a collector terminal and an emitter terminal, respectively. The gate drive circuits 5 correspond one-to-one to the switching elements 8. The control device 4 outputs a plurality of control signals US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, and WS4 (12 in the example of FIG. 25 ) to the plurality of gate drive circuits 5, respectively. As shown in FIG. 2 or 3 , each of the plurality of gate drive circuits 5 includes a gate driver 50, a first gate resistance circuit 51, and a second gate resistance circuit 52. The first gate resistance circuit 51 is connected between the gate driver 50 and a gate terminal of a corresponding one of the plurality of switching elements 8. The first gate resistance circuit 51 includes a first gate resistor 511 and a first diode 512 through which a current flows when the corresponding switching element 8 is turned on. The second gate resistance circuit 52 is connected in parallel with the first gate resistance circuit 51. The second gate resistor circuit 52 includes a second gate resistor 521 and a second diode 522 through which a current flows when the corresponding switching element 8 is turned off.

[0087] 25, the power conversion device 100A further includes a DC power supply unit 3. The power conversion device 100A further includes a DC-DC converter 6.

[0088] In the power conversion device 100A, the three-phase inverter circuit 2A is a T-type three-level three-phase inverter circuit. In the power conversion device 100A, the three-phase inverter circuit 2A includes three inverter circuits 1U, 1V, and 1W, each of which has an output terminal 9. In the power conversion device 100A, AC loads are connected to the three output terminals 9.

[0089] The AC load is, for example, a three-phase servo motor. In the power conversion device 100A, one inverter circuit 1U of the three inverter circuits 1U, 1V, and 1W is an inverter circuit that outputs a U-phase voltage, another inverter circuit 1V is an inverter circuit that outputs a V-phase voltage, and the remaining inverter circuit 1W is an inverter circuit that outputs a W-phase voltage. In each of the three inverter circuits 1U, 1V, and 1W, the potential level of the output voltage changes in three levels depending on the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4. Note that the output voltage of the inverter circuit 1U, the output voltage of the inverter circuit 1V, and the output voltage of the inverter circuit 1W are out of phase with each other.

[0090] (2) Details of the Power Conversion Device The DC power supply unit 3 further has a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1.

[0091] In the DC power supply unit 3, a first end of the first capacitor C11 is connected to the positive electrode P1, a second end of the first capacitor C11 is connected to the first end of the second capacitor C12, and a second end of the second capacitor C12 is connected to the negative electrode N1. For example, an external power supply that outputs a DC output voltage is connected between the first DC terminal 31 and the second DC terminal 32. The series circuit of the first capacitor C11 and the second capacitor C12 forms a voltage divider circuit.

[0092] Each of the three inverter circuits 1U, 1V, and 1W includes a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4. Each of the three inverter circuits 1U, 1V, and 1W further includes four diodes D1 to D4. In each of the three inverter circuits 1U, 1V, and 1W, the diode D1 is connected in anti-parallel to the first switching element Q1. In each of the three inverter circuits 1U, 1V, and 1W, the diode D2 is connected in anti-parallel to the second switching element Q2. In each of the three inverter circuits 1U, 1V, and 1W, the diode D3 is connected in anti-parallel to the third switching element Q3. In each of the three inverter circuits 1U, 1V, and 1W, the diode D4 is connected in anti-parallel to the fourth switching element Q4.

[0093] In each of the three inverter circuits 1U, 1V, and 1W, the diode D1 may be substituted with a parasitic diode of the IGBT that constitutes the first switching element Q1. In each of the three inverter circuits 1U, 1V, and 1W, the diode D2 may be substituted with a parasitic diode of the IGBT that constitutes the second switching element Q2. In each of the three inverter circuits 1U, 1V, and 1W, the diode D3 may be substituted with a parasitic diode of the IGBT that constitutes the third switching element Q3. In each of the three inverter circuits 1U, 1V, and 1W, the diode D4 may be substituted with a parasitic diode of the IGBT that constitutes the fourth switching element Q4.

[0094] In each of the three inverter circuits 1U, 1V, and 1W, the first switching element Q1 and the second switching element Q2 are connected in series from the positive electrode P1 side to the negative electrode N1 side in the order of the first switching element Q1 and the second switching element Q2. That is, as shown in FIG. 25 , a series circuit of the first switching element Q1 and the second switching element Q2 is connected between the positive electrode P1 and the negative electrode N1. In each of the three inverter circuits 1U, 1V, and 1W, a series circuit of the third switching element Q3 and the fourth switching element Q4 is connected between the intermediate potential point M1 and an output point 13. The output point 13 is the connection point between the first switching element Q1 and the second switching element Q2. The output point 13 is not limited to the connection point between the first switching element Q1 and the second switching element Q2, but may also be a node between the second main terminal of the first switching element Q1 and the first main terminal of the second switching element Q2. Each of the three inverter circuits 1U, 1V, and 1W has a bidirectional switch including a third switching element Q3, a fourth switching element Q4, and diodes D3 and D4. In each of the three inverter circuits 1U, 1V, and 1W, the bidirectional switch is a common-emitter bidirectional switch in which second main terminals (emitter terminals) of the third switching element Q3 and the fourth switching element Q4 are connected to each other.

[0095] In the second embodiment, when the voltage between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3 is Vdc, the potential difference between the positive electrode P1 of the DC power supply unit 3 and the intermediate potential point M1 is approximately Vdc / 2, and the potential difference between the negative electrode N1 and the intermediate potential point M1 is approximately Vdc / 2.

[0096] A corresponding one of the plurality of gate drive circuits 5 is connected between the gate terminal of each of the plurality of switching elements 8 and the second main terminal. Each of the plurality of switching elements 8 is driven (turned on and off) by a corresponding one of the plurality of gate drive circuits 5.

[0097] The plurality of gate drive circuits 5 are connected to the control device 4. Each of the plurality of gate drive circuits 5 is connected between the gate terminal of a corresponding one of the plurality of switching elements 8 and the second main terminal.

[0098] The multiple gate drive circuits 5 include three gate drive circuits 5 (hereinafter also referred to as first gate drive circuits 5A) that correspond one-to-one to the three second switching elements Q2, and nine gate drive circuits 5 (hereinafter also referred to as second gate drive circuits 5B) that correspond one-to-one to the three first switching elements Q1, three third switching elements Q3, and three fourth switching elements Q4.

[0099] Each of the multiple gate drive circuits 5 controls the on / off state of the switching element 8 based on a control signal provided thereto. More specifically, the gate drive circuit 5 connected to the first switching element Q1 of the inverter circuit 1U controls the on / off state of the switching element 8 based on a control signal US1. The gate drive circuit 5 connected to the second switching element Q2 of the inverter circuit 1U controls the on / off state of the switching element 8 based on a control signal US2. The gate drive circuit 5 connected to the third switching element Q3 of the inverter circuit 1U controls the on / off state of the switching element 8 based on a control signal US3. The gate drive circuit 5 connected to the fourth switching element Q4 of the inverter circuit 1U controls the on / off state of the switching element 8 based on a control signal US4. The gate drive circuit 5 connected to the first switching element Q1 of the inverter circuit 1V controls the on / off state of the switching element 8 based on a control signal VS1. The gate drive circuit 5 connected to the second switching element Q2 of the inverter circuit 1V controls the on / off state of the switching element 8 based on a control signal VS2. The gate drive circuit 5 connected to the third switching element Q3 of the inverter circuit 1V controls the on / off state of the switching element 8 based on a control signal VS3. The gate drive circuit 5 connected to the fourth switching element Q4 of the inverter circuit 1V controls the on / off state of the switching element 8 based on a control signal VS4. The gate drive circuit 5 connected to the first switching element Q1 of the inverter circuit 1W controls the on / off state of the switching element 8 based on a control signal WS1. The gate drive circuit 5 connected to the second switching element Q2 of the inverter circuit 1W controls the on / off state of the switching element 8 based on a control signal WS2. The gate drive circuit 5 connected to the third switching element Q3 of the inverter circuit 1W controls the on / off state of the switching element 8 based on a control signal WS3. The gate drive circuit 5 connected to the fourth switching element Q4 of the inverter circuit 1W controls the on / off state of the switching element 8 based on a control signal WS4.

[0100] The circuit configuration of the plurality of gate drive circuits 5 is the same as that of embodiment 1. Therefore, each of the plurality of gate drive circuits 5 has a gate driver 50, a first gate resistance circuit 51, and a second gate resistance circuit 52, as shown in FIG.

[0101] The first gate resistance circuit 51 is connected between the gate terminal of a corresponding one of the multiple switching elements 8 and the gate driver 50. The first gate resistance circuit 51 includes a first gate resistor 511 and a first diode 512 through which a current flows when the corresponding switching element 8 is turned on. In the first gate resistance circuit 51 of this embodiment, a first end of the first gate resistor 511 is connected to the output terminal 503 of the gate driver 50, a second end of the first gate resistor 511 is connected to the anode of the first diode 512, and a cathode of the first diode 512 is connected to the gate terminal of the switching element 8.

[0102] The second gate resistance circuit 52 is connected in parallel to the first gate resistance circuit 51. The second gate resistance circuit 52 includes a second gate resistance 521 and a second diode 522 through which a current flows when the corresponding switching element 8 is turned off. In the second gate resistance circuit 52 of this embodiment, a first end of the second gate resistance 521 is connected to the output terminal 503 of the gate driver 50, a second end of the second gate resistance 521 is connected to the anode of the second diode 522, and a cathode of the second diode 522 is connected to the gate terminal of the switching element 8.

[0103] In each of the plurality of gate drive circuits 5, the resistance value Rg1 of the first gate resistor 511 is greater than the resistance value Rg2 of the second gate resistor 521.

[0104] Each of the three first gate drive circuits 5A is configured to be able to switch the output voltage of the gate driver 50 between a positive voltage (e.g., 15 V) and a negative voltage (e.g., −9 V) that are higher than the gate threshold voltage of the IGBT, based on a corresponding one of the control signals US2, VS2, and WS2. Each of the three first gate drive circuits 5A is configured to be able to apply a positive voltage between the gate terminal and the second main terminal of a corresponding one of the multiple switching elements 8, and to apply a negative voltage between the gate terminal and the second main terminal of the corresponding one of the switching elements 8. More specifically, as shown in FIG. 2 , each of the three first gate drive circuits 5A includes a gate driver 50, a first gate resistor circuit 51, and a second gate resistor circuit 52, as well as a bipolar power supply circuit (positive / negative power supply circuit) 53 that outputs a positive voltage and a negative voltage. The bipolar power supply circuit 53 has, for example, a positive input terminal 531, a negative input terminal 532, a reference output terminal 533, a high-potential output terminal 534, and a low-potential output terminal 535. The bipolar power supply circuit 53 also has a smoothing capacitor C53, a resistor 556, two smoothing capacitors C54 and C55 connected in series, a Zener diode 557, a resistor 558, and two capacitors C56 and C57 connected in series. The positive input terminal 531 and the negative input terminal 532 of the bipolar power supply circuit 53 are connected to the positive output terminal and the negative output terminal of the DC-DC converter 6, respectively. In the bipolar power supply circuit 53, a positive voltage of 15 V is output between the high-potential output terminal 534 and the reference output terminal 533, with the potential of the reference output terminal 533 serving as a reference potential. In addition, in the bipolar power supply circuit 53, a negative voltage of -9V is output between the low potential side output terminal 535 and the reference output terminal 533, with the potential of the reference output terminal 533 being used as the reference potential.

[0105] 2 , in each of the three first gate drive circuits 5A, the high-potential output terminal 534 of the bipolar power supply circuit 53 is connected to the positive power supply terminal 504 of the gate driver 50, and the low-potential output terminal 535 is connected to the negative power supply terminal 505 of the gate driver 50. The reference output terminal 533 is connected to the second main terminal of the switching element 8.

[0106] Each of the nine second gate drive circuits 5B is configured to be able to switch the output voltage of the gate driver 50 between a voltage higher than the gate threshold voltage of the IGBT (e.g., 15 V) and 0 V, based on a corresponding one of the control signals US1, US3, US4, VS1, VS3, VS4, WS1, WS3, and WS4. More specifically, each of the nine second gate drive circuits 5B includes a gate driver 50, a first gate resistance circuit 51, and a second gate resistance circuit 52, as shown in FIG. 3 , and has a first end of a capacitor C1 of the bootstrap circuit 7 connected to a positive power supply terminal 504 of the gate driver 50 and a second end of the capacitor C1 connected to a negative power supply terminal 505 of the gate driver 50.

[0107] The DC-DC converter 6 is, for example, an isolated DC-DC converter that boosts a first voltage (for example, 5 V) and outputs a second voltage (for example, 24 V). The first voltage is, for example, a voltage input to the DC-DC converter 6 from a DC power supply (not shown) connected between the positive and negative input terminals of the DC-DC converter 6.

[0108] The DC-DC converter 6 supplies voltage to the six bootstrap circuits 7 and the three first gate drive circuits 5A.

[0109] Each of the six bootstrap circuits 7 corresponds to one of the nine second gate drive circuits 5B. Each of the six bootstrap circuits 7 supplies a voltage to a corresponding one of the nine second gate drive circuits 5B. Each of the six bootstrap circuits 7 includes a diode D1, a resistor R1, and a capacitor C1. As shown in FIG. 3 , in each of the six bootstrap circuits 7, a first end of the capacitor C1 is connected to the positive power supply terminal 504 of the gate driver 50 in the corresponding gate drive circuit 5, and a second end of the capacitor C1 is connected to the negative power supply terminal 505 of the gate driver 50. The bootstrap circuit 7 supplies the gate driver 50 with a voltage required to turn on the switching element 8 in the gate driver 50.

[0110] In the bootstrap circuit 7 connected to the second gate drive circuit 5 B corresponding to the first switching element Q 1 , the anode of the diode D 1 is connected to the positive terminal of the DC-DC converter 6 .

[0111] In the bootstrap circuit 7 connected to the second gate drive circuit 5B corresponding to the third switching element Q3 and the fourth switching element Q4, the anode of the diode D1 is connected to the positive terminal of the DC-DC converter 6.

[0112] The control device 4 generates, for example, control signals US1 to US4 for the first switching element Q1 to the fourth switching element Q4 of the inverter circuit 1U, control signals VS1 to VS4 for the first switching element Q1 to the fourth switching element Q4 of the inverter circuit 1V, and control signals WS1 to WS4 for the first switching element Q1 to the fourth switching element Q4 of the inverter circuit 1W based on a U-phase voltage command, a V-phase voltage command, and a W-phase voltage command relating to the output voltages of the inverter circuits 1U, 1V, and 1W, respectively.

[0113] The U-phase voltage command, the V-phase voltage command, and the W-phase voltage command are, for example, sinusoidal signals whose phases are different from each other by 120°, and whose values ​​(voltage command values) change over time. The U-phase voltage command, the V-phase voltage command, and the W-phase voltage command have the same cycle length. The control device 4 may perform proportional integral (PI) control of the U-phase voltage command, the V-phase voltage command, and the W-phase voltage command based on information output from a detection unit (not shown) that detects the state of the AC load. When the AC load is a three-phase servo motor, the information output from the detection unit includes, for example, at least one of information on the detection results of multiple current sensors that detect output currents flowing through the U-phase terminals, the V-phase terminals, and the W-phase terminals of the three-phase servo motor, and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase servo motor.

[0114] The control device 4 outputs a plurality of control signals US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, and WS4. The control signals US1, US2, US3, and US4 are provided to gate drive circuits 5 connected to the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the inverter circuit 1U, respectively. The control signals VS1, VS2, VS3, and VS4 are provided to gate drive circuits 5 connected to the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the inverter circuit 1U, respectively. The control signals WS1, WS2, WS3, and WS4 are provided to gate drive circuits 5 connected to the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the inverter circuit 1U, respectively.

[0115] Each of the multiple control signals US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, and WS4 is a signal whose potential level changes between, for example, a first potential level V1 (see FIG. 4) and a second potential level V2 (see FIG. 4) that is higher than the first potential level V1.

[0116] The first potential level V1 is, for example, 0 V, and the second potential level V2 is, for example, a potential level that can make conductive an input stage diode included in the gate driver 50 of the gate drive circuit 5. The input stage diode is, for example, a light-emitting diode of a photocoupler, but is not limited to a light-emitting diode.

[0117] The control device 4 controls the plurality of gate drive circuits 5 by performing voltage vector control.

[0118] In this embodiment, when performing voltage vector control, the control device 4 generates control signals US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, and WS4 using space vector modulation. The control device 4 also charges multiple bootstrap circuits 7 using space vector modulation. The voltage vector control using space vector modulation in this embodiment will be described in more detail below.

[0119] The control device 4 selects, for example, a plurality of voltage vectors adjacent to the command voltage vector from a group (27 voltage vectors). Each of the group of voltage vectors is determined by a combination of the potential levels of the three output points 13 of the three inverter circuits 1U, 1V, and 1W. The group of voltage vectors includes 12 voltage vectors each having a reference magnitude, 6 voltage vectors each having a magnitude twice the reference magnitude, and 12 voltage vectors each having a magnitude three times the reference magnitude. １／２ The control device 4 replaces one of two first voltage vectors, which have a reference magnitude and are closest to the command voltage vector, with a zero vector (third zero vector) of a combination in which the potential levels of the three output points in the three inverter circuits 1U, 1V, and 1W are the potential of the negative pole N1, and a second voltage vector having the same direction as the first voltage vector but twice the magnitude of the first voltage vector. The control device 4 controls the multiple (12) gate drive circuits 5 within a predetermined control period so that the composite vector of the voltage vectors other than the first voltage vector, the third zero vector, and the second voltage vector among the multiple voltage vectors matches the command voltage vector.

[0120] The executing entity of the control device 4 includes a computer system. The computer system has one or more computers. The computer system is mainly composed of a processor and memory as hardware. The processor executes a program recorded in the memory of the computer system to realize the function of the executing entity of the control device 4 in the present disclosure. The program may be pre-recorded in the memory of the computer system, provided via a telecommunications line, or recorded and provided on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The multiple electronic circuits may be integrated into a single chip or distributed across multiple chips. The multiple chips may be integrated into a single device or distributed across multiple devices.

[0121] (3) Advantages In the power conversion device 100A according to the second embodiment, each of the multiple gate drive circuits 5 includes a gate driver 50, a first gate resistance circuit 51, and a second gate resistance circuit 52. The first gate resistance circuit 51 is connected between the gate driver 50 and a gate terminal of a corresponding one of the multiple switching elements 8. The first gate resistance circuit 51 includes a first gate resistor 511 and a first diode 512 through which a current flows when the corresponding switching element 8 is turned on. The second gate resistance circuit 52 is connected in parallel with the first gate resistance circuit 51. The second gate resistance circuit 52 includes a second gate resistor 521 and a second diode 522 through which a current flows when the corresponding switching element 8 is turned off. The resistance value Rg1 of the first gate resistor 511 is greater than the resistance value Rg2 of the second gate resistor 521.

[0122] The above configuration makes it possible to reduce noise. More specifically, the above configuration makes it possible to reduce noise (common mode noise) that occurs when the switching element 8 is turned on, and to reduce noise without adding a noise reduction circuit.

[0123] The power conversion device 100A according to the second embodiment further includes a plurality of (six) bootstrap circuits 7 that supply power supply voltages to corresponding nine gate drive circuits 5 (second gate drive circuits 5) among the plurality of (twelve) gate drive circuits 5. The control device 4 charges the plurality of bootstrap circuits 7 by space vector modulation.

[0124] According to the above configuration, it is possible to reduce noise while miniaturizing the power conversion device 100A.

[0125] (4) Modifications In the power conversion device 100A according to the second embodiment, similarly to the first and second modifications of the first embodiment, the control device 4 may be configured to control the impedance adjustment element 513 by employing the gate drive circuits 5 of FIGS. 19 and 20 instead of the gate drive circuits 5 of FIGS. 2 and 3 , respectively.

[0126] In addition, in the power conversion device 100A of embodiment 2, the control device 4 may be configured to perform space vector modulation operations similar to those of the control device 4 of the power conversion device 100 of variant 3 of embodiment 1.

[0127] In the power conversion device 100A according to the second embodiment, the control device 4 may be configured to perform PWM control instead of voltage vector control.

[0128] (Embodiment 3) A power conversion device 100B according to embodiment 3 will be described below with reference to Fig. 26. Note that, with respect to the power conversion device 100B according to embodiment 3, components similar to those of the power conversion device 100 according to embodiment 1 are denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0129] (1) Overall Configuration of the Power Conversion Device FIG. 26 is a circuit diagram of a power conversion device 100B according to the third embodiment. As shown in FIG. 26 , the power conversion device 100B includes, for example, a three-phase inverter circuit 2B, a plurality of (six in the example of FIG. 26 ) gate drive circuits 5, and a control device 4B. The three-phase inverter circuit 2B includes a plurality of (six in the example of FIG. 26 ) switching elements 8 (three first switching elements Q1 and three second switching elements Q2). Each of the switching elements 8 has a gate terminal, a first main terminal, and a second main terminal. In this embodiment, each of the switching elements 8 is an insulated gate bipolar transistor (IGBT). The first main terminal and the second main terminal of each of the switching elements 8 are a collector terminal and an emitter terminal, respectively. The gate drive circuits 5 correspond one-to-one to the switching elements 8. The control device 4B outputs multiple (six in the example of FIG. 26 ) control signals US1, US2, VS1, VS2, WS1, and WS2 to the multiple gate drive circuits 5, respectively. Each of the multiple gate drive circuits 5 includes, for example, a gate driver 50, a first gate resistance circuit 51, and a second gate resistance circuit 52, as shown in FIG. 2 . The first gate resistance circuit 51 is connected between the gate driver 50 and a gate terminal of a corresponding one of the multiple switching elements 8. The first gate resistance circuit 51 includes a first gate resistor 511 and a first diode 512 through which a current flows when the corresponding switching element 8 is turned on. The second gate resistance circuit 52 is connected in parallel with the first gate resistance circuit 51. The second gate resistance circuit 52 includes a second gate resistor 521 and a second diode 522 through which a current flows when the corresponding switching element 8 is turned off.

[0130] 26 , the power conversion device 100B further includes a first input terminal 21, a second input terminal 22, and a capacitor C10. In the power conversion device 100B, for example, a DC power supply (not shown) is connected between the first input terminal 21 and the second input terminal 22. The capacitor C10 is connected between the first input terminal 21 and the second input terminal 22.

[0131] The power conversion device 100B further includes six DC-DC converters (not shown). The six DC-DC converters correspond one-to-one to the six gate drive circuits 5, and output DC voltages to the corresponding gate drive circuits 5.

[0132] In the power conversion device 100B, the three-phase inverter circuit 2B includes three inverter circuits 1U, 1V, and 1W, and each of the three inverter circuits 1U, 1V, and 1W has an output terminal 9. In the power conversion device 100B, AC loads are connected to the three output terminals 9.

[0133] The AC load is, for example, a three-phase servo motor. In the power conversion device 100B, one inverter circuit 1U of the three inverter circuits 1U, 1V, and 1W is an inverter circuit that outputs a U-phase voltage, another inverter circuit 1V is an inverter circuit that outputs a V-phase voltage, and the remaining inverter circuit 1W is an inverter circuit that outputs a W-phase voltage. Note that the output voltages of the inverter circuits 1U, 1V, and 1W are out of phase with each other.

[0134] (2) Details of the Power Conversion Device Each of the three inverter circuits 1U, 1V, and 1W has a first switching element Q1 and a second switching element Q2 connected in series to each other.

[0135] Each of the three inverter circuits 1U, 1V, and 1W includes a first switching element Q1 and a second switching element Q2. Each of the three inverter circuits 1U, 1V, and 1W further includes two diodes D1 and D2. In each of the three inverter circuits 1U, 1V, and 1W, the diode D1 is connected in anti-parallel to the first switching element Q1. In each of the three inverter circuits 1U, 1V, and 1W, the diode D2 is connected in anti-parallel to the second switching element Q2.

[0136] In each of the three inverter circuits 1U, 1V, and 1W, the diode D1 may be substituted with a parasitic diode of the IGBT that constitutes the first switching element Q1. Also, in each of the three inverter circuits 1U, 1V, and 1W, the diode D2 may be substituted with a parasitic diode of the IGBT that constitutes the second switching element Q2.

[0137] In each of the three inverter circuits 1U, 1V, and 1W, the first switching element Q1 and the second switching element Q2 are connected in series from the positive electrode P1 side to the negative electrode N1 side in the order of the first switching element Q1 and the second switching element Q2. That is, as shown in FIG. 26 , a series circuit of the first switching element Q1 and the second switching element Q2 is connected between the positive electrode P1 and the negative electrode N1. The output point 13 of each of the three inverter circuits 1U, 1V, and 1W is the connection point between the first switching element Q1 and the second switching element Q2. The output point 13 is not limited to the connection point between the first switching element Q1 and the second switching element Q2, but may also be a node between the second main terminal of the first switching element Q1 and the first main terminal of the second switching element Q2.

[0138] The control device 4 generates and outputs control signals US1, US2, VS1, VS2, WS1, and WS2 based on, for example, the detected values ​​of the U-phase current, the V-phase current, and the W-phase current. Each of the control signals US1, US2, VS1, VS2, WS1, and WS2 is, for example, a PWM (Pulse Width Modulation) signal.

[0139] The control signal US1 is input to the gate drive circuit 5 connected to the first switching element Q1 of the inverter circuit 1U. The control signal US2 is input to the gate drive circuit 5 connected to the second switching element Q2 of the inverter circuit 1U. The control signal VS1 is input to the gate drive circuit 5 connected to the first switching element Q1 of the inverter circuit 1V. The control signal VS2 is input to the gate drive circuit 5 connected to the second switching element Q2 of the inverter circuit 1V. The control signal WS1 is input to the gate drive circuit 5 connected to the first switching element Q1 of the inverter circuit 1W. The control signal WS2 is input to the gate drive circuit 5 connected to the second switching element Q2 of the inverter circuit 1W.

[0140] The executing entity of the control device 4B includes a computer system. The computer system has one or more computers. The computer system is mainly composed of a processor and memory as hardware. The processor executes a program recorded in the memory of the computer system, thereby realizing the function of the executing entity of the control device 4B in the present disclosure. The program may be pre-recorded in the memory of the computer system, provided via a telecommunications line, or recorded and provided on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The multiple electronic circuits may be integrated into a single chip or distributed across multiple chips. The multiple chips may be integrated into a single device or distributed across multiple devices.

[0141] (3) Characteristics FIG. 27 is a graph showing the relationship between dv / dt and Rg1 / Rg2 in the power conversion device 100B according to the third embodiment. FIG. 27 is a graph showing the relationship between Rg1 / Rg2 and the voltage change rate (dv / dt) when the value of Rg1 / Rg2, which is the ratio of the resistance value Rg1 of the first gate resistor 511 to the resistance value Rg2 of the second gate resistor 521 in the gate drive circuit 5, is changed. In FIG. 27 , dv / dt represents the dv / dt of the collector-emitter voltage Vce of the first switching element Q1. In the power conversion device 100B, by making Rg1 / Rg2 greater than 1, it is possible to reduce dv / dt. Furthermore, in the power conversion device 100B, it is preferable to make the value of Rg1 / Rg2 three times or more in order to reduce dv / dt. It can be seen from FIG. 27 that in the power conversion device 100B, the larger the value of Rg1 / Rg2, the more dv / dt can be reduced.

[0142] (4) Advantages In the power conversion device 100B according to the third embodiment, each of the multiple gate drive circuits 5 includes a gate driver 50, a first gate resistance circuit 51, and a second gate resistance circuit 52. The first gate resistance circuit 51 is connected between the gate driver 50 and a gate terminal of a corresponding one of the multiple switching elements 8. The first gate resistance circuit 51 includes a first gate resistor 511 and a first diode 512 through which a current flows when the corresponding switching element 8 is turned on. The second gate resistance circuit 52 is connected in parallel with the first gate resistance circuit 51. The second gate resistance circuit 52 includes a second gate resistor 521 and a second diode 522 through which a current flows when the corresponding switching element 8 is turned off. The resistance value Rg1 of the first gate resistor 511 is greater than the resistance value Rg2 of the second gate resistor 521.

[0143] The above configuration makes it possible to reduce noise. More specifically, the above configuration makes it possible to reduce noise (common mode noise) that occurs when the switching element 8 is turned on, and to reduce noise without adding a noise reduction circuit.

[0144] (5) Modifications In the power conversion device 100B according to the third embodiment, similarly to the first and second modifications of the first embodiment, the control device 4B may be configured to control the impedance adjustment element 513 by employing the gate drive circuits 5 of FIGS. 19 and 20 instead of the gate drive circuits 5 of FIGS. 2 and 3 .

[0145] Furthermore, the control device 4B is not limited to being configured to perform PWM control, but may also be configured to perform voltage vector control.

[0146] (Other Modifications) The above-described first to third embodiments are merely examples of various embodiments of the present disclosure. The above-described first to third embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0147] For example, each of the multiple switching elements 8 is not limited to an IGBT but may be a MOSFET. In this case, the first main terminal and the second main terminal of each of the multiple switching elements 8 are a drain terminal and a source terminal, respectively. The MOSFET constituting each of the multiple switching elements 8 is, for example, a normally-off n-channel MOSFET. Note that although the MOSFET is a Si-based MOSFET, it is not limited to a Si-based MOSFET and may be, for example, a SiC-based MOSFET.

[0148] In the first and second embodiments, each of the bootstrap circuits 7 may include a Zener diode connected in parallel to the capacitor C1.

[0149] (Aspects) The following aspects are disclosed in this specification.

[0150] A power conversion device (100; 100A; 100B) according to a first aspect includes a three-phase inverter circuit (2; 2A; 2B), a plurality of gate drive circuits (5), and a control device (4). The three-phase inverter circuit (2) includes a plurality of switching elements (8). Each of the plurality of switching elements (8) has a gate terminal. The plurality of gate drive circuits (5) correspond one-to-one to the plurality of switching elements (8). The control device (4) outputs a plurality of control signals (US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, WS4; US1, US3, VS1, VS3, WS1, WS3) to be applied to each of the plurality of gate drive circuits (5). Each of the multiple gate drive circuits (5) includes a gate driver (50), a first gate resistor circuit (51), and a second gate resistor circuit (52). The first gate resistor circuit (51) is connected between the gate driver (50) and a gate terminal of a corresponding switching element (8) among the multiple switching elements (8). The first gate resistor circuit (51) includes a first gate resistor (511) and a first diode (512) through which a current flows when the corresponding switching element (8) is turned on. The second gate resistor circuit (52) is connected in parallel to the first gate resistor circuit (51). The second gate resistor circuit (52) includes a second gate resistor (521) and a second diode (522) through which a current flows when the corresponding switching element (8) is turned off. The resistance value (Rg1) of the first gate resistor (511) is greater than the resistance value (Rg2) of the second gate resistor (521).

[0151] According to this aspect, it is possible to reduce noise.

[0152] In the power conversion device (100; 100A; 100B) according to the second aspect, in the first aspect, the resistance value (Rg1) of the first gate resistor (511) is three times or more the resistance value (Rg2) of the second gate resistor (521).

[0153] A power conversion device (100; 100A; 100B) according to a third aspect is based on the first or second aspect. In each of the plurality of gate drive circuits (5), the first gate resistor circuit (51) is a variable resistance circuit that varies the resistance value of the first gate resistor circuit (51). A control device (4) controls the first gate resistor circuit (51) for each of the plurality of gate drive circuits (5) so that the resistance value of the first gate resistor circuit (51) becomes smaller than the resistance value (Rg1) of the first gate resistor (511) after the voltage value of the gate voltage reaches a gate threshold voltage (Vth) of a corresponding one of the plurality of switching elements (8).

[0154] A power conversion device (100; 100A; 100B) according to a fourth aspect is based on the first or second aspect. In each of the plurality of gate drive circuits (5), the first gate resistor circuit (51) is a variable resistance circuit that varies the resistance value of the first gate resistor circuit (51). A control device (4) controls the first gate resistor circuit (51) for each of the plurality of gate drive circuits (5) so that the resistance value of the first gate resistor circuit (51) becomes smaller than the resistance value (Rg1) of the first gate resistor (511) before the voltage value of the gate voltage reaches the gate threshold voltage (Vth) of a corresponding one of the plurality of switching elements (8).

[0155] In a power conversion device (100; 100A; 100B) according to a fifth aspect, in any one of the first to fourth aspects, the control device (4) generates control signals (US1, US2, US3, US4, VS1, VS2, VS3, VS4, WS1, WS2, WS3, WS4; US1, US3, VS1, VS3, WS1, WS3) by space vector modulation.

[0156] In the power conversion device (100) according to a sixth aspect, in any one of the first to fifth aspects, the three-phase inverter circuit (2) is a diode-clamped three-level three-phase inverter circuit.

[0157] In a power conversion device (100A) according to a seventh aspect, in any one of the first to fifth aspects, the three-phase inverter circuit (2A) is a T-type three-level three-phase inverter circuit.

[0158] The power conversion device (100; 100A) according to an eighth aspect is the sixth or seventh aspect, further comprising a plurality of bootstrap circuits (7) that supply power supply voltages to corresponding gate drive circuits (5) among the plurality of gate drive circuits (5). The control device (4) charges the plurality of bootstrap circuits (7) by space vector modulation.

[0159] According to this aspect, it is possible to reduce noise while miniaturizing the power conversion device (100; 100A).

[0160] The power conversion device of the present disclosure can reduce noise, and is thus industrially useful.

[0161] 2, 2A, 2B Three-phase inverter circuit 4, 4B Control device 5 Gate drive circuit 5A First gate drive circuit 5B Second gate drive circuit 50 Gate driver 51 First gate resistance circuit 511 First gate resistance 512 First diode 52 Second gate resistance circuit 521 Second gate resistance 522 Second diode 7 Bootstrap circuit 8 Switching element 100, 100A, 100B Power conversion device Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element

Claims

1. A power conversion device comprising: a three-phase inverter circuit including a plurality of switching elements, each having a gate terminal; a plurality of gate drive circuits corresponding one-to-one to the plurality of switching elements; and a control device that outputs a plurality of control signals to be given to each of the plurality of gate drive circuits, wherein each of the plurality of gate drive circuits has: a gate driver; a first gate resistor circuit connected between the gate driver and a gate terminal of a corresponding one of the plurality of switching elements, the first gate resistor and a first diode through which a current flows when the corresponding switching element is turned on; and a second gate resistor circuit connected in parallel to the first gate resistor circuit, the second gate resistor and a second diode through which a current flows when the corresponding switching element is turned off, wherein the resistance value of the first gate resistor is greater than the resistance value of the second gate resistor.

2. The power conversion device according to claim 1, wherein the resistance value of the first gate resistor is three times or more the resistance value of the second gate resistor.

3. The power conversion device according to claim 1 or 2, wherein, in each of the plurality of gate drive circuits, the first gate resistance circuit is a variable resistance circuit that varies the resistance value of the first gate resistance circuit, and the control device controls, for each of the plurality of gate drive circuits, the first gate resistance circuit so that the resistance value of the first gate resistance circuit becomes smaller than the resistance value of the first gate resistor after the voltage value of the gate voltage reaches a gate threshold voltage of a corresponding switching element among the plurality of switching elements.

4. The power conversion device according to claim 1 or 2, wherein in each of the plurality of gate drive circuits, the first gate resistance circuit is a variable resistance circuit that varies the resistance value of the first gate resistance circuit, and the control device controls the first gate resistance circuit for each of the plurality of gate drive circuits so that the resistance value of the first gate resistance circuit becomes smaller than the resistance value of the first gate resistor before the voltage value of the gate voltage reaches the gate threshold voltage of a corresponding one of the plurality of switching elements.

5. The power conversion device according to any one of claims 1 to 4, wherein the control device generates the control signal by space vector modulation.

6. The power conversion device according to any one of claims 1 to 5, wherein the three-phase inverter circuit is a diode-clamped three-level three-phase inverter circuit.

7. The power conversion device according to any one of claims 1 to 5, wherein the three-phase inverter circuit is a T-type three-level three-phase inverter circuit.

8. The power conversion device according to claim 6 or 7, further comprising a plurality of bootstrap circuits that supply power supply voltages to corresponding gate drive circuits among the plurality of gate drive circuits, and the control device charges the plurality of bootstrap circuits by space vector modulation.

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