Layered structure

Abstract

This layered structure comprises: an amorphous substrate; a crystalline first buffer layer on the amorphous substrate; an amorphous second buffer layer on the first buffer layer; and a nitride semiconductor layer on the second buffer layer. The amorphous substrate may be a glass substrate. The first buffer layer may include a first element, and the second buffer layer may include a compound containing the first element. The compound containing the first element may be an oxide. The first element may be titanium.

Description

Laminated structure

[0001] An embodiment of the present invention relates to a stacked layer structure including a nitride semiconductor layer.

[0002] Nitride semiconductors such as gallium nitride (GaN) are characterized by being direct transition semiconductors with a wide band gap. Taking advantage of the characteristics of gallium nitride, light-emitting diodes (LEDs) using gallium nitride have already been put to practical use. Gallium nitride also has the characteristics of high electron saturation mobility and high breakdown voltage. In recent years, the development of transistors for high-frequency power devices has been progressing by utilizing these characteristics of gallium nitride. Gallium nitride films for light-emitting diodes or transistors are generally formed on sapphire substrates at high temperatures of 800°C to 1000°C using metal organic chemical vapor deposition (MOCVD) or hydride vapor phase epitaxy (HVPE).

[0003] Recently, development of so-called micro LED display devices or mini LED display devices, which incorporate tiny LED chips within the pixels of a circuit board, has been progressing as next-generation display devices. Micro LED display devices or mini LED display devices have high efficiency, high brightness, and high reliability. Such micro LED display devices or mini LED display devices are manufactured by transferring LED chips to a backplane on which transistors made of oxide semiconductors or low-temperature polysilicon are formed (see, for example, Patent Document 1). A method of forming a gallium nitride transistor and a light-emitting diode on the same substrate has also been investigated (see, for example, Patent Document 2).

[0004] U.S. Patent No. 8,791,474 U.S. Patent Application Publication No. 2020 / 0075664

[0005] As mentioned above, gallium nitride films are generally formed on sapphire substrates at high temperatures. However, sapphire substrates are difficult to enlarge and are difficult to use as backplanes. Therefore, there is a demand for gallium nitride films formed on large-area substrates, such as amorphous glass substrates or amorphous plastic substrates, which are used as backplanes. However, large-area substrates, such as amorphous glass substrates, have low heat resistance, and gallium nitride films formed at low temperatures have the problem of low crystallinity.

[0006] In view of the above-mentioned problems, one object of one embodiment of the present invention is to provide a stacked structure including a nitride semiconductor layer having a highly crystalline c-axis orientation.

[0007] A stacked structure according to one embodiment of the present invention includes an amorphous substrate, a first buffer layer having crystallinity on the amorphous substrate, a second buffer layer having amorphousness on the first buffer layer, and a nitride semiconductor layer on the second buffer layer.

[0008] 1 is a schematic cross-sectional view showing the configuration of a stacked structure according to one embodiment of the present invention; FIG. 2 is a cross-sectional TEM photograph of a stacked structure according to one embodiment of the present invention; FIG. 3 is an electron beam diffraction image of a first buffer layer of a stacked structure according to one embodiment of the present invention; FIG. 4 is an electron beam diffraction image of a nitride semiconductor layer of a stacked structure according to one embodiment of the present invention; FIG. 5 is a cross-sectional TEM photograph of a stacked structure according to one embodiment of the present invention; FIG. 6 is an electron beam diffraction image of a region including a first buffer layer and a nitride semiconductor layer of a stacked structure according to one embodiment of the present invention; FIG. 7 is a schematic cross-sectional view showing the configuration of a light-emitting device according to one embodiment of the present invention; FIG. 8 is a schematic cross-sectional view showing the configuration of a semiconductor element according to one embodiment of the present invention.

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. Note that each embodiment is merely an example, and any embodiment that a person skilled in the art could easily come up with by making appropriate modifications while maintaining the gist of the invention is naturally included in the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention.

[0010] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other components.

[0011] In this specification, for the sake of convenience, the terms "above" or "upper" or "below" or "belower" are used. In principle, the substrate on which the structure is formed is used as the reference, and the direction from the substrate toward the structure is referred to as "above." Conversely, the direction from the structure toward the substrate is referred to as "below." Therefore, in the expression "structure on a substrate," the surface of the structure facing the substrate is the lower surface of the structure, and the surface opposite to that is the upper surface of the structure. Furthermore, the expression "structure on a substrate" merely describes the vertical relationship between the substrate and the structure, and other components may be disposed between the substrate and the structure. Furthermore, the terms "above" or "upper" or "below" or "belower" refer to the stacking order in a structure in which multiple layers are stacked, and do not necessarily have to be in an overlapping positional relationship in a planar view.

[0012] In this specification, the letters "first," "second," or "third" attached to each component are convenient labels used to distinguish each component, and have no other meaning unless otherwise specified.

[0013] In this specification and drawings, the same reference numeral is used to collectively represent multiple identical or similar components, and when these multiple components are to be distinguished from one another, they may be accompanied by lowercase or uppercase letters. Furthermore, when multiple parts of a single component are to be distinguished from one another, a hyphen and a natural number may be used.

[0014] First Embodiment A laminated structure 10 according to one embodiment of the present invention will be described with reference to FIGS.

[0015] 1 is a schematic cross-sectional view showing the configuration of a stacked structure according to one embodiment of the present invention. The stacked structure 10 includes an amorphous substrate 100, an underlayer 110, a first buffer layer 120, a second buffer layer 130, and a nitride semiconductor layer 140. That is, the stacked structure 10 is a structure in which the underlayer 110, the first buffer layer 120, the second buffer layer 130, and the nitride semiconductor layer 140 are stacked in this order on the amorphous substrate 100.

[0016] The amorphous substrate 100 is a support substrate that supports each layer formed on the amorphous substrate 100. As will be described in detail later, the nitride semiconductor layer 140 of the stacked structure 10 is formed by sputtering. Therefore, the amorphous substrate 100 only needs to have heat resistance of, for example, about 600°C. The amorphous substrate 100 is, for example, a glass substrate or a plastic substrate such as polyimide that can be made large and used as a backplane for a display device such as a liquid crystal display. In the following description, the amorphous substrate 100 will be described as an amorphous glass substrate 100.

[0017] The underlayer 110 can prevent the diffusion of impurities (e.g., moisture or sodium (Na)) from the amorphous glass substrate 100. Since the layered structure 10 having the underlayer 110 formed thereon does not have the impurities diffused from the amorphous glass substrate 100, the crystallinity of the first buffer layer 120 on the underlayer 110 can be improved. The underlayer 110 can be made of, for example, silicon oxide (SiO ｘ ) or silicon nitride (SiN ｘThe underlayer 110 may be a single film or a laminated film. For example, when the underlayer 110 is a laminated film, the underlayer 110 may be a laminated film of silicon nitride and silicon oxide (SiO ｘ / SiN ｘ The base layer 110 may be provided in accordance with the properties of the amorphous glass substrate 100, and the laminated structure 10 may not include the base layer 110.

[0018] The first buffer layer 120 and the second buffer layer 130 can improve the crystallinity of the nitride semiconductor film formed on the second buffer layer 130. Specifically, the first buffer layer 120 and the second buffer layer 130 can control the c-axis of the nitride semiconductor film formed on the second buffer layer 130 to grow in the film thickness direction. In other words, the first buffer layer 120 and the second buffer layer 130 can control the nitride semiconductor layer 140 to have a c-axis orientation. Nitride semiconductors having a hexagonal close-packed structure grow in the c-axis direction so as to minimize surface energy, but forming a nitride semiconductor film on the first buffer layer 120 via the second buffer layer 130 promotes crystal growth of the nitride semiconductor film in the c-axis direction. The first buffer layer 120 can be made of a material having a hexagonal close-packed structure, a face-centered cubic structure, or a structure equivalent thereto. Here, a hexagonal close-packed structure or a structure similar to a face-centered cubic structure includes a crystal structure in which the c-axis is not 90° relative to the a-axis and b-axis. The first buffer layer 120 made of a material having a hexagonal close-packed structure or a structure similar thereto is oriented in the (0001) direction, i.e., the c-axis direction, relative to the amorphous glass substrate 100 (hereinafter referred to as the (0001) orientation of the hexagonal close-packed structure). Furthermore, the first buffer layer 120 made of a material having a face-centered cubic structure or a structure similar thereto is oriented in the (111) direction relative to the amorphous glass substrate 100 (hereinafter referred to as the (111) orientation of the face-centered cubic structure). Since the first buffer layer 120 has a (0001) orientation of a hexagonal close-packed structure or a (111) orientation of a face-centered cubic structure, crystal growth in the c-axis direction of the nitride semiconductor film formed on the first buffer layer 120 via the second buffer layer 130 is promoted, and the nitride semiconductor layer 140 has a highly crystalline c-axis orientation.

[0019] The first buffer layer 120 has crystallinity. The crystallinity of the first buffer layer 120 is obtained by XRD measurement. It can also be determined that the first buffer layer 120 has crystallinity when lattice fringes are observed in a TEM image of the first buffer layer 120. Examples of the first buffer layer 120 include titanium (Ti), titanium nitride (TiN), and the like.ｘ ), titanium oxide (TiO ｘ ), graphene, zinc oxide (ZnO), magnesium diboride (MgB ２ ), aluminum (Al), silver (Ag), calcium (Ca), nickel (Ni), copper (Cu), strontium (Sr), rhodium (Rh), palladium (Pd), cerium (Ce), ytterbium (Yb), iridium (Ir), platinum (Pt), gold (Au), lead (Pb), actinium (Ac), thorium (Th), BiLaTiO, SrFeO, BiFeO, BaFeO, ZnFeO, or PMnN-PZT. In particular, it is preferable to use titanium, graphene, or zinc oxide for the first buffer layer 120.

[0020] The second buffer layer 130 is amorphous. The amorphous nature of the second buffer layer 130 is determined by XRD measurement. Furthermore, the second buffer layer 130 can be determined to be amorphous when no lattice fringes are observed in a TEM image of the second buffer layer 130. For example, a compound containing the elements contained in the first buffer layer 120 can be used as the second buffer layer 130. It is preferable to use an oxide or a nitride as the second buffer layer 130. It is particularly preferable to use titanium oxide or titanium nitride as the second buffer layer 130. The second buffer layer 130 may be crystalline or amorphous. The thickness of the second buffer layer 130 is preferably greater than 0 nm and less than or equal to 10 nm. If the thickness of the second buffer layer 130 is greater than 10 nm, the nitride semiconductor film formed on the second buffer layer 130 will be less susceptible to the influence of the first buffer layer 120, and the crystallinity of the nitride semiconductor layer 140 will be reduced.

[0021] The nitride semiconductor layer 140 can be used as a semiconductor layer of devices such as light-emitting diodes (LEDs) or high electron mobility transistors (HEMTs). The nitride semiconductor layer 140 has a c-axis orientation with high crystallinity. The nitride semiconductor layer 140 can be made of, for example, aluminum nitride (AlN), gallium nitride (GaN), or indium nitride (InN), but is not limited to these. The nitride semiconductor layer 140 may be a nitride semiconductor containing at least two elements of gallium (Ga), aluminum (Al), and indium (In). The nitride semiconductor layer 140 can be made of not only an intrinsic semiconductor but also a p-type semiconductor or n-type semiconductor doped with impurities. For example, the nitride semiconductor layer 140 may be a p-type nitride semiconductor obtained by adding magnesium (Mg) to the above-mentioned nitride semiconductor, or an n-type nitride semiconductor obtained by adding silicon (Si) to the above-mentioned nitride semiconductor.

[0022] Although the details of the fabrication method of the nitride semiconductor layer 140 will be described later, since the nitride semiconductor layer 140 is formed on the second buffer layer 130, it is affected by the surface condition of the second buffer layer 130. Large unevenness on the surface of the second buffer layer 130 can cause random crystal nuclei to form during the initial deposition of the nitride semiconductor layer 140. As a result, crystal growth of the nitride semiconductor occurs in random directions, or adjacent crystals interfere with each other, inhibiting crystal growth. Therefore, it is preferable that the surface roughness of the second buffer layer 130 be small. However, if surface treatment is performed on each of the first buffer layer 120 and the second buffer layer 130 to orient the nitride semiconductor layer 140, the surfaces of the first buffer layer 120 and the second buffer layer 130 may be contaminated. In this case, contaminants on the surface of the second buffer layer 130 become crystal nuclei, causing random crystal nuclei to form and reducing the crystallinity of the nitride semiconductor layer 140. Therefore, in the stacked structure 10, it is preferable that the surface roughness of the amorphous glass substrate 100 or the underlayer 110 below the first buffer layer 120 and the second buffer layer 130 be small. For example, the arithmetic mean roughness (Ra) of the surface of the amorphous glass substrate 100 or the underlayer 110 is preferably smaller than 0.33 nm. Furthermore, it is preferable that the root-mean-square roughness (Rq) of the surface of the amorphous glass substrate 100 and the underlayer 110 is smaller than 0.39 nm. When the surface roughness of the amorphous glass substrate 100 or the underlayer 110 is within the above range, the surface roughness of the first buffer layer 120 and the second buffer layer 130 is small, and the crystallinity of the nitride semiconductor layer 140 can be improved.

[0023] 2. Method for Producing Nitride Semiconductor Layer 140 A method for producing the nitride semiconductor layer 140 using sputtering will be described below. Here, as an example of a method for producing the nitride semiconductor layer 140, deposition of a gallium nitride film will be described.

[0024] An amorphous glass substrate 100 on which a first buffer layer 120 and a second buffer layer 130 have been formed is placed in a vacuum chamber, facing the gallium nitride target. The gallium nitride composition ratio in the gallium nitride target is preferably 0.7 or more and 2 or less (gallium to nitrogen). Nitrogen can also be supplied to the vacuum chamber as a gas other than the sputtering gas (e.g., argon (Ar) or krypton (Kr)). In this case, the gallium nitride composition ratio in the gallium nitride target is preferably higher in gallium than in nitrogen. For example, nitrogen can be supplied using a nitrogen radical source. The sputtering power source may be a DC power source, an RF power source, or a pulsed DC power source.

[0025] The amorphous glass substrate 100 in the vacuum chamber may be heated. For example, the amorphous glass substrate 100 can be heated to a temperature of 400° C. or higher and lower than 600° C. This heating temperature can be applied to an amorphous glass substrate 100 with low heat resistance. Furthermore, this heating temperature is lower than the film formation temperature in MOCVD or HVPE.

[0026] After the vacuum chamber is fully evacuated, a sputtering gas is supplied to the vacuum chamber, and a voltage is applied between the amorphous glass substrate 100 and the gallium nitride target at a predetermined pressure to generate plasma, thereby depositing a gallium nitride film.

[0027] Although the deposition of a gallium nitride film using sputtering has been described above, the configuration or conditions of the sputtering can be changed as appropriate. Note that, if a magnesium-doped gallium nitride target or a silicon-doped gallium nitride target is used instead of a gallium nitride target, an n-type gallium nitride film and a p-type gallium nitride film can be deposited, respectively.

[0028] 2 is a cross-sectional TEM photograph of a stacked structure 10 according to one embodiment of the present invention. A stacked structure 10 containing titanium, titanium oxide, and gallium nitride as the first buffer layer 120 (100 nm), the second buffer layer 130 (3 nm), and the nitride semiconductor layer 140 (100 nm), respectively, was fabricated, and cross-sectional TEM observation of the stacked structure 10 was performed. The cross-sectional TEM observation was performed using an H-9500 manufactured by Hitachi High-Technologies Corporation and a JEM-ARM200F manufactured by JEOL Ltd.

[0029] Lattice fringes corresponding to crystals were observed in the first buffer layer 120 and the nitride semiconductor layer 140. In contrast, lattice fringes corresponding to crystals were not observed in the second buffer layer 130. These results indicate that the first buffer layer 120 and the nitride semiconductor layer 140 are crystalline, while the second buffer layer 130 is amorphous. Surprisingly, the inventors discovered that, even though the nitride semiconductor layer 140 is formed on the amorphous second buffer layer 130, the nitride semiconductor layer 140 is formed with crystallinity so as to lattice-match with the crystallinity of the first buffer layer 120. Although the detailed mechanism is unknown, it is speculated that, although the lattice constant of titanium in the first buffer layer 120 differs from the lattice constant of gallium nitride in the nitride semiconductor layer 140, the formation of the second buffer layer 130 between the first buffer layer 120 and the nitride semiconductor layer 140 reduces the lattice constant mismatch. In other words, in the stacked structure 10, it is presumed that the second buffer layer 130 has the function of adjusting the lattice constant of the first buffer layer 120, and that the nitride semiconductor layer 140 having crystallinity is formed via the second buffer layer 130 so as to match the adjusted lattice constant of the first buffer layer 120.

[0030] Fig. 3 is an electron beam diffraction image of the first buffer layer 120 of the stacked structure 10 according to one embodiment of the present invention. Fig. 4 is an electron beam diffraction image of the nitride semiconductor layer 140 of the stacked structure 10 according to one embodiment of the present invention. Specifically, Figs. 3 and 4 are electron beam diffraction images of measurement points A and B shown in Fig. 2. Measurement point B is located almost directly above measurement point A. The electron beam diffraction was performed using an H-9500 manufactured by Hitachi High-Technologies Corporation and a JEM-ARM200F manufactured by JEOL Ltd.

[0031] The appearance of clear spots in the electron beam diffraction image also confirmed that the first buffer layer 120 and the nitride semiconductor layer 140 were crystalline. It was also confirmed that each of the first buffer layer 120 and the nitride semiconductor layer 140 had a c-axis orientation, and that the c-axis direction of the nitride semiconductor layer 140 substantially coincided with the c-axis direction of the first buffer layer 120. In other words, it was found that the nitride semiconductor layer 140 was influenced by the c-axis orientation of the first buffer layer 120 and had a c-axis orientation with high crystallinity.

[0032] 5 is a cross-sectional TEM photograph of a stacked structure 10 according to one embodiment of the present invention. A stacked structure 10 was fabricated containing amorphous glass, silicon nitride, silicon oxide, titanium, titanium oxide, and gallium nitride as an amorphous glass substrate 100, a first underlayer 110-1 (150 nm), a second underlayer 110-2 (100 nm), a first buffer layer 120 (100 nm), a second buffer layer 130 (3 nm), and a nitride semiconductor layer 140 (100 nm), respectively, and a cross-sectional TEM observation of the stacked structure 10 was performed.

[0033] It was confirmed that the first buffer layer 120 and the nitride semiconductor layer 140 each contained multiple crystalline regions. A highly crystalline c-axis-oriented crystalline region was also formed in the nitride semiconductor layer 140 on the crystalline region having the c-axis orientation in the first buffer layer 120. Surprisingly, a crystalline region having crystallinity was formed in the nitride semiconductor layer 140 on the amorphous region of the first buffer layer 120. Although the crystallinity of the crystalline region of the nitride semiconductor layer 140 formed on the amorphous region of the first buffer layer 120 was lower than that of the crystalline region of the nitride semiconductor layer 140 formed on the crystalline region of the first buffer layer 120, it was surprising that a crystalline region of the nitride semiconductor layer 140 was formed on the amorphous region of the first buffer layer 120. It is speculated that the lattice constant of the first buffer layer 120 was adjusted by the second buffer layer 130, thereby expanding the crystalline region in the nitride semiconductor layer 140. Therefore, the amorphous region of the first buffer layer 120 has the function of adjusting lattice matching, and depending on the material of the first buffer layer 120, the crystallinity of the crystalline region of the nitride semiconductor layer 140 formed on the amorphous region of the first buffer layer 120 may be superior to the crystallinity of the crystalline region of the nitride semiconductor layer 140 formed on the crystalline region of the first buffer layer 120.

[0034] The above points will be described with reference to Fig. 1. As shown in Fig. 1, the first buffer layer 120 includes a first crystalline region 121, a second crystalline region 122, and an amorphous region 123 between the first crystalline region 121 and the second crystalline region 122. The nitride semiconductor layer 140 also includes a first crystalline region 141, a second crystalline region 142, and a third crystalline region 143 between the first crystalline region 141 and the second crystalline region 142. The first crystalline region 141 and the second crystalline region 142 of the nitride semiconductor layer 140 are formed on the first crystalline region 121 and the second crystalline region 122 of the first buffer layer 120, respectively, with the second buffer layer 130 interposed therebetween. Since the first crystalline region 121 and the second crystalline region 122 of the first buffer layer 120 have a c-axis orientation, the first crystalline region 141 and the second crystalline region 142 of the nitride semiconductor layer 140 also have a c-axis orientation. On the other hand, the third crystalline region 143 of the nitride semiconductor layer 140 is formed on the amorphous region 123 of the first buffer layer 120 via the second buffer layer 130. However, the crystallinity of the third crystalline region 143 of the nitride semiconductor layer 140 is lower than the crystallinity of each of the first crystalline region 141 and the second crystalline region 142.

[0035] The size of the crystal grains (diameter of the crystal grains in the in-plane direction) of each of the first crystal region 141 and the second crystal region 142 of the nitride semiconductor layer 140 is 50 nm or more, and the size of the crystal grains of the third crystal region 143 is 25 nm or less. That is, the size of the crystal grains of the third crystal region 143 is smaller than the size of the crystal grains of each of the first crystal region 141 and the second crystal region 142. Therefore, the nitride semiconductor layer 140 has high crystallinity as a whole.

[0036] 6 is an electron beam diffraction image of a region including the first buffer layer 120 and the nitride semiconductor layer 140 of the stacked structure 10 according to one embodiment of the present invention. Specifically, Fig. 6 is an electron beam diffraction image of region C shown in Fig. 5.

[0037] Clear spots of the first buffer layer 120 and the nitride semiconductor layer 140 could be confirmed even in a wide range such as region C. Furthermore, since the spots of the first buffer layer 120 and the spots of the nitride semiconductor layer 140 appeared in the same direction, it was found that the c-axis orientation of the nitride semiconductor layer 140 was strongly influenced by the c-axis orientation of the first buffer layer 120. In other words, the c-axis direction of the nitride semiconductor layer 140 approximately coincides with the c-axis direction of the first buffer layer.

[0038] As described above, the stacked structure 10 according to one embodiment of the present invention includes not only the first buffer layer 120 but also the second buffer layer 130. The nitride semiconductor layer 140 is affected by the c-axis orientation of the first buffer layer 120, and the mismatch in lattice constant is alleviated by the second buffer layer 130. Therefore, the nitride semiconductor layer 140 of the stacked structure 10 has a c-axis orientation with high crystallinity.

[0039] Second Embodiment A light-emitting device 1000 according to one embodiment of the present invention will be described with reference to Fig. 7. The light-emitting device 1000 includes a stacked structure 10. Note that, in the following, description of the configuration of the stacked structure 10 may be omitted in some cases.

[0040] Fig. 7 is a schematic cross-sectional view showing the configuration of a light-emitting device 1000 according to one embodiment of the present invention. As shown in Fig. 7, the light-emitting device 1000 includes a stacked structure 10, an n-type semiconductor layer 200, a light-emitting layer 210, a p-type semiconductor layer 220, an n-type electrode layer 230, and a p-type electrode layer 240. The light-emitting device 1000 is a so-called LED, but is not limited to this.

[0041] The n-type semiconductor layer 200 may be an n-type nitride semiconductor doped with silicon (Si). The light-emitting layer 210 may be a stack of two different nitride semiconductors alternately stacked. For example, the light-emitting layer 210 may be a stack of indium gallium nitride and gallium nitride alternately stacked. The p-type semiconductor layer 220 may be a p-type nitride semiconductor doped with magnesium (Mg). The n-type electrode layer 230 may be a metal such as indium. The p-type electrode layer 240 may be a metal such as palladium or gold.

[0042] The light emitting device 1000 is manufactured as follows: An n-type nitride semiconductor film is formed on the stacked structure 10. A stacked film is formed on the n-type nitride semiconductor film, in which two different nitride semiconductor films are alternately formed. A p-type nitride semiconductor film is formed on the stacked film.

[0043] Next, the p-type nitride semiconductor film, the stacked film, and the n-type nitride semiconductor film are etched using photolithography to form the p-type semiconductor layer 220, the light emitting layer 210, and the n-type semiconductor layer 200. At this time, the etching is performed so as to expose a part of the surface of the n-type nitride semiconductor film.

[0044] Next, an n-type electrode layer 230 and a p-type electrode layer 240 are formed on the n-type semiconductor layer 200 and the p-type semiconductor layer 220, respectively.

[0045] The n-type nitride semiconductor film, the stacked film, and the p-type nitride semiconductor film can be formed using a sputtering ring. The n-type nitride semiconductor film, the stacked film, and the p-type nitride semiconductor film may be formed continuously without breaking the vacuum by connecting multiple vacuum chambers in which these films are formed via a substrate transfer unit.

[0046] As described above, the light-emitting device 1000 according to one embodiment of the present invention can be manufactured using the laminated structure 10. The laminated structure 10 includes an amorphous glass substrate 100 that can be made large, and the light-emitting device 1000 can be manufactured using a large-area substrate. Therefore, the manufacturing cost of the light-emitting device 1000 can be reduced.

[0047] Third Embodiment A semiconductor device 2000 according to one embodiment of the present invention will be described with reference to Fig. 8. The semiconductor device 2000 includes a stacked structure 10. Note that, in the following, description of the configuration of the stacked structure 10 may be omitted.

[0048] 8 is a schematic cross-sectional view showing the configuration of a semiconductor device 2000 according to one embodiment of the present invention. As shown in FIG. 8, the semiconductor device 2000 includes a stacked structure 10, a first aluminum gallium nitride layer 300, a second aluminum gallium nitride layer 310, a third aluminum gallium nitride layer 320, a source electrode layer 330, a drain electrode layer 340, a gate electrode layer 350, a first insulating layer 360, a second insulating layer 370, and a shield electrode layer 380. The semiconductor device 2000 is a so-called HEMT, but is not limited to this.

[0049] The first aluminum gallium nitride layer 300 may be made of aluminum gallium nitride. The second aluminum gallium nitride layer 310 may be made of aluminum gallium nitride doped with silicon (Si). The third aluminum gallium nitride layer 320 may be made of aluminum gallium nitride. The source electrode layer 330 and the drain electrode layer 340 may each be made of a metal such as titanium or aluminum. The gate electrode layer 350 may be made of a metal such as nickel or gold. The first insulating layer 360 may be made of silicon nitride. The second insulating layer 370 may be made of silicon oxide. The shield electrode layer 380 may be made of a stacked metal such as aluminum / titanium (Al / Ti).

[0050] The semiconductor device 2000 is manufactured as follows: A first aluminum gallium nitride layer 300 is formed on the stacked structure 10. Furthermore, an aluminum gallium nitride film doped with silicon (Si) and an aluminum gallium nitride film are formed on the first aluminum gallium nitride layer 300.

[0051] Next, the aluminum gallium nitride film and the aluminum gallium nitride film doped with silicon (Si) are etched using photolithography to form the third aluminum gallium nitride layer 320 and the second aluminum gallium nitride layer 310. At this time, etching is performed so as to expose a portion of the surface of the aluminum gallium nitride film doped with silicon (Si).

[0052] Next, a source electrode layer 330 and a drain electrode layer 340 are formed on the second aluminum gallium nitride layer 310. A gate electrode layer 350 is formed on the third aluminum gallium nitride layer 320. A first insulating layer 360 and a second insulating layer 370 are formed so as to cover the source electrode layer 330, the drain electrode layer 340, and the gate electrode layer 350. A shield electrode layer 380 is formed on the second insulating layer 370.

[0053] The aluminum gallium nitride film and the aluminum gallium nitride film doped with silicon (Si) can be formed using a sputtering ring.

[0054] As described above, the semiconductor device 2000 according to one embodiment of the present invention can be manufactured using the stacked structure 10. The stacked structure 10 includes the amorphous glass substrate 100 that can be made large, and the semiconductor device 2000 can be manufactured using a large-area substrate. Therefore, the manufacturing cost of the semiconductor device 2000 can be reduced.

[0055] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies the design based on each embodiment, or adds or omits steps or modifies conditions, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0056] Even if there are other effects and advantages different from those brought about by the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0057] 10: Stacked structure, 100: Amorphous substrate (amorphous glass substrate), 110: Underlayer, 120: First buffer layer, 121: First crystalline region, 122: Second crystalline region, 123: Amorphous region, 130: Second buffer layer, 140: Nitride semiconductor layer, 141: First crystalline region, 142: Second crystalline region, 143: Third crystalline region, 200: N-type semiconductor layer, 210: Light-emitting layer, 220: P-type semiconductor layer, 230: N-type electrode layer, 240: P-type electrode layer, 300: First aluminum gallium nitride layer, 310: Second aluminum gallium nitride layer, 320: Third aluminum gallium nitride layer, 330: Source electrode layer, 340: Drain electrode layer, 350: Gate electrode layer 360: First insulating layer, 370: Second insulating layer, 380: Shield electrode layer, 400: Protective layer, 1000: Light emitting element, 2000: Semiconductor element

Claims

1. A stacked layer structure comprising: an amorphous substrate; a first buffer layer having crystalline properties on the amorphous substrate; a second buffer layer having amorphous properties on the first buffer layer; and a nitride semiconductor layer on the second buffer layer.

2. The stacked structure according to claim 1, wherein the first buffer layer contains a first element, and the second buffer layer contains a compound containing the first element.

3. The laminate structure according to claim 2, wherein the compound containing the first element is an oxide.

4. The laminate structure according to claim 2, wherein the first element is titanium.

5. The stacked structure according to claim 1, wherein the first buffer layer has a c-axis orientation, the nitride semiconductor layer has crystallinity, and the c-axis direction of the nitride semiconductor layer substantially coincides with the c-axis direction of the first buffer layer.

6. The stacked structure according to claim 5, wherein the first buffer layer includes a first crystalline region and a second crystalline region, and the nitride semiconductor layer includes a third crystalline region on the first crystalline region and a fourth crystalline region on the second crystalline region.

7. The stacked structure according to claim 6, wherein the nitride semiconductor layer includes a fifth crystal region between the third crystal region and the fourth crystal region, the fifth crystal region having lower crystallinity than each of the third crystal region and the fourth crystal region, and the crystal grain size of the fifth crystal region being smaller than the crystal grain size of each of the third crystal region and the fourth crystal region.

8. The stacked structure according to claim 7, wherein the size of the crystal grains in each of the third crystalline region and the fourth crystalline region is 50 nm or more.

9. The stacked structure according to claim 1, wherein the thickness of the second buffer layer is greater than 0 nm and not greater than 10 nm.

10. The layered structure according to claim 1, further comprising an underlayer between said amorphous substrate and said first buffer layer.

11. The laminated structure according to claim 1, wherein the amorphous substrate is a glass substrate.

12. The laminate structure of claim 1, wherein the amorphous substrate is a plastic substrate.

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