Power semiconductor device

Abstract

A power semiconductor device according to the present invention comprises: a semiconductor element having a gate electrode and a first electrode formed on one surface thereof; a first conductor joined to the first electrode; gate wiring joined to the gate electrode; and a gate conductor to which the gate wiring is joined. The semiconductor element has an active region where heat is generated significantly. The active region is formed so as to be adjacent to the gate electrode on a plurality of sides in a plan view seen in a thickness direction of the semiconductor element. The joining surface of the first conductor joined to the semiconductor element has a substantially rectangular outer diameter with the periphery of the gate electrode cut out. The first conductor has, on the side where the gate conductor is disposed, a recess forming a space in which the gate wiring is to be installed. The space of the recess on the side where the gate conductor is disposed is formed wider than a space on the opposite side, with the boundary therebetween being a plane that passes through the joining portion at which the gate electrode and the gate wiring are joined and is orthogonal to the joining surface and a side surface.

Description

Power Semiconductor Devices

[0001] The present invention relates to a power semiconductor device.

[0002] In recent years, hybrid and electric vehicles have become more popular to reduce environmental impact. Hybrid and electric vehicles require smaller and more cost-effective components. Power semiconductor devices used in power conversion systems are no exception, and these demands are also increasing. Among the electronic components that make up power conversion systems, power semiconductor devices generate a large amount of heat, so miniaturization requires improved cooling performance. Patent Document 1 (JP-A-2005-102626) discloses a power module that includes: multiple semiconductor elements constituting upper and lower arms of an inverter circuit; multiple conductor plates disposed opposite the electrode surfaces of the semiconductor elements; and a module case that houses the semiconductor elements and the conductor plates. The module case includes a metal heat dissipation member facing the surface of the conductor plate and a metal frame having an opening that is closed by the heat dissipation member. The metal heat dissipation member has a central heat dissipation fin portion with multiple upstanding fins, and the heat dissipation member has a joint portion for connecting to the frame at its outer periphery. The heat dissipation member has higher thermal conductivity than the frame, and the frame has higher rigidity than the heat dissipation member.

[0003] Japanese Patent Application Publication No. 2012-257369

[0004] The invention described in Patent Document 1 leaves room for improvement in terms of heat dissipation from the semiconductor element.

[0005] A power semiconductor device according to a first aspect of the present invention comprises: a semiconductor element having a gate electrode and a first electrode formed on one surface thereof; a first conductor bonded to the first electrode; a gate wiring bonded to the gate electrode; and a gate conductor bonded to the gate wiring; the semiconductor element has an active region which is a region where heat is significantly generated; the active region is formed so as to be adjacent to the gate electrode on multiple sides in a plan view seen from the thickness direction of the semiconductor element; the bonding surface of the first conductor bonded to the semiconductor element has a substantially rectangular outer diameter with the periphery of the gate electrode cut out; the first conductor has a recess on its side on which the gate conductor is disposed that forms a space in which the gate wiring is installed; and the space of the recess on the side on which the gate conductor is disposed is wider than the space on the opposite side, with a plane that passes through the bond between the gate electrode and the gate wiring and is perpendicular to the bonding surface and the side surface as the boundary.

[0006] According to the present invention, the heat generated by the semiconductor element can be dissipated using a larger heat transfer area.

[0007] 3A perspective view of a power semiconductor device. 4A cross-sectional view of a power semiconductor device. 4A cross-sectional view of a power semiconductor device taken along line IV-IV in FIG. 3A perspective view of a first conductor 10. 4A cross-sectional view of a power semiconductor device taken along line VI-VI in FIG. 4A cross-sectional view of a power semiconductor device according to modified example 1. 4A cross-sectional view of a power semiconductor device according to modified example 2. 4A cross-sectional view of a power semiconductor device according to modified example 3. 4A diagram showing variations of a gate electrode, a first electrode, and an active projection region according to modified example 4. 4A cross-sectional view of a power semiconductor device according to modified example 6. 4A cross-sectional view of a power semiconductor device according to modified example 7. 4A plan view of a power semiconductor device according to a second embodiment. 4A cross-sectional view of a power semiconductor device according to a second embodiment.

[0008] -First Embodiment- A first embodiment of a power semiconductor device will be described below with reference to FIGS.

[0009] FIG. 1 is a perspective view of a power semiconductor device 100. FIG. 2 is an exploded perspective view of the power semiconductor device 100. FIG. 3 is a cross-sectional view of the power semiconductor device 100, and FIG. 4 is a plan view of the power semiconductor device 100. In this embodiment, mutually orthogonal X, Y, and Z axes are also shown to clearly show the correlation between the drawings. The power semiconductor device 100 includes two flat-plate-shaped power semiconductor elements 1, a first conductor 10, a second conductor 20, a gate conductor 30, and an insulating layer 40. The first conductor 10 and the second conductor 20 sandwich the power semiconductor element 1 in the Z-axis direction. The power semiconductor element 1 includes a first element 1-1 arranged on the negative side of the X-axis and a second element 1-2 arranged on the positive side of the X-axis. The first element 1-1 and the second element 1-2 have the same configuration.

[0010] The power semiconductor element 1 has a gate electrode 2 and a first electrode 3 on its surface on the positive side of the Z axis, and a second electrode 4 on its surface on the negative side of the Z axis. The first electrode 3 and the second electrode 4 are source and drain electrodes, or drain and source electrodes. The gate electrode 2 of the first element 1-1 is referred to as the first element gate electrode 2-1, and the gate electrode 2 of the second element 1-2 is referred to as the second element gate electrode 2-2. The first electrode 3 of the first element 1-1 is referred to as the first element first electrode 3-1, and the first electrode 3 of the second element 1-2 is referred to as the second element first electrode 3-2. The second electrode 4 of the first element 1-1 is referred to as the first element second electrode 4-1, and the second electrode 4 of the second element 1-2 is referred to as the second element second electrode 4-2.

[0011] The power semiconductor element 1 becomes hot during use, but heat is not generated uniformly throughout; it is divided into areas where heat is generated significantly and areas where heat is hardly generated at all. Hereinafter, the area in the power semiconductor element 1 where heat is generated significantly will be referred to as the active area 5, and the area obtained by projecting the active area 5 onto the surface on the positive side of the Z axis will be referred to as the active projection area 6. In other words, the active area 5 is an area present inside the power semiconductor element 1, and the area on the surface on the positive side of the Z axis in the power semiconductor element 1 where this heat is transferred and becomes hot is the active projection area 6. In this embodiment, the active projection area 6 substantially coincides with the first electrode 3.

[0012] The first conductor 10 has a flat base 11 and a protrusion 12 shaped like a rectangular parallelepiped. The protrusion 12 includes a first protrusion 12-1 that contacts the first element 1-1 and a second protrusion 12-2 that contacts the second element 1-2. The protrusion 12 has a recess 13 that forms a space over which the gate wiring 86 is installed. The recess 13 includes a first recess 13-1 formed in the first protrusion 12-1 and a second recess 13-2 formed in the second protrusion 12-2. Roughly speaking, the shape of the recess 13 is a shape obtained by dividing a sphere centered on the gate electrode 2 into four equal parts. By providing the recess 13, the gate wiring 86 can connect the gate electrode 2 and the gate conductor 30 without being obstructed by the first conductor 10. The recess 13 does not extend to the base 11.

[0013] The first protrusion 12-1 and the second protrusion 12-2 have shapes that are approximately symmetrical with the YZ plane as a mirror plane. Details will be described later. Here, the base 11 and the protrusion 12 are separated to explain the shape of the first conductor 10, but the two may be integrally formed by, for example, cutting. The insulating layer 40 includes a first insulating layer 40-1 disposed on the positive side of the Z axis and a second insulating layer 40-2 disposed on the negative side of the Z axis. The first insulating layer 40-1 contacts the first conductor 10 from the positive side of the Z axis. The second insulating layer 40-2 contacts the second conductor 20 from the negative side of the Z axis. In other words, the insulating layer 40 sandwiches the first conductor 10 and the second conductor 20 in the Z axis direction.

[0014] 3 , the first electrode 3 arranged on the surface on the positive side of the power semiconductor element 1 along the Z axis is connected to the first protrusion 12-1 and the second protrusion 12-2 of the first conductor 10 by a first bonding material 81. The second electrode 4 arranged on the surface on the negative side of the power semiconductor element 1 along the Z axis is bonded to the second conductor 20 by a second bonding material 82. The first conductor 10 and the second conductor 20 are formed of, for example, copper, a copper alloy, aluminum, or an aluminum alloy. The first bonding material 81 and the second bonding material 82 are formed of a solder material, a sintered material, or the like.

[0015] The insulating layer 40 conducts heat generated from the power semiconductor element 1 to the outside and is made of a material with high thermal conductivity and high dielectric strength. The insulating layer 40 is made of ceramics such as aluminum oxide (alumina), aluminum nitride, or silicon nitride. The insulating layer 40 may be an insulating sheet or adhesive containing fine powder of these materials.

[0016] The space between the first insulating layer 40-1 and the second insulating layer 40-2 is sealed with sealing resin 8. That is, the power semiconductor element 1, the first conductor 10, and the second conductor 20 are sealed with sealing resin 8. The surface of the first insulating layer 40-1 on the positive side of the Z axis and the surface of the second insulating layer 40-2 on the negative side of the Z axis are exposed from the sealing resin 8 and serve as heat dissipation surfaces for the power semiconductor device 100. Note that the insulating layer 40 and the sealing resin 8 are not shown in FIGS. 1 and 2 .

[0017] As shown in FIG. 2 , the active projection region 6 is formed to extend laterally from the gate electrode 2. It can be said that the area remaining after subtracting the rectangular region centered on the gate electrode 2 from the rectangular region is set as the active projection region 6 and the first electrode 3. In the example shown in FIG. 2 , the gate electrode 2, the first electrode 3, and the active projection region 6 are positioned in the negative Y-axis direction. It can also be said that the active projection region 6 is formed so as to be adjacent to the gate electrode 2 on multiple sides in a plan view seen from the thickness direction of the power semiconductor device 1. One end of a gate wiring 86 is connected to the gate electrode 2, and the other end of the gate wiring 86 is connected to the gate conductor 30. Specifically, a first gate wiring 86-1 is connected to the first element gate electrode 2-1, and a second gate wiring 86-2 is connected to the second element gate electrode 2-2. The gate conductor 30 is provided to electrically connect the gate electrode 2 to the outside of the power semiconductor device 100.

[0018] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3, showing the shape of the recess 13. FIG. 4 shows the second conductor 20 at the top and the gate conductor 30 at the bottom. The first element 1-1 and the second element 1-2 are shown on the inner periphery of the second conductor 20. As described above, the first element 1-1 has a first element gate electrode 2-1, and the second element 1-2 has a second element gate electrode 2-2. The region indicated by a dashed line on the inner periphery of the first element 1-1 is a first protrusion 12-1, and the recess existing around the first element gate electrode 2-1 indicates the shape of a first recess 13-1 on the surface of the first element 1-1. The region indicated by a dashed line on the inner periphery of the second element 1-2 is a second protrusion 12-2, and the recess existing around the second element gate electrode 2-2 indicates the shape of a second recess 13-2 on the surface of the second element 1-2.

[0019] The shape of the first recess 13-1 will be described in detail. An imaginary plane parallel to the YZ plane and passing through the junction between the first element gate electrode 2-1 and the first gate wiring 86-1 is referred to as a first reference plane 91. A first space X1 on the positive side of the X-axis obtained by dividing the first recess 13-1 at the first reference plane 91 is wider than a second space X2 on the negative side of the X-axis obtained by dividing the first recess 13-1 at the first reference plane 91. An imaginary plane parallel to the YZ plane and passing through the junction between the second element gate electrode 2-2 and the second gate wiring 86-2 is referred to as a second reference plane 92. A third space X3 on the negative side of the X-axis obtained by dividing the second recess 13-2 at the second reference plane 92 is wider than a fourth space X4 on the positive side of the X-axis obtained by dividing the second recess 13-2 at the second reference plane 92. In this way, the first recess 13-1 and the second recess 13-2 have plane-symmetric shapes with the YZ plane as the plane of symmetry. The recess 13 does not communicate with the base 11 of the first conductor 10 .

[0020] FIG. 5 is a perspective view of the first conductor 10 as viewed from the connection surface side of the power semiconductor element 1. In FIG. 5, the Z-axis direction is reversed from that in FIGS. 1 and 2. The first conductor 10 has a first protrusion 12-1 and a second protrusion 12-2 for connection to the power semiconductor element 1. The base 11 can also be considered a member that connects the first protrusion 12-1 and the second protrusion 12-2. The first recess 13-1 is provided in the first protrusion 12-1 near the first element gate electrode 2-1. The second recess 13-2 is provided in the second protrusion 12-2 near the second element gate electrode 2-2.

[0021] 6 is a cross-sectional view taken along line VI-VI of FIG. 4, taken on the XZ plane passing through the gate electrode 2. The shape of the first recess 13-1 is defined by the aforementioned first reference plane 91, and the first space X1 on the side where the gate conductor 30 is disposed is larger than the second space X2 on the opposite side. The shape of the second recess 13-2 is defined by the aforementioned second reference plane 92, and the third space X3 on the side where the gate conductor 30 is disposed is larger than the fourth space X4 on the opposite side.

[0022] (Effects) The power semiconductor device 100 includes a power semiconductor element 1 having an active projection region 6 that protrudes laterally from the gate electrode 2. The first conductor 10 has a substantially rectangular outer diameter with a recess 13 cut out around the gate electrode 2 in a region where the gate wiring 86, which connects the gate electrode 2 to the gate conductor 30, is provided. The first conductor 10 has the recess 13, which forms a space in which the gate wiring 86 is installed, on a side parallel to the XZ plane on the side where the gate conductor 30 is disposed. In the space formed by the recess 13, the space on the side closer to the gate conductor 30 is wider than the space on the opposite side. Specifically, the first space X1 is wider than the second space X2, and the third space X3 is wider than the fourth space X4. This prevents the gate wiring 86 from interfering with the first conductor 10, maximizing the area over which the first conductor 10 covers the active projection region 6.

[0023] The bonding surface of the first conductor 10 bonded to the power semiconductor element 1 has an outer diameter corresponding to a shape with the periphery of the gate electrode 2 cut out, i.e., a substantially rectangular outer diameter in FIG. 4 . Because the active projection region 6 has a substantially rectangular shape, the area over which the first conductor 10 covers the active region 5 can be maximized. This allows the first conductor 10 to be connected so as to cover almost the entire active projection region 6 that protrudes laterally from the gate electrode 2 of the power semiconductor element 1. Therefore, when the power semiconductor element 1 is energized and generates heat, a local temperature rise on the surface of the power semiconductor element 1 is suppressed. This suppresses a temperature rise in the gate electrode 2 even when the power semiconductor element 1 is energized, and reduces thermal stress in the gate wiring 86. This makes the gate wiring 86 less susceptible to damage during power cycles, resulting in a power semiconductor device 100 with high heat dissipation performance and high reliability.

[0024] Furthermore, the recess 13 does not communicate with the base 11 of the first conductor 10. This allows heat from the power semiconductor element 1 to be conducted to the protrusion 12, spread to the base 11, and dissipated from the heat dissipation surface on the positive side of the Z axis. This further suppresses the temperature rise of the gate electrode 2, further reduces the stress on the gate wiring 86, and provides a power semiconductor device 100 with high heat dissipation performance and high reliability.

[0025] The power semiconductor device 100 includes a plurality of power semiconductor elements 1, and when the gate wiring 86 is connected from the gate electrode 2 of each power semiconductor element 1 to the same gate conductor 30, the extending directions of the gate wiring 86 are different. The first recess 13-1 and the second recess 13-2 provided in the first conductor 10 are provided in bridge regions of the first gate wiring 86-1 and the second gate wiring 86-2, respectively. By making the shapes of the first recess 13-1 and the second recess 13-2 different from each other in accordance with the extending direction of the gate wiring 86, the area over which the first conductor 10 covers the active projection region 6 can be maximized. This further suppresses the temperature rise of the gate electrode 2, further reduces the stress on the gate wiring 86, and provides a power semiconductor device 100 with high heat dissipation performance and high reliability.

[0026] The first embodiment described above provides the following advantageous effects. (1) The power semiconductor device 100 includes a power semiconductor element 1 having a gate electrode 2 and a first electrode 3 formed on one surface thereof, a first conductor 10 bonded to the first electrode 3, a gate wiring 86 bonded to the gate electrode 2, and a gate conductor 30 bonded to the gate wiring 86. The power semiconductor element 1 has an active region 5 that is a region where significant heat is generated. The active region 5 is formed so as to be adjacent to the gate electrode 2 on multiple sides in a plan view seen from the thickness direction of the power semiconductor element 1. The bonding surface of the first conductor 10 bonded to the power semiconductor element 1 has a substantially rectangular outer diameter with the periphery of the gate electrode 2 cut out as shown by the dashed line in FIG. 4 . The first conductor 10 has a recess 13 on the side where the gate conductor 30 is disposed, forming a space in which the gate wiring 86 is installed. The space of the recess 13 on the side where the gate conductor 30 is disposed is wider than the space on the opposite side, with the boundaries being a junction plane parallel to the XY plane that passes through the junction between the gate electrode 2 and the gate wiring 86, and a plane perpendicular to the side surface parallel to the XZ plane, i.e., a plane parallel to the YZ plane. For example, in the first recess 13-1, the plane parallel to the YZ plane that passes through the junction between the first element gate electrode 2-1 and the first gate wiring 86-1 is the first reference plane 91. The first space X1 on the positive side of the X axis obtained by dividing the first recess 13-1 by the first reference plane 91 is wider than the second space X2 on the negative side of the X axis obtained by dividing the first recess 13-1 by the first reference plane 91. Therefore, the gate wiring 86 does not interfere with the first conductor 10, and the area that the first conductor 10 covers the active projection region 6 can be maximized, allowing heat generated by the power semiconductor element 1 to be dissipated using a wider heat transfer area. Furthermore, since the thermal stress on the gate wiring 86 is reduced, the gate wiring 86 is less likely to be damaged during power cycles, and the power semiconductor device 100 has high heat dissipation performance and high reliability.

[0027] (2) The first conductor 10 includes a flat base 11 and a protrusion 12 that protrudes from the base 11 toward the power semiconductor element 1. A recess 13 is formed at the tip of the protrusion 12. As shown by the dashed line in Fig. 4 , the area from the tip of the protrusion 12 excluding the space of the recess 13 contacts the first electrode 3. The recess 13 does not communicate with the base 11. Therefore, heat from the power semiconductor element 1 is easily transferred from the protrusion 12 to the base 11, and can be dissipated from the heat dissipation surface of the base 11 on the positive side of the Z axis.

[0028] (3) A plurality of power semiconductor elements 1 and a plurality of gate wirings 86 are provided for each pair of first conductors 10 and gate conductors 30 .

[0029] (4) The shapes of the recesses 13 provided corresponding to the gate wirings 86 are different from each other. By varying the shapes of the recesses 13 depending on the positional relationship between each power semiconductor element 1 and the gate conductor 30, the area of ​​the first conductor 10 covering the active projection region 6 can be maximized.

[0030] 7 is a cross-sectional view of a power semiconductor device 100 according to Modification 1, corresponding to FIG. 6 of the first embodiment. The recess 13 in this modification includes a recess insulating layer 14. The recess insulating layer 14 is made of, for example, a resin. A first recess insulating layer 14-1 is provided on the inner wall of the first recess 13-1, and a second recess insulating layer 14-2 is provided on the inner wall of the second recess 13-2.

[0031] According to this modification, in addition to the effects of the first embodiment, the following effects can be obtained: (5) An insulating resin is applied to the recess 13. Therefore, there is no need to worry about an electrical short between the gate wiring 86 and the first conductor 10, and the same effects as in the first embodiment can be obtained. Furthermore, since the space in the recess 13 is reduced, there is an advantage that heat from the power semiconductor element 1 can be more easily dissipated.

[0032] (Modification 2) Fig. 8 is a cross-sectional view of the power semiconductor device 100 in Modification 2, and corresponds to Fig. 6 in the first embodiment. In the first embodiment, the recess 13 provided in the first conductor 10 has a curved shape, but it may have a rectangular shape as shown in Fig. 8. In this modification, the relationship in which the first space X1 is larger than the second space X2 and the third space X3 is larger than the fourth space X4 remains the same.

[0033] (Modification 3) Fig. 9 is a cross-sectional view of a power semiconductor device 100 in Modification 3, and corresponds to Fig. 6 in the first embodiment. In the first embodiment, the recess 13 provided in the first conductor 10 has a curved shape, but even if it has a tapered shape as shown in Fig. 9, the same effect as in the first embodiment can be obtained. In this modification, the relationship in which the first space X1 is wider than the second space X2 and the third space X3 is wider than the fourth space X4 remains the same.

[0034] (Variation 4) FIG. 10 shows variations of the gate electrode 2, the first electrode 3, and the active projection region 6. Note that in this figure, the regions of the first electrode 3 and the active projection region 6 are hatched to clearly show the first electrode 3 and the active projection region 6. In the first embodiment, as shown in FIG. 2, the positions of the gate electrode 2, the first electrode 3, and the active projection region 6 in the negative Y-axis direction are aligned. However, as shown in FIG. 10( a), the end of the gate electrode 2 may protrude in the negative Y-axis direction beyond the first electrode 3 and the active projection region 6. Conversely, the end of the first electrode 3 and the active projection region 6 may protrude in the negative Y-axis direction beyond the gate electrode 2. Furthermore, as shown in FIG. 10( b), the periphery of the gate electrode 2 may be cut out in a shape other than a rectangle. Furthermore, as shown in FIG. 10( c), the gate electrode 2 may be disposed within a hollowed-out region of the first electrode 3 and the active projection region 6, rather than being disposed at the end of the first electrode 3 and the active projection region 6.

[0035] (Variation 5) In the first embodiment described above, the insulating layer 40 is also sealed with the sealing resin 8 except for the heat dissipation surface. However, the insulating layer 40 does not have to be sealed with the sealing resin 8. It is sufficient that the sealing resin 8 seals at least the first conductors 10 and the second conductors 20.

[0036] (Variation 6) In the first embodiment described above, the power semiconductor device 100 includes two semiconductor elements, specifically, the first element 1-1 and the second element 1-2. However, the power semiconductor device 100 may include only one element. Even in this case, as long as the positions of the gate conductor 30 and the gate electrode 2 are misaligned, the same effects as those of the first embodiment can be obtained.

[0037] FIG. 11 is a cross-sectional view of a power semiconductor device 100 according to Modification 6, corresponding to FIG. 6 for the first embodiment. In this modification, the power semiconductor device 100 includes only one element, namely, the first element 1-1, and no other elements. In this modification, the positions of the first element 1-1 and the gate conductor 30 on the X-axis are also offset, and the gate wiring 86 is routed diagonally. Therefore, in order to maximize the heat transfer area from the first element 1-1 to the first conductor 10 and to avoid adverse effects on the gate wiring 86, the first space X1 is made larger than the second space X2.

[0038] (Seventh Modification) FIG. 12 is a cross-sectional view of a power semiconductor device 100 according to a seventh modification, corresponding to FIG. 6 in the first embodiment. As shown in FIG. 12, the power semiconductor device 100 may include a heat dissipation member 15. A refrigerant circulates inside the heat dissipation member 15, for example. The heat dissipation member 15 includes a first heat dissipation member 15-1 and a second heat dissipation member 15-2. The first heat dissipation member 15-1 contacts the first insulating layer 40-1 via the heat transfer member 83. The second heat dissipation member 15-2 contacts the second insulating layer 40-2 via the heat transfer member 83. In other words, the heat dissipation member 15 sandwiches the first insulating layer 40-1 and the second insulating layer 40-2 from both sides of the Z axis.

[0039] - Second embodiment - A second embodiment of a power semiconductor device will be described with reference to Figures 13 and 14. In the following description, the same components as in the first embodiment are denoted by the same reference numerals, and differences will be mainly described. Points that are not particularly described are the same as in the first embodiment. This embodiment differs from the first embodiment mainly in that three semiconductor elements are housed in one power semiconductor device.

[0040] Fig. 13 is a plan view of a power semiconductor device 100A according to the second embodiment, corresponding to Fig. 4 in the first embodiment. Fig. 14 is a cross-sectional view of the power semiconductor device 100A, corresponding to Fig. 6 in the first embodiment. The power semiconductor device 100A includes a third element 1-3 in addition to a first element 1-1 and a second element 1-2. The third element 1-3 has a third element gate electrode 2-3, which is connected to the gate conductor 30 via a third gate wiring 86-3.

[0041] The first conductor 10A further includes a third protrusion 12-3 in addition to the base 11, the first protrusion 12-1, and the second protrusion 12-2. The third protrusion 12-3 is bonded to the third element 1-3 by a first bonding material 81. The third protrusion 12-3 has a third recess 13-3, which is a notch, near the third element gate electrode 2-3. In FIG. 13 , the region indicated by a dashed line on the inner periphery of the third element 1-3 is the third protrusion 12-3, and the depression present around the third element gate electrode 2-3 indicates the shape of the third recess 13-3 on the surface of the third element 1-3.

[0042] The gate conductor 30 is located approximately in the center of the power semiconductor device 100A in the X-axis direction, but slightly to the negative side of the X-axis. Therefore, the positional relationship between each gate electrode 2 and gate conductor 30 is such that only the first element gate electrode 2-1 has the gate conductor 30 on the positive side of the X-axis, while the second element gate electrode 2-2 and the third element gate electrode 2-3 have the gate conductor 30 on the negative side of the X-axis. Because the gate wiring 86 connects the gate electrode 2 and gate conductor 30, the direction in which the gate wiring 86 exits from the gate electrode 2, i.e., whether it is on the positive side or the negative side of the X-axis, is determined by the positional relationship between each gate electrode 2 and gate conductor 30. To prevent the protrusion 12 from obstructing the gate wiring 86, it is necessary to ensure a large space in the recess 13 in the direction in which the gate wiring 86 exits. However, to maximize the heat transfer area for the heat emitted by the power semiconductor element 1, the recess 13, which is a cutout, should be small. Therefore, only the first recess 13-1 has a larger area on the positive side of the X axis than the first reference plane 91, while the second recess 13-2 and the third recess 13-3 have larger areas on the negative side of the X axis.

[0043] Furthermore, let Y1 be the distance on the X-axis between the gate conductor 30 and the first element 1-1, Y2 be the distance on the X-axis between the gate conductor 30 and the second element 1-2, and Y3 be the distance on the X-axis between the gate conductor 30 and the third element 1-3. In addition to the definitions of the first space X1 to the fourth space X4, a fifth space X5 and a sixth space X6 are defined as follows. A virtual plane parallel to the YZ plane and passing through the junction between the third element gate electrode 2-3 and the third gate wiring 86-3 is referred to as the third reference plane 93. The space on the negative side of the X-axis obtained by dividing the third recess 13-3 by the third reference plane 93 is referred to as the fifth space X5, and the space on the opposite side is referred to as the sixth space X6. In this case, Y1 to Y3 have a relationship of Y3 > Y1 > Y2, and the size of the spaces has a relationship of X5 > X1 > X3. Therefore, the gate wiring 86 does not interfere with the first conductor 10, and the area over which the first conductor 10 covers the active region 5 can be maximized.

[0044] According to the second embodiment described above, the following advantageous effects can be obtained. That is, similar to the first embodiment, the gate wiring 86 does not interfere with the first conductor 10, the area over which the first conductor 10 covers the active projection region 6 can be maximized, and the heat generated by the power semiconductor element 1 can be dissipated using a wider heat transfer area. Furthermore, since the thermal stress of the gate wiring 86 is reduced, the gate wiring 86 is less likely to be damaged during power cycles, and a power semiconductor device 100 with high heat dissipation performance and high reliability can be obtained.

[0045] The above-described embodiments and modifications may be combined with each other. Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments conceivable within the scope of the technical concept of the present invention are also included within the scope of the present invention.

[0046] 1: Power semiconductor element 2: Gate electrode 3: First electrode 4: Second electrode 5: Active region 6: Active projection region 10, 10A: First conductor 11: Base 12: Protrusion 13: Recess 14: Recess insulating layer 30: Gate conductor 40: Insulating layer 86: Gate wiring 91: First reference surface 92: Second reference surface 93: Third reference surface 100, 100A: Power semiconductor device

Claims

1. A power semiconductor device comprising: a semiconductor element having a gate electrode and a first electrode formed on one surface thereof; a first conductor bonded to the first electrode; a gate wiring bonded to the gate electrode; and a gate conductor bonded to the gate wiring; the semiconductor element has an active region which is a region where heat is significantly generated; the active region is formed so as to be adjacent to the gate electrode on multiple sides in a plan view seen in the thickness direction of the semiconductor element; the bonding surface of the first conductor bonded to the semiconductor element has a substantially rectangular outer diameter with the periphery of the gate electrode cut out; the first conductor has a recess on its side on which the gate conductor is disposed that forms a space in which the gate wiring is installed; and the space of the recess on the side on which the gate conductor is disposed is formed wider than the space on the opposite side, with a plane that passes through the junction of the gate electrode and the gate wiring and is perpendicular to the bonding surface and the side surface as the boundary.

2. A power semiconductor device according to claim 1, wherein the first conductor includes a flat base and a protrusion protruding from the base toward the semiconductor element, the recess is formed at the tip of the protrusion, the area from the tip excluding the space of the recess is in contact with the first electrode, and the recess does not communicate with the base.

3. A power semiconductor device according to claim 1, wherein a plurality of said semiconductor elements and a plurality of said gate wirings are provided for each pair of said first conductors and said gate conductors.

4. A power semiconductor device according to claim 1, wherein the shapes of the recesses provided corresponding to the gate wirings are different from each other.

5. A power semiconductor device according to claim 1, wherein an insulating resin is applied to the recess.

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