Multi-color micro-display chip and manufacturing method therefor

Abstract

The present invention relates to a multi-color micro-display chip and a manufacturing method therefor. The chip comprises a parent pixel, a driver wafer, and at least two pixel layers; the parent pixel comprises at least four sub-pixels; at least two sub-pixels in the parent pixel have different light-emitting colors and the parent pixel comprises sub-pixels with red light-emitting color, wherein the number of the sub-pixels with red light-emitting color is not less than 50% of the number of all the sub-pixels in the parent pixel; the sub-pixels are all electrically connected to the driver wafer; all the pixel layers are sequentially stacked on the driver wafer in a Z direction; and all the sub-pixels of the parent pixel are respectively arranged in corresponding pixel layers. Further disclosed in the present invention is a manufacturing method for the micro-display chip. In the present invention, the number of red sub-pixels is effectively increased, thereby effectively controlling the attenuation of red light in the parent pixel, and thus ensuring an ideal color display effect.

Description

Multicolor microdisplay chip and its fabrication method

[0001] Priority information: This application claims priority to Chinese Patent Application No. 2024110133874, filed on July 26, 2024, and Chinese Patent Application No. 2024110133817, filed on July 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor technology, and in particular to a multicolor microdisplay chip and its fabrication method. Background Technology

[0003] In the LED field, color displays are mainly produced by combining RGB sub-pixels to form a parent pixel and then mixing them in different proportions. Theoretically, all colors in the spectrum can be produced by matching the three primary colors: red (R), green (G), and blue (B). Our perception of a certain color depends on two factors: the physical characteristics of the external object on the human eye and the visual characteristics of the human eye in processing stimuli. However, the final color labeling must conform to the visual laws of the human eye. The human retina has two types of photoreceptor cells: cone cells and rod cells. Rod cells are used to perceive light intensity and mainly work in low-light environments, while cone cells are used to perceive color and mainly work in bright light environments. Cone cells are further divided into three types: blue cone cells, green cone cells, and red cone cells. In order for the human retina to better perceive the corresponding colors, the brightness of the three primary colors of red, green and blue or two primary colors needs to reach a specific ratio when distributing light in an LED display. For example, three primary color pixels with a brightness ratio of 3 (red): 6 (green): 1 (blue) or 2 (red): 7 (green): 1 (blue) can be selected to achieve white light synthesis. At this time, color pixel layout methods such as RGB, RGGB or RGBW can generally be selected.

[0004] However, in the field of micro-displays, such as Micro-LED displays, the chip size is significantly smaller than that of conventional LED chips. As the size decreases, the brightness of red pixels decreases significantly. According to the conventional color pixel layout, it is difficult to achieve a specific brightness ratio, thus failing to achieve the ideal color display effect and failing to meet production and usage requirements. Summary of the Invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the defect of poor color display effect of micro display chips in the prior art.

[0006] To address the aforementioned technical problems, this invention provides a multicolor microdisplay chip, comprising:

[0007] A mother pixel includes at least four sub-pixels, at least two of the sub-pixels in the mother pixel have different light-emitting colors, and there is a sub-pixel with a light-emitting color of red, and the number of sub-pixels with a light-emitting color of red is not less than 50% of the total number of sub-pixels in the mother pixel.

[0008] A driving wafer, wherein each sub-pixel is electrically connected to the driving wafer;

[0009] At least two pixel layers are provided, and all of the pixel layers are stacked sequentially along the Z direction on the driving wafer. All of the sub-pixels of the mother pixel are respectively disposed in the corresponding pixel layers.

[0010] This invention also discloses a method for fabricating a multicolor microdisplay chip, comprising,

[0011] Step M1: Prepare the driving wafer;

[0012] Step M2: At least two pixel layers are stacked sequentially along the Z direction on the driving wafer, such that all sub-pixels in the mother pixel are respectively disposed in the corresponding pixel layers and the sub-pixels are electrically connected to the driving wafer, so as to drive the sub-pixels to emit light using the driving wafer.

[0013] The technical solution of the present invention has the following advantages compared with the prior art:

[0014] The multicolor microdisplay chip and its fabrication method described in this invention effectively increase the number of red sub-pixels, thereby effectively controlling the attenuation of red light in the mother pixel and ensuring an ideal color display effect. Attached Figure Description

[0015] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0016] Figure 1 is a brightness curve of a multicolor microdisplay chip according to the present invention;

[0017] Figure 2 is a schematic diagram of the first pixel distribution of the multicolor microdisplay chip of the present invention;

[0018] Figure 3 is a schematic diagram of the second pixel distribution of the multicolor microdisplay chip of the present invention;

[0019] Figure 4 is a comparative diagram of trapezoidal sub-pixels and hemispherical sub-pixels;

[0020] Figure 5 is a top view of the overall structure of the multicolor microdisplay chip of the present invention;

[0021] Figure 6 is a magnified view of part A in Figure 5;

[0022] Figure 7 is an internal structure diagram of the first type of mother pixel of the present invention;

[0023] Figure 8 is a schematic diagram of the arrangement of the bottom pixel layer in Figure 7;

[0024] Figure 9 is an internal structure diagram of the second type of mother pixel of the present invention;

[0025] Figure 10 is an internal structure diagram of the third type of mother pixel of the present invention;

[0026] Figure 11 is a schematic diagram of the arrangement of the bottom pixel layer in Figure 10;

[0027] Figure 12 is an internal structure diagram of the fourth type of mother pixel of the present invention;

[0028] Figure 13 is a magnified view of part Q in Figure 12;

[0029] Figure 14 is an internal structure diagram of the fifth type of mother pixel of the present invention;

[0030] Figure 15 is a magnified view of a portion of point S in Figure 14;

[0031] Figure 16 is an internal structure diagram of the sixth type of mother pixel of the present invention;

[0032] Figure 17 is a schematic diagram of one arrangement of the anode connector in this invention;

[0033] Figure 18 is a schematic diagram of another arrangement of the anode connector in this invention;

[0034] Figure 19 is a schematic diagram of the third pixel distribution of the present invention;

[0035] Figure 20 is an internal structure diagram of the seventh type of mother pixel of the present invention;

[0036] Figure 21 is a flowchart of the preparation process of the structure shown in Figure 20;

[0037] Figure 22 is an internal structure diagram of the eighth type of mother pixel of the present invention;

[0038] Figure 23 is a partial flowchart of the chip fabrication process of the present invention;

[0039] Figure 24 is a flowchart of the preparation process of the structure shown in Figure 7;

[0040] Figure 25 is an internal structure diagram of the ninth type of mother pixel of the present invention;

[0041] Figure 26 is a schematic diagram of the arrangement of the first pixel layer in Figure 25;

[0042] Figure 27 is an internal structure diagram of the tenth type of mother pixel of the present invention;

[0043] Figure 28 is a schematic diagram of the arrangement of the first pixel layer in Figure 27;

[0044] Figure 29 is a flowchart of the preparation process of the structure shown in Figure 25;

[0045] Explanation of reference numerals in the accompanying drawings: 10, Mother pixel; 20, Sub-pixel; 201, Pixel body; 2011, P-type ohmic contact layer; 2012, P-type semiconductor layer; 2013, Active layer; 2014, N-type semiconductor layer; 2015, N-type ohmic contact layer; 30, First pixel layer; 301, Insulating body; 302, Bonding layer; 3021, Bonding metal component; 3022, Conductive metal component; 303, Insulating passivation layer; 3031, Opening; 304, Common cathode layer; 3041, Second notch; 3042, Auxiliary hole; 305, Metal mesh layer; 3051, First notch; 306, Anode hole; 3061, Recess; 307, Anode connector; 3071, Protrusion; 308, Cathode hole; 309, Cathode connector; 40. Second pixel layer; 401. Red light color transfer element; 402. Filling hole; 403. Isolation layer; 50. Third pixel layer; 60. Interface; 70. Excitation pixel; 80. Driving wafer; 801. Anode contact; 802. Cathode contact; 90. Compound semiconductor; 901. Substrate; 100. Pixel array area; 110. Peripheral common cathode area; 120. Auxiliary pixel; 130. Lens. Detailed Implementation

[0046] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0047] In the description of this invention, it should be understood that the terms "vertical," "upper," "lower," "top," "side," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0048] Referring to Figures 1-29, this embodiment discloses a multicolor microdisplay chip, including a mother pixel 10, a driving wafer 80, and at least two pixel layers;

[0049] The mother pixel 10 includes at least four sub-pixels 20. At least two of the sub-pixels 20 in the mother pixel 10 have different light-emitting colors and have a sub-pixel with a light-emitting color of red. The number of sub-pixels with a light-emitting color of red is not less than 50% of the total number of sub-pixels in the mother pixel 10.

[0050] All sub-pixels 20 are electrically connected to the driving wafer 80, which contains a driving circuit to control the light emission of the sub-pixels 20; the driving wafer 80 can be a CMOS driving wafer.

[0051] At least two pixel layers are stacked sequentially along the Z direction on the driving wafer 80, and all sub-pixels 20 of the mother pixel 10 are respectively disposed in the corresponding pixel layers.

[0052] Furthermore, the number of sub-pixels with red light output can be 50% to 90% of the total number of sub-pixels in the mother pixel 10; specifically, it can be 60%, 65%, 70%, 75%, 85%, etc.

[0053] It should be noted that the specific pixel layer in which different colored subpixels are located can be selected as needed, and no limitation is made here;

[0054] In the above structure, by making the mother pixel include at least four sub-pixels and making the number of sub-pixels that produce red light greater than or equal to 50% of the total number of sub-pixels in the mother pixel, the number of red sub-pixels is effectively increased. This effectively controls the attenuation of red light in the mother pixel, thereby maintaining the brightness ratio of various colors at a specific ratio and achieving the ideal color display effect.

[0055] Each sub-pixel 20 includes a pixel body 201, and each pixel body 201 includes a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014 arranged sequentially along the Z direction. The active layer 2013 is used to emit light. The P-type semiconductor layer 2012 is disposed close to the driving wafer 80. A P-type ohmic contact layer 2011 is also disposed on the side of the P-type semiconductor layer 2012 that is close to the driving wafer 80. The P-type semiconductor layer 2012 is used to connect with the anode of the driving wafer 80 to achieve anode connection. The N-type semiconductor layer 2014 is used to connect with the cathode of the driving wafer 80 to achieve cathode connection.

[0056] It should be noted that, for ease of description, the microdisplay chip in this invention has a Z-direction, an X-direction, and a Y-direction, with each of the three directions being perpendicular to the others. The Z-direction is generally the direction away from the driving wafer. In this invention, "up" and "down" are relative terms in the Z-direction. Similarly, "top" and "bottom" or "high" and "low" are also relative terms in the Z-direction. The top pixel layer refers to the uppermost pixel layer, and the bottom pixel layer refers to the lowermost pixel layer. The bottom pixel layer is also called the first pixel layer. The pixel layers stacked on top of it are called the second layer, the third layer, and so on.

[0057] Example 1

[0058] The structure of the multicolor microdisplay chip in this embodiment will be further described in detail below with reference to Figures 1-18.

[0059] Referring to Figures 1-6, this embodiment discloses a multi-color microdisplay chip, including a mother pixel 10, a driving wafer 80, and three pixel layers, which are, from bottom to top (Z direction), the first pixel layer 30, the second pixel layer 40, and the third pixel layer 50.

[0060] The mother pixel 10 includes at least four sub-pixels 20. At least two of the sub-pixels 20 in the mother pixel 10 have different light-emitting colors and have a sub-pixel with a light-emitting color of red. The number of sub-pixels with a light-emitting color of red is not less than 50% of the total number of sub-pixels in the mother pixel 10.

[0061] Each sub-pixel 20 is electrically connected to the driving wafer 80 so that the driving wafer 80 can control the light emission of the sub-pixel 20;

[0062] The three pixel layers mentioned above are stacked sequentially along the Z direction. All the sub-pixels 20 of the mother pixel 10 are respectively set in the corresponding pixel layer. Each pixel layer has at least one sub-pixel 20. The light emitted by each sub-pixel 20 in the same pixel layer is the same, and the light emitted by the sub-pixels 20 in two adjacent pixel layers is different.

[0063] In this embodiment, the sub-pixel with the emitted light color of red has its own emitted light color of red, that is, it can emit red light directly without the need for a color conversion material layer to obtain red light.

[0064] For ease of description, the sub-pixel 20 with red light color is called the red sub-pixel, the sub-pixel 20 with green light color is called the green sub-pixel, and the sub-pixel 20 with blue light color is called the blue sub-pixel.

[0065] The aforementioned mother pixel has three sub-pixels with different emitted light colors: red sub-pixel R, green sub-pixel G, and blue sub-pixel B. These three sub-pixels are located in different pixel layers. The red sub-pixel can be placed in the first pixel layer 30 (bottom pixel layer), the green sub-pixel in the second pixel layer 40, and the blue sub-pixel in the third pixel layer 50 (top pixel layer). Alternatively, the red sub-pixel can be placed in the third pixel layer 50 (top pixel layer) to shorten the transmission path of red light emitted from above and further reduce attenuation. However, in actual operation, the specific pixel layer in which the different colored sub-pixels are located can be selected as needed and is not limited here.

[0066] For example, as shown in Figures 2 and 3, a mother pixel 10 includes four sub-pixels 20. Each sub-pixel 20 has a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The red sub-pixel R emits red light, the green sub-pixel G emits green light, and the blue sub-pixel B emits blue light. A microdisplay chip includes multiple mother pixels 10. In each mother pixel 10, the four sub-pixels 20 can be arranged in the RGRB pattern shown in Figure 2, with one green sub-pixel G and one blue sub-pixel B, and two red sub-pixels R arranged diagonally. The sub-pixels can be arranged in a single row along the Y direction, either as shown in Figure 3 (RRGB arrangement) or as shown in Figure 3 (one green sub-pixel G, one blue sub-pixel B, and two red sub-pixels R). If the combination of four sub-pixels still cannot meet the light distribution requirements of red light, the surrounding red sub-pixels can be used for light distribution. For example, in Figure 2, the mother pixel located in the lower right corner can use one red sub-pixel of the mother pixel above it for light distribution, or in Figure 3, the mother pixel located in the lower left corner can use two red sub-pixels of the mother pixel to the right for light distribution.

[0067] Figure 1 shows the brightness curves of the mother pixel 10. In Figure 1, "G" represents the brightness curve of the green sub-pixel, "B" represents the brightness curve of the blue sub-pixel, "R75%" represents the brightness curve of all red sub-pixels in the mother pixel (75% of the total number), "R50%" represents the brightness curve of all red sub-pixels in the mother pixel (50% of the total number), and "R25%" represents the brightness curve of all red sub-pixels in the mother pixel (25% of the total number). As can be seen from the brightness curves shown in Figure 1, when the number of red sub-pixels in the mother pixel is 50% or 75%, compared with 25%, its brightness curve shifts upward, and the overall brightness increases. This effectively controls the attenuation of red light, which is more conducive to ensuring the stability of light distribution, thereby achieving the ideal color display effect.

[0068] Understandably, the number of sub-pixels 20 in the mother pixel 10 can be more than four, and the specific number is not limited here.

[0069] Furthermore, the projections of all sub-pixels 20 in the mother pixel 10 onto the driving wafer 80 do not overlap, so as to minimize optical crosstalk or color noise caused by photoexcitation between sub-pixels 20, thereby controlling the light combining effect more precisely.

[0070] Figure 5 is a top view of a microdisplay chip. Each microdisplay chip includes multiple mother pixels 10 arranged in an array to form a pixel array area 100, and a peripheral common cathode area 110 is provided on the periphery. Figure 6 is a partial enlarged view of point A in Figure 5, showing the situation of a mother pixel and its surrounding common cathode area. Figure 7 is a cross-sectional view of the structure in Figure 6 along the a1-a2 path; the cross-sectional views of subsequent mother pixels, as shown in Figures 8-16, 20, 22, etc., are also cross-sectional views along this path.

[0071] The sub-pixel includes a pixel body 201, which includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014 arranged sequentially upward along the Z direction.

[0072] In one embodiment, as shown in Figure 7, the pixel body 201 can be trapezoidal or cylindrical. Compared to pixels with hemispherical or semi-ellipsoidal structures, the trapezoidal or cylindrical pixel body can effectively increase the pixel's light-emitting area, thereby increasing the light-emitting intensity. The pixel body generally has an active layer 2013 to emit light. As shown in Figure 4, with the same bottom size, the area of ​​the active layer 2013 (the entire shaded portion) in the trapezoidal pixel body is larger than the area of ​​the active layer (the shaded portion inside the hemisphere) in the hemispherical pixel body, thus effectively increasing the light-emitting intensity. Similarly, the cylindrical pixel body, compared to the hemispherical pixel body, can also increase the area of ​​the active layer, thereby effectively increasing the light-emitting intensity.

[0073] Furthermore, the tilt angle θ of the sidewall of the pixel body 201 relative to the driving wafer 80 is 45° to 135°; it can be understood that the sidewall of the pixel body 201 here refers to the wall between the top and bottom surfaces of the sub-pixel 20.

[0074] The aforementioned tilt angle can reduce total internal reflection and facilitate light extraction. Exceeding this range will reduce light extraction efficiency. In addition, due to the limited horizontal space, a certain amount of space needs to be reserved for subsequent processes. If the tilt angle is too small, the bottom surface of the pixel will occupy too much horizontal space, which will increase the difficulty of pixel spacing arrangement.

[0075] Preferably, the tilt angle θ of the sidewall of the pixel body 201 relative to the driving wafer 80 is 75° to 105°, which has the best light extraction efficiency and the best pixel pitch design.

[0076] In one embodiment, an anode contact 801 and a cathode contact 802 are provided on the driving wafer 80. Each pixel layer includes an insulating body 301. The pixel body 201 of the sub-pixel 20 in the pixel layer is covered inside the insulating body 301. Each pixel body 201 is provided with a bonding metal part 3021 on the side close to the driving wafer 80. That is, each pixel body has a bonding metal part 3021. The bonding metal part 3021 is electrically connected to the corresponding anode contact 801.

[0077] Each pixel body 201 is covered with an insulating passivation layer 303. The bonding metal part 3021 is located inside the insulating passivation layer 303. The upper part of the insulating passivation layer 303 has an opening 3031. The outer part of the insulating passivation layer 303 is covered with a common cathode layer 304. The pixel body 201 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to electrically connect to the cathode contact 802.

[0078] Understandably, each sub-pixel 20's pixel body 201 includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014 arranged sequentially upward along the Z direction. The P-type semiconductor layer 2012 has a bonding metal member 3021 disposed on the side near the driving wafer 80. A P-type ohmic contact layer 2011 is disposed between the P-type semiconductor layer 2012 and the bonding metal member 3021 to achieve ohmic contact between the P-type semiconductor layer 2012 and the bonding metal member 3021. Ultimately, the P-type semiconductor layer 2012 is electrically connected to the corresponding anode contact 801 through the bonding metal member 3021. The N-type semiconductor layer is exposed at the opening 3031, and the exposed portion is electrically connected to the common cathode layer 304. The insulating passivation layer 303 is used to insulate and isolate the N-type semiconductor layer 2014 and the P-type semiconductor layer 2012 in the sub-pixel 20 to prevent short circuits.

[0079] The bonding metal part 3021 can correspond one-to-one with the anode contact 801, or multiple anode contacts 801 can correspond to one bonding metal part 3021.

[0080] In some embodiments, as shown in stage d of FIG24, the height D of the pixel body 201 in the Z direction is 0.3um to 5um; preferably, D is 0.3um to 1.5um; wherein, the height of the pixel body 201 is the distance between its P-type semiconductor layer 2012 and N-type semiconductor layer 2014 (including the thickness of the P-type semiconductor layer 2012 to N-type semiconductor layer 2014 itself).

[0081] In some embodiments, the thickness of the P-type ohmic contact layer 2011 is 10 nm to 300 nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), or a metal alloy film such as AuBe or AnZn.

[0082] In some embodiments, the thickness d1 of the insulating passivation layer 303 is 30nm to 500nm to better ensure insulation and passivation capabilities.

[0083] In some embodiments, the thickness d2 of the common cathode layer 304 is 50nm to 500nm, so as to maximize its transmittance while ensuring current spread capability. The thicker the common cathode layer 304, the better the current spread, but the lower the transmittance, which will cause greater light loss and increase the processing difficulty. If the thickness is too thin, it will affect the metal current spread capability.

[0084] In one embodiment, the bonding metal part 3021 of the sub-pixel 20 in the upper pixel layer is electrically connected to the corresponding anode contact 801 by the anode connector 307 passing through the lower pixel layer. In the other pixel layers except the top layer, there are anode holes 306 corresponding to the anode connector 307. The anode holes 306 are filled with anode metal material to form the anode connector 307, so as to realize the anode connection between the upper sub-pixel 20 and the driving wafer 80 through the anode connector 307.

[0085] Understandably, subpixels in the bottom pixel layer can be directly connected to their corresponding anode contacts via bonding metal components.

[0086] As shown in Figure 7, in the first pixel layer, a sub-pixel 20 is disposed between two anode connectors 307. This sub-pixel can be a red sub-pixel. In other ways, multiple sub-pixels 20 can also be disposed between two anode connectors 307. The aforementioned anode connectors can surround the sub-pixels, serving not only as anode electrical connections but also as optical resonant cavities, thus preventing optical crosstalk between pixel units and improving pixel brightness.

[0087] In some embodiments, the cross-sectional area of ​​the portion of the anode hole 306 that is relatively far from the driving wafer 80 is larger than the cross-sectional area of ​​the portion that is relatively close to the driving wafer 80. This cross-sectional area refers to the area of ​​the cross section (section) obtained by cutting the anode hole with a plane perpendicular to the axis of the anode hole 306. That is, the anode hole has a shape that is wider at the top and narrower at the bottom, for example, it can be conical or Y-shaped.

[0088] In some preferred embodiments, as shown in Figure 8, the anode hole 306 is tapered with a cross-sectional area that increases toward the side away from the driving wafer. The aforementioned cross-sectional area refers to the area of ​​the cross section (section) obtained by cutting the anode hole with a plane perpendicular to the axis of the anode hole 306. The inclination angle φ of the inner wall of the anode hole 306 relative to the top surface of the driving wafer 80 is 90° to 120°.

[0089] The shape of the anode connector 307 is adapted to the shape of the anode hole 306, so that the anode connector 307 also has a structure that is wider at the top and narrower at the bottom. When the bottom length is the same, this shape can produce a thicker anode connector compared to the structure that is narrower at the top and wider at the bottom, thereby enhancing the anode electrical transmission capability.

[0090] In some embodiments, as shown in FIG8, in the Z direction, the distance H between the top surface of the insulating body 301 of each pixel layer and the common cathode layer 304 at the top of the sub-pixel of that layer is not less than 100nm, so as to prevent interlayer leakage caused by insulation abnormalities.

[0091] In one embodiment, an anode hole 306 corresponding to an anode connector 307 is provided on the interface 60 of two adjacent pixel layers. The anode hole 306 is filled with an anode connector 307. As shown in Figures 7-9, the top surface of the anode connector 307 filled in the anode hole 306 is lower than the interface 60 to form a recess 3061. The bonding metal part 3021 of the sub-pixel 20 in the pixel layer is embedded in the recess 3061 of the corresponding anode hole 306 of the adjacent pixel layer below and makes electrical contact with the anode connector 307.

[0092] Alternatively, as shown in Figures 10-11, the top surface of the anode connector 307 filling the anode hole 306 is higher than the interface 60 to form a protrusion 3071. The bonding metal 3021 of the sub-pixel 20 in the pixel layer is fitted with the protrusion 3071 of the corresponding anode connector 307 in the adjacent pixel layer below. This fitting method can avoid the formation of bonding voids between the bonding metal 3021 and the anode connector 307. Bonding voids will lead to poor electrical transmission. By using the above-mentioned protrusion-concave fitting method, the above problems can be effectively avoided, ensuring excellent electrical transmission effect. At the same time, it can also effectively increase the connection stability and connection strength of the bonding metal 3021 and the anode connector 307.

[0093] Furthermore, as shown in Figure 8, the height h1 of the recessed portion 3061 is 10nm to 300nm, and as shown in Figure 11, the height h2 of the protruding portion 3071 is 10nm to 300nm, in order to better avoid bonding voids and ensure electrical transmission performance. The aforementioned heights should not be too large, as excessive heights can increase manufacturing complexity, while insufficient heights will fail to guarantee adequate electrical transmission performance.

[0094] In some embodiments, the microdisplay chip includes three pixel layers. The bottom pixel layer is also called the first pixel layer 30, and the pixel layers stacked above it are called the second pixel layer 40, the third pixel layer 50, and so on. In the third and above pixel layers, the bonding metal parts 3021 of the subpixels can be electrically connected to the corresponding anode contacts 801 by multiple anode connectors 307 connected in sequence along the Z direction. Each anode connector 307 connected in sequence along the Z direction is located in a different pixel layer.

[0095] As shown in Figure 16, two adjacent anode connectors 307 along the Z direction are in direct contact. This method does not retain the bonding metal parts and other components between the two adjacent anode connectors, which is more conducive to avoiding poor electrical transmission caused by bonding voids. In the case where there are multiple pixel layers between the top sub-pixel 20 and the driving wafer 80, only one anode connector 307 can be set between the top sub-pixel 20 and the driving wafer 80, so that the anode connector directly penetrates all pixel layers between the top sub-pixel 20 and the driving wafer 80. For example, in Figure 17, there are three pixel layers, and one anode connector can be used to penetrate the two pixel layers below the top sub-pixel at the same time.

[0096] Alternatively, as shown in Figure 14, a conductive metal part 3022 can be provided between two adjacent anode connectors 307 along the Z direction. This method retains the bonding metal part of the two anode connectors 307 as the conductive metal part 3022, and the processing technology is simpler.

[0097] In one embodiment, cathode holes 308 are provided in all pixel layers except the top layer. Cathode holes 308 are filled with cathode connectors 309. Cathode connectors 309 are electrically connected to cathode contacts 802. The common cathode layers 304 in the upper pixel layers are electrically connected to the cathode connectors 309 and cathode contacts 802 in the lower pixel layers.

[0098] Understandably, in the specific arrangement, the common cathode layer 304 of the third pixel layer 50 is electrically connected sequentially through the cathode connectors 309 and cathode contacts 802 in the second pixel layer 40 and the first pixel layer 30. Similarly, the common cathode layer 304 of the second pixel layer 40 can be directly electrically connected to the cathode contact 802. Alternatively, the cathode connectors 309 in the second pixel layer 40 can be directly connected to the cathode contact 802, in which case the common cathode layer 304 of the third pixel layer 50 can also be directly electrically connected through the cathode connectors 309 and cathode contacts 802 in the second pixel layer 40. That is, the common cathode layer 304 in each pixel layer can be electrically connected sequentially through multiple cathode connectors 309 and cathode contacts 802 in the lower pixel layer, or it can be directly electrically connected to the cathode contact 802 through the pixel layer of the adjacent layer below.

[0099] In the case where there are multiple pixel layers between the top sub-pixel 20 and the driving wafer 80, only one cathode connector 309 can be provided between the pixel layer where the top sub-pixel is located and the driving wafer 80, so that the cathode connector 309 directly penetrates all pixel layers between the top pixel layer and the driving wafer 80. For example, in Figure 18, there are three pixel layers, so one cathode connector can be used to penetrate the two lower pixel layers at the same time.

[0100] Furthermore, a cathode hole 308 is also provided on the interface 60 between two adjacent pixel layers. The top surface of the cathode connector 309 filled in the cathode hole 308 is lower than the interface 60 to form a recess, or the top surface of the cathode connector 309 filled in the cathode hole 308 is higher than the interface 60 to form a protrusion. This is similar to the arrangement of the anode connector 307, and will not be described in detail here.

[0101] In one embodiment, as shown in Figures 12 and 14, the interface 60 between two adjacent pixel layers is also covered by an insulating passivation layer 303. The upper part of the insulating passivation layer 303 at the interface is covered by a common cathode layer 304. A metal mesh layer 305 is provided on the upper part of the common cathode layer 304 so as to achieve the effect of enhancing the cathode current through the metal mesh layer 305.

[0102] Furthermore, the metal mesh layer 305 can be made of one or more materials selected from Cr, Pt, Ti, Au, Al, Cu, TiN and TaN.

[0103] In one embodiment, the thickness d3 of the metal mesh layer 305 is 100nm to 5000nm. This relatively thin thickness increases the spacing between the metal mesh layer 305 and the upper bonding metal part 3021, allowing sufficient space between the metal mesh layer 305 and the upper bonding metal part 3021 to fill the insulating body 301. This effectively avoids the risk of short circuit between the metal mesh layer 305 and the upper bonding metal part 3021, resulting in better insulation and higher safety.

[0104] In one embodiment, as shown in Figures 12-13, the light emitted from the sub-pixel 20 in the lower pixel layer is emitted through the first notch 3051 in the upper pixel layer. The first notch 3051 is formed on the metal mesh layer 305. The length L1 of the first notch 3051 in the X direction is greater than the top surface length L2 of the corresponding sub-pixel 20 in the lower layer, so that the light emitted from the lower sub-pixel 20 can be emitted through the first notch 3051 to the maximum extent, thereby improving the light extraction efficiency of the pixel.

[0105] Understandably, the "corresponding sub-pixel" here refers to the sub-pixel 20 through which the emitted light passes the first notch 3051. If all sub-pixels in this layer have the same size, then the length L1 of the first notch 3051 in the X direction is greater than the top surface length L2 of each sub-pixel in this layer.

[0106] The above method creates a first notch 3051 on the metal mesh layer 305 at the interface 60 between two adjacent pixel layers, that is, removes the metal mesh material in the first notch 3051, so as to reduce the obstruction of the light emitted from the bottom sub-pixel by the metal mesh in the original notch, so that the light emitted from the sub-pixel in the lower pixel layer does not have to pass through the metal mesh layer 305, reducing light loss and making the bottom sub-pixel have higher light extraction efficiency.

[0107] The above method allows for the setting of notches only on the metal mesh layer 305, without setting notches on the common cathode layer 304.

[0108] The number of openings in the first gap 3051 can be determined based on the number of lower-layer sub-pixels 20.

[0109] Alternatively, a large gap can be made in the metal mesh layer 305 of the top pixel layer, such that the length of the large gap in the X direction is greater than the sum of the top surface lengths of all sub-pixels in the two layers below that emit light through that gap.

[0110] In each pixel layer, the metal mesh layer 305 is a whole, and the first notch 3051 is equivalent to a hole opened in the metal mesh layer 305.

[0111] In one embodiment, as shown in Figures 14-15, the light emitted from the sub-pixel 20 in the lower pixel layer passes through the second notch 3041 and the first notch 3051 in the upper pixel layer in sequence before being emitted. The second notch 3041 is formed on the common cathode layer 304, and the length L3 of the second notch 3041 in the X direction is greater than the top surface length L2 of the corresponding sub-pixel in the lower layer.

[0112] Understandably, the "corresponding sub-pixel" here refers to the sub-pixel 20 whose emitted light rays pass through the second notch 3041 and the first notch 3051 in sequence. If all sub-pixels in this layer have the same size, then the length of the second notch 3041 in the X direction is greater than the top surface length of each sub-pixel in this layer.

[0113] The above method creates a second notch 3041 on the common cathode layer 304 at the interface 60 between two adjacent pixel layers, which removes the common cathode material in the second notch 3041. This allows the light emitted from the sub-pixel 20 in the lower pixel layer to be emitted without passing through the common cathode, further reducing light loss and giving the bottom sub-pixel higher light extraction efficiency.

[0114] The number of openings of the second gap 3041 can be determined according to the number of sub-pixels 20 in the lower layer. The second gap 3041 and the first gap 3051 can correspond one-to-one.

[0115] In each pixel layer, the common cathode layer 304 is a whole, and the second notch 3041 is equivalent to a hole opened in the common cathode layer 304.

[0116] The anode connector 307 in the bottom pixel layer can be configured in the following two ways:

[0117] In one approach, an anode connector 307 is provided in a separate space between two adjacent sub-pixels 20 in the X direction in the bottom pixel layer, wherein the X direction and the Z direction are perpendicular.

[0118] In another approach, the original sub-pixel 20 between two adjacent sub-pixels 20 in the X direction of the bottom pixel layer is retained as an auxiliary pixel 120. This allows the anode connector 307 in the bottom pixel layer to pass through an auxiliary pixel 120 and then be electrically connected to the corresponding anode contact 801 on the driving wafer 80. This approach avoids the need to re-fabricate the bottom pixel layer and allows the existing single-layer monochrome product to be used directly. In other words, the second and higher pixel layers can be directly superimposed on the existing single-layer product. This method is faster and reduces the cost of separately fabricating the bottom pixel layer.

[0119] It should be noted that after the auxiliary pixel 120 is penetrated by the anode connector 307, the auxiliary pixel 120 cannot emit light normally and is only used as a connector.

[0120] Understandably, the anode connector 307 needs to pass through the common cathode layer 304 and the insulating passivation layer 303 outside the auxiliary pixel 120 in sequence before being electrically connected to the anode contact 801 of the driving wafer 80. In order to avoid the anode connector 307 from contacting the common cathode layer 304 outside the auxiliary pixel 120, an auxiliary hole 3042 is provided on the common cathode layer 304 for the anode connector 307 to pass through, as shown in stage a of Figure 21. The length L4 of the auxiliary hole 3042 in the X direction is greater than the length L5 of the opening 3031 of the insulating passivation layer 303 at the top of the auxiliary pixel 120.

[0121] In one embodiment, at least one lens 130 is connected to the upper part of the top pixel layer. The lens 130 can be arranged in two ways: one is that the lens 130 corresponds one-to-one with the mother pixel 10, and the other is that each lens 130 corresponds one-to-one with the sub-pixel 20. This method is to better collimate the emitted light of each sub-pixel 20 and further reduce light interference in the mother pixel.

[0122] This embodiment also discloses a method for fabricating a microdisplay chip, including,

[0123] Step M1: Prepare driver wafer 80;

[0124] Step M2: Three pixel layers are stacked sequentially along the Z direction on the driving wafer 80, so that all sub-pixels 20 in the mother pixel 10 are respectively set in the corresponding pixel layer. Each pixel layer has at least one sub-pixel 20. The light emitted by each sub-pixel 20 in the same pixel layer is the same, and the light emitted by the sub-pixels 20 in two adjacent pixel layers is different. The sub-pixels 20 are electrically connected to the driving wafer 80 so that the driving wafer 80 drives the sub-pixels 20 to emit light.

[0125] In one embodiment, when fabricating the driving wafer 80, an anode contact 801 and a cathode contact 802 need to be fabricated on the driving wafer 80; and when fabricating the pixel layer, the sub-pixels 20 in the pixel layer are all covered inside the insulating body 301. A bonding metal part 3021 is provided on the side of each sub-pixel 20 near the driving wafer 80, so that the bonding metal part 3021 is electrically connected to the corresponding anode contact 801. The outside of each sub-pixel 20 is covered with an insulating passivation layer 303. The bonding metal part 3021 is located inside the insulating passivation layer 303. The upper part of the insulating passivation layer 303 has an opening 3031. The outside of the insulating passivation layer 303 is covered with a common cathode layer 304. The sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to be electrically connected to the cathode contact 802.

[0126] In the specific preparation process, step M2 includes:

[0127] Step M21: Bond a compound semiconductor 90 onto the driving wafer 80;

[0128] As shown in Figure 23, the compound semiconductor 90 includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014, and a substrate 901, which are sequentially disposed away from the driving wafer direction. After the compound semiconductor 90 is bonded to the driving wafer 80, the substrate 901 needs to be removed to expose the N-type semiconductor layer 2014. After removing the substrate 901, an N-type ohmic contact layer 2015 can also be disposed on the N-type semiconductor layer 2014.

[0129] Furthermore, the thickness of the N-type ohmic contact layer 2015 is in the range of 10nm to 300nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), or a metal alloy film such as gold-germanium alloy (AuGe) or gold-nickel alloy (AuNi).

[0130] Preferably, the thickness of the N-type ohmic contact layer 2015 is 10nm to 100nm, so as to ensure ohmic contact while also giving it high transmittance, thereby reducing light loss.

[0131] Among them, the compound semiconductor 90 can be bonded to the driving wafer 80 through the bonding layer 302, and the bonding alignment accuracy can be 10~500um.

[0132] Step M22: Pattern the compound semiconductor 90 to obtain at least one sub-pixel 20, such that the sub-pixel 20 is electrically connected to the corresponding anode contact 801 through the bonding layer 302; the bonding layer 302 includes a plurality of bonding metal elements 3021, such that the pixel body 201 of each sub-pixel 20 corresponds to a bonding metal element 3021, and the pixel body 201 of the sub-pixel 20 is electrically connected to the corresponding anode contact 801 through the corresponding bonding metal element 3021;

[0133] Each bonding metal part 3021 is obtained by etching the bonding layer 302; here, the anode contact 801 and the sub-pixel 20 correspond one-to-one, or multiple anode contacts 801 can correspond to one sub-pixel 20.

[0134] Step M23: Deposit an insulating passivation layer 303 on the outside of the pixel body 201 of the sub-pixel 20, and provide an opening 3031 on the upper part of the insulating passivation layer 303 to expose the N-type semiconductor layer 2014 or N-type ohmic contact layer 2015 of the sub-pixel 20.

[0135] Step M24: Deposit a common cathode layer 304 on the outside of the insulating passivation layer 303, so that the pixel body 201 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to electrically connect with the cathode contact 802. See stage d in Figure 24.

[0136] That is, the N-type semiconductor layer 2014 of the pixel body 201 is electrically connected through the common cathode layer 304 and the cathode contact 802 to achieve cathode connection;

[0137] The driver wafer 80 may have only one cathode contact 802, or the number of cathode contacts 802 may be determined as needed.

[0138] Step M25: Fill the outside of the common cathode layer 304 with an insulating body 301 so that the pixel body 201 of the sub-pixel 20 is located inside the insulating body 301, thereby obtaining a pixel layer, see stage e in Figure 24.

[0139] Understandably, the insulating passivation layer 303 and the common cathode layer 304 outside the pixel body 201 are also located inside the insulating body 301.

[0140] Step M26: Bond another compound semiconductor 90 to the top of the previous pixel layer through bonding layer 302, and perform steps M22-M25 to obtain the next pixel layer, see stage f in Figure 24;

[0141] Step M27, repeat step M26 until all pixel layers are prepared, see stage g in Figure 24;

[0142] In this system, each sub-pixel in the same pixel layer emits the same light color, while sub-pixels in two adjacent pixel layers emit different light colors.

[0143] Understandably, the bonding metal part 3021 located between adjacent anode connectors in the Z direction can be directly used as the conductive metal part 3022. Understandably, since the light-emitting colors of sub-pixels in two adjacent pixel layers are different, the materials of the compound semiconductor 90 used in the fabrication of adjacent pixel layers are also different, so that the light-emitting colors of the compound semiconductor 90 used are different; when fabricating each pixel layer, the light-emitting color of the selected compound semiconductor 90 is determined according to the actual situation. If it is necessary to fabricate a sub-pixel with a red light-emitting color, then a compound semiconductor with a red light-emitting color is selected.

[0144] Among them, the compound semiconductor 90 uses inorganic compound materials. For example, the compound semiconductor corresponding to the blue light pixel layer uses InGaN material, the compound semiconductor corresponding to the green light pixel layer uses InGaN material, and the compound semiconductor corresponding to the red light pixel layer uses InGaN or AlGaInP material.

[0145] In practical applications, the layers of compound semiconductors are more complex, or there may be cross-use of materials. A typical compound semiconductor structure mainly includes a P-type semiconductor layer, an N-type semiconductor layer, and an active layer (MQW active quantum well) sandwiched between the two, as well as other functional layers. For the materials of each layer of red compound semiconductors, please refer to Table 1; for the materials of each layer of green and blue compound semiconductors, please refer to Table 2.

[0146] Table 1. Material of each film layer in compound semiconductor (R)

[0147] Table 2 Material of each film layer in compound semiconductors (G / B)

[0148] In one embodiment, the insulating passivation layer 303 may be made of one or more of aluminum oxide, silicon dioxide, and silicon nitride.

[0149] In one embodiment, the insulating body 301 may be made of one or more of silicon oxide, silicon nitride, silicon carbide (SiC), silicon carbon nitride (SiCN), phosphate glass (PSG), and borosilicate glass (BPSG).

[0150] In one embodiment, the common cathode layer 304 includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), Al-doped zinc oxide (AZO), Al-doped indium tin oxide, Ag-doped indium tin oxide, and Au-doped indium tin oxide.

[0151] In one embodiment, the metal mesh layer 305 may be made of one or more of the following materials: Cr, Pt, Ti, Au, Al, Cu, TiN, and TaN.

[0152] In one embodiment, the anode connector 307 may be made of one or more of aluminum, copper, and tungsten.

[0153] Furthermore, the cathode connector 309 can be made of the same material as the anode connector, which is a conductive material.

[0154] In one embodiment, the material of the bonding metal part 3021 can be one of Al, Au, Cu, or a stacked structure of Ni, Au, Cu and Sn, or a bonding stack of Au with In or Ge, or a bonding stack of Au with Si.

[0155] Furthermore, the aforementioned bonding metal part 3021 can adopt the following structural form: Cr2nm / Pt50nm / Ti10nm / Pt50nm / Au100nm / Sn150nm / Au50nm, wherein Cr is the adhesive layer and Pt / Ti / Pt is the barrier layer.

[0156] Furthermore, after the fabrication of all pixel layers is completed in step M2, referring to stage h in Figure 24, a dielectric layer is deposited on top of the top pixel layer, and the dielectric layer is patterned and etched to form a lens 130, so that the lens 130 corresponds one-to-one with the mother pixel 10, that is, one mother pixel 10 corresponds to one lens 130; or, each lens 130 corresponds one-to-one with the sub-pixel 20, that is, each sub-pixel 20 corresponds to a lens 130, so as to better collimate the emitted light of each sub-pixel 20 and further reduce light interference within the mother pixel;

[0157] In one embodiment, when other pixel layers besides the top layer are fabricated, an anode hole 306 is also formed on the insulating body 301, and the anode hole 306 is filled with anode metal material to form an anode connector 307, so that the bonding metal part 3021 of the sub-pixel 20 in the pixel layer is electrically connected to the corresponding anode contact 801 by the anode connector 307 passing through the lower pixel layer.

[0158] After the insulating body 301 is prepared, CMP planarization can be performed first, and then patterned dry etching can be performed on the insulating body 301 to prepare the above-mentioned anode hole 306.

[0159] Furthermore, in the specific fabrication of the anode connector 307, an anode hole 306 is first formed on the interface 60 between two adjacent pixel layers. Then, an anode metal material is filled into the anode hole 306 to form the anode connector 307. Ultimately, the top surface of the anode connector 307 filled in the anode hole 306 is lower than the interface 60, forming a recess 3061; or,

[0160] Anode metal material is filled into anode hole 306 to form anode connector 307, such that the top surface of anode connector 307 filled in anode hole 306 is higher than interface 60 to form protrusion 3071.

[0161] In some embodiments, auxiliary pixels 120 are also prepared during the preparation of the bottom pixel layer, such that the anode connector 307 in the bottom pixel layer corresponds to the auxiliary pixel 120. A through anode hole 306 is prepared in the auxiliary pixel 120, and the anode hole 306 is filled with anode metal material to form the anode connector 307. Thus, the anode connector 307 located in the bottom pixel layer passes through the corresponding auxiliary pixel 120 and is electrically connected to the corresponding anode contact 801 on the driving wafer 80.

[0162] This embodiment can be used to prepare a chip structure with three pixel layers, as shown in Figure 7. Each pixel layer emits a different light color. The three pixel layers can be configured as the layer containing red sub-pixels, the layer containing green sub-pixels, and the layer containing blue sub-pixels, respectively, to achieve a three-primary-color configuration. Here, the red sub-pixel emits red light, the green sub-pixel emits green light, and the blue sub-pixel emits blue light.

[0163] In one embodiment, multiple pixel structures corresponding to microdisplay chips can be arranged on each driving wafer 80. Each microdisplay chip can correspond to an independent bonding layer 302. That is, before the pixel fabrication of the microdisplay chip, multiple non-continuous independent bonding layers 302 can be fabricated on the driving wafer 80, so that the bonding layer at this time corresponds one-to-one with the subsequent microdisplay chip. In the subsequent fabrication process of the microdisplay chip, the bonding layer can be further etched to form multiple bonding metal parts 3021.

[0164] An insulating dielectric layer may be filled between the discontinuous bonding layers 302; the aforementioned discontinuous bonding layers can achieve better improvement of bonding warpage and be used for metal cost control; in each microdisplay chip, the four sides of the bonding layer 302 are more outward than the peripheral common cathode region 110, with an outward expansion width of at least 50um, and further, the outward expansion width is between 50um and 500um.

[0165] Understandably, if necessary, more pixel layers can be added on top of the above three pixel layers.

[0166] Example 2

[0167] As shown in Figures 19-22, the main difference between this embodiment and Embodiment 1 is that the multi-color microdisplay chip in this embodiment includes a mother pixel 10, a driving wafer 80, and two pixel layers to achieve a dual-color configuration.

[0168] The mother pixel 10 includes at least four sub-pixels 20. At least two of the sub-pixels 20 in the mother pixel 10 have different light-emitting colors and have a sub-pixel with a light-emitting color of red. The number of sub-pixels with a light-emitting color of red is not less than 50% of the total number of sub-pixels in the mother pixel 10.

[0169] Each sub-pixel 20 is electrically connected to the driving wafer 80 so that the driving wafer 80 can control the light emission of the sub-pixel 20;

[0170] Two pixel layers are stacked sequentially along the Z direction. All sub-pixels 20 of the mother pixel 10 are set in the corresponding pixel layer. Each pixel layer has at least one sub-pixel 20. The emitted light color of each sub-pixel 20 in the same pixel layer is the same, while the emitted light color of the sub-pixels 20 in two adjacent pixel layers is different.

[0171] The aforementioned mother pixel 10 has two sub-pixels 20 with different emitted light colors: a red sub-pixel R and a green sub-pixel. These two types of sub-pixels 20 are located in different pixel layers. The red sub-pixel can be placed in the first pixel layer 30 (the bottom pixel layer), and the green sub-pixel can be placed in the second pixel layer 40. In actual operation, the specific pixel layer in which the different colored sub-pixels are located can be selected as needed; no limitation is made here.

[0172] Specifically, the mother pixel 10 includes four sub-pixels 20. The four sub-pixels 20 in each mother pixel 10 can be arranged in the RGRR manner shown in Figure 19, with three red sub-pixels R and one green sub-pixel G. In the specific arrangement, as shown in Figure 20, three red sub-pixels can be arranged in the first pixel layer 30 and one green sub-pixel can be arranged in the second pixel layer 40; or as shown in Figure 22, one green sub-pixel can be arranged in the first pixel layer 30 and three red sub-pixels can be arranged in the second pixel layer 40.

[0173] Furthermore, the projections of all sub-pixels 20 in the mother pixel 10 onto the driving wafer 80 do not overlap, so as to minimize optical crosstalk or color noise caused by photoexcitation between sub-pixels, thereby controlling the light combining effect more precisely.

[0174] In one embodiment, the cathode connector 309 in the bottom pixel layer can also penetrate through an auxiliary pixel 120 and be electrically connected to the corresponding cathode contact 802 on the driving wafer 80. This method avoids the need to re-fabricate the bottom pixel layer and allows the existing single-layer monochrome product to be directly reused. That is, the second and higher pixel layers can be directly superimposed on the existing single-layer product, making the fabrication process faster and reducing the cost of separately fabricating the bottom pixel layer. It is understood that the cathode connector 309 in Embodiment 1 can also adopt this configuration that penetrates through the bottom auxiliary pixel 120, which will not be elaborated here.

[0175] In this embodiment, the sub-pixel colors in the two pixel layers can be red and blue sub-pixels respectively, or red sub-pixels and other color sub-pixels. The choice can be made according to actual needs.

[0176] The fabrication method of the microdisplay chip in this embodiment is shown in Figure 21. The fabrication method is basically the same as that in Embodiment 1, except that the number of pixel layers is two. The specific fabrication method will not be described in detail here.

[0177] Example 3

[0178] In Embodiments 1 and 2, sub-pixels form sub-pixels corresponding to their emitted light colors based on their own emitted light colors. For example, a sub-pixel emitting red light has red emitted light, a sub-pixel emitting green light has green emitted light, and a sub-pixel emitting blue light has blue emitted light. It is understood that a sub-pixel emitting a certain color does not necessarily need to emit light of that color itself; the color of its emitted light can be changed to the corresponding color through other methods, such as color conversion, which will be discussed below.

[0179] Referring to Figures 25-30, this embodiment discloses a multicolor microdisplay chip based on color conversion. The main difference between this embodiment and embodiments one and two is that each sub-pixel with a red light emission color includes an excitation pixel 70 and a red light color conversion element 401. The red light color conversion element 401 is located on the light emission path of the excitation pixel 70 to form a sub-pixel with a red light emission color.

[0180] The multicolor microdisplay chip in this embodiment includes a mother pixel 10, a driving wafer 80, and two pixel layers, which are the first pixel layer 30 and the second pixel layer 40 from bottom to top (Z direction);

[0181] As shown in Figures 2 and 3, the mother pixel 10 includes at least four sub-pixels 20. At least two of the sub-pixels 20 in the mother pixel 10 have different light-emitting colors and have a sub-pixel with a light-emitting color of red. The number of sub-pixels with a light-emitting color of red is not less than 50% of the total number of sub-pixels in the mother pixel 10.

[0182] Each sub-pixel with a red light emission color includes an excitation pixel 70 and a red light color converter 401. The red light color converter 401 is located on the light emission path of the corresponding excitation pixel 70, so that the excitation pixel 70 emits light to excite the red light color converter 401 to emit red light, thereby forming a sub-pixel with a red light emission color.

[0183] As shown in Figure 25, the first pixel layer 30 is stacked on the driving wafer 80 along the Z direction, and the first pixel layer 30 is provided with excitation pixels 70.

[0184] The second pixel layer 40 is stacked on the first pixel layer 30 along the Z direction. The second pixel layer 40 is provided with a green light-emitting sub-pixel 20 and a red light color converter 401. Each red light color converter 401 corresponds to an excitation pixel 70. Optionally, the green light-emitting sub-pixel 20 emits green light itself.

[0185] All of the sub-pixels 20 mentioned above are electrically connected to the driving wafer 80, which has a driving circuit to control the sub-pixels 20 to emit light. It can be understood that a sub-pixel that emits red light only needs to be electrically connected to the excitation pixel 70 and the driving wafer 80.

[0186] The driver wafer 80 can be a CMOS driver wafer;

[0187] It should be noted that the light emission wavelength of the excitation pixel 70 is shorter than that of red light, so that the shorter wavelength light is used to excite the red light color transfer element 401 to undergo color transfer and emit red light. The red light color transfer element 401 is made of quantum dot material or red phosphor material.

[0188] With the above structure, all the sub-pixels of the mother pixel 10 are set in the corresponding pixel layer, and can eventually emit light of the corresponding color.

[0189] In some methods, as shown in Figure 27, the red light color converter 401 and the excitation pixel 70 are in one-to-one correspondence. Alternatively, one red light color converter 401 can correspond to multiple excitation pixels 70, as long as the red light color converter 401 is located on the light emission path of the corresponding excitation pixel 70.

[0190] When arranging the red light color transfer element 401, the red light color transfer element can be positioned entirely above the corresponding excitation pixel 70, or the red light color transfer element 401 can cover part of the corresponding excitation pixel 70, so that the upper part or a part of the side of the excitation pixel 70 is covered by the red light color transfer element 401.

[0191] Furthermore, the number of sub-pixels with red light output can be 50% to 90% of the total number of sub-pixels in the mother pixel 10; specifically, it can be 60%, 65%, 70%, 75%, 85%, etc.

[0192] In the above structure, by making the mother pixel include at least four sub-pixels and making the number of sub-pixels that produce red light greater than or equal to 50% of the total number of sub-pixels in the mother pixel, the number of red sub-pixels is effectively increased. This effectively controls the attenuation of red light in the mother pixel, thereby maintaining the brightness ratio of various colors at a specific ratio and achieving the ideal color display effect.

[0193] Furthermore, as shown in Figure 25, the first pixel layer 30 also includes a sub-pixel 20 with a blue light emission color. The light emission color of this sub-pixel is blue, and the light emission color of the excitation pixel 70 is also blue. This makes the first pixel layer 30 consist entirely of pixels with a blue light emission color, which is easier to manufacture. It is only necessary to make some pixels in this layer only used as excitation pixels 70, and other pixels used as blue sub-pixels 20. No other sub-pixels are set on the light emission path above the blue sub-pixel 20, so that blue light can be emitted through the second pixel layer 40. Then, the light emitted by the mother pixel 10 through the second pixel layer 40 will have three different colors of light: blue light emitted by the blue sub-pixel 20, green light emitted by the green sub-pixel 20, and red light emitted by the red light color converter 401.

[0194] In one embodiment, the emitted color of the excitation pixel 70 may also be different from that of the blue sub-pixel.

[0195] In this invention, the microdisplay chip has a Z-direction, an X-direction, and a Y-direction, which are perpendicular to each other. The Z-direction is generally the direction away from the driving wafer. In this invention, "up" and "down" are relative terms in the Z-direction. Similarly, "top" and "bottom" or "high" and "low" are also relative terms in the Z-direction.

[0196] For ease of description, subpixels emitting red light are called red subpixels, subpixels emitting green light are called green subpixels, and subpixels emitting blue light are called blue subpixels.

[0197] For example, as shown in Figures 2 and 3, a mother pixel 10 includes four sub-pixels 20. Each sub-pixel 20 has a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The red sub-pixel R emits red light, the green sub-pixel G emits green light, and the blue sub-pixel B emits blue light. A microdisplay chip includes multiple mother pixels 10. In each mother pixel 10, the four sub-pixels 20 can be arranged in the RGRB pattern shown in Figure 2, with one green sub-pixel G and one blue sub-pixel B, and two red sub-pixels R arranged diagonally. The sub-pixels can be arranged in a single row along the Y direction, either as shown in Figure 3 (RRGB arrangement) or as shown in Figure 3 (one green sub-pixel G, one blue sub-pixel B, and two red sub-pixels R). If the combination of four sub-pixels still cannot meet the light distribution requirements of red light, the surrounding red sub-pixels can be used for light distribution. For example, in Figure 2, the mother pixel located in the lower right corner can use one red sub-pixel of the mother pixel above it for light distribution, or in Figure 3, the mother pixel located in the lower left corner can use two red sub-pixels of the mother pixel to the right for light distribution.

[0198] Figure 1 shows the brightness curves of the mother pixel 10. In Figure 1, "G" represents the brightness curve of the green sub-pixel, "B" represents the brightness curve of the blue sub-pixel, "R75%" represents the brightness curve of all red sub-pixels in the mother pixel (75% of the total number), "R50%" represents the brightness curve of all red sub-pixels in the mother pixel (50% of the total number), and "R25%" represents the brightness curve of all red sub-pixels in the mother pixel (25% of the total number). As can be seen from the brightness curves shown in Figure 1, when the number of red sub-pixels in the mother pixel is 50% or 75%, compared with 25%, its brightness curve shifts upward, and the overall brightness increases. This effectively controls the attenuation of red light, which is more conducive to ensuring the stability of light distribution, thereby achieving the ideal color display effect.

[0199] Understandably, the number of child pixels in a mother pixel can be more than four, and the specific number is not limited here.

[0200] Furthermore, the projections of all sub-pixels in the mother pixel 10 onto the driving wafer do not overlap, in order to minimize optical crosstalk between sub-pixels or color noise caused by photoexcitation, thereby controlling the light combining effect more precisely.

[0201] The red sub-pixel is the whole consisting of the excitation pixel 70 and the corresponding red light color transfer element 401. The projections of the excitation pixel 70 and the red light color transfer element 401 on the driving wafer are preferably overlapping, so that the projection of one is located inside the projection of the other, so that the two are coaxially arranged, so that the light emitted by the excitation pixel can reach the red light color transfer element well, thereby exciting the red light color transfer element to emit red light.

[0202] Figure 5 is a top view of a microdisplay chip. Each microdisplay chip includes multiple mother pixels 10 arranged in an array, forming a pixel array area 100. A peripheral common cathode area 110 is provided on the periphery. Figure 6 is a partial enlarged view of point A in Figure 5, showing the situation of a mother pixel and its surrounding common cathode area. Figure 25 is a cross-sectional view of the structure in Figure 6 at the a1-a2 path. The cross-sectional views of the subsequent mother pixels, as shown in Figures 26-28, are also cross-sectional views at this path.

[0203] In some embodiments, as shown in FIG25, the second pixel layer 40 is provided with filling holes 402, and each filling hole 402 is filled with a red light color transfer element 401.

[0204] Furthermore, as shown in Figure 27, the inner wall of the filling hole 402 is inclined relative to the driving wafer 80, with an inclination angle C of 60° to 90°, to facilitate etching and ensure filling effect.

[0205] In some embodiments, the length Ls of the filling hole 402 along the X direction is not less than the maximum length of the lower excitation pixel 70 in the X direction, wherein the X direction is perpendicular to the Z direction. This method can provide a good light path for the lower excitation pixel 70 and reduce the occurrence of light crosstalk, thereby maximizing the color conversion effect.

[0206] In some embodiments, an insulating layer 403 is formed on the inner wall of the filling hole 402; the insulating layer 403 is used to shield the light interference from the pixels below the non-filled space, so that the color transfer component inside the filling hole can have a better color transfer effect.

[0207] The insulating layer 403 can be a metal reflective layer or a light-absorbing layer.

[0208] The metal reflective layer can be made of one or more metals such as Al, Ti, Pt, Au, Cr and Ni, to shield light interference through metal reflection; the light-absorbing layer can be made of light-absorbing materials such as carbon film, black glue, polycrystalline silicon, etc., to shield light interference through light absorption.

[0209] Furthermore, the thickness of the insulating layer 403 is 50nm to 2um. If the thickness is too thin, leakage is likely to occur, while if it is too thick, the cost will increase.

[0210] Specifically, the required thickness for optical interference shielding can be achieved based on the different materials used, such as Al ≥ 50nm and black glue ≥ 1um.

[0211] In some embodiments, the red light color transfer element 401 can be made of quantum dot material, such as indium phosphide (InP); or it can be made of phosphor material, such as fluoride system phosphor-KSF red phosphor (K2SiF6:Mn4+), or nitride Eu2+ doped CaAlSiN3 based red phosphor, etc.

[0212] In some embodiments, the excitation pixel 70, the sub-pixel with blue light emission color, and the sub-pixel with green light emission color all include a pixel body 201, wherein the pixel body 201 includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014 arranged sequentially along the Z direction.

[0213] In some embodiments, the aforementioned pixel body 201 may be trapezoidal or cylindrical.

[0214] As shown in Figure 25, the pixel body 201 is trapezoidal or cylindrical. Compared to hemispherical or semi-ellipsoidal pixel bodies, the trapezoidal or cylindrical shape effectively increases the pixel's light-emitting area, thereby increasing the light-emitting intensity. The pixel body generally contains an active layer 2013 to emit light. As shown in Figure 4, with the same bottom pixel size, the active layer area (the entire shaded area) of the trapezoidal pixel body is larger than the active layer area (the shaded area inside the hemisphere) of the hemispherical pixel body, thus effectively increasing the light-emitting intensity. Similarly, the cylindrical pixel body, compared to the hemispherical pixel body, can also increase the area of ​​the active layer, thereby effectively increasing the light-emitting intensity.

[0215] In some embodiments, as shown in Figures 25-26, an anode contact 801 and a cathode contact 802 are provided on the driving wafer 80. The excitation pixel, the blue sub-pixel, and the green sub-pixel all include a pixel body 201. The first pixel layer 30 and the second pixel layer 40 both include an insulating body 301. The pixel bodies 201 in the pixel layer are all covered inside the insulating body 301. Each pixel body 201 is provided with a bonding metal part 3021 on the side near the driving wafer 80. The bonding metal part 3021 is electrically connected to the corresponding anode contact 801.

[0216] Each pixel body 201 is covered with an insulating passivation layer 303. The bonding metal part 3021 is located inside the insulating passivation layer 303. The upper part of the insulating passivation layer 303 has an opening 3031. The outer part of the insulating passivation layer 303 is covered with a common cathode layer 304. The pixel body 201 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to electrically connect with the cathode contact 802.

[0217] The bonding metal part 3021 can correspond one-to-one with the anode contact 801, or multiple anode contacts 801 can correspond to one bonding metal part 3021.

[0218] The pixel body 201 includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014 arranged sequentially along the Z direction. The active layer 2013 is used to emit light. Each side of the P-type semiconductor layer 2012 near the driving wafer 80 is provided with a bonding metal member 3021. A P-type ohmic contact layer 2011 is provided between the P-type semiconductor layer 2012 and the bonding metal member 3021 to achieve ohmic contact between the P-type semiconductor layer 2012 and the bonding metal member 3021. This allows the P-type semiconductor layer 2012 to be electrically connected to the corresponding anode contact 801 through the bonding metal member 3021, thereby achieving anode connection. The N-type semiconductor layer is exposed at the opening 3031, and the exposed part is electrically connected to the common cathode layer 304. The common cathode layer 304 is used to connect to the cathode contact 802 of the driving wafer 80 to achieve cathode connection. The insulating passivation layer 303 is used to insulate and isolate the N-type semiconductor layer 2014 and the P-type semiconductor layer 2012 in the pixel body to avoid short circuits.

[0219] The filling hole 402 is formed in the insulating body 301 of the second pixel layer 40.

[0220] In some embodiments, as shown in FIG26, the height D of the pixel body 201 in the Z direction is 0.3um to 5um; preferably, D is 0.3um to 1.5um; wherein, the height of the pixel body 201 is the distance between its P-type semiconductor layer 2012 and N-type semiconductor layer 2014 (including the thickness of the P-type semiconductor layer and the N-type semiconductor layer itself).

[0221] Furthermore, the tilt angle θ of the sidewall of the pixel body 201 relative to the driving wafer 80 is 45° to 135°; it can be understood that the sidewall of the pixel body 201 here refers to the wall between the top and bottom surfaces of the pixel body 201.

[0222] The aforementioned tilt angle can reduce total internal reflection and facilitate light extraction. Exceeding this range will reduce light extraction efficiency. In addition, due to the limited horizontal space, a certain amount of space needs to be reserved for subsequent processes. If the tilt angle is too small, the bottom surface of the pixel will occupy too much horizontal space, which will increase the difficulty of pixel spacing arrangement.

[0223] Preferably, the tilt angle θ of the sidewall of the pixel body 201 relative to the driving wafer 80 is 75° to 105°, which has the best light extraction efficiency and the best pixel pitch design.

[0224] In some embodiments, the thickness of the P-type ohmic contact layer 2011 is 10 nm to 300 nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), or a metal alloy film such as AuBe or AnZn.

[0225] In some embodiments, the thickness of the insulating passivation layer 303 is 30nm to 500nm to better ensure insulation and passivation capabilities.

[0226] In some embodiments, the thickness of the common cathode layer 304 is 50nm to 500nm to maximize its transmittance while ensuring current spread capability. The thicker the common cathode layer 304 is, the better the current spread, but the lower the transmittance, which will cause greater light loss and increase the processing difficulty. If the thickness is too thin, it will affect the metal current spread capability.

[0227] In some embodiments, the bonding metal part 3021 of the green-emitting sub-pixel in the second pixel layer 40 is electrically connected to the corresponding anode contact 801 by an anode connector 307 passing through the first pixel layer 30. Each of the first pixel layers 30 is provided with an anode hole 306 corresponding to the anode connector 307. The anode hole 306 is filled with anode metal material to form the anode connector 307, so as to realize the anode connection between the upper sub-pixel 20 and the driving wafer 80 through the anode connector 307.

[0228] Furthermore, the aforementioned anode hole 306 is formed on the insulating body 301 of the first pixel layer 30.

[0229] In some embodiments, the cross-sectional area of ​​the portion of the anode hole 306 that is relatively far from the driving wafer 80 is larger than the cross-sectional area of ​​the portion that is relatively close to the driving wafer 80. This cross-sectional area refers to the area of ​​the cross section (section) obtained by cutting the anode hole with a plane perpendicular to the axis of the anode hole 306. That is, the anode hole has a shape that is wider at the top and narrower at the bottom, for example, it can be conical or Y-shaped.

[0230] In some preferred embodiments, as shown in Figure 28, the anode hole 306 is tapered with a cross-sectional area that increases toward the side away from the driving wafer. The cross-sectional area refers to the area of ​​the cross section (section) obtained by cutting the anode hole with a plane perpendicular to the axis of the anode hole 306. The inclination angle φ of the inner wall of the anode hole 306 relative to the top surface of the driving wafer 80 is 90° to 120°.

[0231] The shape of the anode connector 307 is adapted to the shape of the anode hole 306, so that the anode connector also has a structure that is wider at the top and narrower at the bottom. When the bottom length is the same, this shape can produce a thicker anode connector compared to the structure that is narrower at the top and wider at the bottom, thereby enhancing the anode electrical transmission capability.

[0232] In some embodiments, an anode hole 306 is provided on the interface 60 of the first pixel layer 30 and the second pixel layer 40, as shown in Figures 27-28. The top surface of the anode connector 307 filled in the anode hole 306 is lower than the interface 60 to form a recess 3061. The bonding metal part 3021 of the green sub-pixel is embedded in the recess 3061 of the corresponding anode hole 306 of the first pixel layer 30 and makes electrical contact with the anode connector 307.

[0233] or,

[0234] As shown in Figures 25 and 26, the top surface of the anode connector 307 filling the anode hole 306 is higher than the interface 60, forming a protrusion 3071. The bonding metal part 3021 of the green sub-pixel is fitted with the protrusion 3071 of the corresponding anode connector 307 of the adjacent pixel layer below. This fitting method can avoid the formation of bonding voids between the bonding metal part 3021 and the anode connector 307. Bonding voids will lead to poor electrical transmission. The above-mentioned protrusion-concave fitting method can effectively avoid the above problems, ensure excellent electrical transmission effect, and also effectively increase the connection stability and connection strength of the bonding metal part 3021 and the anode connector 307.

[0235] Furthermore, as shown in Figure 28, the height h1 of the recessed portion 3061 is 10nm to 300nm, and as shown in Figure 26, the height h2 of the protruding portion 3071 is 10nm to 300nm, in order to better avoid bonding voids and ensure electrical transmission performance. The aforementioned heights should not be too large, as excessive heights can increase manufacturing complexity, while insufficient heights will fail to guarantee adequate electrical transmission performance.

[0236] In some embodiments, the first pixel layer 30 is further provided with a cathode hole 308, the cathode hole 308 is filled with a cathode connector 309, and the cathode connector 309 is electrically connected to the cathode contact 802. The common cathode layer 304 in the second pixel layer 40 is electrically connected to the cathode contact 802 through the cathode connector 309.

[0237] The common cathode layer 304 of the first pixel layer 30 can be directly electrically connected to the cathode contact 802.

[0238] Furthermore, a cathode hole 308 is also provided on the interface 60 between the first pixel layer 30 and the second pixel layer 40. The top surface of the cathode connector 309 filled in the cathode hole 308 is lower than the interface 60 to form a recess, or the top surface of the cathode connector 309 filled in the cathode hole 308 is higher than the interface 60 to form a protrusion. This is similar to the arrangement of the anode connector 307, and will not be described in detail here.

[0239] In some embodiments, an insulating passivation layer 303 is also covered on the interface 60 between the first pixel layer 30 and the second pixel layer 40. A common cathode layer 304 is also covered on the upper part of the insulating passivation layer 303 of the interface 60. A metal mesh layer 305 is provided on the upper part of the common cathode layer 304 so as to achieve the effect of enhancing the cathode current through the metal mesh layer 305.

[0240] Furthermore, a metal mesh layer 305 is also provided on the outer periphery of the filling hole 402; a metal mesh layer 305 is also provided on the common cathode layer 304 in the first pixel layer 30.

[0241] Furthermore, the metal mesh layer 305 can be made of one or more materials selected from Cr, Pt, Ti, Au, Al, Cu, TiN and TaN.

[0242] In one embodiment, the thickness of the metal mesh layer 305 is 100nm to 5000nm. This relatively thin thickness increases the spacing between the metal mesh layer 305 and the upper bonding metal part 3021, allowing sufficient space between the metal mesh layer 305 and the upper bonding metal part 3021 to fill the insulating body 301. This effectively avoids the risk of short circuit between the metal mesh layer and the upper bonding metal part, resulting in better insulation and higher safety.

[0243] In one embodiment, as shown in FIG27, the light emitted from the blue sub-pixel 20 in the first pixel layer 30 is emitted through the first notch 3051 in the first pixel layer 30. The first notch 3051 is formed on the metal mesh layer 305. The length L1 of the first notch 3051 in the X direction is greater than the top surface length L2 of the corresponding blue sub-pixel in the lower layer, so that the light emitted from the lower sub-pixel can be emitted through the first notch 3051 to the maximum extent, thereby improving the light extraction efficiency of the pixel.

[0244] Understandably, "corresponding blue sub-pixel" here refers to the blue sub-pixel 20 through which the emitted light passes the first notch 3051.

[0245] The above method creates a first notch 3051 on the metal mesh layer 305 at the interface, that is, removes the metal mesh material in the first notch 3051, so as to reduce the obstruction of the light emitted from the bottom sub-pixel by the metal mesh in the original notch, so that the light emitted from the sub-pixel in the bottom pixel layer does not have to pass through the metal mesh layer, reducing light loss and making the bottom sub-pixel have higher light extraction efficiency.

[0246] Furthermore, the light emitted by the blue-emitting sub-pixel 20 in the first pixel layer 30 passes through the second notch and the first notch 3051 in the second pixel layer 40 in sequence before being emitted. The second notch is formed on the common cathode layer 304, and the length of the second notch in the X direction is greater than the top surface length of the corresponding blue-emitting sub-pixel 20 in the lower layer.

[0247] Understandably, "the corresponding blue-colored sub-pixel" here refers to the blue sub-pixel through which the emitted light passes sequentially between the second notch and the first notch 3051.

[0248] The above method creates a second notch on the common cathode layer 304 at the interface 60 between two adjacent pixel layers, which removes the common cathode material in the second notch. This allows the light emitted from the sub-pixels in the lower pixel layer to be emitted without passing through the common cathode, further reducing light loss and giving the bottom sub-pixels higher light extraction efficiency.

[0249] In each pixel layer, the common cathode layer 304 is a whole, and the second notch is equivalent to a hole opened in the common cathode layer 304.

[0250] The anode connector 307 in the first pixel layer 30 can be configured in the following two ways:

[0251] In one embodiment, as shown in Figure 28, an anode connector 307 is provided in a separate space between two adjacent excitation pixels 70 in the X direction in the first pixel layer 30, wherein the X direction and the Z direction are perpendicular.

[0252] In another approach, as shown in Figure 26, the original pixel between two adjacent excitation pixels 70 in the X direction of the first pixel layer 30 is retained as an auxiliary pixel 120. This allows the anode connector 307 in the first pixel layer 30 to pass through an auxiliary pixel 120 and then be electrically connected to the corresponding anode contact 801 on the driving wafer 80. This approach avoids the need to redo the fabrication of the first pixel layer 30 and allows the use of the existing single-layer monochrome product. In other words, the second pixel layer 40 can be directly superimposed on the existing single-layer product. This method is faster and reduces the cost of fabricating the bottom pixel layer separately.

[0253] Understandably, the anode connector 307 needs to pass through the common cathode layer 304 and the insulating passivation layer 303 outside the auxiliary pixel 120 in sequence before connecting to the anode contact of the driving wafer 80. To avoid contact between the anode connector 307 and the common cathode layer 304 outside the auxiliary pixel 120, as shown in Figure 26, an auxiliary hole 3042 is provided on the common cathode layer 304 for the anode connector 307 to pass through. The length L4 of the auxiliary hole 3042 in the X direction is greater than the length L5 of the opening 3031 of the insulating passivation layer 303 at the top of the auxiliary pixel.

[0254] In some embodiments, similar to the above, the cathode connector 309 may also penetrate through another auxiliary pixel 120 in the first pixel layer 30 and be electrically connected to the cathode contact 802 on the driving wafer 80.

[0255] As shown in Figure 25, the first pixel layer 30 has two excitation pixels 70, two auxiliary pixels 120 (one with an anode connector 307 and the other with a cathode connector 309), and a blue sub-pixel. The second pixel layer 40 has two red light color converters 401, and a green sub-pixel is set between the two red light color converters 401.

[0256] It should be noted that after the auxiliary pixel 120 is penetrated by the anode connector 307 (or cathode connector 309), the auxiliary pixel 120 cannot emit light normally and is only used as a connector.

[0257] In some embodiments, as shown in FIG25, at least one lens 130 is connected to the upper part of the second pixel layer 40. The lens 130 can be arranged in two ways: one is that the lens 130 corresponds one-to-one with the mother pixel 10, and the other is that each lens 130 corresponds one-to-one with the sub-pixel 20. This method is to better collimate the emitted light of each sub-pixel 20 and further reduce light interference in the mother pixel.

[0258] In some configurations, as shown in Figure 27, the red light transducer 401 and the excitation pixel 70 are in a one-to-one correspondence. Alternatively, one red light transducer 401 can correspond to multiple excitation pixels 70, simply by placing the red light transducer 401 on the light emission path of the corresponding excitation pixel 70. When arranging the red light transducers, the entire red light transducer can be positioned above the corresponding excitation pixel, or the red light transducer can partially cover the corresponding excitation pixel.

[0259] This embodiment also discloses a method for fabricating the above-mentioned multicolor microdisplay chip, including the following steps:

[0260] Step M1: Prepare driver wafer 80;

[0261] Step M2: A first pixel layer 30 and a second pixel layer 40 are stacked sequentially along the Z direction on the driving wafer 80, such that the first pixel layer 30 is provided with an excitation pixel 70, and the second pixel layer 40 is provided with a green-emitting sub-pixel 20 and a red light color transfer element 401. The red light color transfer element 401 corresponds to the excitation pixel 70. Each red light color transfer element 401 is located on the light emission path of the corresponding excitation pixel 70 to excite and form a red-emitting sub-pixel. The sub-pixels 20 are electrically connected to the driving wafer 80 so that the driving wafer 80 drives the sub-pixels 20 to emit light.

[0262] In one embodiment, after step M2, referring to stage f in FIG29, a dielectric layer is deposited on the upper part of the second pixel layer 40, and the dielectric layer is patterned and etched to form a lens 130, so that the lens 130 corresponds one-to-one with the mother pixel 10, that is, one mother pixel 10 corresponds to one lens 130; or, each lens 130 corresponds one-to-one with the sub-pixel 20, that is, each sub-pixel 20 corresponds to a lens 130, so as to better collimate the emitted light of each sub-pixel 20 and further reduce light interference in the mother pixel;

[0263] In some implementations, step M2 includes:

[0264] Step M21: Bond a compound semiconductor 90 onto the driving wafer 80; for example, the compound semiconductor 90 can be bonded onto the driving wafer 80 through a bonding layer 302.

[0265] The aforementioned compound semiconductor 90 includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, an N-type semiconductor layer 2014, and a substrate 901 arranged sequentially away from the driving wafer direction. After the compound semiconductor 90 is bonded to the driving wafer 80, the substrate 901 needs to be removed to expose the N-type semiconductor layer 2014. As shown in stage c of Figure 23, after removing the substrate 901, an N-type ohmic contact layer 2015 can also be disposed on the N-type semiconductor layer 2014.

[0266] Furthermore, the N-type ohmic contact layer 2015 has a thickness of 10nm to 300nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), or a metal alloy film such as gold-germanium alloy (AuGe) or gold-nickel alloy (AuNi).

[0267] Preferably, the thickness of the N-type ohmic contact layer 2015 is 10nm to 100nm, so as to ensure ohmic contact while also giving it high transmittance, thereby reducing light loss.

[0268] Step M22: Pattern the compound semiconductor 90 to obtain at least one set of pixels. This set of pixels includes an excitation pixel 70 and a blue-emitting sub-pixel 20. Both the excitation pixel 70 and the blue-emitting sub-pixel 20 include a pixel body 201. Each pixel body 201 is electrically connected to a corresponding bonding metal part 3021 and a corresponding anode contact 801. Each pixel body 201 corresponds to one bonding metal part 3021. The bonding metal part 3021 can be obtained by etching the bonding layer 302.

[0269] Step M23: Deposit an insulating passivation layer 303 on the outside of the pixel body 201, and provide an opening 3031 on the upper part of the insulating passivation layer 303 to expose the N-type semiconductor layer 2014 or N-type ohmic contact layer 2015 of the pixel body 201.

[0270] Step M24: Deposit a common cathode layer 304 on the outside of the insulating passivation layer 303, so that the pixel body 201 is electrically connected to the common cathode layer 304 through the opening 3031, and the common cathode layer 304 is used to electrically connect to the cathode contact 802.

[0271] That is, the N-type semiconductor layer 2014 of the pixel body 201 is electrically connected through the common cathode layer 304 and the cathode contact 802 to achieve cathode connection;

[0272] The driver wafer 80 may have only one cathode contact 802, or the number of cathode contacts 802 may be determined as needed.

[0273] Step M25: Fill the outside of the common cathode layer 304 with an insulating body 301, so that the pixel bodies 201 are all located inside the insulating body 301, thereby obtaining the first pixel layer 30 as shown in stage c of Figure 29.

[0274] Understandably, the insulating passivation layer 303 and the common cathode layer 304 outside the pixel body 201 are also located inside the insulating body 301.

[0275] Step M26: Bond another compound semiconductor 90 to the top of the first pixel layer 30, and perform patterned etching on the compound semiconductor 90 to obtain a sub-pixel 20 with a green light emission color. The sub-pixel 20 with a green light emission color also includes a pixel body 201. The pixel body 201 is electrically connected to the corresponding bonding metal part 3021 and the corresponding anode contact 801. Then repeat steps M23-M24.

[0276] Step M27: Fill the outside of the common cathode layer 304 with an insulating body 301, so that the pixel bodies 201 are all located inside the insulating body 301, and set a filling hole 402 on the insulating body 301. Fill the filling hole 402 with color transfer material to form a red light color transfer element 401, thereby completing the preparation of the second pixel layer 40. See stages c-e in Figure 29.

[0277] Understandably, the position of the filling hole 402 should be located on the light emission path of the excitation pixel 70 so that the light emitted by the excitation pixel 70 can pass through the red light color transfer element 401 in the hole, thereby exciting the red light color transfer element 401 to emit color and generate red light.

[0278] Understandably, since the sub-pixels in the two pixel layers emit different colors of light, the compound semiconductor materials used in the fabrication of the two pixel layers are also different, so that the compound semiconductors used emit different colors of light.

[0279] For example, both the P-type semiconductor layer 2012 and the N-type semiconductor layer 2014 in the compound semiconductor 90 can be made of gallium nitride (GaN) material, and the substrate 901 can be made of gallium nitride (GaN), silicon (Si) or sapphire material.

[0280] In some embodiments, when the first pixel layer 30 is prepared, an anode hole 306 is also formed on the insulating body 301 of the first pixel layer 30, and an anode metal material is filled in the anode hole 306 to form an anode connector 307, so as to realize the anode connection between the upper green sub-pixel 20 and the driving wafer 80 through the anode connector 307.

[0281] In some embodiments, during the fabrication of the first pixel layer 30, a through anode hole 306 is also fabricated in the auxiliary pixel 120, and an anode metal material is filled in the anode hole 306 to form an anode connector 307, so that the anode connector 307 passes through the corresponding auxiliary pixel 120 and is electrically connected to the corresponding anode contact 801 on the driving wafer 80.

[0282] In one embodiment, the insulating passivation layer 303 may be made of one or more of aluminum oxide, silicon dioxide, and silicon nitride.

[0283] In one embodiment, the insulating body 301 may be made of one or more of silicon oxide, silicon nitride, silicon carbide (SiC), silicon carbon nitride (SiCN), phosphate glass (PSG), and borosilicate glass (BPSG).

[0284] In one embodiment, the common cathode layer 304 includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), Al-doped zinc oxide (AZO), Al-doped indium tin oxide, Ag-doped indium tin oxide, and Au-doped indium tin oxide.

[0285] In one embodiment, the metal mesh layer 305 may be made of one or more of the following materials: Cr, Pt, Ti, Au, Al, Cu, TiN, and TaN.

[0286] In one embodiment, the anode connector 307 may be made of one or more of aluminum, copper, and tungsten.

[0287] Furthermore, the cathode connector 309 can be made of the same material as the anode connector 307, which is a conductive material.

[0288] In one embodiment, the material of the bonding metal part 3021 can be one of Al, Au, Cu, or a stacked structure of Ni, Au, Cu and Sn, or a bonding stack of Au with In or Ge, or a bonding stack of Au with Si.

[0289] Furthermore, the aforementioned bonding metal part 3021 can adopt the following structural form: Cr2nm / Pt50nm / Ti10nm / Pt50nm / Au100nm / Sn150nm / Au50nm, wherein Cr is the adhesive layer and Pt / Ti / Pt is the barrier layer.

[0290] This embodiment can be used to prepare a chip structure with two pixel layers. Finally, three different colors of light (red, green, and blue) can be emitted through the second pixel layer 40 to achieve a three-color configuration.

[0291] Example 4

[0292] This embodiment discloses a multicolor microdisplay chip based on color conversion. The main difference between this embodiment and Embodiment 3 is that only excitation pixels 70 are set in the first pixel layer 30, so the entire chip emits only two colors of light.

[0293] Furthermore, the excitation pixel 70 in the first pixel layer 30 emits blue light. When the blue light emitted by the laser pixel passes through the corresponding red light color converter 401 above, it will excite the red light color converter 401 to emit red light. Therefore, the light emitted by the structure through the second pixel layer 40 is only red light and green light emitted by the green sub-pixel. At this time, the chip product is a dual-color product.

[0294] The fabrication method of the microdisplay chip in this embodiment is basically the same as that in Embodiment 3, and will not be repeated here.

[0295] The microdisplay chips and their fabrication methods described in the above embodiments effectively increase the number of red sub-pixels, thereby effectively controlling the attenuation of red light in the mother pixel, so that the brightness ratio of various colors can be maintained at a specific ratio, thus ensuring an ideal color display effect.

[0296] All the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention. That is, any number of embodiments can be combined to meet the needs of different application scenarios. All of these are within the protection scope of this application and will not be described in detail here.

[0297] It should be noted that the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A multi-color microdisplay chip, characterized by: The application relates to a display device, comprising, a mother pixel comprising at least four sub-pixels, at least two of which have different light-emitting colors, and at least one of which has a red light-emitting color, and the number of sub-pixels with a red light-emitting color is not less than 50% of the total number of sub-pixels in the mother pixel; a driving wafer, each of the sub-pixels being electrically connected to the driving wafer; at least two pixel layers, all of which are stacked in the Z direction on the driving wafer, and all of the sub-pixels of the mother pixel are arranged in the corresponding pixel layers.

2. The multi-color micro-display chip of claim 1, wherein: At least one sub-pixel is arranged in each of the pixel layers, and the light-emitting colors of each of the sub-pixels in the same pixel layer are the same, and the light-emitting colors of the sub-pixels in adjacent two pixel layers are different.

3. The multi-color micro-display chip of claim 2, wherein: The sub-pixel with a red light-emitting color has a red light-emitting color.

4. The multi-color micro-display chip of claim 2, wherein: The projections of all the sub-pixels in the mother pixel on the driving wafer do not coincide.

5. The multi-color micro-display chip of claim 1, wherein: An anode contact and a cathode contact are arranged on the driving wafer, each of the sub-pixels comprises a pixel body, each of the pixel layers comprises an insulating body, the pixel bodies in the pixel layers are all wrapped inside the insulating bodies, each of the pixel bodies is arranged with a bonding metal piece on the side close to the driving wafer, the bonding metal piece is electrically connected to the corresponding anode contact, the outside of each of the pixel bodies is wrapped with an insulating passivation layer, the bonding metal piece is located inside the insulating passivation layer, the upper part of the insulating passivation layer has an opening, the outside of the insulating passivation layer is wrapped with a common cathode layer, the pixel body is electrically connected through the opening and the common cathode layer, and the common cathode layer is used for being electrically connected to the cathode contact.

6. The multi-color micro-display chip of claim 5, wherein: Each of the pixel bodies comprises a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged in sequence in the Z direction, the P-type semiconductor layer is arranged with the bonding metal piece on the side close to the driving wafer, and the N-type semiconductor layer is electrically connected through the opening and the common cathode layer.

7. The multi-color micro-display chip of claim 5, wherein: The bonding metal piece of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact through an anode connecting piece penetrating through the lower pixel layer.

8. The multi-color micro-display chip of claim 7, wherein: An anode hole corresponding to the anode connecting piece is arranged on the interface between adjacent two pixel layers, the anode hole is filled with an anode connecting piece, the top surface of the anode connecting piece filled in the anode hole is lower than the interface to form a recessed part, and the bonding metal piece of the sub-pixel in the pixel layer is embedded in the recessed part of the corresponding anode hole in the lower adjacent pixel layer to be in electrical contact with the anode connecting piece. Alternatively, the top surface of the anode connecting piece filled in the anode hole is higher than the interface to form a protruding part, and the bonding metal piece of the sub-pixel in the pixel layer is embedded with the protruding part of the corresponding anode connecting piece in the lower adjacent pixel layer.

9. The multi-color micro-display chip of claim 8, wherein: The pixel layers include at least three layers, and the bonding metal piece of the sub-pixel in the third layer and the pixel layers above is electrically connected to the corresponding anode contact by a plurality of anode connecting pieces connected in sequence along the Z direction, each anode connecting piece connected in sequence along the Z direction is located in a different pixel layer, and the adjacent two anode connecting pieces connected in sequence along the Z direction are directly in contact or are provided with a conductive metal piece.

10. The multi-color micro-display chip of claim 7, wherein: The anode connecting piece located in the bottom pixel layer penetrates through an auxiliary pixel and is electrically connected to the corresponding anode contact on the driving wafer.

11. The multi-color micro-display chip of claim 5, wherein: A cathode hole is formed on the interface between the adjacent two pixel layers, the cathode hole is filled with a cathode connecting piece, and the cathode connecting piece is electrically connected to a cathode contact.

12. The multi-color micro-display chip of claim 5, wherein: The interface between the adjacent two pixel layers is also covered with the insulating passivation layer, the upper part of the insulating passivation layer of the interface is also covered with the common cathode layer, and the upper part of the common cathode layer is provided with a metal mesh gate layer.

13. The multi-color micro-display chip of claim 12, wherein: The light emitted by the sub-pixel in the lower pixel layer is emitted through a first gap in the upper pixel layer, the first gap is formed on the metal mesh gate layer, and the length of the first gap in the X direction is greater than the length of the top surface of the corresponding sub-pixel in the lower layer, wherein the X direction is perpendicular to the Z direction.

14. The multi-color micro-display chip of claim 13, wherein: The light emitted by the sub-pixel in the lower pixel layer is emitted through a second gap and a first gap in the upper pixel layer in sequence, the second gap is formed on the common cathode layer, and the length of the second gap in the X direction is greater than the length of the top surface of the corresponding sub-pixel in the lower layer.

15. The multi-color micro-display chip of claim 5, wherein: The pixel body is trapezoidal or cylindrical.

16. The multi-color micro-display chip of claim 1, wherein: At least one lens is connected to the upper part of the pixel layer located at the top layer, the lens and the parent pixel correspond one-to-one, or each lens and the sub-pixel correspond one-to-one.

17. The multi-color micro-display chip of claim 1, wherein: Each sub-pixel with red light emission color includes an excitation pixel and a red light color conversion piece, the red light color conversion piece is located on the light emission path of the excitation pixel to form a sub-pixel with red light emission color; the multi-color micro display chip includes two pixel layers, the upper pixel layer is provided with a sub-pixel with green light emission color and a red light color conversion piece, and the lower pixel layer is provided with an excitation pixel corresponding to the red light color conversion piece.

18. The multi-color micro-display chip of claim 17, wherein: The excitation pixel, the sub-pixel with blue light emission color, and the sub-pixel with green light emission color each include a pixel body, and each pixel body is provided with a bonding metal piece close to one side of the driving wafer.

19. The multi-color micro-display chip of claim 18, wherein: The driving wafer is provided with an anode contact and a cathode contact, each of the pixel layers comprises an insulating body, each of the pixel bodies in the pixel layer is wrapped inside the insulating body, each of the pixel bodies is provided with a bonding metal piece near one side of the driving wafer, the bonding metal piece is electrically connected with the corresponding anode contact, the outside of each of the pixel bodies is wrapped with an insulating passivation layer, the bonding metal piece is located inside the insulating passivation layer, the upper part of the insulating passivation layer has an opening, the outside of the insulating passivation layer is wrapped with a common cathode layer, the pixel body is electrically connected through the opening and the common cathode layer, and the common cathode layer is used for being electrically connected with the cathode contact.

20. The multi-color micro-display chip of claim 17, wherein: The pixel layer where the red light color conversion piece is located is provided with a filling hole, and each of the filling holes is filled with the red light color conversion piece.

21. The multi-color micro-display chip of claim 20, wherein: The length of the filling hole in the X direction is not less than the maximum length of the excitation pixel in the X direction, and the X direction is perpendicular to the Z direction.

22. The multi-color micro-display chip of claim 20, wherein: An isolation layer is formed on the inner wall of the filling hole, and the isolation layer is a metal reflection layer or a light absorption layer.

23. The multi-color micro-display chip of claim 22, wherein: The thickness of the isolation layer is 50 nm to 2 um.

24. The multi-color micro-display chip of claim 17, wherein: The pixel layer where the excitation pixel is located is also provided with a sub-pixel with blue light emission color, and the excitation pixel also has blue light emission color.

25. The method of claim 1-24, wherein: Comprising, Step M1, preparing a driving wafer; step M2, sequentially stacking at least two pixel layers on the driving wafer in the Z direction, so that all sub-pixels in the parent pixel are arranged in the corresponding pixel layer and the sub-pixels are electrically connected with the driving wafer, so as to drive the sub-pixels to emit light by using the driving wafer.

26. The method of claim 25, wherein: When the at least two pixel layers are sequentially stacked on the driving wafer in the Z direction, at least one of the sub-pixels is arranged in each of the pixel layers, the light emission colors of each of the sub-pixels in the same pixel layer are the same, and the light emission colors of the sub-pixels in adjacent two pixel layers are different.

27. The method of claim 25, wherein: The driving wafer is provided with an anode contact and a cathode contact; the sub-pixels each comprise a pixel body, when the pixel layer is prepared, the pixel bodies in the pixel layer are wrapped inside an insulating body, a bonding metal piece is arranged on one side of each of the pixel bodies close to the driving wafer, the bonding metal piece is electrically connected with the corresponding anode contact, the outside of each of the pixel bodies is wrapped with an insulating passivation layer, the bonding metal piece is located inside the insulating passivation layer, the upper part of the insulating passivation layer has an opening, the outside of the insulating passivation layer is wrapped with a common cathode layer, the pixel body is electrically connected through the opening and the common cathode layer, and the common cathode layer is used for being electrically connected with the cathode contact.

28. The method of claim 27, wherein: In addition to the top layer, when other pixel layers are prepared, an anode hole is formed on the insulating body, and an anode connecting piece is filled in the anode hole, so that the bonding metal piece of the sub-pixel in the pixel layer is electrically connected to the corresponding anode contact through the anode connecting piece of the lower pixel layer.

29. The method of claim 28, wherein: The bottom pixel layer is also prepared with auxiliary pixels when prepared, so that the anode connecting pieces in the bottom pixel layer correspond to the auxiliary pixels, and the anode connecting pieces in the bottom pixel layer are electrically connected to the corresponding anode contact points on the driving wafer after penetrating through the corresponding auxiliary pixels.

30. The method of claim 25, wherein: In step M2, two pixel layers are sequentially stacked in the Z direction on the driving wafer, so that the upper pixel layer is provided with sub-pixels with green light color and red light color conversion pieces, the lower pixel layer is provided with excitation pixels corresponding to the red light color conversion pieces, each red light color conversion piece is located on the light emitting path of the corresponding excitation pixel to excite the formation of a sub-pixel with red light color, and the sub-pixels are all electrically connected to the driving wafer to drive the sub-pixels to emit light by using the driving wafer.

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