Multilayer micro-display chip and method for manufacturing same

Abstract

The present invention relates to a multilayer micro-display chip and a method for manufacturing same. The chip comprises a driving wafer and at least two pixel layers, wherein anode contacts are provided on the driving wafer. All pixel layers are sequentially stacked on the driving wafer in a Z direction, wherein at least one pixel layer is internally provided with sub-pixels, and each sub-pixel comprises a pixel main body; a bonding metal member is provided on the side of each pixel main body close to the driving wafer, a bonding metal member of a sub-pixel in an upper pixel layer is electrically connected to a corresponding anode contact by means of an anode connector passing through a lower pixel layer, the bonding metal member of the sub-pixel in the upper pixel layer has a first contact surface, the first contact surface is a non-flat surface, and the first contact surface is embedded in the pixel layer where the anode connector is located and in contact with the anode connector, or the anode connector is embedded in the first contact surface. Also disclosed in the present invention is a method for manufacturing the described chip. In the present invention, the bonding metal member is in full contact with the anode connector, thereby effectively ensuring the reliability of anode current transmission.

Description

Multi-layer micro display chip and preparation method thereof

[0001] Priority information: This application claims priority to Chinese patent application No. 2024110133910 filed on July 26, 2024, Chinese patent application No. 2024217972974 filed on July 26, 2024, Chinese patent application No. 2024217935316 filed on July 26, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, in particular to a multi-layer micro display chip and a preparation method thereof. BACKGROUND

[0003] In the field of LED display, micro display technology has been widely developed in recent years, especially Micro-LED display technology, which has the advantages of high efficiency, low power consumption, high integration and high stability, and is considered to be one of the most promising next-generation new display and light-emitting devices. Micro-LED display technology has been widely applied to near-eye display terminal products, including virtual reality (VR), augmented reality (AR), and mixed reality (MR). The display area of the existing micro display chip is usually arranged with a plurality of pixel units arranged in an array. In order to further reduce the horizontal size of the micro display chip and improve the pixel density, the chip can be set as a multi-layer structure vertically stacked, each layer being provided with a light-emitting pixel unit. In this multi-layer structure, the adjacent two layers are generally bonded by a bonding layer, and the pixel unit of the upper layer is connected to the anode connecting piece of the lower layer through the bonding layer, so as to realize the connection of the pixel unit and the anode of the driving wafer. However, in the existing structure, the bonding layer and the anode connecting piece in the adjacent two layers are prone to gaps, which affects the electrical transmission and cannot meet the use requirements. SUMMARY

[0004] To this end, the technical problem to be solved by the present application is to overcome the defect that the bonding layer and the anode connecting piece are prone to poor contact and affect electrical transmission in the prior art.

[0005] To solve the above technical problems, the present application provides a multi-layer micro display chip, comprising,

[0006] a driving wafer, the driving wafer being provided with an anode contact;

[0007] At least two pixel layers are provided, all of which are stacked sequentially along the Z direction on the driving wafer. At least one pixel layer has a sub-pixel, which includes a pixel body. Each pixel body has a bonding metal member on the side closest to the driving wafer. The bonding metal member of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact by an anode connector passing through the lower pixel layer. The bonding metal member of the sub-pixel in the upper pixel layer has a first contact surface for contacting the anode connector. The first contact surface is a non-planar surface. The first contact surface is embedded in the pixel layer where the anode connector is located and contacts the anode connector, or the anode connector is embedded in the first contact surface.

[0008] In one embodiment of the present invention, an anode hole corresponding to the anode connector is formed at the interface between two adjacent pixel layers. The anode hole is filled with an anode connector, and the top surface of the anode connector filled in the anode hole is lower than the interface to form a recess. An embedding protrusion is formed on the first contact surface. The embedding protrusion of the sub-pixel in the pixel layer is embedded in the recess of the corresponding anode hole in the adjacent pixel layer below and makes electrical contact with the anode connector; or...

[0009] The top surface of the anode connector filled in the anode hole is higher than the interface to form a protrusion. An embedding recess is formed on the first contact surface. The embedding recess of the sub-pixel in the pixel layer is engaged with the protrusion of the corresponding anode connector in the adjacent pixel layer below.

[0010] In one embodiment of the present invention, the height of the recessed portion is 10nm to 300nm, and the height of the protruding portion is 10nm to 300nm.

[0011] In one embodiment of the present invention, the multilayer microdisplay chip includes at least three pixel layers. The bonding metal members of the sub-pixels in the third and above pixel layers are electrically connected to the corresponding anode contacts by a plurality of anode connectors connected sequentially along the Z direction. Each anode connector connected sequentially along the Z direction is located in a different pixel layer. Adjacent anode connectors connected sequentially along the Z direction are in direct contact; or, a conductive metal member is provided between adjacent anode connectors.

[0012] In one embodiment of the invention, the cross-sectional area of ​​the portion of the anode hole that is relatively far from the driving wafer is larger than the cross-sectional area of ​​the portion that is relatively close to the driving wafer.

[0013] In one embodiment of the present invention, the anode hole is a cone shape with a cross-sectional area increasing toward the side away from the driving wafer, and the inclination angle of the inner wall of the anode hole relative to the top surface of the driving wafer is 90° to 120°.

[0014] In one embodiment of the present invention, the driving wafer is further provided with a cathode contact, each pixel layer includes an insulating body, the pixel body in the pixel layer is covered inside the insulating body, the outside of each pixel body is covered with an insulating passivation layer, the bonding metal is located inside the insulating passivation layer, the upper part of the insulating passivation layer has an opening, the outside of the insulating passivation layer is covered with a common cathode layer, the pixel body is electrically connected to the common cathode layer through the opening, and the common cathode layer is used to electrically connect to the cathode contact.

[0015] In one embodiment of the present invention, each pixel body includes a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged sequentially along the Z direction. The bonding metal element is disposed on the side of the P-type semiconductor layer near the driving wafer. The N-type semiconductor layer is electrically connected to the common cathode layer through the opening.

[0016] In one embodiment of the present invention, a cathode hole is provided at the interface between two adjacent pixel layers, and a cathode connector is filled in the cathode hole. The cathode connector is electrically connected to a cathode contact. The common cathode layers in the upper pixel layer are electrically connected to the cathode connector and cathode contact in the lower pixel layer.

[0017] In one embodiment of the present invention, the distance between the top surface of the insulating body of each pixel layer and the common cathode layer on top of the sub-pixel of that layer is not less than 100 nm.

[0018] In one embodiment of the present invention, the thickness of the common cathode layer is 50 nm to 500 nm.

[0019] In one embodiment of the present invention, the pixel body is trapezoidal or cylindrical.

[0020] In one embodiment of the present invention, the light emitted by sub-pixels in each pixel layer is the same.

[0021] In one embodiment of the present invention, the light emitted by each sub-pixel in the same pixel layer is the same, and the light emitted by sub-pixels in two adjacent pixel layers is different.

[0022] In one embodiment of the invention, the projections of all sub-pixels on the driving wafer do not overlap.

[0023] In one embodiment of the present invention, at least one lens is connected to the upper part of the top pixel layer, and each sub-pixel corresponds to one lens, or multiple sub-pixels correspond to one lens.

[0024] In one embodiment of the present invention, the multilayer microdisplay chip includes two pixel layers. The upper pixel layer is provided with a color transfer element and a sub-pixel with a light emission color different from that of the color transfer element. The lower pixel layer is provided with an excitation pixel corresponding to the color transfer element. The color transfer element is located on the light emission path of the corresponding excitation pixel. Both the excitation pixel and the sub-pixel include a pixel body. Each pixel body is provided with a bonding metal element on the side close to the driving wafer.

[0025] In one embodiment of the present invention, the light emitted by the color transfer element is red, and the light emitted by the excitation pixel is blue.

[0026] In one embodiment of the present invention, sub-pixels are also provided in the pixel layer where the excitation pixel is located. The light emission color of the sub-pixels in the pixel layer where the excitation pixel is located is blue, and the light emission color of the sub-pixels in the pixel layer where the color converter is located is green.

[0027] In one embodiment of the present invention, a filling hole is provided in the pixel layer where the color transfer component is located, and each filling hole is filled with the color transfer component.

[0028] In one embodiment of the present invention, the length of the filling hole along the X direction is not less than the maximum length of the excitation pixel in the X direction, and the X direction is perpendicular to the Z direction.

[0029] In one embodiment of the present invention, an insulating layer is formed on the inner wall of the filling hole, the insulating layer being a metal reflective layer or a light-absorbing layer.

[0030] In one embodiment of the present invention, at least one lens is connected to the upper part of the top pixel layer, and each of the sub-pixels and color transfer components corresponds to a different lens, or all of the sub-pixels and color transfer components correspond to the same lens.

[0031] This invention also discloses a method for fabricating a multilayer microdisplay chip, comprising,

[0032] Step M1: Prepare a driving wafer, wherein an anode contact is provided on the driving wafer;

[0033] Step M2: At least two pixel layers are stacked sequentially along the Z direction on the driving wafer. At least one pixel layer has a sub-pixel. The sub-pixel includes a pixel body. Each pixel body has a bonding metal member on the side closest to the driving wafer. The bonding metal member of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact by an anode connector passing through the lower pixel layer. The bonding metal member of the sub-pixel in the upper pixel layer has a first contact surface for contacting the anode connector. The first contact surface is a non-planar surface. The first contact surface is embedded in the pixel layer where the anode connector is located and contacts the anode connector, or the anode connector is embedded in the first contact surface.

[0034] In one embodiment of the present invention, during the fabrication of the pixel layer, an anode hole corresponding to the anode connector is formed at the interface between two adjacent pixel layers, and the anode connector is filled into the anode hole. The top surface of the anode connector filled in the anode hole is lower than the interface to form a recess. An embedding protrusion is formed on the first contact surface, such that the embedding protrusion of the sub-pixel in the pixel layer is embedded into the recess of the corresponding anode hole in the adjacent pixel layer below and makes electrical contact with the anode connector; or...

[0035] The top surface of the anode connector filled in the anode hole is higher than the interface to form a protrusion. An embedding recess is formed on the first contact surface. The embedding recess of the sub-pixel in the pixel layer is engaged with the protrusion of the corresponding anode connector in the adjacent pixel layer below.

[0036] The technical solution of the present invention has the following advantages compared with the prior art:

[0037] The multilayer microdisplay chip and its fabrication method described in this invention, through mutual interlocking, ensures full contact between the bonding metal parts and the anode connector, thereby effectively guaranteeing the reliability of anode current transmission and the connection strength between the bonding metal parts and the anode connector. Attached Figure Description

[0038] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0039] Figure 1 is a comparative diagram of trapezoidal pixels and hemispherical pixels;

[0040] Figure 2 is an internal structure diagram of the first type of multilayer microdisplay chip of the present invention;

[0041] Figure 3 is an enlarged internal view of U1 in Figure 2;

[0042] Figure 4 is a schematic diagram of the arrangement of the bottom pixel layer in Figure 2;

[0043] Figure 5 is an internal structure diagram of the second type of multilayer microdisplay chip of the present invention;

[0044] Figure 6 is an internal structure diagram of the third type of multilayer microdisplay chip of the present invention;

[0045] Figure 7 is an enlarged internal view of V1 in Figure 6;

[0046] Figure 8 is a schematic diagram of the arrangement of the bottom pixel layer in Figure 6;

[0047] Figures 9a to 9c are internal structure diagrams of the fourth type of multilayer microdisplay chip of the present invention;

[0048] Figure 10 is a partial flowchart of the chip fabrication process of the present invention;

[0049] Figure 11 is a flowchart of the preparation process of the structure shown in Figure 2;

[0050] Figure 12 is an internal structure diagram of the first multi-layer multi-color microdisplay chip based on color conversion according to this utility model;

[0051] Figure 13 is an enlarged internal view of U2 in Figure 12;

[0052] Figure 14 is a schematic diagram of the structure of the first pixel layer in Figure 12;

[0053] Figure 15 is an internal structure diagram of the second type of multilayer multicolor microdisplay chip based on color conversion according to this utility model;

[0054] Figure 16 is an enlarged internal view of V2 in Figure 15;

[0055] Figure 17 is a schematic diagram of the structure of the first pixel layer in Figure 15;

[0056] Figure 18 is an internal structure diagram of the third type of multilayer multicolor microdisplay chip based on color conversion according to this utility model;

[0057] Figure 19 is a flowchart of the preparation process of the structure shown in Figure 18;

[0058] Explanation of reference numerals in the accompanying drawings: 10, driving wafer; 101, anode contact; 102, cathode contact; 20, sub-pixel; 201, pixel body; 2011, P-type ohmic contact layer; 2012, P-type semiconductor layer; 2013, active layer; 2014, N-type semiconductor layer; 2015, N-type ohmic contact layer; 30, first pixel layer; 301, insulating body; 302, bonding layer; 3021, bonding metal component; 30211, first contact surface; 30212, embedded protrusion; 30213, embedded recess; 3022, conductive metal component; 303, insulating passivation layer; 3031, opening; 304, common cathode layer; 305, anode hole; 3051, recess; 306, anode connector; 3061, protrusion; 307, cathode hole; 308, cathode connector; 40. Second pixel layer; 401. Filling hole; 402. Isolation layer; 50. Third pixel layer; 60. Interface; 70. Excitation pixel; 80. Color transfer element; 90. Compound semiconductor; 901. Substrate; 100. Lens. Detailed Implementation

[0059] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present disclosure or its application or use.

[0060] In the description of this invention, it should be understood that the terms "vertical," "upper," "lower," "top," "side," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0061] The structure of the multilayer microdisplay chip in this embodiment will be further described below with reference to Figures 1-19.

[0062] It should be noted that, for ease of description, the microdisplay chip in this invention has mutually perpendicular Z and X directions, where the Z direction is generally the direction away from the driving wafer. In this invention, "up" and "down" are relative terms in the Z direction, and similarly, "top" and "bottom" or "high" and "low" are also relative terms in the Z direction. The top pixel layer refers to the uppermost pixel layer, and the bottom pixel layer refers to the lowermost pixel layer. The bottom pixel layer is also called the first pixel layer, and the pixel layers stacked on top of it are called the second layer, the third layer, and so on.

[0063] Example 1

[0064] Referring to Figures 2-11, this embodiment discloses a multilayer microdisplay chip, including a driving wafer 10 and at least two pixel layers; for example, only two pixel layers can be provided, from bottom to top (Z direction) as a first pixel layer 30 and a second pixel layer 40; or three pixel layers can be provided, from bottom to top as a first pixel layer 30, a second pixel layer 40 and a third pixel layer 50, or three or more layers can be provided.

[0065] The driving wafer 10 can be a CMOS driving wafer, used to control the light emission of sub-pixels 20 in the pixel layer;

[0066] Among them, the driving wafer 10 is provided with an anode contact 101;

[0067] All pixel layers are stacked sequentially along the Z direction on the driving wafer 10. At least one pixel layer is provided with a sub-pixel 20. The sub-pixel 20 includes a pixel body 201. Each pixel body 201 is provided with a bonding metal part 3021 on the side close to the driving wafer 10. The bonding metal part 3021 of the sub-pixel 20 in the upper pixel layer is electrically connected to the corresponding anode contact 101 by an anode connector 306 passing through the lower pixel layer to achieve anode connection.

[0068] The bonding metal part 3021 has a first contact surface 30211, which is used to contact the anode connector 306. The first contact surface 30211 is a non-flat surface. The first contact surface 30211 is embedded in the pixel layer where the anode connector 306 is located and is in contact with the anode connector 306, or the anode connector 306 is embedded in the first contact surface 30211.

[0069] In this embodiment, each sub-pixel 20 in the same pixel layer emits the same light color, while the sub-pixels 20 in two adjacent pixel layers emit different light colors, so as to realize the configuration of a multi-layer multi-color microdisplay chip.

[0070] In the above structure, when the bonding metal part 3021 of the sub-pixel 20 in the upper pixel layer is connected to the anode connector 306 of the lower pixel layer, the contact surfaces of the bonding metal part 3021 and the anode connector 306 are non-flat surfaces. This allows the first contact surface 30211 to be embedded in the pixel layer where the anode connector 306 is located and to contact the anode connector 306, or the anode connector 306 to be embedded in the first contact surface 30211. This interlocking structure can effectively avoid bonding gaps or voids between the bonding metal part 3021 and the anode connector 306, ensuring full contact between the bonding metal part 3021 and the anode connector 306, thereby effectively guaranteeing the reliability of anode current transmission. In addition, the above-mentioned interlocking structure also effectively guarantees the connection strength between the bonding metal part 3021 and the anode connector 306, and is also more conducive to alignment and positioning.

[0071] The bonding metal part 3021 can correspond one-to-one with the anode contact 101, or multiple anode contacts 101 can correspond to one bonding metal part 3021.

[0072] In some embodiments, as shown in Figures 2-4, an anode hole 305 corresponding to an anode connector 306 is provided on the interface 60 of two adjacent pixel layers. The anode hole 305 is filled with an anode connector 306. The top surface of the anode connector 306 filled in the anode hole 305 is lower than the interface 60 to form a recess 3051. An embedding protrusion 30212 is formed on the first contact surface 30211. The embedding protrusion 30212 on the bonding metal part 3021 of the sub-pixel in the pixel layer is embedded in the recess 3051 of the corresponding anode hole 305 of the adjacent pixel layer below and makes electrical contact with the anode connector 306.

[0073] Alternatively, as shown in Figures 6-8, the top surface of the anode connector 306 filled in the anode hole 305 is higher than the interface 60 to form a protrusion 3061. An embedding recess 30213 is formed on the first contact surface 30211. The embedding recess 30213 of the bonding metal part 3021 of the sub-pixel in the pixel layer is fitted with the protrusion 3061 of the corresponding anode connector 306 of the adjacent pixel layer below. This method is easier to process. Through the above-mentioned protrusion-recession fitting method, excellent electrical transmission effect can be effectively guaranteed.

[0074] In addition, compared to making the interface between two adjacent pixel layers into a completely flat structure, the interface with the above-mentioned convex and concave characteristics is easier to process, simplifies the processing technology, and is more conducive to the mass production of products.

[0075] Furthermore, as shown in Figure 4, the height h1 of the recessed portion 3051 is 10nm to 300nm, and as shown in Figure 8, the height h2 of the protruding portion 3061 is 10nm to 300nm, in order to better avoid bonding voids and ensure electrical transmission performance. The aforementioned heights should not be too large, as excessive heights can increase manufacturing complexity, while insufficient heights cannot adequately guarantee electrical transmission performance.

[0076] Furthermore, the projections of all sub-pixels 20 onto the driving wafer 10 do not overlap, so as to minimize optical crosstalk or color noise caused by photoexcitation between sub-pixels 20, thereby controlling the light combining effect more precisely.

[0077] In some implementations, there are at least three pixel layers. The bottom pixel layer is also called the first pixel layer, and the pixel layers stacked above it are called the second layer, the third layer, and so on. In the third and above pixel layers, the bonding metal parts 3021 of the sub-pixels are electrically connected to the corresponding anode contacts 101 by a plurality of anode connectors 306 connected in sequence along the Z direction. Each anode connector 306 connected in sequence along the Z direction is located in a different pixel layer.

[0078] In this configuration, adjacent anode connectors 306 connected sequentially along the Z direction are in direct contact, as shown in Figure 9a. This method does not retain the bonding metal parts and other components between adjacent anode connectors 306, which is more conducive to avoiding poor electrical transmission caused by bonding voids. In the case where there are multiple pixel layers between the top sub-pixel 20 and the driving wafer 10, only one anode connector 306 can be provided between the top sub-pixel 20 and the driving wafer 10, so that the anode connector directly penetrates all pixel layers between the top sub-pixel 20 and the driving wafer 10. For example, in Figure 9b, there are three pixel layers, and one anode connector can be used to penetrate the two pixel layers below the top sub-pixel at the same time.

[0079] Alternatively, as shown in Figure 2, a conductive metal part 3022 can be provided between two adjacent anode connectors 306. This method retains the bonding metal part between the two anode connectors 306 as the conductive metal part 3022, making the processing technology simpler.

[0080] In some embodiments, the cross-sectional area of ​​the portion of the anode hole 305 that is relatively far from the driving wafer 10 is larger than the cross-sectional area of ​​the portion that is relatively close to the driving wafer 10. This cross-sectional area refers to the area of ​​the cross section (section) obtained by cutting the anode hole with a plane perpendicular to the axis of the anode hole 305. That is, the anode hole has a shape that is wider at the top and narrower at the bottom, for example, it can be conical or Y-shaped.

[0081] In some preferred embodiments, as shown in Figure 4, the anode hole 305 is tapered with a cross-sectional area increasing towards the side away from the driving wafer. This cross-sectional area refers to the area of ​​the cross-section obtained by cutting the anode hole with a plane perpendicular to its axis. The inclination angle φ of the inner wall of the anode hole 305 relative to the top surface of the driving wafer 10 is 90°–120°. The shape of the anode connector 306 is adapted to the shape of the anode hole 305, resulting in a structure that is wider at the top and narrower at the bottom. With the same bottom length, this shape provides a thicker anode connector compared to a structure that is narrower at the top and wider at the bottom, thereby enhancing the anode's electrical transmission capability.

[0082] In some embodiments, a cathode contact 102 is also provided on the driving wafer 10. Each pixel layer includes an insulating body 301. The pixel bodies 201 in the pixel layer are all covered inside the insulating body 301. The outer side of the pixel body 201 of each sub-pixel 20 is covered with an insulating passivation layer 303. The bonding metal part 3021 of the sub-pixel 20 is located inside the insulating passivation layer 303. The upper part of the insulating passivation layer 303 has an opening 3031. The outer side of the insulating passivation layer 303 is covered with a common cathode layer 304. The pixel body is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to electrically connect with the cathode contact 102.

[0083] Each pixel body 201 includes a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014 arranged sequentially along the Z direction. The active layer 2013 is used to emit light, the P-type semiconductor layer 2012 is used to connect with the anode of the driving wafer 10 to achieve anode connection, and the N-type semiconductor layer 2014 is used to connect with the cathode of the driving wafer 10 to achieve cathode connection.

[0084] Furthermore, the sub-pixel 20 includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014 sequentially disposed upward along the Z-direction. A bonding metal element 3021 is disposed on the side of the P-type semiconductor layer 2012 near the driving wafer 10. A P-type ohmic contact layer 2011 is disposed between the P-type semiconductor layer 2012 and the bonding metal element 3021 to achieve ohmic contact. This ultimately allows the P-type semiconductor layer 2012 to be electrically connected to the corresponding anode contact 101 through the bonding metal element 3021. The N-type semiconductor layer is exposed at the opening 3031, and the exposed portion is electrically connected to the common cathode layer 304. An insulating passivation layer 303 is used to insulate and isolate the N-type semiconductor layer 2014 and the P-type semiconductor layer 2012 in the sub-pixel 20 to prevent short circuits.

[0085] In some embodiments, as shown in FIG4, the height D of the pixel body 201 in the Z direction is 0.3um to 5um; preferably, D is 0.3um to 1.5um; wherein, the height of the pixel body 201 is the distance between its P-type semiconductor layer 2012 and N-type semiconductor layer 2014 (including the thickness of the P-type semiconductor layer and the N-type semiconductor layer itself).

[0086] In some embodiments, the thickness of the P-type ohmic contact layer 2011 is 10 nm to 300 nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), or a metal alloy film such as AuBe or AnZn.

[0087] In some embodiments, as shown in stage d of FIG11, the thickness d1 of the insulating passivation layer 303 is 30nm to 500nm to better ensure insulation and passivation capabilities.

[0088] In some embodiments, the thickness d2 of the common cathode layer 304 is 50nm to 500nm, so as to maximize its transmittance while ensuring current spread capability. The thicker the common cathode layer 304, the better the current spread, but the lower the transmittance, which will cause greater light loss and increase the processing difficulty. If the thickness is too thin, it will affect the metal current spread capability.

[0089] In some embodiments, a cathode hole 307 is provided on the interface 60 of two adjacent pixel layers, and a cathode connector 308 is filled in the cathode hole 307. The cathode connectors 308 are all electrically connected to the cathode contacts 102. The common cathode layers 304 in the upper pixel layer are all electrically connected to the cathode connectors 308 and cathode contacts 102 in the lower pixel layer.

[0090] Understandably, when only three pixel layers are arranged, from bottom to top, they are the first pixel layer 30, the second pixel layer 40, and the third pixel layer 50. In specific arrangements, the common cathode layer 304 of the third pixel layer 50 can be electrically connected to the cathode connector 308 and cathode contact 102 in the second and first layers in sequence. The common cathode layer 304 of the second pixel layer 40 can be electrically connected to the cathode connector 308 and cathode contact 102 in the first pixel layer 30 in sequence. The common cathode layer 304 of the first pixel layer 30 can be directly electrically connected to the cathode contact 102. Alternatively, the cathode connector 308 of the second layer can be directly connected to the cathode contact 102. In this case, the common cathode layer 304 of the third pixel layer 50 can also be directly electrically connected to the cathode connector 308 and cathode contact 102 in the second pixel layer 40. That is, the common cathode layer 304 in the pixel layer can be electrically connected to the cathode contact 102 in sequence through multiple cathode connectors 308 and cathode contacts 102 in the lower pixel layer, or it can be electrically connected to the cathode contact 102 directly through the pixel layer of the adjacent layer below.

[0091] In the case where there are multiple pixel layers between the top sub-pixel 20 and the driving wafer 10, only one cathode connector 308 can be provided between the pixel layer where the top sub-pixel is located and the driving wafer 10, so that the cathode connector 308 directly penetrates all pixel layers between the top pixel layer and the driving wafer 10. For example, in Figure 9c, there are three pixel layers, so one cathode connector can be used to penetrate the two lower pixel layers at the same time.

[0092] Furthermore, a cathode hole 307 is also provided on the interface 60 between two adjacent pixel layers. The top surface of the cathode connector 308 filled in the cathode hole 307 is lower than the interface 60 to form a recess 3051, or the top surface of the cathode connector 308 filled in the cathode hole 307 is higher than the interface 60 to form a protrusion 3061. The recess 3051 / protrusion 3061 are fitted with the corresponding bonding metal part 3021. This is similar to the arrangement of the anode connector 306, and will not be described in detail here.

[0093] The shape of the cathode hole 307 can be the same as that of the anode hole 305, which will not be described in detail here.

[0094] In some embodiments, as shown in FIG4, in the Z direction, the distance H between the top surface of the insulating body 301 of each pixel layer and the common cathode layer 304 at the top of the sub-pixel 20 of that layer is not less than 100nm, so as to prevent interlayer leakage caused by insulation abnormalities.

[0095] In some embodiments, the pixel body 201 is trapezoidal or cylindrical. Compared to a hemispherical or semi-ellipsoidal pixel body, a trapezoidal or cylindrical pixel body can effectively increase the pixel's light-emitting area, thereby increasing the light-emitting intensity. The pixel body generally has an active layer 2013 to emit light. As shown in Figure 1, with the same pixel bottom size, the area of ​​the active layer 2013 (the entire shaded portion) in the trapezoidal pixel body is larger than the area of ​​the active layer (the shaded portion inside the hemisphere) in the hemispherical pixel body, thus effectively increasing the light-emitting intensity. Similarly, a cylindrical pixel body, compared to a hemispherical pixel body, can also increase the area of ​​the active layer 2013, thereby effectively increasing the light-emitting intensity.

[0096] Furthermore, as shown in stage d of Figure 11, the tilt angle θ of the sidewall of the pixel body 201 relative to the driving wafer 10 is 45° to 135°; it can be understood that the sidewall of the sub-pixel 20 here refers to the wall between the top and bottom surfaces of the sub-pixel 20.

[0097] The aforementioned tilt angle can reduce total internal reflection and facilitate light extraction. Exceeding this range will reduce light extraction efficiency. In addition, due to the limited horizontal space, a certain amount of space needs to be reserved for subsequent processes. If the tilt angle is too small, the bottom surface of the pixel will occupy too much horizontal space, which will increase the difficulty of pixel spacing arrangement.

[0098] Preferably, the tilt angle θ of the sidewall of the pixel body 201 relative to the driving wafer 10 is 75° to 105°, which has the best light extraction efficiency and the best pixel pitch design.

[0099] In some implementations, at least one lens 100 is connected to the upper part of the top pixel layer, as shown in FIG2. Each sub-pixel 20 corresponds to one lens 100. This method is to better collimate the emitted light of each sub-pixel 20 and further reduce light interference within the parent pixel. Alternatively, as shown in FIG5, multiple sub-pixels 20 correspond to one lens 100.

[0100] This embodiment also discloses a method for fabricating a multilayer microdisplay chip, including,

[0101] Step M1: Prepare a driving wafer 10, on which an anode contact 101 is provided;

[0102] Step M2: At least two pixel layers are stacked sequentially along the Z direction on the driving wafer 10. Each pixel layer has at least one sub-pixel 20. Each sub-pixel 20 has a bonding metal part 3021 on the side closest to the driving wafer 10. The bonding metal part 3021 of the sub-pixel 20 in the upper pixel layer is electrically connected to the corresponding anode contact 101 by an anode connector 306 passing through the lower pixel layer. The bonding metal part 3021 has a first contact surface 30211 for contacting the anode connector 306. The first contact surface 30211 is a non-planar surface. The first contact surface 30211 is embedded in the pixel layer where the anode connector 306 is located and is in contact with the anode connector 306, or the anode connector 306 is embedded in the first contact surface 30211.

[0103] Furthermore, during the fabrication of the pixel layer, an anode hole 305 corresponding to the anode connector 306 needs to be opened on the interface 60 of two adjacent pixel layers, and the anode connector 306 is filled in the anode hole 305. The top surface of the anode connector 306 filled in the anode hole 305 is lower than the interface 60 to form a recess 3051. An embedding protrusion 30212 is formed on the first contact surface 30211, so that the embedding protrusion 30212 corresponding to the bonding metal part 3021 of the sub-pixel in the pixel layer is embedded in the recess 3051 of the corresponding anode hole 305 of the adjacent pixel layer below and makes electrical contact with the anode connector 306.

[0104] Alternatively, the top surface of the anode connector 306 filled in the anode hole 305 is higher than the interface 60 to form a protrusion 3061, and an embedding recess 30213 is formed on the first contact surface 30211. The embedding recess 30213 corresponding to the bonding metal part 3021 of the sub-pixel in the pixel layer is fitted with the protrusion 3061 of the corresponding anode connector 306 of the adjacent pixel layer below.

[0105] In the specific preparation process, step M2 includes:

[0106] Step M21: Bond a compound semiconductor 901 onto the driving wafer 10;

[0107] As shown in Figure 10, the compound semiconductor 901 includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, an N-type semiconductor layer 2014, and a substrate 901 sequentially disposed away from the driving wafer direction. After the compound semiconductor 901 is bonded to the driving wafer 10, the substrate 901 needs to be removed to expose the N-type semiconductor layer 2014. After removing the substrate 901, an N-type ohmic contact layer 2015 can also be disposed on the N-type semiconductor layer 2014.

[0108] Furthermore, the thickness of the N-type ohmic contact layer 2015 is in the range of 10nm to 300nm, and its material can be transparent conductive films such as indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO), or metal alloy films such as gold germanium alloy (AuGe) and gold nickel alloy (AuNi).

[0109] Preferably, the thickness of the N-type ohmic contact layer 2015 is 10nm to 100nm, so as to ensure ohmic contact while also giving it high transmittance, thereby reducing light loss.

[0110] Among them, the compound semiconductor 901 can be bonded to the driving wafer 10 through the bonding layer 302, and the bonding alignment accuracy can be 10~500um.

[0111] Step M22: Pattern the compound semiconductor 901 to obtain at least one sub-pixel 20, such that the sub-pixel 20 is electrically connected to the corresponding anode contact 101 through the bonding layer 302; the bonding layer 302 includes a plurality of bonding metal elements 3021, such that the pixel body 201 of each sub-pixel 20 corresponds to one bonding metal element 3021, and the pixel body 201 of the sub-pixel 20 is electrically connected to the corresponding anode contact 101 through the corresponding bonding metal element 3021;

[0112] Each bonding metal component 3021 is obtained by etching the bonding layer 302; here, the anode contact 101 and the sub-pixel 20 correspond one-to-one, or multiple anode contacts 101 can correspond to one sub-pixel 20.

[0113] Step M23: Deposit an insulating passivation layer 303 on the outside of the pixel body 201, and provide an opening 3031 on the upper part of the insulating passivation layer 303 to expose the N-type semiconductor layer 2014 or N-type ohmic contact layer 2015 of the sub-pixel 20.

[0114] Step M24: Deposit a common cathode layer 304 on the outside of the insulating passivation layer 303, so that the pixel body 201 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to electrically connect with the cathode contact 102, resulting in the structure shown in stage d of Figure 11.

[0115] That is, the N-type semiconductor layer 2014 of the pixel body 201 is electrically connected through the common cathode layer 304 and the cathode contact 102 to achieve cathode connection;

[0116] The driving wafer 10 may have only one cathode contact 102, or the number of cathode contacts may be determined as needed.

[0117] Step M25, as shown in stage e of Figure 11, fill the outside of the common cathode layer 304 with an insulating body 301 so that the pixel body 201 of the sub-pixel 20 is located inside the insulating body 301, and prepare an anode connector 306 in the insulating body 301 to obtain a pixel layer.

[0118] Understandably, the insulating passivation layer 303 and the common cathode layer 304 outside the pixel body 201 are also located inside the insulating body 301.

[0119] Step M26, as shown in stage f of Figure 11, another compound semiconductor 901 is bonded to the top of the previous pixel layer through the bonding layer 302, and step M22 is executed. The bonding metal 3021 of the sub-pixel in this pixel layer is electrically connected to the corresponding anode contact by the anode connector 306 passing through the previous pixel layer. When the bonding metal 3021 of the sub-pixel is connected to the anode connector 306 of the previous pixel layer, the first contact surface 30211 of the bonding metal is embedded in the previous pixel layer and in contact with the anode connector 306, or the anode connector 306 is embedded in the first contact surface 30211. Then steps M23-M25 are executed to obtain the next pixel layer.

[0120] Step M27: Repeat step M26 until all pixel layers have been prepared.

[0121] In this context, each sub-pixel 20 in the same pixel layer emits the same light color, while sub-pixels 20 in two adjacent pixel layers emit different light colors.

[0122] Understandably, the bonding metal part 3021 located between adjacent anode connectors 306 in the Z direction can be directly used as the conductive metal part 3022.

[0123] Specifically, in this embodiment, three pixel layers can be set, as shown in Figure 2. From bottom to top, they are the first pixel layer 30, the second pixel layer 40, and the third pixel layer 50, so that the emitted light color of the sub-pixels 20 in each pixel layer is different, so as to achieve a three-color configuration.

[0124] In other methods, two pixel layers can be set, in which the light emitted by sub-pixels 20 is different, thus achieving a dual-color configuration. Alternatively, more layers can be added on top of three pixel layers to achieve the desired configuration.

[0125] For ease of description, subpixels emitting red light are called red subpixels, subpixels emitting green light are called green subpixels, and subpixels emitting blue light are called blue subpixels.

[0126] In actual configuration, if only three pixel layers are set, as shown in Figure 2, from bottom to top, they are the first pixel layer 30, the second pixel layer 40, and the third pixel layer 50. Red sub-pixels can be arranged in the first pixel layer 30 (bottom pixel layer), green sub-pixels can be arranged in the second pixel layer 40, and blue sub-pixels can be arranged in the third pixel layer 50 (top pixel layer). In actual operation, the specific pixel layer in which the sub-pixels of different colors are located can be selected as needed, and there is no limitation here.

[0127] Understandably, since the light-emitting colors of sub-pixels 20 in two adjacent pixel layers are different, the materials of the compound semiconductor 901 used in the fabrication of the two adjacent pixel layers are also different, so that the light-emitting colors of the compound semiconductors used are different; when fabricating each pixel layer, the light-emitting color of the selected compound semiconductor is determined according to the actual situation. If it is necessary to fabricate a sub-image with a red light-emitting color, then a compound semiconductor with a red light-emitting color is selected.

[0128] Among them, the compound semiconductor 901 uses inorganic compound materials. For example, the compound semiconductor corresponding to the blue light pixel layer uses InGaN material, the compound semiconductor corresponding to the green light pixel layer uses InGaN material, and the compound semiconductor corresponding to the red light pixel layer uses InGaN or AlGaInP material.

[0129] In practical applications, the layers of compound semiconductors are more complex, or there may be cross-use of materials. A typical compound semiconductor structure mainly includes a P-type semiconductor layer 2012, an N-type semiconductor layer 2014, an active layer 2013 (MQW active quantum well) sandwiched between the two, and other functional layers. For the materials of each layer of red compound semiconductors, please refer to Table 1. For the materials of each layer of green and blue compound semiconductors, please refer to Table 2.

[0130] Table 1. Material of each film layer in compound semiconductor (R)

[0131] Table 2 Material of each film layer in compound semiconductors (G / B)

[0132] In one embodiment, the insulating passivation layer 303 may be made of one or more of aluminum oxide, silicon dioxide, and silicon nitride.

[0133] In one embodiment, the insulating body 301 may be made of one or more of silicon oxide, silicon nitride, silicon carbide (SiC), silicon carbon nitride (SiCN), phosphate glass (PSG), and borosilicate glass (BPSG).

[0134] In one embodiment, the common cathode layer 304 includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), Al-doped zinc oxide (AZO), Al-doped indium tin oxide, Ag-doped indium tin oxide, and Au-doped indium tin oxide.

[0135] In one embodiment, the anode connector 306 may be made of one or more of aluminum, copper, and tungsten.

[0136] Furthermore, the cathode connector 308 can be made of the same material as the anode connector 306, which is a conductive material.

[0137] In one embodiment, the material of the bonding metal part 3021 can be one of Al, Au, Cu, or a stacked structure of Ni, Au, Cu and Sn, or a bonding stack of Au with In or Ge, or a bonding stack of Au with Si.

[0138] Furthermore, the aforementioned bonding metal part 3021 can adopt the following structural form: Cr2nm / Pt50nm / Ti10nm / Pt50nm / Au100nm / Sn150nm / Au50nm, wherein Cr is the adhesive layer and Pt / Ti / Pt is the barrier layer.

[0139] In some implementations, after step M2, as shown in stage h in FIG11, a dielectric layer is deposited on top of the top pixel layer, and the dielectric layer is patterned and etched to form a lens 100, such that each sub-pixel 20 corresponds to a lens 100, or multiple sub-pixels 20 correspond to one lens 100.

[0140] The multilayer microdisplay chip and its fabrication method described in the above embodiments, through mutual interlocking, enable the bonding metal parts and the anode connectors to make full contact, thereby effectively ensuring the reliability of anode current transmission; it also effectively ensures the connection strength of the bonding metal parts and the anode connectors, and at the same time, it is more conducive to the alignment and positioning of the two.

[0141] Example 2

[0142] As shown in Figures 12-19, this embodiment discloses a multi-layer multicolor microdisplay chip based on color transfer. The main difference between this embodiment and Embodiment 1 is that it includes two pixel layers. The upper pixel layer is provided with a color transfer component and a sub-pixel with a different light color from the color transfer component. The lower pixel layer is provided with an excitation pixel. The excitation pixel and the color transfer component correspond one-to-one. The color transfer component is located on the light emission path of the corresponding excitation pixel. Both the excitation pixel and the sub-pixel include a pixel body. Each pixel body is provided with a bonding metal component on the side close to the driving wafer.

[0143] As shown in Figure 12, the multi-layer multicolor microdisplay chip based on color conversion includes a driver wafer 10 and two pixel layers, namely the first pixel layer 30 and the second pixel layer 40.

[0144] Among them, the driving wafer 10 can be a CMOS driving wafer, and the sub-pixel 20 and the excitation pixel 70 are both electrically connected to the driving wafer 10 so as to control the light emission of the sub-pixel 20 and the excitation pixel 70 in the pixel layer through the driving wafer.

[0145] An anode contact 101 is provided on the driver wafer 10;

[0146] The first pixel layer 30 is stacked along the Z direction on the driving wafer 10, and an excitation pixel 70 is provided in the first pixel layer 30.

[0147] The second pixel layer 40 is stacked on the first pixel layer 30 along the Z direction. The second pixel layer 40 is provided with a color transfer element 80 and a sub-pixel 20 with a different light color from the color transfer element 80.

[0148] Each color transfer element 80 corresponds one-to-one with an excitation pixel 70. The color transfer element 80 is located on the light emission path of the corresponding excitation pixel 70, so as to excite the color transfer element 80 to emit light of the corresponding color. When the light emitted by the excitation pixel 70 is directed to the corresponding color transfer element 80, the color transfer element 80 will be excited and emit light of a certain color.

[0149] Both the excitation pixel 70 and the sub-pixel 20 include a pixel body 201. Each pixel body 201 is provided with a bonding metal part 3021 on the side near the driving wafer 10. In the second pixel layer 40, the bonding metal part 3021 of the sub-pixel 20 is electrically connected to the corresponding anode contact 101 by an anode connector 306 passing through the first pixel layer 30, so as to realize anode connection.

[0150] The bonding metal part 3021 of the sub-pixel 20 in the second pixel layer 40 has a first contact surface 30211. The first contact surface 30211 is used to contact the anode connector 306. The first contact surface 30211 is a non-flat surface, as shown in Figure 12. The first contact surface 30211 is embedded in the first pixel layer 30 and contacts the anode connector 306. Alternatively, as shown in Figure 15, the anode connector 306 is embedded in the first contact surface 30211.

[0151] The color-transfer element 80 can be made of quantum dot material or phosphor material, so that it can be excited by external light and emit light of a specific color.

[0152] In the above structure, when the bonding metal 3021 of the sub-pixel 20 in the second pixel layer 40 is connected to the anode connector 306 of the first pixel layer 30 below, the contact surfaces of the bonding metal 3021 and the anode connector 306 are non-flat surfaces. This allows the first contact surface 30211 to be embedded in the first pixel layer 30 and in contact with the anode connector 306, or the anode connector 306 to be embedded in the first contact surface 30211. This interlocking structure can effectively prevent bonding gaps or voids between the bonding metal 3021 and the anode connector 306, ensuring full contact between them and effectively guaranteeing the reliability of anode current transmission. In addition, the above-mentioned interlocking structure also effectively guarantees the connection strength between the bonding metal 3021 and the anode connector 306, and is also more conducive to alignment and positioning.

[0153] The bonding metal part 3021 can correspond one-to-one with the anode contact 101, or multiple anode contacts 101 can correspond to one bonding metal part 3021.

[0154] In some implementations, the color converter 80 emits red light and the excitation pixel 70 emits blue light.

[0155] It should be noted that the light emission wavelength of the excitation pixel 70 is shorter than that of red light, so the shorter wavelength light is used to excite the color transfer element 80 to emit red light. The color transfer element 80 is made of quantum dot material or red phosphor material.

[0156] Furthermore, as shown in Figure 12, sub-pixels 20 are also provided in the first pixel layer 30. The light emitted by sub-pixels 20 in the first pixel layer 30 is blue, and the light emitted by sub-pixels 20 in the second pixel layer 40 is green.

[0157] Blue light emitted from sub-pixel 20 in the first pixel layer 30 is emitted through the second pixel layer 40. Green light emitted from sub-pixel 20 in the second pixel layer 40 is emitted through the second pixel layer 40. Red light emitted by the color converter 80 after being excited is also emitted through the second pixel layer 40. Therefore, the light emitted through the second pixel layer 40 is green light, blue light and red light, thus achieving a three-color configuration.

[0158] Specifically, as shown in Figures 12 and 15, the first pixel layer 30 has two excitation pixels 70 and a sub-pixel 20 with a blue light emission color, and the second pixel layer 40 has two color switching components 80 and a sub-pixel 20 with a green light emission color.

[0159] In some implementations, the red light transducer can be made of quantum dot materials, such as indium phosphide (InP); or it can be made of phosphor materials, such as fluoride-based phosphors, KSF red phosphor (K2SiF6:Mn4+), or nitride Eu2+ doped CaAlSiN3-based red phosphor, etc.

[0160] The sub-pixel 20 and the excitation pixel 70 are both electrically connected to the driving wafer 10. The driving wafer 10 has a driving circuit to control the light emission of the sub-pixel 20 and the excitation pixel 70.

[0161] The structure of the excitation pixel is basically the same as that of the sub-pixel, including the P-type semiconductor layer, active layer and N-type semiconductor layer, etc., which will not be elaborated here.

[0162] In some embodiments, the projections of the excitation pixel 70 and the color transfer element 80 onto the driving wafer 10 are mutually overlapping, allowing them to be coaxially arranged so that the light emitted by the excitation pixel 70 can reach the color transfer element 80 well, thereby exciting the color transfer element 80 to emit light of a specific color.

[0163] In some embodiments, an anode hole 305 is formed on the interface 60 between the first pixel layer 30 and the second pixel layer 40. An anode connector 306 is filled within the anode hole 305, as shown in Figures 2-4. The top surface of the anode connector 306 filling the anode hole 305 is lower than the interface 60, forming a recess 3051. An embedding protrusion 30212 is formed on the first contact surface 30211. The embedding protrusion 30212 of the sub-pixel 20 in the second pixel layer 40 is embedded in the corresponding recess 3051 of the anode hole 305 in the first pixel layer 30 and makes electrical contact with the anode connector 306; or…

[0164] As shown in Figures 15-17, the top surface of the anode connector 306 filled in the anode hole 305 is higher than the interface 60 to form a protrusion 3061. An embedding recess 30213 is formed on the first contact surface 30211. The embedding recess 30213 of the sub-pixel in the second pixel layer 40 is fitted with the protrusion 3061 of the corresponding anode connector 306 in the first pixel layer 30. This method is easier to process. Through the above-mentioned protrusion-recession fitting method, excellent electrical transmission effect can be effectively guaranteed.

[0165] In addition, compared to making the interface between two adjacent pixel layers into a completely flat structure, the interface with the above-mentioned convex and concave characteristics is easier to process, simplifies the processing technology, and is more conducive to the mass production of products.

[0166] In some embodiments, as shown in Figure 14, the height h1 of the recess 3051 is 10 nm to 300 nm, and as shown in Figure 7, the height h2 of the protrusion 3061 is 10 nm to 300 nm. This is to better avoid bonding voids and ensure electrical transmission performance. The above heights should not be too large, as excessive heights can increase manufacturing difficulty, while insufficient heights cannot guarantee adequate electrical transmission performance.

[0167] In some embodiments, the cross-sectional area of ​​the portion of the anode hole 305 that is relatively far from the driving wafer 10 is larger than the cross-sectional area of ​​the portion that is relatively close to the driving wafer 10. This cross-sectional area refers to the area of ​​the cross section (section) obtained by cutting the anode hole with a plane perpendicular to the axis of the anode hole 305. That is, the anode hole has a shape that is wider at the top and narrower at the bottom, for example, it can be conical or Y-shaped.

[0168] In some preferred embodiments, as shown in Figure 14, the anode hole 305 is tapered with a cross-sectional area that increases toward the side away from the driving wafer. The cross-sectional area refers to the area of ​​the cross section (section) obtained by cutting the anode hole with a plane perpendicular to the axis of the anode hole 305. The inclination angle φ of the inner wall of the anode hole 305 relative to the top surface of the driving wafer 10 is 90° to 120°.

[0169] The shape of the anode connector 306 is adapted to the shape of the anode hole 305, so that the anode connector also has a structure that is wider at the top and narrower at the bottom. When the bottom length is the same, this shape can produce a thicker anode connector compared to the structure that is narrower at the top and wider at the bottom, thereby enhancing the anode electrical transmission capability.

[0170] In some embodiments, a cathode contact 102 is also provided on the driving wafer 10. The first pixel layer 30 and the second pixel layer 40 both include an insulating body 301. The pixel body 201 in the first pixel layer 30 is covered inside the insulating body 301 of the layer. Similarly, the pixel body 201 in the second pixel layer 40 is covered inside the insulating body 301 of the layer.

[0171] Each pixel body 201 is covered with an insulating passivation layer 303. The bonding metal part 3021 is located inside the insulating passivation layer 303. The upper part of the insulating passivation layer 303 has an opening 3031. The outer part of the insulating passivation layer 303 is covered with a common cathode layer 304. The pixel body 201 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to electrically connect to the cathode contact 102.

[0172] Each pixel body 201 includes a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014 arranged sequentially along the Z direction. The active layer 2013 is used to emit light, the P-type semiconductor layer 2012 is used to connect with the anode of the driving wafer 10 to achieve anode connection, and the N-type semiconductor layer 2014 is used to connect with the cathode of the driving wafer 10 to achieve cathode connection.

[0173] Furthermore, each of the P-type semiconductor layers 2012 near the driving wafer 10 is provided with a bonding metal element 3021. A P-type ohmic contact layer 2011 is provided between the P-type semiconductor layer 2012 and the bonding metal element 3021 to achieve ohmic contact between them. This allows the P-type semiconductor layer 2012 to be electrically connected to the corresponding anode contact 101 via the bonding metal element 3021, thus achieving anode connection. The N-type semiconductor layer is exposed at the opening 3031, and the exposed portion is electrically connected to the common cathode layer 304. The common cathode layer 304 is used to connect to the cathode contact 102 of the driving wafer 10 to achieve cathode connection. The insulating passivation layer 303 is used to insulate and isolate the N-type semiconductor layer 2014 and the P-type semiconductor layer 2012 in the pixel body 201 to prevent short circuits.

[0174] Furthermore, the aforementioned anode hole 305 is formed on the insulating body 301 of the first pixel layer 30.

[0175] In some embodiments, as shown in FIG14, the height D of the pixel body 201 in the Z direction is 0.3um to 5um; preferably, D is 0.3um to 1.5um; wherein, the height of the pixel body 201 is the distance between its P-type semiconductor layer 2012 and N-type semiconductor layer 2014 (including the thickness of the P-type semiconductor layer 2012 and N-type semiconductor layer 2014 themselves).

[0176] Furthermore, the tilt angle θ of the sidewall of the pixel body 201 relative to the driving wafer 10 is 45° to 135°; it can be understood that the sidewall of the pixel body 201 here refers to the wall between the top and bottom surfaces of the pixel body 201.

[0177] The aforementioned tilt angle can reduce total internal reflection and facilitate light extraction. Exceeding this range will reduce light extraction efficiency. In addition, due to the limited horizontal space, a certain amount of space needs to be reserved for subsequent processes. If the tilt angle is too small, the bottom surface of the pixel will occupy too much horizontal space, which will increase the difficulty of pixel spacing arrangement.

[0178] Preferably, the tilt angle θ of the sidewall of the pixel body 201 relative to the driving wafer 10 is 75° to 105°, which has the best light extraction efficiency and the best pixel pitch design.

[0179] In some embodiments, the thickness of the P-type ohmic contact layer 2011 is 10 nm to 300 nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), or a metal alloy film such as AuBe or AnZn.

[0180] In some embodiments, the thickness of the insulating passivation layer 303 is 30nm to 500nm to better ensure insulation and passivation capabilities.

[0181] In some embodiments, the thickness of the common cathode layer 304 is 50nm to 500nm, so as to maximize its transmittance while ensuring current spread capability. The thicker the common cathode layer 304, the better the current spread, but the lower the transmittance, which will cause greater light loss and increase the processing difficulty. If the thickness is too thin, it will affect the metal current spread capability.

[0182] In one embodiment, the top end of the anode connector 306 is longer than its bottom end in the X direction, exhibiting a structure that is wider at the top and narrower at the bottom. When the bottom end length is the same, this shape can produce a thicker anode connector compared to a structure that is wider at the bottom and narrower at the top, thereby enhancing the anode's electrical transmission capability. The X and Z directions are perpendicular.

[0183] In some embodiments, a cathode hole 307 is provided on the interface 60 between the first pixel layer 30 and the second pixel layer 40. The cathode hole 307 is filled with a cathode connector 308. The cathode connectors 308 are all electrically connected to the cathode contacts 102. The common cathode layer 304 in the second pixel layer 40 is electrically connected to the cathode contacts 102 through the cathode connectors 308 in the first pixel layer 30.

[0184] The common cathode layer 304 of the first pixel layer 30 can be directly electrically connected to the cathode contact 102.

[0185] Furthermore, as shown in Figures 14 and 17, a cathode hole 307 is also provided on the interface 60 between the first pixel layer 30 and the second pixel layer 40. The top surface of the cathode connector 308 filled in the cathode hole 307 is lower than the interface 60 to form a recess 3051, or the top surface of the cathode connector 308 filled in the cathode hole 307 is higher than the interface 60 to form a protrusion 3061. This is similar to the arrangement of the anode connector 306, and will not be described in detail here.

[0186] In some embodiments, the second pixel layer 40 is provided with filling holes 401, and each filling hole 401 is filled with a color transfer element 80.

[0187] The filling hole 401 is formed in the insulating body 301 of the second pixel layer 40.

[0188] Furthermore, as shown in Figure 12, the inner wall of the filling hole 401 is inclined relative to the driving wafer 10, with an inclination angle C of 60° to 90°, to facilitate etching and ensure filling effect.

[0189] In some embodiments, the length Ls of the filling hole 401 along the X direction is not less than the maximum length of the excitation pixel 70 in the X direction, and the X direction is perpendicular to the Z direction. This method can provide a good light path for the excitation pixel 70 below and is less prone to light crosstalk, thereby maximizing the color conversion effect.

[0190] In some embodiments, an insulating layer 402 is formed on the inner wall of the filling hole 401. The insulating layer 402 is used to shield the light interference from the pixels below the non-filled space, so that the color transfer element 80 inside the filling hole 401 can have a better color transfer effect.

[0191] Among them, the insulating layer 402 is a metal reflective layer or a light-absorbing layer.

[0192] The metal reflective layer can be made of one or more metals such as Al, Ti, Pt, Au, Cr and Ni, to shield light interference through metal reflection; the light-absorbing layer can be made of light-absorbing materials such as carbon film, black glue, polycrystalline silicon, etc., to shield light interference through light absorption.

[0193] Furthermore, the thickness of the insulating layer 402 is 50nm to 2um. If the thickness is too thin, leakage is likely to occur, while if the thickness is too thick, the cost will increase.

[0194] Specifically, the required thickness for optical interference shielding can be achieved based on the different materials used, such as Al ≥ 50nm and black glue ≥ 1um.

[0195] In some implementations, the pixel body 201 is trapezoidal or cylindrical.

[0196] In some implementations, as shown in FIG18, at least one lens 100 is connected to the upper part of the second pixel layer 40, and each sub-pixel 20 and color transfer element 80 corresponds to a different lens in order to better collimate the emitted light of each sub-pixel 20 and further reduce light interference between pixels; or, all multiple sub-pixels 20 and color transfer elements 80 correspond to the same lens.

[0197] This embodiment also discloses a method for fabricating the above-mentioned microdisplay chip, including the following steps:

[0198] Step M1: Prepare a driving wafer 10, on which an anode contact 101 is provided;

[0199] Step M2: A first pixel layer 30 and a second pixel layer 40 are sequentially stacked along the Z direction on the driving wafer 10, such that the first pixel layer 30 contains an excitation pixel 70, and the second pixel layer 40 contains a color transfer element 80 and a sub-pixel 20 with a different light emission color from the color transfer element 80. Each color transfer element 80 corresponds one-to-one with an excitation pixel 70, and each color transfer element 80 is located on the light emission path of the corresponding excitation pixel 70. Both the excitation pixel 70 and the sub-pixel 20 include a pixel body 201, and each pixel body 201 is close to the driving wafer 10. Each side of the first pixel layer 30 has a bonding metal part 3021. The bonding metal part 3021 of the sub-pixel 20 in the second pixel layer 40 is electrically connected to the corresponding anode contact 101 by the anode connector 306 passing through the first pixel layer 30. The bonding metal part 3021 has a first contact surface 30211 for contacting the anode connector 306. The first contact surface 30211 is a non-flat surface. The first contact surface 30211 is embedded in the first pixel layer 30 and contacts the anode connector 306, or the anode connector 306 is embedded in the first contact surface 30211.

[0200] In one embodiment, after step M2, as shown in stage f of FIG19, a dielectric layer is deposited on the upper part of the second pixel layer 40, and the dielectric layer is patterned and etched to form a lens 100, such that each sub-pixel 20 and color transfer element 80 corresponds to a different lens, or all multiple sub-pixels 20 and color transfer elements 7 correspond to the same lens.

[0201] In some implementations, step M2 includes:

[0202] Step M21: Bond a compound semiconductor 901 onto the driving wafer 10; for example, the compound semiconductor 901 can be bonded onto the driving wafer 10 through the bonding layer 302.

[0203] The aforementioned compound semiconductor 901 includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014, and a substrate 901, which are sequentially disposed away from the direction of the driving wafer 10. After the compound semiconductor 901 is bonded to the driving wafer 10, the substrate 901 needs to be removed to expose the N-type semiconductor layer 2014. After removing the substrate 901, an N-type ohmic contact layer 2015 can also be disposed on the N-type semiconductor layer 2014.

[0204] Furthermore, the thickness of the N-type ohmic contact layer 2015 is 10nm to 300nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), or a metal alloy film such as gold-germanium alloy (AuGe) or gold-nickel alloy (AuNi).

[0205] Preferably, the thickness of the N-type ohmic contact layer 2015 is 10nm to 100nm, so as to ensure ohmic contact while also giving it high transmittance, thereby reducing light loss.

[0206] Step M22: Pattern the compound semiconductor 901 to obtain at least one set of pixels. The set of pixels includes an excitation pixel 70 and a blue-emitting sub-pixel 20. Both the excitation pixel 70 and the blue-emitting sub-pixel 20 include a pixel body 201. Each pixel body 201 is electrically connected to a corresponding anode contact 101 through a corresponding bonding metal part 3021. Each pixel body 201 corresponds to one bonding metal part 3021. The bonding metal part 3021 can be obtained by etching the bonding layer 302.

[0207] Step M23: Deposit an insulating passivation layer 303 on the outside of the pixel body 201, and provide an opening 3031 on the upper part of the insulating passivation layer 303 to expose the N-type semiconductor layer 2014 or N-type ohmic contact layer 2015 of the pixel body 201.

[0208] Step M24: Deposit a common cathode layer 304 on the outside of the insulating passivation layer 303, so that the pixel body 201 is electrically connected to the common cathode layer 304 through the opening 3031, and the common cathode layer 304 is used to be electrically connected to the cathode contact 102.

[0209] That is, the N-type semiconductor layer 2014 of the pixel body 201 is electrically connected through the common cathode layer 304 and the cathode contact 102 to achieve cathode connection;

[0210] The driving wafer 10 may have only one cathode contact 102, or the number of cathode contacts 102 may be determined as needed.

[0211] Step M25: Fill the outside of the common cathode layer 304 with an insulating body 301 so that the pixel bodies 201 are all located inside the insulating body 301, and prepare an anode connector 306 in the first pixel layer 30 to obtain the first pixel layer 30 as shown in stage c of Figure 19.

[0212] Understandably, the insulating passivation layer 303 and the common cathode layer 304 outside the pixel body 201 are also located inside the insulating body 301.

[0213] Step M26: Bond another compound semiconductor 80 and compound semiconductor 901 to the top of the first pixel layer 30. Perform patterned etching on the compound semiconductor 901 to obtain a green sub-pixel 20. The green sub-pixel also includes a pixel body 201. The bonding metal 3021 of the green sub-pixel in the second pixel layer 40 is electrically connected to the corresponding anode contact 101 by an anode connector 306 passing through the first pixel layer 30. The bonding metal 3021 has a first contact surface 30211 for contacting the anode connector 306. The first contact surface 30211 is a non-planar surface. The first contact surface 30211 is embedded in the first pixel layer 30 and in contact with the anode connector 306, or the anode connector 306 is embedded in the first contact surface 30211. Then repeat steps M23-M24.

[0214] Step M27: Fill the outside of the common cathode layer 304 with an insulating body 301, so that the pixel bodies 201 are all located inside the insulating body 301. As shown in stage d of Figure 19, fill holes 401 are provided on the insulating body 301, and color transfer material is filled in the fill holes 401 to form a color transfer element 80, as shown in stage e of Figure 19, thereby completing the preparation of the second pixel layer 40.

[0215] Understandably, the position of the filling hole 401 should be located on the light emission path of the excitation pixel 70 so that the light emitted by the excitation pixel 70 can pass through the color transfer element 80 in the hole, thereby exciting the red light color transfer element 80 to emit color and produce red light.

[0216] Understandably, since the light emitted by sub-pixels 20 in the two pixel layers is different, the compound semiconductor 901 used in the fabrication of the two pixel layers is also different, so that the light emitted by the compound semiconductor 901 used is different.

[0217] For example, both the P-type semiconductor layer 2012 and the N-type semiconductor layer 2014 in the compound semiconductor 901 can be made of gallium nitride (GaN) material, and the substrate 901 can be made of gallium nitride (GaN), silicon (Si) or sapphire material.

[0218] In one embodiment, the insulating passivation layer 303 may be made of one or more of aluminum oxide, silicon dioxide, and silicon nitride.

[0219] In one embodiment, the insulating body 301 may be made of one or more of silicon oxide, silicon nitride, silicon carbide (SiC), silicon carbon nitride (SiCN), phosphate glass (PSG), and borosilicate glass (BPSG).

[0220] In one embodiment, the common cathode layer 304 includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), Al-doped zinc oxide (AZO), Al-doped indium tin oxide, Ag-doped indium tin oxide, and Au-doped indium tin oxide.

[0221] In one embodiment, the anode connector 306 may be made of one or more of aluminum, copper, and tungsten.

[0222] Furthermore, the cathode connector 308 can be made of the same material as the anode connector 306, which is a conductive material.

[0223] In one embodiment, the material of the bonding metal part 3021 can be one of Al, Au, Cu, or a stacked structure of Ni, Au, Cu and Sn, or a bonding stack of Au with In or Ge, or a bonding stack of Au with Si.

[0224] Furthermore, the aforementioned bonding metal part 3021 can adopt the following structural form: Cr2nm / Pt50nm / Ti10nm / Pt50nm / Au100nm / Sn150nm / Au50nm, wherein Cr is the adhesive layer and Pt / Ti / Pt is the barrier layer.

[0225] In some other implementations, only excitation pixels 70 can be set in the first pixel layer 30, and in this case, the light emitted by the entire chip through the second pixel layer 40 has only two colors.

[0226] For example, the light emitted by the excitation pixel 70 in the first pixel layer 30 is also blue. When the blue light emitted by the laser pixel passes through the corresponding red light color converter above, it will excite the red light color converter to emit red light. Then, the light emitted by the structure through the second pixel layer 40 is only red light and green light emitted by the green sub-pixel. At this time, the chip product is a dual-color product.

[0227] Example 3

[0228] The main difference between this embodiment and Embodiment 1 is that the light emitted by sub-pixels 20 in each pixel layer is the same, so as to prepare a multi-layer monochrome product.

[0229] The fabrication method of the multilayer microdisplay chip in this embodiment is basically the same as that in Embodiment 1, except that the light emission color of the sub-pixels in each pixel layer is the same, which will not be described again here.

[0230] All the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention. That is, any number of embodiments can be combined to meet the needs of different application scenarios. All of these are within the protection scope of this application and will not be described in detail here.

[0231] It should be noted that the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A multi-layer microdisplay chip, characterized by: The application relates to a display device, comprising: a driving wafer, wherein an anode contact is arranged on the driving wafer; at least two pixel layers, wherein all the pixel layers are arranged in sequence along the Z direction on the driving wafer, at least one of the pixel layers is provided with a sub-pixel, the sub-pixel comprises a pixel body, a bonding metal piece is arranged on one side of each pixel body close to the driving wafer, the bonding metal piece of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact through an anode connecting piece passing through the lower pixel layer, the bonding metal piece of the sub-pixel in the upper pixel layer has a first contact surface for contacting the anode connecting piece, the first contact surface is a non-flat surface, the first contact surface is embedded in the pixel layer where the anode connecting piece is arranged and contacts the anode connecting piece, or the anode connecting piece is embedded in the first contact surface.

2. The multi-layer microdisplay chip of claim 1, wherein: An anode hole corresponding to the anode connecting piece is arranged on the interface between two adjacent pixel layers, the anode hole is filled with the anode connecting piece, the top surface of the anode connecting piece filled in the anode hole is lower than the interface and forms a recess, the first contact surface is provided with an embedded protrusion, the embedded protrusion of the sub-pixel in the pixel layer is embedded in the recess of the corresponding anode hole of the lower adjacent pixel layer and electrically contacts the anode connecting piece; or, the top surface of the anode connecting piece filled in the anode hole is higher than the interface and forms a protrusion, the first contact surface is provided with an embedded recess, the embedded recess of the sub-pixel in the pixel layer is embedded in the protrusion of the corresponding anode connecting piece of the lower adjacent pixel layer.

3. The multi-layer microdisplay chip of claim 2, wherein: The height of the recess is 10nm-300nm, and the height of the protrusion is 10nm-300nm.

4. The multi-layer microdisplay chip of claim 2, wherein: The pixel layers comprise at least three layers, the bonding metal piece of the sub-pixel in the third layer and the pixel layers above the third layer is electrically connected to the corresponding anode contact through a plurality of anode connecting pieces connected in sequence along the Z direction, each anode connecting piece connected in sequence along the Z direction is arranged in a different pixel layer, and the two anode connecting pieces connected in sequence along the Z direction directly contact each other; or, a conductive metal piece is arranged between the two anode connecting pieces.

5. The multi-layer microdisplay chip of claim 2, wherein: The cross-sectional area of the part of the anode hole far away from the driving wafer is larger than that of the part of the anode hole close to the driving wafer.

6. The multi-layer microdisplay chip of claim 5, wherein: The anode hole is conical, the cross-sectional area of the anode hole increases away from the side where the driving wafer is arranged, and the inclination angle of the inner wall of the anode hole relative to the top surface of the driving wafer is 90-120 degrees.

7. The multi-layer microdisplay chip of claim 1, wherein: The driving wafer is further provided with a cathode contact, each pixel layer comprises an insulating body, the pixel body in the pixel layer is wrapped inside the insulating body, the outer part of each pixel body is wrapped with an insulating passivation layer, the bonding metal piece is arranged inside the insulating passivation layer, the upper part of the insulating passivation layer has an opening, the outer part of the insulating passivation layer is wrapped with a common cathode layer, the pixel body is electrically connected to the common cathode layer through the opening, and the common cathode layer is electrically connected to the cathode contact.

8. The multi-layer microdisplay chip of claim 7, wherein: The pixel body comprises a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged in sequence along the Z direction, the P-type semiconductor layer is provided with the bonding metal piece close to one side of the driving wafer, and the N-type semiconductor layer is electrically connected through the opening and the common cathode layer.

9. The multi-layer microdisplay chip of claim 7, wherein: A cathode hole is arranged on the interface between two adjacent pixel layers, the cathode hole is filled with a cathode connecting piece, and the cathode connecting piece is electrically connected with a cathode contact.

10. The multi-layer microdisplay chip of claim 7, wherein: The spacing between the top surface of the insulating body of each pixel layer and the common cathode layer on the top of the sub-pixel of the layer is not less than 100 nm.

11. The multi-layer microdisplay chip of claim 10, wherein: The thickness of the common cathode layer is 50 nm to 500 nm.

12. The multi-layer microdisplay chip of claim 1, wherein: The pixel body is in the shape of a trapezoid or a cylinder.

13. The multi-layer microdisplay chip of claim 1, wherein: The light-emitting colors of the sub-pixels in each pixel layer are the same.

14. The multi-layer microdisplay chip of claim 1, wherein: The light-emitting colors of each sub-pixel in the same pixel layer are the same, and the light-emitting colors of the sub-pixels in two adjacent pixel layers are different.

15. The multi-layer microdisplay chip of claim 14, wherein: The projections of all the sub-pixels on the driving wafer do not coincide.

16. The multi-layer microdisplay chip of claim 1, wherein: The upper part of the pixel layer at the top is connected with at least one lens, each sub-pixel corresponds to one lens, or a plurality of sub-pixels correspond to one lens.

17. The multi-layer microdisplay chip of claim 1, wherein: The pixel layer at the top is connected with at least one lens, each sub-pixel corresponds to one lens, or a plurality of sub-pixels correspond to one lens.

18. The multi-layer microdisplay chip of claim 17, wherein: The color conversion piece and the sub-pixel with a different light-emitting color from the color conversion piece are arranged in the upper pixel layer, and the corresponding excitation pixel is arranged in the lower pixel layer.

19. The multi-layer microdisplay chip of claim 18, wherein, The light-emitting color of the color conversion piece is red, and the light-emitting color of the excitation pixel is blue.

20. The multi-layer microdisplay chip of claim 17, wherein, The pixel layer where the excitation pixel is located also has sub-pixels, the light-emitting color of the sub-pixel in the pixel layer where the excitation pixel is located is blue, and the light-emitting color of the sub-pixel in the pixel layer where the color conversion piece is located is green.

21. The multi-layer microdisplay chip of claim 20, wherein, The pixel layer where the color conversion piece is located is provided with a filling hole, and the filling hole is filled with the color conversion piece.

22. The multi-layer microdisplay chip of claim 20, wherein, The length of the filling hole along the X direction is not less than the maximum length of the excitation pixel in the X direction, and the X direction is perpendicular to the Z direction.

23. The multi-layer microdisplay chip of claim 17, wherein, An isolation layer is formed on the inner wall of the filling hole, and the isolation layer is a metal reflection layer or a light-absorbing layer.

24. The method of claim 1-23, wherein: The upper part of the pixel layer at the top is connected with at least one lens, the sub-pixel and the color conversion piece each correspond to a different lens, or all the sub-pixels and the color conversion piece correspond to one lens. The pixel layer at the top is connected with at least one lens, each sub-pixel corresponds to one lens, or a plurality of sub-pixels correspond to one lens. Step M1, preparing a driving wafer provided with an anode contact; Step M2, sequentially stack at least two pixel layers along the Z direction on the driving wafer, at least one of the pixel layers is provided with a sub-pixel, the sub-pixel comprises a pixel body, each pixel body is provided with a bonding metal piece near one side of the driving wafer, the bonding metal piece of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact by the anode connecting piece passing through the lower pixel layer, the bonding metal piece of the sub-pixel in the upper pixel layer has a first contact surface for contacting the anode connecting piece, the first contact surface is a non-flat surface, the first contact surface is embedded in the pixel layer where the anode connecting piece is located and contacts the anode connecting piece, or the anode connecting piece is embedded in the first contact surface.

25. The method of claim 24, wherein: When the pixel layer is prepared, an anode hole corresponding to the anode connecting piece is formed on the interface between two adjacent pixel layers, and the anode connecting piece is filled in the anode hole, the top surface of the anode connecting piece filled in the anode hole is lower than the interface to form a recess, and the first contact surface is formed with an embedded protrusion, so that the embedded protrusion of the sub-pixel in the pixel layer is embedded in the recess of the corresponding anode hole of the lower adjacent pixel layer to be in electrical contact with the anode connecting piece; or, so that the top surface of the anode connecting piece filled in the anode hole is higher than the interface to form a protrusion, the first contact surface is formed with an embedded recess, and the embedded recess of the sub-pixel in the pixel layer is embedded in the protrusion of the corresponding anode connecting piece of the lower adjacent pixel layer.

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