Semiconductor structure

Abstract

According to the invention, a semiconductor structure (1) comprises: - a substrate (2) comprising - a first surface (4), - a second surface (6), opposite to the first surface (4), - at least one through-substrate via (8) in the first surface (4), and - at least one through-substrate via (10) in the second surface (6), and - wherein the at least one through-substrate via (8) in first surface (4) and the at least one through-substrate via (10) in the second surface (6) are arranged on top of each other. Furthermore, a corresponding method for manufacturing a semi-conductor structure is disclosed.

Description

[0001] 2024PF00157

[0002] SEMICONDUCTOR STRUCTURE

[0003] DESCRIPTION

[0004] TECHNICAL FIELD

[0005] The present invention relates to a semiconductor structure and a method for manufacturing a semiconductor structure .

[0006] BACKGROUND

[0007] Through-substrate vias , often abbreviated as TSVs , are vertical electrical connections that pass entirely through e . g . a silicon wafer or die . With this , stacking circuits can be built on top of each other in 3D for a broad range of applications and performance improvements .

[0008] In the context of through-substrate vias ( TSVs ) , opting for smaller diameters yields several benefits . It enables more efficient utili zation of layout space , contributing to overall compactness in microelectronic devices . Reduced through-substrate via dimensions minimi ze the required clear area around them ( known as the keep-out zone or KOZ ) , allowing for denser packing of components .

[0009] Thus , choosing smaller through-substrate via diameters enhances integration ef ficiency and optimi zes space utili zation within 3D semiconductor packaging .

[0010] The aspect ratio of a through-substrate via refers to the proportion between its depth and diameter . The through-substrate via depth is the length of the via, extending traditionally from the top surface of the silicon wafer to the bottom . It represents how far the through-substrate via penetrates through the substrate . The through-substrate via diameter is the width of the through-substrate via opening at the top 2024PF00157 surface . It determines the cross-sectional area available for electrical or thermal conduction .

[0011] In practical terms , a higher aspect ratio means a longer, narrower through-substrate via . Large aspect ratios are desirable for certain applications , as they allow more ef ficient use of space within the silicon substrate , but they also pose challenges during fabrication .

[0012] Fabricating smaller through-substrate vias demands exceptional precision . The lithography, etching, and deposition processes must operate at sub-micron scales to achieve the desired dimensions . Any deviation can impact through-substrate via performance .

[0013] Furthermore , achieving uni form through-substrate vias across an entire wafer becomes increasingly complex with smaller diameters . Variations in etching rates , material properties , and mask alignment can lead to non-uni form through-substrate via depths and diameters . Yet , uni formity is critical for consistent electrical and thermal performance .

[0014] Also , smaller through-substrate vias require smoother sidewalls . Rough surfaces can trap voids or impurities during the filling process , af fecting electrical conductivity and thermal dissipation . Techniques like chemical mechanical polishing ( CMP ) are employed to enhance inner wall smoothness .

[0015] As diameters shrink, ensuring void- free filling becomes challenging . Void formation can lead to reliability issues , such as electromigration or thermal hotspots .

[0016] And last , but not least : The aspect ratio between through-substrate via diameter and through-substrate via depth has a limit , as with a given device thickness of the wafer, there is a limited through-substrate via diameter . 2024PF00157

[0017] SUMMARY

[0018] The obj ect of the present invention is therefore to provide a semiconductor structure and a method for manufacturing the same , which solve the above addressed problems and present a solution in which the density of through-substrate vias can be higher on a given wafer thickness , i . e . the through-substrate via diameter can be reduced without changing the aspect ratio of the wafer thickness , while the manufacturing poses less challenges .

[0019] According to the invention, the obj ect is met by a device speci fied in claim 1 and by a method with the steps speci fied in claim 15 .

[0020] Therefore , a semiconductor structure is proposed by the invention, comprising :

[0021] A semiconductor structure , comprising

[0022] - a substrate comprising

[0023] - a first surface ,

[0024] - a second surface , opposite to the first surface ,

[0025] - at least one through-substrate via in the first surface , and

[0026] - at least one through-substrate via in the second surface , and

[0027] - wherein the at least one through-substrate via in first surface and the at least one through-substrate via in the second surface are arranged on top of each other .

[0028] With this , the through-substrate via diameter can be reduced . This reduction has two direct consequences . First , the decrease in through-substrate via diameter results in a corresponding reduction in through-substrate via volume . This volume reduction is beneficial during the temporary bonding process as it minimi zes the risk of void formation, thereby improving the reliability of the process . 2024PF00157

[0029] Second, the reduced through-substrate via diameter can be achieved without altering the substrate thickness . This allows for a smaller through-substrate via diameter with the same substrate thickness .

[0030] Furthermore , the bottom of the through-silicon via ( TSV) is no longer positioned at the substrate surface . This modi fication provides mechanical damage protection to the through-substrate via .

[0031] Finally, given the substrate thickness , the smallest possible through-substrate via diameter achievable with the current aspect ratio can be further reduced with the innovation .

[0032] In an embodiment of the invention, the at least one through- substrate via in the first surface may have a smaller diameter than the at least one through-substrate via in the second surface .

[0033] With this , when the through-substrate via ( TSV) in the second surface has a larger diameter than the through-substrate via in the first surface , the larger through-substrate via serves as a receptive landing space for the smaller through-substrate via . This arrangement ensures ef ficient vertical communication between di f ferent layers of the semiconductor device , optimi zing both space utili zation and interconnect ef ficiency .

[0034] The through-substrate via diameter is the width of the through-substrate via opening at the surface . It determines the cross-sectional area available for electrical or thermal conduction .

[0035] Moreover, the diameter of the at least one through-substrate via in the first surface and the diameter of the at least one through-substrate via in the second surface may be in a ratio of 1 : 2 to 2 : 3 to each other .

[0036] With this ratio , through-substrate vias facilitate ef ficient data trans fer between di f ferent layers of the chip . 2024PF00157

[0037] Moreover, these dimensions contribute to increased integration density . Within a limited chip area, more components— such as memory cells , logic gates , or sensors— can be accommodated, leading to powerful and compact devices .

[0038] Furthermore , the depth between the first and the second surfaces of the at least one through-substrate via in the first surface and the depth between the first and the second surfaces of the at least one through-substrate via in the second surface , each measured from the respective surface towards the interior of the substrate , may be in a ratio of 1 : 1 to 1 : 2 to each other .

[0039] This innovation enables a reduction in the diameter of the through-substrate via .

[0040] Given a speci fic substrate thickness , this advancement allows for a further decrease in the smallest possible diameter of the through-substrate via achievable with the current aspect ratio .

[0041] Moreover, a ratio of length to diameter of the at least one through-substrate via in the second surface and / or a ratio of length to diameter of the at least one through-substrate via in the first surface may be between 2 , 5 and 5 .

[0042] In the context of through-substrate vias ( TSVs ) , the aspect ratio is defined as the quotient of the height to the diameter of the via .

[0043] When the aspect ratio is between 2 , 5 and 5 , the diameter and the length of the through-substrate via are in a ratio , where the performance of the semiconductor structure is enhanced .

[0044] In a further advantageous embodiment of the invention, wherein the diameter of the at least one through-substrate via in the second surface may be 80pm or less and / or the diameter of the at least one through-substrate via in the first surface may be 2024PF00157

[0045] 40pm or less , wherein the substrate may have an extension between the first and the second surface of at least 200pm .

[0046] Given the thickness of the through-substrate via ( TSV) , achieving smaller diameters results in decreased parasitic resistance and capacitance . Consequently, the parasitic RC delay is minimi zed, enhancing signal propagation speed within the stacked device .

[0047] In a further embodiment of the invention, the at least one through-substrate via in the first surface and the at least one through-substrate via in the second surface may be arranged so that the bottom of the at least one through-substrate via in the first surface is contacting the bottom of the at least one through-substrate via in the second surface for establishing an electrical connection between the at least one through-substrate via in the first surface and the at least one through-substrate via in the second surface .

[0048] Through-substrate vias ( TSVs ) directly connecting the top and bottom surfaces minimi ze line length and reduce parasitic impedance .

[0049] Through the formation of a conducting through-substrate via membrane in the e . g . center of the substrate , an electrical conducting pathway is formed from the first surface to the second surface .

[0050] Additionally, through-substrate vias enhance electrical performance by ef ficiently linking di f ferent layers vertically, leading to improved signal integrity and reduced power and ground bounce .

[0051] The bottom of a through-substrate via is here the part or plane of the through-substrate via which is the furthest from the surface , in which it is embedded or etched .

[0052] Moreover, the at least one through-substrate via in the first surface and the at least one through-substrate via in the 2024PF00157 second surface may comprise two passivation layers respectively, wherein the respective passivation layer, which is arranged further from a through-substrate via' s contact surface with the substrate , may be thicker than the respective other passivation layer, which is nearer to the through-substrate via' s contact surface with the substrate .

[0053] By incorporating two passivation layers , through-substrate vias ( TSVs ) exhibit reduced chemical reactivity . This design choice enhances their resilience against environmental factors , ensuring robust performance over time .

[0054] The dual passivation layers act as protective barriers , shielding the through-substrate vias from corrosive agents , moisture , and other potentially damaging elements .

[0055] In a further embodiment of the invention, the at least one through-substrate via in the first surface and the at least one through-substrate via in the second surface may each comprise a recess in the passivation layer, which is nearer to the respective through-substrate via' s contact surface with the substrate , arranged at the bottom of the respective through-substrate via .

[0056] The term " recess in the passivation layer" as used herein refers to a locali zed depression or thinning region in the passivation layer at or near the bottom of the through-substrate via cavity .

[0057] The strategically designed recess within the passivation layer of a through-substrate via ( TSV) serves as a conduit for seamless coupling between neighboring through-substrate vias .

[0058] By enabling direct signal transmission from one through-substrate via to another, this architectural feature enhances interconnectivity within stacked devices .

[0059] In an embodiment of the invention, a layer of the at least one through-substrate via in the first surface and / or a layer of 2024PF00157 the at least one through-substrate via in the second surface may comprise titanium nitride .

[0060] A TiN layer acts as a robust barrier, preventing material di ffusion between the through-substrate via and the surrounding substrate .

[0061] Moreover, TiN promotes strong adhesion between the through- substrate via and the substrate , reducing the risk of delamination or detachment during processing or operation .

[0062] Furthermore , TiN mitigates electromigration ef fects , preventing material migration within the through-substrate via and maintaining long-term stability .

[0063] Moreover, wherein a layer of the at least one through-substrate via in the first surface and / or a layer of the at least one through-substrate via in the second surface may comprise tungsten .

[0064] Tungsten has an extraordinarily good conformality of Chemical Vapor Deposition ( CVD) from WF61 . This means that it can evenly coat the walls of high aspect ratio through-substrate vias , ensuring a uni form conductive layer throughout the via .

[0065] Furthermore , tungsten has a high melting point , which means it can withstand the high temperatures often encountered during semiconductor processing .

[0066] Despite its high resistance , tungsten is still a good conductor of electricity . This makes it suitable for use in TSVs , which need to conduct electrical signals between di f ferent layers of the semiconductor .

[0067] In an embodiment of the invention, the second surface may comprise a redistribution layer .

[0068] A redistribution layer (RDL ) is an additional metal layer on a semiconductor structure . It relocates its I / O pads to 2024PF00157 di f ferent parts of the semiconductor structure for easier access . This wiring layer facilitates bonding from various semiconductor structure locations .

[0069] RDL also serves another purpose - it disperses the contact points across the die , allowing for the application of solder balls and distributing the thermal stress of mounting . The RDL is typically composed of polyamide , benzocyclobutene (BCB ) , or polybenzoxazole ( PBO) , with a surface plating of copper .

[0070] In terms of electrical connectivity, RDLs serve as copper metal interconnects that link di f ferent parts of the semiconductor package .

[0071] Thus , the RDL allows for flexible routing of interconnections , which can be particularly beneficial when integrating multiple di f ferent semiconductor structures .

[0072] An RDL also enables high-density integration and allows for the decoupling of front-end and back-end processing, which can lead to cost-ef fective manufacturing and faster time-to-market .

[0073] Furthermore , the substrate may comprise silicon .

[0074] Due to its abundance and established manufacturing processes , silicon substrates are cost-ef fective .

[0075] Furthermore , silicon substrates are engineered with precise speci fications regarding dimensions , surface quality, and electrical properties to meet the requirements of various semiconductor manufacturing processes .

[0076] Moreover, silicon has a stable crystal structure that is ideal for semiconductor devices . Moreover, silicon can easily form silicon dioxide , which is a very good insulator and is useful in the manufacturing process . 2024PF00157

[0077] The electronic properties of the silicon substrate itsel f are crucial in determining the ultimate performance capabilities of devices made on top and, lastly, Silicon is the second most abundant element , making it readily available .

[0078] Moreover, the invention proposes a semiconductor chip with a semiconductor structure as disclosed .

[0079] Moreover, the invention proposes a method for manufacturing a semiconductor structure comprising the steps of :

[0080] - providing a substrate comprising

[0081] - a first surface ,

[0082] - a second surface , opposite to the first surface ,

[0083] - etching a cavity in the second surface

[0084] - depositing at least a passivation layer, a titanium nitride layer, a tungsten layer and another passivation layer in the cavity in the second surface ,

[0085] - etching a cavity, on top of cavity in the second surface , in the first surface ,

[0086] - depositing at least a passivation layer, a titanium nitride layer, a tungsten layer and another passivation layer in the cavity in the first surface .

[0087] What has been said with respect to the device may analogously be applied to the method and therefore need not be repeated there .

[0088] Method embodiments and details have a counterpart in the device and vice versa .

[0089] It shall be noted that the steps given above do not necessarily have to be carried out in the given order . The provided steps may be carried out in any other suitable order or even some or all of them at the same time .

[0090] BRIEF DESCRIPTION OF THE DRAWINGS 2024PF00157

[0091] In the following, the invention will be described in further detail with reference to the accompanying drawings, wherein:

[0092] FIG. 1 depicts an embodiment of the semiconductor structure in a sectional view, and

[0093] FIG. 2 depicts a manufacturing step of a semiconductor structure according to the invention, and

[0094] FIG. 3 depicts a further manufacturing step of a semiconductor structure according to the invention.

[0095] Identical parts are labelled by the same reference signs.

[0096] DETAILED DESCRIPTION

[0097] In FIG. 1 an embodiment of the present invention is shown. In this embodiment, a semiconductor structure is depicted generally with the reference sign 1.

[0098] This semiconductor structure 1 comprises a substrate 2 comprising a first surface 4 and a second surface 6, which is opposite to the first surface 4.

[0099] The substrate 2 can be composed of various materials depending on the specific application and requirements. The substrate 2 can e.g. be made of a semiconductor material like silicon (Si) , germanium (Ge) , or gallium arsenide (GaAs) . Silicon is the most used material due to its semiconductor properties and abundance. However, other materials like gallium arsenide are used for specialized applications where higher electron mobility or direct bandgap are required.

[0100] In some cases, the substrate 2 may be composed of a compound semiconductor material or a silicon-on-insulator (SOI) structure for specific device applications. 2024PF00157

[0101] At least one through-substrate via 8 is arranged in the first surface 4 and at least one through-substrate via 10 is arranged in the second surface 6 .

[0102] The through-substrate vias 8 , 10 are vertical electrical connections that pass through the substrate 2 . The use of through-substrate vias allows for three-dimensional integration of components , thereby reducing the footprint of the device and improving performance by shortening the interconnect lengths .

[0103] The through-substrate vias 8 , 10 are arranged in cavities 12 , 14 in the first surface 4 and the second surface 6 , respectively . The through-substrate vias 8 , 10 line the cavities 12 , 14 .

[0104] The through-substrate via 8 and the through-substrate via 10 are arranged on top of each other, so that the bottom 16 of the through-substrate via 8 and the bottom 18 of the through- substrate via 10 are contacting each other .

[0105] The at least one through-substrate via 8 in the first surface 4 and the at least one through-substrate via 8 in the second surface 6 comprise a recess in the passivation layer, which is nearer to the surface of the through-substrate via' s cavity, arranged at the bottom of the cavity to facilitate the contacting and further a connecting of the two through-substrate vias 8 , 10 .

[0106] The term " recess in the passivation layer" as used herein refers to a locali zed depression or thinning region in the passivation layer at or near the bottom of the through-substrate via cavity .

[0107] The depth of the through-substrate vias 8 in the first surface 4 and the depth of the through-substrate via 8 in the second surface 6 can be in a ratio of 1 : 1 to 1 : 2 to each other . 2024PF00157

[0108] The depth is in this case the extent between the first and the second surfaces 4 , 6 of the at least one through-substrate via 8 in the first surface 4 and the extent between the first and the second surfaces 4 , 6 of the at least one through-substrate via 8 in the second surface 6 , each measured from the respective surface towards the interior of the substrate 2 . This is , the depth refers to the distance between the first surface 4 and the second surface 6 along the at least one through-substrate via 8 , measured from the first surface 4 to the second surface 6 , and likewise from the second surface 6 to the first surface 4 . Thus , In the context of this application, the term ' depth ' refers to the distance from the respective surface 4 or 6 of the substrate 2 to the bottom of the corresponding through-substrate via 8 or 10 .

[0109] Furthermore , there are several layers , e . g . four layers in this embodiment in each through-substrate via 8 , 10 :

[0110] A passivation layer 26 , which is a protective coating, is applied on the surface of the cavity 12 , 14 . It can comprise silicon nitride or silicon dioxide .

[0111] Titanium nitride ( TiN) is comprised in another layer 24 , serving as a further barrier between a tungsten conductor and the substrate . The TiN layer helps manage mechanical stress , reducing the risk of delamination or line failure .

[0112] A further layer 22 is a conducting layer of conductive material , usually metal , that is deposited over the layer 24 . It provides a surface for connecting the through-substrate via 8 , 10 to other components . This layer 22 can comprise tungsten or other suitable conductive material .

[0113] A further passivation layer 20 is applied over the layer 22 for additional protection . This passivation layer, which is arranged further from the surface of the cavity, is thicker than the other passivation layer . 2024PF00157

[0114] The through-substrate vias 8, 10 can be through-silicon vias. The use of a through-silicon via allows for vertical interconnections between different layers of silicon of the semiconductor structure 1. This can significantly enhance the device's performance by reducing the length of interconnections, thereby minimizing signal delay and power consumption. In this case, the substrate 2 comprises silicon.

[0115] On the second surface 6, a Complementary Metal-Oxide-Semicon- ductor (CMOS) 28 is comprised with a redistribution layer (RDL) , passivation and contact to the through-substrate via 10 and a fusion bonded handling wafer 32 is arranged on top of the CMOS 28. On the first surface 4 a RDL layer 30 with a passivation is arranged.

[0116] RDL is a layer of fine wiring metal interconnects within an integrated circuit (IC) package. Its primary purpose is to redistribute input / output (I / O) connections from one part of the chip to another.

[0117] Complementary Metal-Oxide-Semiconductor (CMOS) is a fabrication process for integrated circuits (ICs) that utilizes complementary pairs of p-type and n-type metal-oxide-semiconduc- tor field-effect transistors (MOSFETs) . These MOSFETs work together to perform logic functions.

[0118] The through-substrate via 8 has a smaller diameter than the through-substrate via 10 and the diameter of the at least one through-substrate via 8 and the diameter of the at least one through-substrate via 10 can e.g. be in a ratio of 1:2 to 2:3 to each other.

[0119] Moreover, a ratio of length to diameter of the at least one through-substrate via 10 in the second surface 6 and / or a ratio of length to diameter of the at least one through-substrate via 8 in the first surface 4 is between 2,5 and 5.

[0120] Furthermore, the diameter of the at least one through-substrate via 10 in the second surface 6 is 80pm or less with the 2024PF00157 substrate having an extension between the first and the second surface 4 , 6 of at least 200pm and the diameter of the at least one through-substrate via 8 in the first surface 4 is 40pm or less with the substrate having an extension between the first and the second surface 4 , 6 of at least 200pm .

[0121] Moreover, the at least one through-substrate via 8 in the first surface 4 and the at least one through-substrate via 10 in the second surface 6 may each comprise a recess 34 in the passivation layer 26 , which is nearer to the respective through-substrate via' s contact surface with the substrate 2 , arranged at the bottom 16 , 18 of the respective through-substrate via 8 , 10 .

[0122] The strategically designed recess 34 within the passivation layer 26 of the through-substrate via 8 , 10 serves as a conduit for seamless coupling between neighboring through-substrate vias .

[0123] By enabling direct signal transmission from one through-substrate via to another, this architectural feature enhances interconnectivity within stacked devices .

[0124] Lastly, to manufacture a semiconductor structure 1 , the following steps should be performed :

[0125] In the initial step, the through-substrate via 10 with the larger diameter undergoes etching to create a controlled-depth cavity 14 within the substrate 2 . Following this etching process , standard deposition procedures are employed . A protective passivation layer 26 is deposited to prevent further etching and safeguard the sidewalls of the cavity 14 . Next , a thin layer of titanium nitride ( TiN) 24 enhances adhesion and conductivity . Subsequently, a conducting metal layer 22 ( such as tungsten, W) is added to establish electrical connectivity . Finally, a thick passivation layer 20 encapsulates the through-substrate via 10 , shielding it from external influences . 2024PF00157

[0126] For the second through-substrate via 8 , the wafer is flipped to process the etch from the opposite side , the first surface 4 . This step targets the through-substrate via 8 with the smaller diameter, repeating the through-substrate via etch process to create a cavity 12 on the other side of the substrate 2 .

[0127] List of abbreviations :

[0128] 2024PF00157

[0129] LIST OF REFERENCE SIGNS Semiconductor structure 1

[0130] Substrate 2

[0131] First surface 4

[0132] Second surface 6

[0133] Through-substrate via (TSV, in the first surface) 8 Through-substrate via (TSV, in the second surface) 10

[0134] Cavity (in the first surface) 12

[0135] Cavity (in the second surface) 14

[0136] Bottom (of TSV (in the first surface) ) 16

[0137] Bottom (of TSV (in the second surface) ) 18 Passivation layer 20

[0138] Tungsten layer 22

[0139] TiN layer 24

[0140] Passivation layer 26

[0141] Complementary Metal-Oxide-Semiconductor (CMOS) layer 28 RDL layer 30

[0142] Fusion bonded handling layer 32

[0143] Recess 34

Claims

2024PF00157CLAIMS1. A semiconductor structure (1) , comprising:- a substrate (2) comprising-a first surface (4) , -a second surface (6) , opposite to the first surface ( 4 ) ,- at least one through-substrate via (8) in the first surface ( 4 ) , and- at least one through-substrate via (10) in the second surface ( 6 ) , and- wherein the at least one through-substrate via (8) in first surface (4) and the at least one through-substrate via (10) in the second surface (6) are arranged on top of each other.

2. A semiconductor structure (1) according to claim 1, wherein the at least one through-substrate via (8) in the first surface (4) has a smaller diameter than the at least one through-substrate via (10) in the second surface (6) .

3. A semiconductor structure (1) according to any one of the preceding claims, wherein the diameter of the at least one through-substrate via (8) in the first surface (4) and the diameter of the at least one through-substrate via (10) in the second surface (6) are in a ratio of 1:2 to 2:3 to each other.

4. A semiconductor structure (1) according to any one of the preceding claims, wherein the depth between the first and the second surfaces (4, 6) of the at least one through-substrate via (8) in the first surface (4) and the depth between the first and the second surfaces (4, 6) of the at least one through-substrate via (10) in the second surface (6) , each measured from the respective surface towards the interior of the substrate (2) , are in a ratio of 1:1 to 1:2 to each other.2024PF001575. A semiconductor structure (1) according to any one of the preceding claims, wherein a ratio of length to diameter of the at least one through-substrate via (10) in the second surface (6) and / or a ratio of length to diameter of the at least one through- substrate via (8) in the first surface (4) is between 2,5 and 5.

6. A semiconductor structure (1) according to any one of the preceding claims, wherein the diameter of the at least one through-substrate via (10) in the second surface (6) is 80pm or less and / or the diameter of the at least one through-substrate via (8) in the first surface (4) is 40pm or less, wherein the substrate (2) has an extension between the first (4) and the second surface (6) of at least 200pm.

7. A semiconductor structure (1) according to any one of the preceding claims, wherein the at least one through-substrate via (8) in the first surface (4) and the at least one through-substrate via (10) in the second surface (6) are arranged so that the bottom (16) of the at least one through-substrate via (8) in the first surface (4) is contacting the bottom (18) of the at least one through-substrate via (10) in the second surface (6) for establishing an electrical connection between the at least one through-substrate via (8) in the first surface (4) and the at least one through-substrate via (10) in the second surface (6) .

8. A semiconductor structure (1) according to any one of the preceding claims, wherein the at least one through-substrate via (8) in the first surface (4) and the at least one through-substrate via (10) in the second surface (6) comprise two passivation layers (20, 26) respectively, wherein the respective passivation layer (20) , which is arranged further from a through-substrate via' s contact2024PF00157 surface with the substrate (2) , is thicker than the respective other passivation layer (26) , which is nearer to the through-substrate via' s contact surface with the substrate (2) .

9. A semiconductor structure (1) according to claim 8, wherein the at least one through-substrate via (8) in the first surface (4) and the at least one through-substrate via (10) in the second surface (6) each comprise a recess (34) in the passivation layer (26) , which is nearer to the respective through-substrate via' s contact surface with the substrate (2) , arranged at the bottom (16, 18) of the respective through-substrate via (8, 10) .

10. A semiconductor structure (1) according to any one of the preceding claims, wherein a layer (24) of the at least one through-substrate via (8) in the first surface (4) and / or a layer (24) of the at least one through-substrate via (10) in the second surface (6) comprises titanium nitride.

11. A semiconductor structure (1) according to any one of the preceding claims, wherein a layer (22) of the at least one through-substrate via (8) in the first surface (4) and / or a layer (22) of the at least one through-substrate via (10) in the second surface (6) comprises tungsten.

12. A semiconductor structure (1) according to any one of the preceding claims, wherein the first surface (4) comprises a redistribution layer ( 30 ) .

13. A semiconductor structure (1) according to any one of the preceding claims, wherein the substrate (2) comprises silicon.

14. Semiconductor chip with a semiconductor structure (1) according to any one of claims 1 to 13.2024PF0015715. A method for manufacturing a semiconductor structure (1) , comprising the steps of:- providing a substrate (2) comprising -a first surface (4) ,-a second surface (6) , opposite to the first surface ( 4 ) ,- etching a cavity (14) in the second surface (6) ,- depositing at least a passivation layer (26) , a tita- nium nitride layer (24) , a tungsten layer (22) and another passivation (20) layer in the cavity (14) in the second surface (6) , etching a cavity (12) , on top of cavity (14) in the second surface (6) , in the first surface (4) , - depositing at least a passivation layer (26) , a titanium nitride layer (24) , a tungsten layer (22) and another passivation (20) layer in the cavity (12) in the first surface (4) .

Images