Capacitor and communication device

Abstract

A capacitor according to the present disclosure includes a first unit and a second unit. The capacitor comprises: a multilayer body in which a plurality of internal electrode layers and a plurality of dielectric body layers are layered in a first direction; and a plurality of external electrodes that are positioned on a first main surface and a second main surface of the multilayer body, which face each other in a second direction intersecting with the first direction. The first unit has a first external electrode and a second external electrode positioned on the first main surface. The second unit is positioned neighboring the first unit in the first direction, and has a third external electrode positioned on the first main surface. If a direction intersecting with the first direction and the second direction is defined as a third direction, the position of the third external electrode in the third direction is, when viewed from the first direction, between the positions of the first external electrode and the second external electrode in the third direction.

Description

Capacitors and communication devices

[0001] The present disclosure relates to a capacitor and a communication device.

[0002] Conventionally, multilayer capacitors described in Patent Documents 1 and 2 are known.

[0003] JP 2004-140183 A JP 2023-093670 A

[0004] a first unit configured to stack a first internal electrode layer and a second internal electrode layer on the first main surface of the laminate, the first unit including a first internal electrode layer and a second internal electrode layer, the first internal electrode layer and the second internal electrode layer having a first lead portion that is extended to the first main surface and connected to the first external electrode; a second unit configured to stack a second internal electrode layer and the second internal electrode layer on the first main surface of the laminate, the first unit including a first internal electrode layer and a second internal electrode layer, the first internal electrode layer and the second internal electrode layer having a second lead portion that is extended to the first main surface and connected to the second external electrode; a second unit configured to stack a third internal electrode layer and a fourth internal electrode layer on the first main surface of the laminate, the second unit including a third external electrode layer and a fourth internal electrode layer, the second unit including a third external electrode layer and a fourth internal electrode layer, the second unit including a third external electrode layer and a fourth internal electrode layer, the The third internal electrode layer has a third extension portion that is extended to the first main surface and connected to the third external electrode, and if a direction that intersects the first direction and the second direction is defined as a third direction, when viewed from the first direction, the position of the third external electrode in the third direction is between the position of the first external electrode in the third direction and the position of the second external electrode in the third direction.

[0005] A communication device according to an embodiment of the present disclosure includes a printed wiring board, an IC component, and a package substrate, and the package substrate has the above-described capacitor therein.

[0006] Objects, features, and advantages of the present disclosure will become more apparent from the following detailed description and drawings. A schematic diagram of a capacitor according to an embodiment of the present disclosure. A schematic diagram of a first unit of a capacitor according to an embodiment of the present disclosure, seen through. A schematic diagram of an internal electrode layer of the first unit of FIG. 2A. A schematic diagram of a cross section taken along the section line IIC-IIC of FIG. 2A. A schematic diagram of a second unit of a capacitor according to an embodiment of the present disclosure, seen through. A schematic diagram of an internal electrode layer of the second unit of FIG. 3A. A schematic diagram of a cross section taken along the section line IIIC-IIIC of FIG. 3A. A schematic diagram of a third unit of a capacitor according to an embodiment of the present disclosure, seen through. A schematic diagram of an internal electrode layer of the third unit of FIG. 4A. A schematic diagram of a cross section taken along the section line IVC-IVC of FIG. 4A. A plan view of a capacitor according to an embodiment of the present disclosure. A schematic diagram of a capacitor according to another embodiment of the present disclosure. A schematic diagram of a first unit of a capacitor according to another embodiment of the present disclosure. A schematic diagram of a second unit of a capacitor according to another embodiment of the present disclosure, seen through. 1 is a schematic diagram of a communication device as an example of use of an embodiment of the present disclosure.

[0007] In recent years, capacitors mounted in electronic devices are required to have low equivalent series inductance (ESL).

[0008] Patent Document 1 discloses that in a multilayer capacitor in which dielectric layers and internal electrodes are laminated and the internal electrodes are positioned in a direction perpendicular to the mounting surface, a multilayer capacitor with low ESL can be provided by setting the internal electrodes and their lead electrodes to satisfy a predetermined relational expression. Also, Patent Document 2 discloses a multilayer capacitor that can be applied to high-speed, high-density integrated circuits.

[0009] There is a demand for a capacitor that has a large capacitance per unit volume while reducing the ESL.

[0010] Hereinafter, with reference to the drawings, a capacitor 10 according to one embodiment of the present disclosure and a communication device 1000 including the capacitor 10 will be described. Note that, although a multilayer ceramic capacitor will be described below as an example of the capacitor 10, the capacitor 10 to which the present disclosure is directed is not limited to a multilayer ceramic capacitor and can be applied to various multilayer electronic components such as a multilayer piezoelectric element, a multilayer film capacitor, a multilayer thermistor element, and a multilayer chip coil.

[0011] The drawings used in the following description are schematic, and the dimensional ratios and the like in the drawings do not necessarily correspond to the actual ones. Furthermore, the embodiments described in this specification are merely illustrative, and different embodiments and modified examples may be partially substituted for each other. Furthermore, different embodiments and modified examples may be partially combined with each other.

[0012] For convenience, the drawings may be accompanied by an orthogonal coordinate system consisting of a first direction, a second direction, and a third direction. The first direction is the stacking direction of multiple internal electrode layers and multiple dielectric layers, which will be described later. The direction intersecting with the first direction is defined as the second direction. The direction intersecting with the first and second directions is defined as the third direction. Note that "intersecting" may mean intersecting at any angle, for example, being approximately perpendicular. "Approximately perpendicular" does not necessarily mean being exactly perpendicular, and it is sufficient if it can be recognized as being approximately perpendicular.

[0013] Capacitor 10 has a roughly rectangular parallelepiped shape and has six faces. The faces located at the front and back of capacitor 10 in the first direction are defined as side surface S1 and side surface S2. The faces located at the top and bottom of capacitor 10 in the second direction are defined as main surface M1 and main surface M2. The faces located at the left and right of capacitor 10 in the third direction are defined as end surface E1 and end surface E2.

[0014] In the present disclosure, as an example, the side surfaces S1 and S2 are perpendicular to a first direction, the main surfaces M1 and M2 are perpendicular to a second direction, and the end surfaces E1 and E2 are perpendicular to a third direction. The definitions of the main surfaces M1 and M2, the side surfaces S1 and S2, and the end surfaces E1 and E2 can be similarly defined in the laminate units (described later) that constitute capacitor 10.

[0015] FIG. 1 is a schematic diagram of a capacitor 10 according to one embodiment of the present disclosure. As shown in FIG. 1 , the capacitor 10 includes a laminate formed by stacking multiple internal electrode layers and multiple dielectric layers in a first direction, and multiple external electrodes located on the surface of the laminate. The capacitor 10 also includes a cover portion 6 on both sides of the laminate in the first direction. Hereinafter, with respect to the capacitor 10, the multiple internal electrode layers may be collectively referred to as internal electrode layers IE, the multiple dielectric layers may be collectively referred to as dielectric layers D, and the multiple external electrodes may be collectively referred to as external electrodes EE.

[0016] Capacitor 10 has a plurality of units including a first unit 1, a second unit 2, a third unit 3, a fourth unit 4, and a fifth unit 5. The plurality of units are arranged in the first direction in the order of first to fifth. For example, second unit 2 is located next to first unit 1 in the first direction. For example, third unit 3 is located next to second unit 2 in the first direction, and is located on the opposite side of first unit 1.

[0017] Although the capacitor 10 of the present disclosure has five units, the number of units is not limited to this example and may be more or less than five.

[0018] The first unit 1 has internal electrode layers 11 and 12. The internal electrode layers 11 and 12 are alternately stacked in a first direction with a dielectric layer 13 sandwiched therebetween. The first unit 1 also has external electrodes 101 and 102 located on a main surface M1, and external electrodes 103 and 104 located on a main surface M2.

[0019] 2A, 2B, and 2C are schematic diagrams of the first unit 1. Fig. 2A is a see-through schematic diagram omitting the dielectric layer 13 and external electrodes 101, 102, 103, and 104 of the first unit 1. Fig. 2B is a schematic diagram of the internal electrode layer 11 and the internal electrode layer 12. Fig. 2C is a schematic diagram of a cross section taken along the cutting line IIC-IIC in Fig. 2A.

[0020] The internal electrode layer 11 has a lead portion 111 that is drawn out to the main surface M1 and connected to the external electrode 101. In this case, there may be a plurality of external electrodes 101 that are connected to the internal electrode layer 11. For example, the external electrode 101 may have an external electrode 101a and an external electrode 101b. In this case, the lead portion that is connected to the external electrode 101a is designated 111a, and the lead portion that is connected to the external electrode 101b is designated 111b. The internal electrode layer 11 has a lead portion 112 that is drawn out to the main surface M2 and connected to the external electrode 103. In this case, there may be a plurality of external electrodes 103 that are connected to the internal electrode layer 11. For example, the external electrode 103 may have an external electrode 103a and an external electrode 103b. In this case, the lead portion that is connected to the external electrode 103a is designated 112a, and the lead portion that is connected to the external electrode 103b is designated 112b.

[0021] The internal electrode layer 12 has an extraction portion 121 that is extracted to the main surface M1 and connected to the external electrode 102. In this case, there may be a plurality of external electrodes 102 that are connected to the internal electrode layer 12. The internal electrode layer 12 has an extraction portion 122 that is extracted to the main surface M2 and connected to the external electrode 104. In this case, there may be a plurality of external electrodes 104 that are connected to the internal electrode layer 12.

[0022] The first unit 1 can generate capacitance because the internal electrode layer 11 and the internal electrode layer 12 overlap in the first direction via the dielectric layer 13. A region of the internal electrode layer 11 that contributes to the generation of capacitance is referred to as a capacitance portion 113, and a region of the internal electrode layer 12 that contributes to the generation of capacitance is referred to as a capacitance portion 123.

[0023] In the first unit 1, the direction of the current flowing between the external electrode 101 and the external electrode 103 is opposite to the direction of the current flowing between the external electrode 102 and the external electrode 104. As a result, the inductance generated in the first unit 1 can be reduced. Furthermore, since the current path in the first unit 1 is divided into multiple paths, the inductance can be reduced by the shunt effect. As a result, the ESL of the capacitor 10 can be reduced.

[0024] The second unit 2 has internal electrode layers 21 and 22. The internal electrode layers 21 and 22 are alternately stacked in the first direction with a dielectric layer 23 sandwiched therebetween. The second unit 2 also has external electrodes 201 and 202 located on the main surface M1, and external electrodes 203 and 204 located on the main surface M2.

[0025] 3A, 3B, and 3C are schematic diagrams of the second unit 2. Fig. 3A is a see-through schematic diagram omitting the dielectric layer 23 and external electrodes 201, 202, 203, and 204 of the second unit 2. Fig. 3B is a schematic diagram of the internal electrode layer 21 and the internal electrode layer 22. Fig. 3C is a schematic diagram of a cross section taken along the section line IIIC-IIIC in Fig. 3A.

[0026] The internal electrode layer 21 has an extraction portion 211 that is extracted to the main surface M1 and connected to the external electrode 201. In this case, there may be a plurality of external electrodes 201 that are connected to the internal electrode layer 21. The internal electrode layer 21 has an extraction portion 212 that is extracted to the main surface M2 and connected to the external electrode 203. In this case, there may be a plurality of external electrodes 203 that are connected to the internal electrode layer 21.

[0027] The internal electrode layer 22 has an extraction portion 221 that is extracted to the main surface M1 and connected to the external electrode 202. In this case, there may be a plurality of external electrodes 202 that are connected to the internal electrode layer 22. The internal electrode layer 22 has an extraction portion 222 that is extracted to the main surface M2 and connected to the external electrode 204. In this case, there may be a plurality of external electrodes 204 that are connected to the internal electrode layer 22.

[0028] The second unit 2 can generate capacitance because the internal electrode layer 21 and the internal electrode layer 22 overlap in the first direction via the dielectric layer 23. A region of the internal electrode layer 21 that contributes to the generation of capacitance is referred to as a capacitance portion 213, and a region of the internal electrode layer 22 that contributes to the generation of capacitance is referred to as a capacitance portion 223.

[0029] In the second unit 2, the direction of the current flowing between the external electrode 201 and the external electrode 203 is opposite to the direction of the current flowing between the external electrode 202 and the external electrode 204. As a result, the inductance generated in the second unit 2 can be reduced. Furthermore, since the current path in the second unit 2 is divided into multiple paths, the inductance can be reduced by the shunt effect. As a result, the ESL of the capacitor 10 can be reduced.

[0030] The third unit 3 may have the same configuration as the first unit 1. For example, the third unit 3 has internal electrode layers 31 and 32. The internal electrode layers 31 and 32 are alternately stacked in the first direction with a dielectric layer 33 sandwiched therebetween. The third unit 3 also has external electrodes 301 and 302 located on the main surface M1, and external electrodes 303 and 304 located on the main surface M2.

[0031] 4A, 4B, and 4C are schematic diagrams of the third unit 3. Fig. 4A is a see-through schematic diagram omitting the dielectric layer 33 and external electrodes 301, 302, 303, and 304 of the third unit 3. Fig. 4B is a schematic diagram of the internal electrode layer 31 and the internal electrode layer 32. Fig. 4C is a schematic diagram of a cross section taken along the cutting line IVC-IVC in Fig. 4A.

[0032] The internal electrode layer 31 has a lead portion 311 that is drawn out to the main surface M1 and connected to the external electrode 301. In this case, there may be a plurality of external electrodes 301 that are connected to the internal electrode layer 31. For example, the external electrode 301 may have an external electrode 301a and an external electrode 301b. In this case, the lead portion that is connected to the external electrode 301a is designated 311a, and the lead portion that is connected to the external electrode 301b is designated 311b. The internal electrode layer 31 has a lead portion 312 that is drawn out to the main surface M2 and connected to the external electrode 303. In this case, there may be a plurality of external electrodes 303 that are connected to the internal electrode layer 31. For example, the external electrode 303 may have an external electrode 303a and an external electrode 303b. In this case, the lead portion that is connected to the external electrode 303a is designated 312a, and the lead portion that is connected to the external electrode 303b is designated 312b.

[0033] The internal electrode layer 32 has an extraction portion 321 that is extracted to the main surface M1 and connected to the external electrode 302. In this case, there may be a plurality of external electrodes 302 that are connected to the internal electrode layer 32. The internal electrode layer 32 has an extraction portion 322 that is extracted to the main surface M2 and connected to the external electrode 304. In this case, there may be a plurality of external electrodes 304 that are connected to the internal electrode layer 32.

[0034] The third unit 3 can generate capacitance because the internal electrode layer 31 and the internal electrode layer 32 overlap in the first direction via the dielectric layer 33. A region of the internal electrode layer 31 that contributes to the generation of capacitance is referred to as a capacitance portion 313, and a region of the internal electrode layer 32 that contributes to the generation of capacitance is referred to as a capacitance portion 323.

[0035] In the third unit 3, the direction of the current flowing between the external electrodes 301 and 303 is opposite to the direction of the current flowing between the external electrodes 302 and 304. As a result, the inductance generated in the third unit 3 can be reduced. Furthermore, because the current path in the third unit 3 is divided into multiple paths, the inductance can be reduced by the shunt effect. As a result, the ESL of the capacitor 10 can be reduced.

[0036] The fourth unit 4 may have the same configuration as the second unit 2 (see FIGS. 3A and 3C ). For example, the fourth unit 4 has internal electrode layers 41 and 42. The internal electrode layers 41 and 42 are alternately stacked in the first direction with a dielectric layer 43 sandwiched therebetween. The fourth unit 4 also has external electrodes 401 and 402 located on the main surface M1, and external electrodes 403 and 404 located on the main surface M2.

[0037] The fifth unit 5 may have the same configuration as the first unit 1 (see FIGS. 2A and 2C ). For example, the fifth unit 5 has internal electrode layers 51 and 52. The internal electrode layers 51 and 52 are alternately stacked in the first direction with a dielectric layer 53 sandwiched therebetween. The fifth unit 5 also has external electrodes 501 and 502 located on the main surface M1, and external electrodes 503 and 504 located on the main surface M2.

[0038] The external electrode EE has a base layer and a plated outer layer located outside the base layer. The base layer connects to the internal electrode layer IE, and the plated outer layer facilitates soldering of the external electrode to external wiring. The material of the base layer is not particularly limited, but may include, for example, copper (Cu). The material of the plated outer layer is not particularly limited, but may include, for example, Cu, nickel (Ni), tin (Sn), and gold (Au). The plated outer layer may also have multiple layers containing different materials.

[0039] An example of a method for forming the external electrodes EE will be described. The base layer is formed, for example, by applying a conductive paste mainly composed of Cu to the surface of the laminate and then baking it. However, the method for forming the base layer is not limited to this example. For example, the base layer may be formed by growing a metal plating such as Cu on the internal electrode layer IE exposed from the laminate as a nucleus. In this case, the metal plating may be electroless plating, electrolytic plating, or direct plating. The outer plating layer may be formed, for example, by forming an electrolytic plating layer containing Ni further outside the base layer, and then forming an electrolytic plating layer containing Sn further outside that.

[0040] The dielectric layer D may include various ceramic dielectrics. Examples of ceramic dielectrics include barium titanate (BaTiO ３ ), calcium titanate (CaTiO ３ ), strontium titanate (SrTiO ３ ), calcium zirconate (CaZrO ３ The dielectric layers D belonging to different units (for example, the dielectric layer 13 and the dielectric layer 23) may contain different ceramic dielectrics.

[0041] The internal electrode layers IE contain various metals, such as Ni, Cu, palladium (Pd), silver (Ag), etc. The internal electrode layers IE may contain different metals between different units.

[0042] The cover 6 includes various ceramic dielectrics, such as BaTiO ３ , CaTiO ３, SrTiO ３ , CaZrO ３ Examples of ceramic dielectric materials include:

[0043] 5 is a plan view of the main surface M1 of the capacitor 10 according to the present disclosure, viewed from the second direction. In the capacitor 10, the external electrodes EE are arranged in a staggered pattern on the main surface M1. For example, when viewed from the first direction, the position of the external electrode 201 of the second unit 2 in the third direction is between the position of the external electrode 101a of the first unit 1 in the third direction and the position of the external electrode 102 in the third direction. In other words, when focusing only on the positions in the third direction in the plan view of the main surface M1, the external electrode 201 is located between the external electrodes 101a and 102. Furthermore, when viewed from the first direction, the position of the external electrode 201 of the second unit 2 in the third direction is between the position of the external electrode 301a of the third unit 3 in the third direction and the position of the external electrode 302 in the third direction. In other words, in a plan view of the main surface M1, when focusing only on the position in the third direction, the external electrode 201 is located between the external electrode 301a and the external electrode 302. Although not shown, also on the main surface M2, when focusing only on the position in the third direction, the external electrode 203 is located between the external electrode 103a and the external electrode 104, and is located between the external electrode 303a and the external electrode 304.

[0044] When viewed from the first direction, the position in the third direction of the external electrode 202 of the second unit 2 is between the position in the third direction of the external electrode 102 of the first unit 1 and the position in the third direction of the external electrode 101b. In other words, when focusing only on the position in the third direction in a plan view of the main surface M1, the external electrode 202 is located between the external electrode 102 and the external electrode 101b. Also, when viewed from the first direction, the position in the third direction of the external electrode 202 of the second unit 2 is located between the position in the third direction of the external electrode 302 of the third unit 3 and the position in the third direction of the external electrode 301b. In other words, when focusing only on the position in the third direction in a plan view of the main surface M1, the external electrode 202 is located between the external electrode 302 and the external electrode 301b. Although not shown, even on main surface M2, when focusing only on the position in the third direction, external electrode 204 is located between external electrode 104 and external electrode 103b, and between external electrode 304 and external electrode 303b.

[0045] Furthermore, when focusing only on the position in the first direction, the external electrode 201 of the second unit 2 on the main surface M1 may be arranged without a gap between the external electrode 101 or 102 of the first unit 1 and the external electrode 301 or 302 of the third unit 3. Furthermore, on the main surface M2, the external electrode 203 of the second unit 2 may be arranged without a gap between the external electrode 103 or 104 of the first unit 1 and the external electrode 303 or 304 of the third unit 3 in the first direction.

[0046] For example, when viewed from the third direction, the ends of the external electrodes 101a, 101b, and 102 of the first unit 1 facing the second unit 2 and the ends of the external electrodes 201 and 202 of the second unit 2 facing the first unit 1 may overlap in the first direction. In other words, when focusing only on the positions in the first direction, the external electrodes 101a, 101b, and 102 may partially overlap the external electrodes 201 and 202. Note that this does not mean that the external electrodes 101a, 101b, and 102 are physically connected to the external electrodes 201 and 202. In other words, when viewed from the first direction, the external electrodes 101a, 101b, and 102 are spaced apart from the external electrodes 201 and 202 in the third direction.

[0047] In this case, the distance in the first direction between the external electrode 101a and the external electrode 201 is smaller than the distance in the third direction. The distance in the first direction between the external electrode 101b and the external electrode 202 is smaller than the distance in the third direction. The distance in the first direction between the external electrode 102 and the external electrode 201 is smaller than the distance in the third direction. The distance in the first direction between the external electrode 102 and the external electrode 202 is smaller than the distance in the third direction.

[0048] For example, when viewed from the third direction, the ends of the external electrodes 301a, 301b, and 302 of the third unit 3 facing the second unit 2 and the ends of the external electrodes 201 and 202 of the second unit 2 facing the third unit 3 may overlap in the first direction. In other words, when focusing only on the positions in the first direction, the external electrodes 201 and 202 may partially overlap with the external electrodes 301a, 301b, and 302. Note that this does not mean that the external electrodes 201 and 202 are physically connected to the external electrodes 301a, 301b, and 302. In other words, when viewed from the first direction, the external electrodes 201 and 202 are spaced apart from the external electrodes 301a, 301b, and 302 in the third direction.

[0049] In this case, the distance in the first direction between the external electrode 301a and the external electrode 201 is smaller than the distance in the third direction. The distance in the first direction between the external electrode 301b and the external electrode 202 is smaller than the distance in the third direction. The distance in the first direction between the external electrode 302 and the external electrode 201 is smaller than the distance in the third direction. The distance in the first direction between the external electrode 302 and the external electrode 202 is smaller than the distance in the third direction.

[0050] In a conventional multilayer capacitor such as that described in Patent Document 2, the positions of the external electrodes in the third direction were the same for each unit. In other words, the conventional multilayer capacitor did not have the second unit 2 and the fourth unit 4 of the capacitor 10 of the present disclosure. In such a configuration, only the dielectric layer was located between the first unit 1 and the third unit 3 and between the third unit 3 and the fifth unit 5, resulting in dead space that did not contribute to the formation of capacitance.

[0051] On the other hand, according to the capacitor 10 of the present disclosure, the second unit 2 is disposed between the first unit 1 and the third unit 3, which was previously a dead space. When only the position in the first direction is considered, the capacitor is designed so that the external electrodes of the second unit 2 do not overlap with the external electrodes of the first unit 1 and the third unit 3 in the first direction. In addition, the fourth unit 4 is disposed between the third unit 3 and the fifth unit 5. When only the position in the first direction is considered, the capacitor is designed so that the external electrodes of the fourth unit 4 do not overlap with the external electrodes of the first unit 1 and the third unit 3 in the first direction.

[0052] In this way, by arranging the external electrodes EE in a staggered manner, it is possible to increase the number of external electrodes EE that can be formed per unit area. Furthermore, by arranging the external electrodes EE in a staggered manner, the external electrodes EE can be arranged close to each other in the first direction without short-circuiting. As a result, compared to conventional multilayer capacitors, a capacitive portion can be formed in areas that were previously dead space, and the capacitance obtained per unit volume can be increased.

[0053] The number of external electrodes EE included in one unit can be changed as appropriate. For example, Fig. 6 shows a capacitor 10a according to another embodiment of the present disclosure. In the following, the same components as those in the capacitor 10 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0054] The capacitor 10 a of this embodiment has a plurality of units including a first unit 1 , a second unit 2 , a third unit 3 , a fourth unit 4 and a fifth unit 5 .

[0055] In the capacitor 10a, the first unit 1, the third unit 3, and the fifth unit 5 each have five external electrodes EE on the main surface M1. The second unit 2 and the fourth unit 4 each have four external electrodes EE on the main surface M1. The first unit 1, the third unit 3, and the fifth unit 5 each also have five external electrodes EE on the main surface M2. The second unit 2 and the fourth unit 4 each have four external electrodes EE on the main surface M2.

[0056] 7A and 7B are schematic diagrams of the first unit 1 and the second unit 2 of the capacitor 10a. Fig. 7A shows a perspective view of the first unit 1, omitting the dielectric layer 13 and the external electrode EE. The third unit 3 and the fifth unit 5 may have the same configuration. Fig. 7B shows a perspective view of the second unit 2, omitting the dielectric layer 23 and the external electrode EE. The fourth unit 4 may have the same configuration.

[0057] 1 and 6 , the capacitor 10 and the capacitor 10a of the present disclosure may have a length L in the third direction greater than a length T in the first direction, and the length T in the first direction greater than a length W in the second direction. In other words, the capacitor 10 and the capacitor 10a may satisfy the relationship L>T>W. In this case, the capacitance per unit volume can be increased while reducing the ESL.

[0058] Furthermore, the length L in the third direction, the length T in the first direction, and the length W in the second direction of the capacitor 10 and the capacitor 10a of the present disclosure may be set as appropriate. For example, the capacitor 10 may have L = 2000 μm to 2500 μm, W = 800 μm to 1100 μm, and T = 2000 μm to 2500 μm. For example, the capacitor 10a may have L = 3500 μm to 4000 μm, W = 800 μm to 1100 μm, and T = 2000 μm to 2500 μm.

[0059] 1 and 5 and the capacitor 10a shown in FIG. 6 have a rectangular shape when viewed from the second direction, but this is not limiting. For example, the shape of the external electrode EE may be a circle, a polygon, or the like when viewed from the second direction. As an example, the external electrode EE of the capacitor 10 and the capacitor 10a of the present disclosure has a rectangular shape measuring 400 μm × 250 μm.

[0060] The capacitance values ​​of the capacitor 10 and the capacitor 10a of the present disclosure may be set as appropriate. The materials and the number of layers of the dielectric layers D and the internal electrode layers IE are changed according to the set capacitance value. As an example, the capacitance value of the capacitor 10 is designed to be 5.6 μF, and the capacitance value of the capacitor 10a is designed to be 10.0 μF.

[0061] 8 is a schematic diagram showing a portion of a communication device 1000 as an example of use of the capacitor 10, 10a of the present disclosure. The communication device 1000 of one embodiment of the present disclosure includes a printed wiring board 81, an IC component 82, and a package substrate 80. The package substrate 80 has the capacitor 10, 10a therein. The package substrate 80 is mounted on the printed wiring board 81 by solder bumps. In addition, the IC component 82 is mounted on the package substrate 80.

[0062] Since the electrodes (internal electrode layers IE) of the capacitors 10 and 10a are arranged so as to penetrate the main surfaces M1 and M2, mounting the capacitors 10 and 10a inside the package substrate 80 can shorten the current conductor path between the printed wiring board 81 and the IC component 82. As a result, the inductance of the capacitors 10 and 10a can be reduced, and a communication device with excellent electrical characteristics can be provided.

[0063] According to the present disclosure, it is possible to provide a capacitor that has a large capacitance per unit volume while reducing ESL, and also to provide a communication device that has excellent electrical characteristics.

[0064] The present disclosure can be implemented in the following aspects (1) to (5).

[0065] (1) A capacitor including a first unit and a second unit, comprising: a laminate in which a plurality of internal electrode layers and a plurality of dielectric layers are stacked in a first direction; and a plurality of external electrodes located on first and second main surfaces of the laminate that face each other in a second direction that intersects the first direction, wherein the first unit is configured such that first internal electrode layers and second internal electrode layers are alternately stacked in the first direction with a dielectric layer sandwiched between them, and has a first external electrode and a second external electrode located on the first main surface, the first internal electrode layer has a first lead portion that is drawn out to the first main surface and connected to the first external electrode, and the second internal electrode layer has a second lead portion that is drawn out to the first main surface and connected to the second external electrode, and the second unit is located adjacent to the first unit in the first direction, and third internal electrode layers and fourth internal electrode layers are alternately stacked in the first direction with a dielectric layer sandwiched between them, and has a third external electrode located on the first main surface, the third internal electrode layer has a third extension portion that is extended to the first main surface and connected to the third external electrode, and when a direction intersecting the first direction and the second direction is defined as a third direction, the position of the third external electrode in the third direction, when viewed from the first direction, is between the position of the first external electrode in the third direction and the position of the second external electrode in the third direction.

[0066] (2) The capacitor described in (1) above, wherein, when viewed from the third direction, the end of the first external electrode on the second unit side and the end of the third external electrode on the first unit side overlap in the first direction, and when viewed from the first direction, the first external electrode and the third external electrode are spaced apart in the third direction.

[0067] (3) The capacitor according to (1) or (2) above, wherein, when the length in the first direction is T, the length in the second direction is W, and the length in the third direction is L, a relationship of L>T>W is satisfied.

[0068] (4) A capacitor according to any one of (1) to (3) above, further comprising a third unit located adjacent to the second unit in the first direction, wherein the third unit has fifth internal electrode layers and sixth internal electrode layers alternately stacked in the first direction with a dielectric layer sandwiched therebetween, and has a fourth external electrode and a fifth external electrode located on the first main surface, the fifth internal electrode layer having a fourth lead portion that is drawn out to the first main surface and connected to the fourth external electrode, and the sixth internal electrode layer having a fifth lead portion that is drawn out to the first main surface and connected to the fifth external electrode, and when viewed from the first direction, the position of the third external electrode in the third direction is between the position of the fourth external electrode in the third direction and the position of the fifth external electrode in the third direction.

[0069] (5) A communication device comprising a printed wiring board, an IC component, and a package substrate, the package substrate having the capacitor according to any one of (1) to (4) above therein.

[0070] 1, 2, 3, 4, 5: Unit 10, 10a: Capacitor 11, 12, 21, 22, 31, 32: Internal electrode layer 13, 23, 33: Dielectric layer 101, 102, 103, 104, 201, 202, 203, 204, 301, 302, 303, 304, 401, 402, 403, 404, 501, 502, 503, 504: External electrode 111, 112, 121, 122, 211, 212, 221, 222, 311, 312, 321, 322: Lead-out portion 113, 123, 213, 223, 313, 323: Capacitor portion 80: Package substrate 81: Printed wiring board 82: IC component 1000: Communication device

Claims

1. A capacitor including a first unit and a second unit, comprising: a laminate in which a plurality of internal electrode layers and a plurality of dielectric layers are stacked in a first direction; and a plurality of external electrodes located on first and second main surfaces of the laminate that face each other in a second direction that intersects the first direction, wherein the first unit is configured such that first internal electrode layers and second internal electrode layers are alternately stacked in the first direction with a dielectric layer sandwiched between them, and has a first external electrode and a second external electrode located on the first main surface, the first internal electrode layer has a first lead portion that is drawn out to the first main surface and connected to the first external electrode, and the second internal electrode layer has a second lead portion that is drawn out to the first main surface and connected to the second external electrode, and the second unit is located adjacent to the first unit in the first direction, and third internal electrode layers and fourth internal electrode layers are alternately stacked in the first direction with a dielectric layer sandwiched between them, and has a third external electrode located on the first main surface, the third internal electrode layer has a third extension portion that is extended to the first main surface and connected to the third external electrode, and when a direction intersecting the first direction and the second direction is defined as a third direction, the position of the third external electrode in the third direction, when viewed from the first direction, is between the position of the first external electrode in the third direction and the position of the second external electrode in the third direction.

2. The capacitor according to claim 1, wherein, when viewed from the third direction, an end of the first external electrode on the second unit side and an end of the third external electrode on the first unit side overlap in the first direction, and when viewed from the first direction, the first external electrode and the third external electrode are spaced apart in the third direction.

3. The capacitor according to claim 1 or 2, wherein the length in the first direction is T, the length in the second direction is W, and the length in the third direction is L, and the relationship L>T>W is satisfied.

4. A capacitor as claimed in any one of claims 1 to 3, further comprising a third unit located adjacent to the second unit in the first direction, wherein the third unit has fifth internal electrode layers and sixth internal electrode layers alternately stacked in the first direction with a dielectric layer sandwiched between them, and has a fourth external electrode and a fifth external electrode located on the first main surface, the fifth internal electrode layer having a fourth lead portion that is drawn out to the first main surface and connected to the fourth external electrode, and the sixth internal electrode layer having a fifth lead portion that is drawn out to the first main surface and connected to the fifth external electrode, and when viewed from the first direction, the position of the third external electrode in the third direction is between the position of the fourth external electrode in the third direction and the position of the fifth external electrode in the third direction.

5. A communication device comprising a printed wiring board, an IC component, and a package substrate, the package substrate having a capacitor according to any one of claims 1 to 4 therein.

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