Method for forming wiring groove and via hole of dual damascene structure, and method for manufacturing semiconductor device

Abstract

A method for forming a wiring groove and a via hole of a dual damascene structure including: a step for forming a first film having a flat upper surface by applying a precursor onto at least one insulating layer in which a hole serving as a via hole is formed, such that the amount of the precursor applied in the hole is greater than that applied to other portions; and a step for patterning the first film when forming a groove serving as the wiring groove in the insulating layer.

Description

Method for forming dual damascene wiring trench and via hole, and method for manufacturing semiconductor device

[0001] The present disclosure relates to a method for forming dual damascene interconnect trenches and via holes, and a method for manufacturing semiconductor devices.

[0002] The manufacturing process of semiconductor devices is becoming increasingly miniaturized. Japanese Patent Application Laid-Open No. 2023-65467 discloses a semiconductor device having fine wiring patterns and metal junctions. The wiring patterns and metal junctions are manufactured by the damascene method.

[0003] JP 2023-65467 A

[0004] In the damascene process, the process of forming wiring grooves and via holes involves forming a photoresist on an uneven surface. During this process, the fine unevenness on the top surface of the photoresist makes it impossible to form a fine resist pattern, making it difficult to improve the accuracy of forming the wiring grooves and via holes.

[0005] One aspect of the present disclosure is a method for forming a dual damascene wiring trench and a via hole, comprising the steps of: applying a precursor to at least one insulating layer having a hole formed therein that will become the via hole, so that the amount of precursor applied to the hole is greater than that of other portions, thereby forming a first film having a flat upper surface; and patterning the first film when forming a groove in the insulating layer that will become the wiring trench.

[0006] One aspect of the present disclosure is a method for forming a dual damascene wiring trench and a via hole, comprising the steps of: applying a precursor to at least one insulating layer having a groove formed therein that will become the wiring trench, so that the amount applied in the groove is greater than in other parts, to form a first film having a flat upper surface; and patterning the first film when forming a hole in the insulating layer that will become the via hole.

[0007] Another aspect of the present disclosure includes a step of forming a first film on an insulating layer disposed on a semiconductor layer, with the amount of precursor being increased according to the depression in the upper surface of the insulating layer, planarizing the upper surface, and curing the precursor, and a step of patterning the first film to form a wiring groove in the insulating layer.

[0008] Another aspect of the present disclosure is a method for forming a dual damascene wiring trench and a via hole, comprising the steps of: forming a coating film on at least one insulating layer in which a groove that will become the wiring trench or a hole that will become the via hole is formed; applying a precursor to the coating film so that the amount applied to a recess in the upper surface of the coating film is greater than that to other portions, thereby forming a first film having a flat upper surface; and patterning the first film when forming the hole that will become the via hole or the groove that will become the wiring trench in the insulating layer.

[0009] According to the present disclosure, it is possible to improve the accuracy of forming at least one of the wiring trench and the via hole.

[0010] Schematic diagram showing the configuration of a planarization apparatus. Schematic diagram illustrating a planarization process. Schematic diagram illustrating a planarization process. Schematic diagram illustrating a planarization process. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment. Schematic diagram illustrating a method for manufacturing a semiconductor device according to a third embodiment. Schematic diagram illustrating a semiconductor device according to a third embodiment. Schematic diagram illustrating a semiconductor device according to a third embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment.Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a fifth embodiment. Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a fifth embodiment. Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a fifth embodiment. Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a sixth embodiment. Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a sixth embodiment. Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a sixth embodiment. Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a sixth embodiment. Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a sixth embodiment. Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a seventh ... eighth embodiment. Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a eighth embodiment. Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a eighth embodiment. Schematic diagrams for explaining a method for manufacturing a semiconductor device according to a eighth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to an eighth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to an eighth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to an eighth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to an eighth embodiment. Schematic diagram for explaining a method for manufacturing a semiconductor device according to an ninth ...eleventh embodiment. Schematic diagram for explaining an application example of a semiconductor device according to an eleventh embodiment. Schematic diagram for explaining an application example of a semiconductor device according to an eleventh embodiment.

[0011] The embodiments shown below are intended to embody the technical concept of the present invention and are not intended to limit the present invention. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be designated by the same reference numerals and their description may be omitted.

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) will be used as necessary. The use of these terms is intended to facilitate understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0013] In this specification, a planar view refers to a view from a direction perpendicular to the top surface of the semiconductor layer. A cross-sectional view refers to a surface perpendicular to the top surface of the semiconductor layer. When the top surface of the semiconductor layer is rough when viewed microscopically, the planar view is defined based on the top surface of the semiconductor layer when viewed macroscopically. The top surface of the semiconductor layer refers to a surface on which an element formed in the semiconductor layer, such as a gate of a transistor, is provided, or a surface on which a connection portion with a contact plug is provided.

[0014] Furthermore, expressions such as "A or B," "at least one of A and B," "at least one of A and / or B," and "one or more of A and / or B" can include all possible combinations of the listed items unless expressly defined otherwise. That is, the above expressions are understood to disclose all cases, such as cases including at least one A, cases including at least one B, and cases including both at least one A and at least one B. This applies equally to combinations of three or more elements.

[0015] First Embodiment FIG. 1 is a schematic diagram showing the configuration of a planarization apparatus 100 according to this embodiment. Directions are indicated in an XYZ coordinate system, with the horizontal plane being the XY plane. Generally, a substrate 1, which is the object to be processed, is placed on a substrate stage 3 so that its surface is parallel to the horizontal plane (XY plane). Therefore, hereinafter, the mutually orthogonal directions in a plane along the surface of the substrate 1 are referred to as the X-axis and Y-axis, and the direction perpendicular to the X-axis and Y-axis is referred to as the Z-axis. Furthermore, hereinafter, the directions parallel to the X-axis, Y-axis, and Z-axis in the XYZ coordinate system are referred to as the X-direction, Y-direction, and Z-direction, respectively, and the rotation directions around the X-axis, Y-axis, and Z-axis are referred to as the θX-direction, θY-direction, and θZ-direction, respectively. The substrate 1 is a component capable of being used in semiconductor processes, such as a single-crystal silicon wafer, a single-crystal silicon wafer with a wiring structure formed thereon, or a glass substrate with elements formed thereon.

[0016] The underlying pattern on the substrate has an unevenness profile resulting from the pattern formed in the previous process. In particular, with the recent trend toward multilayer structures for memory devices, some process substrates have steps of around 100 nm. Steps resulting from the gentle waviness of the entire substrate can be corrected using the focus tracking function of the scanning exposure device used in the photolithography process. However, fine-pitch unevenness that falls within the exposure slit area of ​​the exposure device may fall outside the depth of focus (DOF) of the exposure device. Conventional methods for smoothing the underlying pattern on the substrate include forming a planarization layer and flattening. One method for forming a planarization layer is to form a film using spin coating, such as SOC (Spin-On-Carbon). Furthermore, flattening methods include chemical mechanical polishing (CMP) and etching. However, conventional techniques have the problem of not being able to achieve sufficient planarization performance. For example, manufacturing processes are evolving to new technology nodes such as 22 nm, 16 nm, 14 nm, and 10 nm. Even if a planarization layer sufficient for practical use was obtained at the previous generation node, the planarization layer may not be practical for use at the next node. For example, the surface unevenness of the planarization layer that was acceptable at the previous node may not be acceptable at the next node. Furthermore, CMP has high process costs and is limited in its applicable processes, while the unevenness of the underlying layer is likely to increase further due to future multi-layering.

[0017] To solve this problem, a planarization apparatus that uses imprint technology to planarize a substrate has been developed. The planarization apparatus brings the flat surface of a member or a member (flat template) on which no pattern is formed into contact with an uncured composition that has been previously applied to the substrate, thereby planarizing a local area within the substrate surface or the entire substrate surface. The composition is then cured while in contact with the flat template, and the flat template is separated from the cured composition.

[0018] This creates a planarized layer on the substrate. Unlike the commonly used planarization method using an SOC sacrificial film, this planarization device is not affected by the unevenness of the substrate's pattern surface, and is therefore expected to achieve higher planarization accuracy than existing methods.

[0019] 1 can be realized by a molding device that uses a plate 9, which is a pressing member, to mold a composition on a substrate 1. The planarization device 100 hardens the composition while the material on the substrate 1 is in contact with the plate 9, and forms a planarized layer of the material on the substrate 1 by separating the plate 9 from the hardened composition.

[0020] The substrate 1 is a semiconductor, insulator, or metal substrate, and its shape may be circular, such as a silicon wafer or quartz wafer, or rectangular, such as (mother) glass for a flat panel display (FPD). The material of the substrate 1 may be, but is not limited to, a single-crystal silicon wafer. The substrate material may be an elemental or compound semiconductor, such as silicon, germanium, diamond, silicon carbide, silicon germanium, gallium nitride, gallium arsenide, or indium arsenide. The substrate material may also be an inorganic insulator, such as silicon oxide, silicon nitride, aluminum oxide, or aluminum nitride. Furthermore, the substrate material may also be an organic insulator, such as polyimide, polyamide, or polycarbonate. Furthermore, the substrate 1 may be aluminum, a titanium-tungsten alloy, an aluminum-silicon alloy, or an aluminum-copper-silicon alloy. In short, the substrate 1 may be made of a material arbitrarily selected from the materials listed above. At least one layer of a semiconductor, insulator, or metal film may be formed on the surface of the substrate 1, and the surface may be flat or have an irregular surface. Alternatively, the substrate may have an adhesion layer formed on the surface by surface treatment such as silane coupling treatment, silazane treatment, or organic thin film formation, thereby improving adhesion to the composition. The substrate 1 is typically circular with a diameter of 300 mm, but is not limited to this.

[0021] The plate 9 may be made of a light-transmitting material, taking into account the light irradiation process. Such materials may be inorganic materials such as glass, quartz, fused silica, borosilicate glass, silicon, metal, or hardened sapphire. Alternatively, the material may be organic materials such as PMMA (Polymethyl methacrylate), siloxane polymer, fluorocarbon polymer, or polycarbonate resin. The plate 9 may be a rigid plate or a flexible film. The surface of the plate 9 that contacts the composition is flat. The plate 9 is preferably circular with a diameter greater than 300 mm and less than 500 mm, but this is not limited thereto. The thickness of the plate 9 is preferably greater than or equal to 0.25 mm and less than 2 mm, but is not limited thereto. If the composition is a thermosetting material rather than a photocurable material, the plate 9 does not need to be light-transmitting; it may be made of a material having the above-described properties.

[0022] The composition is a precursor that hardens to become at least a part of the planarization film, and is a curable composition that can be hardened by application of light or thermal energy. The curable composition that can be hardened by application of light or thermal energy may be a photocurable composition that hardens by application of light, a thermosetting composition that hardens by application of heat, or a photothermal curable composition that hardens by application of light and thermal energy. Examples of photocurable compositions include UV-curable liquids. Monomers such as acrylates and methacrylates can typically be used as UV-curable liquids. The curable composition may also be referred to as a moldable material. Hereinafter, the moldable material will also be simply referred to as a "material."

[0023] 1 , the planarization apparatus 100 includes a substrate chuck 2, a substrate stage 3, a base surface plate 4, support columns 5, a top plate 6, a guide bar 7, support columns 8, a plate chuck 11, a head 12, and an alignment shelf 13. The planarization apparatus 100 further includes a pressure adjustment unit 15, a supply unit 17, a substrate transport unit 18, an alignment scope 19, a light source 20, a stage drive unit 21, a plate transport unit 22, a cleaning unit 23, an input unit 24, and a control unit 200. The substrate chuck 2 and the substrate stage 3 can hold and move a substrate 1. The plate chuck 11 and the head 12 can hold and move a plate 9.

[0024] The substrate 1 is carried in from outside the planarization apparatus 100 by a substrate transport unit 18 including a transport hand and the like, and is held by the substrate chuck 2. The substrate stage 3 is supported by a base surface plate 4 and is driven in the X and Y directions to position the substrate 1 held by the substrate chuck 2 at a predetermined position. The stage drive unit 21 includes, for example, a linear motor or an air cylinder, and drives the substrate stage 3 at least in the X and Y directions, but may also have the function of driving the substrate stage 3 in two or more axial directions (e.g., six axial directions). The stage drive unit 21 also includes a rotation mechanism and can rotate the substrate chuck 2 or the substrate stage 3 in the θZ direction.

[0025] The plate 9, which serves as a pressing member, is carried in from outside the planarization apparatus 100 by a plate transport unit 22 including a transport hand and is held by a plate chuck 11. The plate 9 has, for example, a circular or rectangular outer shape and includes a first surface including a flat surface 10 that contacts a material placed on the substrate, and a second surface opposite the first surface. In this embodiment, the flat surface 10 has the same size as the substrate 1 or a larger size than the substrate 1. The plate chuck 11 is supported by a head 12 and can function to correct the position of the plate 9 in the θZ direction (tilt around the Z axis). Each of the plate chuck 11 and the head 12 includes an opening that allows light (ultraviolet light) emitted from the light source 20 through a collimator lens to pass through. The plate chuck 11 functions as a holder that mechanically holds the plate 9. For example, the plate chuck 11 holds the plate 9 by attracting the second surface of the plate 9 with the second surface facing upward. The head 12 also mechanically holds the plate chuck 11. The plate chuck 11 and head 12 constitute a forming unit 50 that performs the planarization film formation process. The head 12 constitutes a drive mechanism (not shown) for positioning the gap between the substrate 1 and the plate 9 when the plate 9 is brought into contact with and separated from the material on the substrate 1, and moves the plate 9 in the Z direction. The drive mechanism for the head 12 may be composed of an actuator such as a linear motor, an air cylinder, or a voice coil motor. A load cell may be disposed on the plate chuck 11 or the head 12 to measure the pressing force (impression force) of the plate 9 against the material on the substrate. The plate deformation mechanism (plate deformation unit) first includes a sealing member 14 that seals a spatial region A formed by the space inside the plate chuck 11 and the internal space enclosed by the plate 9. The plate deformation mechanism also includes a pressure adjustment unit 15 installed outside the plate chuck 11 and that adjusts the pressure within the spatial region A. The sealing member 14 is formed of a light-transmitting flat member such as quartz glass, and includes a connection port (not shown) at one part thereof for a pipe 16 connected to the pressure adjusting unit 15. The pressure adjusting unit 15 increases the pressure in the spatial region A, thereby increasing the amount by which the plate 9 deforms convexly toward the substrate side.Furthermore, the pressure adjustment unit 15 can reduce the amount of convex deformation of the plate 9 by reducing the pressure in the spatial region A. Support columns 5 that support a top plate 6 are arranged on the base surface plate 4. A guide bar 7 is suspended from the top plate 6, passes through an alignment shelf 13, and is fixed to the head 12. The alignment shelf 13 is suspended from the top plate 6 via support columns 8. The guide bar 7 passes through the alignment shelf 13. Furthermore, a height measurement system (not shown) is arranged on the alignment shelf 13 to measure the height (flatness) of the substrate 1 held by the substrate chuck 2, for example, using an oblique incidence image shift method.

[0026] The alignment scope 19 includes an optical system and an imaging system for observing the reference mark provided on the substrate stage 3 and the alignment mark provided on the plate 9. However, if no alignment mark is provided on the plate 9, the alignment scope 19 is not necessary. The alignment scope 19 is used for alignment to measure the relative positions of the reference mark provided on the substrate stage 3 and the alignment mark provided on the plate 9 and correct any positional deviation.

[0027] The supply unit 17 includes a dispenser with a nozzle that ejects uncured material onto the substrate 1, and supplies (coats) the material onto the substrate. The supply unit 17 employs, for example, a piezo-jet system or a microsolenoid system, and can supply a minute volume of material, approximately 1 pL (picoliter), onto the substrate 1 while the substrate stage 3 is being scanned. The number of nozzles in the supply unit 17 is not limited and may be one (single nozzle) or multiple (e.g., 100 or more). Multiple nozzles may form a linear nozzle array with one or multiple rows. Dispensers based on a type known as an inkjet head are particularly suitable because they can apply liquid material to the substrate as minute droplets. Piezo-inkjet heads, which have at least one piezoelectric element ejection energy generator per nozzle, are particularly suitable because they can change the volume of the ejected droplets.

[0028] The cleaning unit 23 cleans the plate 9 while the plate 9 is held by the plate chuck 11. In this embodiment, the cleaning unit 23 removes the material adhering to the plate 9, particularly the flat surface 10, by separating the plate 9 from the hardened material on the substrate. The cleaning unit 23 may, for example, wipe off the material adhering to the plate 9, or may remove the material adhering to the plate 9 using UV irradiation, electrostatic discharge, wet cleaning, dry plasma cleaning, or the like.

[0029] The control unit 200 is configured by a computer device including a CPU and memory, and controls the entire planarization apparatus 100. The control unit 200 functions as a processing unit that performs planarization processing by comprehensively controlling each unit of the planarization apparatus 100. Here, the planarization processing is a process in which the flat surface 10 of the plate 9 is brought into contact with the material on the substrate and the flat surface 10 is made to conform to the surface shape of the substrate 1, thereby planarizing the material. Note that the planarization processing is generally performed on a lot-by-lot basis, that is, for each of the multiple substrates included in the same lot.

[0030] Next, the planarization process will be described with reference to FIGS. 2A to 2C. First, material IM is supplied from a supply unit 17 to a substrate 1 having a base pattern 1a formed thereon. FIG. 2A shows the state after material IM has been placed on the substrate but before the plate 9 is brought into contact with it. Next, as shown in FIG. 2B, material IM on the substrate 1 is brought into contact with the flat surface 10 of the plate 9. The plate 9 presses against material IM, spreading material IM over the entire surface of the substrate 1. FIG. 2B shows the state in which the entire flat surface 10 of the plate 9 is in contact with material IM on the substrate 1, conforming to the surface shape of the substrate 1. Then, in the state shown in FIG. 2B, light is irradiated from a light source 20 through the plate 9 onto material IM on the substrate 1, thereby hardening the material IM. Then, the plate 9 is pulled away from the hardened material IM on the substrate. This forms a layer of material IM of approximately uniform thickness over the entire surface of the substrate 1. Here, the layer of material IM is referred to as a material layer ML. The material layer ML functions as a flat layer that flattens the uneven surface. Figure 2C shows the state in which the material layer ML has been formed on the substrate 1. Hereinafter, the contact (adhesion) or separation between the flat surface 10 of the plate 9 and the material IM on the substrate will be simply referred to as the contact (adhesion) or separation between the plate 9 and the material IM on the substrate, respectively. Also, below, the material IM in the supplied state will be referred to as a precursor, and after curing, as a film.

[0031] Next, a method for manufacturing an article (such as a semiconductor device, a liquid crystal display device, a color filter, or a MEMS) using the planarization apparatus 100 will be described. The manufacturing method includes the steps of using the planarization apparatus described above to contact a mold with a composition disposed on a substrate (such as a wafer or glass substrate) to planarize the composition, curing the composition, and separating the composition from the mold. This results in a planarization film being formed on the substrate. The substrate on which the planarization film has been formed is then subjected to processing such as pattern formation using a lithography apparatus, and the processed substrate is then subjected to other well-known processing steps to manufacture an article. These other well-known processing steps include etching, resist stripping, dicing, bonding, packaging, and the like. This manufacturing method enables the manufacture of higher-quality articles than conventional methods.

[0032] The following description will be given using a semiconductor device as a specific example of an article. FIGS. 3A and 3B are schematic diagrams illustrating a method for manufacturing a semiconductor device according to this embodiment, showing the process of forming a second wiring layer. Semiconductor device 300a and semiconductor device 300b each have a semiconductor layer 301, an insulating layer 311, an insulating layer 312, a contact plug layer 321, and a wiring layer 322. Surface P1 is the top surface of semiconductor layer 301, and surface P2 is the bottom surface of semiconductor layer 301. Insulating layer 311 and insulating layer 312 are disposed in this order on surface P1 of semiconductor layer 301. Contact plug layer 321 is disposed in contact holes in insulating layer 311 and forms multiple plugs electrically connected to elements in semiconductor layer 301. Wiring layer 322 is disposed in insulating layer 312 and has multiple wirings. The insulating layers 311 and 312 can be formed of a single layer or multiple layers of any insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxide carbide, spin-on glass (SOG), or a low-dielectric material. Each contact plug in the contact plug layer 321 can be formed of a conductive material containing a barrier metal such as titanium or titanium nitride and an embedded metal such as tungsten. The wiring layer 322 provided in the insulating layer 312 can be formed of a conductive material containing aluminum, copper, or the like. The wiring layer and plugs can be formed by forming a conductive film made of a conductive material and then removing any excess conductive film.

[0033] An insulating layer 313 is formed on the insulating layer 312. A second wiring layer is then formed on the insulating layer 313 by a dual damascene process. Therefore, the insulating layer 313 can be a laminated film formed by repeatedly stacking a first insulating thin film, such as silicon nitride, which has a relatively high etching resistance, and a second insulating thin film, such as silicon oxide. The second insulating thin film has, for example, a lower dielectric constant, lower etching resistance, and a thicker film than the first insulating thin film. Specifically, a first insulating thin film can be formed, a second insulating thin film can be formed thereon, a first insulating thin film can be formed thereon again, a second insulating thin film can be formed thereon again, and finally the first insulating thin film can be formed again, resulting in a total of five laminated layers.

[0034] FIG. 3A shows a state in which a photoresist film 332 for forming a resist pattern for a wiring groove is formed after a via hole 331 is formed in an insulating layer 313. The photoresist film 332 is formed to fill the via hole 331 in the insulating layer 313 and cover the upper surface of the insulating layer 313. The position of the upper surface of the insulating layer 313 is referred to as plane P3. A concave portion may be formed on the surface S1 of the photoresist film 332 in accordance with the via hole 331. If the surface S1 of the photoresist film 332 is not flat, an image cannot be formed during exposure of the photoresist film 332, making it difficult to form a fine resist pattern. Since the depth of focus of an exposure device is shallow when using short wavelength light such as EUV, the flatness and film thickness uniformity of the photoresist are particularly important.

[0035] Therefore, in this embodiment, as shown in FIG. 3B, a liquid precursor (material IM) of a material that can later become an etching mask is applied in a predetermined amount so that it is more concentrated in the area where the via holes are located and less concentrated in other areas. The liquid precursor can be a precursor of an energy-curable resin or a precursor of SOC (spin-on carbon). If necessary, the flat surface of a plate is pressed against the liquid to harden it. After hardening, a photoresist film is formed. Because the liquid is applied to the via holes before the photoresist film is formed, the surface of the photoresist film formed thereafter is even flatter than the state shown in FIG. 3A, allowing for sufficient exposure even with a shallow depth of focus. The exposed photoresist film is then developed to form a resist pattern.

[0036] The uncured material is deposited using an inkjet head equipped with a piezoelectric element as a discharge actuator within a pre-formed via hole. Specifically, droplets are deposited multiple times (N+1 or more times per unit area, where N is a natural number) within the via hole, and N times per unit area onto the other flat surface of the insulator. The number of droplets deposited can be determined based on the via hole formation pattern. Specifically, droplets are deposited while changing the relative position of the discharge port and the substrate according to a drawing map that determines the number (or amount) of droplets to be deposited on the substrate and their deposition positions on the upper surface based on the pattern data of the resist mask used to form the via holes.

[0037] Since the via holes are filled in this way, the surface of the subsequently formed resist film will be flat. The liquid used here is preferably a composition that hardens when exposed to light energy (a precursor of the hardened film).

[0038] On the other hand, the resist film is preferably a so-called positive resist, which is exposed to light energy and generates portions that become soluble in a developer. The device for exposing the resist film is preferably an EUV exposure device, and particularly preferably a device with a numerical aperture NA of greater than 0.55. Alternatively, an ArF immersion exposure device, an ArF dry exposure device, or a KrF exposure device may be used.

[0039] Next, a method for manufacturing a semiconductor device according to this embodiment will be described. Figures 4A to 4F are schematic diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. The manufacturing method shown in Figures 4A to 4F applies the planarization method described in Figures 1 and 2A to 2C to the manufacture of a wiring structure formed by the dual damascene method described in Figures 3A and 3B. Here, a method for forming vias first (via first) in the dual damascene method will be described.

[0040] 4A , similar to FIGS. 3A and 3B , after the process of forming a via hole 331 in the insulating layer 313, the cured film material IM is applied. The amount of material IM applied is adjusted according to the shape of the upper surface of the insulating layer 313. Here, the material IM is supplied so that the amount applied to the via hole 331 is greater than that applied to the surrounding flat upper surface. This can be achieved by controlling the amount applied, for example, by changing the number of droplets of the precursor (liquid) of material IM ejected by the inkjet method or by changing the size of the droplets.

[0041] Next, as shown in FIG. 4B , if necessary, a plate 9 is brought into contact with the material IM to planarize the upper surface of the material IM. Then, light is irradiated onto the material IM through the plate 9. The light irradiation hardens the material IM, forming a material layer ML. The plate 9 is then separated from the hardened material layer ML on the semiconductor layer 301. This planarization process forms a material layer ML with a highly flat upper surface. Here, the material IM can be, for example, a precursor of an energy-curable resin or a precursor of SOC (spin-on carbon), as described above.

[0042] As shown in FIG. 4C , a photoresist film 334 is formed on the upper surface of the material layer ML. Because it is formed on the material layer ML, which has a highly flat upper surface, the upper surface of the photoresist film 334 also has a high flatness. The photoresist film 334 is exposed to light in a desired pattern. At this time, the exposure may be EUV exposure. The EUV-exposed photoresist film is developed, and the exposed portions become soluble in a developer, thereby forming a resist pattern. In this way, as shown in FIG. 4D , a resist pattern 335 is formed. The resist pattern 335 has an opening 336. The opening 336 exposes the material layer ML.

[0043] In the state shown in FIG. 4D , a portion of the material layer ML and the insulating layer 313 is removed to form a wiring trench 337 in the insulating layer 313. Using the resist pattern 335 as a mask, anisotropic etching is performed on the material layer ML and the insulating layer 313 using a reactive ion etching apparatus, thereby forming the wiring trench 337 that communicates with the opening 336. If the resist pattern 335 has high etching resistance during this etching, the resist pattern 335 may remain as shown in FIG. 4E . In this case, after the wiring trench 337 is formed, the resist pattern 335, the material layer ML remaining in the via hole 331, and the material layer ML remaining on the insulating layer 313 are removed. In this manner, a structure having a dual damascene structure wiring trench 337 and via hole 331 can be formed.

[0044] However, if there is no significant difference in etching rate for the resist pattern 335, the material layer ML, and the insulating layer 313, the resist pattern 335 and the material layer ML will be sequentially removed when etching the insulating layer 313. Therefore, when the groove 337 is formed by etching as shown in Fig. 4F, the resist pattern 335 and the material layer ML will have disappeared except for residues.

[0045] Alternatively, there is the following method. After using a resist pattern 335 to remove a portion of the material layer ML by etching, the resist pattern 335 is removed. Then, a pattern of the material layer ML is formed in the material layer ML according to the resist pattern 335 (patterning). This can also be used as an etching mask (hard mask) to remove the underlying insulating layer 313, thereby forming the wiring trench 337. Thereafter, the material layer ML remaining in the via hole 331 and on the upper surface of the insulating layer 313 is removed, thereby obtaining the structure shown in FIG. 4F.

[0046] This method is preferable when forming fine patterns.

[0047] Residues of the resist pattern 335 and the material layer ML may be removed as necessary. Then, a conductor film is formed to fill the via hole 331 and the wiring groove 337, and excess conductor film is removed. This forms a conductor portion that fills the via hole 331 and the wiring groove 337. Here, the conductor may be composed of multiple layers of a barrier metal made of a transition metal such as Ti or Ta or a transition metal compound such as TiN or TaN, and a buried metal such as Cu. The filling process can be performed using known techniques, such as film formation by CVD, sputtering, or plating, followed by conductor polishing by CMP.

[0048] According to the method described above in detail, the flatness of the upper surface of the photoresist before exposure and the uniformity of the photoresist film thickness can be improved, thereby improving the precision of forming the resist pattern, i.e., the precision of forming the wiring trench or via hole can be improved.

[0049] Here, for example, the flatness of the upper surface of the photoresist required for EUV exposure is an unevenness of less than 10 nm. The planarization method of this embodiment makes it easy to satisfy the flatness of the upper surface of the photoresist. Furthermore, for EUV exposure, it is suitable when the numerical aperture NA is greater than 0.33, particularly greater than 0.55.

[0050] As described above, according to the method for forming dual damascene wiring trenches and via holes of this embodiment, it is possible to form wiring trenches or via holes with high precision.

[0051] Second Embodiment A method for manufacturing a semiconductor device according to this embodiment will now be described. Figures 5A to 5F are schematic diagrams illustrating a method for manufacturing a semiconductor device according to the second embodiment. The manufacturing method shown in Figures 5A to 5F differs from the manufacturing method described in Figures 4A to 4F in the order in which the dual damascene wiring trenches and via holes are formed. That is, Figures 5A to 5F illustrate a method in which the wiring trenches are formed first (trench first) in the dual damascene method. Detailed descriptions of the same configurations and steps as those in Figures 4A to 4F will be omitted below.

[0052] 5A shows a step of applying the material IM after the step of forming the wiring groove 337 in the insulating layer 313. The amount of the material IM applied is adjusted according to the shape of the upper surface of the insulating layer 313.

[0053] Here, the material IM is supplied so that the amount of material applied to the wiring trench 337 is large.

[0054] As shown in Fig. 5B, if necessary, the flat surface of the plate 9 is brought into contact with the material IM to flatten the upper surface of the material IM. Then, light is irradiated onto the material IM through the plate 9 to harden the material IM. This process is similar to that shown in Fig. 4B.

[0055] After removing the plate 9, a photoresist film 334 is formed on the flat upper surface of the material layer ML as shown in Fig. 5C. Then, the photoresist film 334 is exposed to light in the areas that will become via holes, forming a latent image in the photoresist film, which is then developed and post-baked.

[0056] In this way, a resist pattern 339 is formed as shown in Fig. 5D. The resist pattern 339 has an opening 340 for forming a via hole. In the state shown in Fig. 5D, a portion of the material layer ML and the insulating layer 313 are removed to form a via hole 331. This step is also performed by etching in the same manner as in the case of forming the wiring trench shown in Fig. 4D. Then, as shown in Fig. 5E, a via hole 331 communicating with the opening 340 is formed in the insulating layer 313.

[0057] As described above, if there is no significant difference in etching rate for the resist pattern 339, the material layer ML, and the insulating layer 313, the resist pattern 339 and the material layer ML will be sequentially removed when etching the via hole in the insulating layer 313. Therefore, as shown in Fig. 5F, when the via hole 331 overlapping the groove 337 formed by etching is formed, the resist pattern 339 and the material layer ML will have disappeared except for residues.

[0058] Alternatively, there is the following method. After etching and removing the material layer ML using the resist pattern 339, the resist pattern 339 is removed to form a pattern of the material layer ML in accordance with the resist pattern 339. This can also be used as an etching mask (hard mask) to remove the underlying insulating layer 313, thereby forming the via hole 331. Thereafter, the material layer ML remaining in the via hole 331 and on the upper surface of the insulating layer 313 is removed, thereby obtaining the structure shown in FIG. 5F.

[0059] If necessary, the resist pattern 339 and residues of the material layer ML are removed. This results in the structure shown in Fig. 5F. Thereafter, similar to the method described above, a conductor is filled into the via hole 331 and the wiring groove 337, thereby providing wiring and vias of a dual damascene structure.

[0060] According to this method, the flatness of the upper surface of the photoresist can be improved, thereby improving the precision of forming the resist pattern. That is, the precision of forming the wiring trench or via hole can be improved. As described above, according to the method for forming the dual damascene wiring trench and via hole of this embodiment, it is possible to form the wiring trench or via hole with high precision.

[0061] Third Embodiment A method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 6A, 6B, and 7. Figures 6A and 6B are schematic diagrams illustrating the semiconductor device according to this embodiment. A CMOS image sensor will be used as an example of the semiconductor device.

[0062] FIG. 6A shows a functional block diagram of a CMOS image sensor. The CMOS image sensor 1000 has a pixel region 101 and an other region 102. The pixel region 101 has a plurality of pixels 103 arranged two-dimensionally. Each pixel 103 has a photoelectric conversion element. The other region 102 is arranged with, for example, a scanning circuit 104, a control circuit 105, a readout circuit 106, a horizontal scanning circuit 107, and an output circuit 108. The scanning circuit 104 controls the operation of the plurality of pixels 103. The control circuit 105 outputs signals that control the operation of the scanning circuit 104, readout circuit 106, horizontal scanning circuit 107, output circuit 108, etc. The readout circuit 106 is a circuit, such as an analog-to-digital converter, for processing and outputting signals from the pixels 103. The horizontal scanning circuit 107 outputs a signal that controls the operation of the readout circuit 106.

[0063] Fig. 6B shows a wiring pattern of a wiring layer of the CMOS image sensor shown in Fig. 6A. A grid-like wiring 121 is provided in the pixel region 101, and wirings 122, 123, 124, and 125 are arranged so as to substantially surround the pixel region 101.

[0064] It should be noted that a plurality of terminals 130 for exchanging signals with the outside are arranged in the other region 102. The widths of the wiring 122, wiring 123, wiring 124, and wiring 125 are wider than the width of the wiring 121. In other words, it can be said that the wiring density is higher in the other region 102. Here, the wiring 122, wiring 123, wiring 124, and wiring 125 may, for example, completely surround the pixel region 101 or may be arranged on at least one side of the pixel region 101.

[0065] 7 is a schematic cross-sectional view corresponding to the line segment AB in FIG. 6B and shows a process corresponding to FIG. 5A. As in FIG. 5A, the material IM is supplied so that the amount of material IM is greater in the wiring groove 337. Furthermore, the material IM is supplied so that the amount of material IM is greater in the wiring groove 337 in region 102 than in the wiring groove 337 in region 101. This manufacturing method can reduce not only small irregularities but also macroscopic irregularities that can occur in a structure with such differences in wiring density.

[0066] As described above, the manufacturing method of this embodiment is particularly effective for semiconductor devices such as CMOS image sensors in which pattern variations can occur between pixel regions and other regions. Other than CMOS image sensors, other devices in which pattern variations can occur include display devices and memory devices.

[0067] 8A to 8D and 9A to 9C, a method for manufacturing a semiconductor device according to this embodiment will be described. A CMOS image sensor will be used as an example of the semiconductor device according to this embodiment. Descriptions of steps and structures similar to those of the other embodiments will be omitted.

[0068] 8A shows a semiconductor layer 301 on which a plurality of insulating layers 311-316 and wiring layers 322-324 are disposed. The wiring layers 323 and 324 are formed by the dual damascene method, and the wiring and vias are integrated. An insulating layer 317 is formed on the insulating layer 316. Macroscopic irregularities may be formed on the upper surface of the insulating layer 317, for example, by a planarization process in the process of embedding a conductor in the wiring layer 324. Here, a case is shown in which there is a depression in the center of the cross section of the semiconductor layer 301.

[0069] In FIG. 8B, material IM is applied. The amount of material IM applied is adjusted according to the shape of the upper surface of the insulating layer 317. Here, material IM is applied so that the amount applied is greater at the center of the X-direction width of the insulating layer 317. Here, the shape of the upper surface of the insulating layer 317 may be measured in advance or determined by simulation. Subsequent processes are similar to those of other embodiments. In FIG. 8C, the material IM is planarized and hardened using a plate 9. A material layer ML is formed from the material IM. As shown in FIG. 8D, a photoresist is formed on the material layer ML and exposed to light to form a resist pattern 630.

[0070] Thereafter, as shown in FIG. 9A , etching is performed using a resist pattern 630 to remove portions of the material layer ML and the insulating layer 317, thereby forming wiring grooves 631. The removal of the material layer ML and the insulating layer 317 may be performed by performing separate etching on each layer, or may be performed simultaneously by performing etching under the same conditions. In the latter case, it is desirable to select the same or similar materials, for example, materials and etching conditions that result in equivalent etching rates under certain etching conditions. After removing the resist pattern 630, a conductive material is filled into the wiring grooves 631 to form connection portions 641. This configuration results in the formation of the structure 650 shown in FIG. 9B .

[0071] Another structure 660 is formed in the same manner as in the manufacturing method shown in FIGS. 8A to 9B. Specifically, the another structure 660 has a semiconductor layer 601, multiple insulating layers 611 to 617, multiple wiring layers, a contact plug layer, etc., and has a connection portion 642. In the step shown in FIG. 9C, the structure 650 and the structure 660 are bonded at a bonding surface BP. At the bonding surface BP, the connection portion 641 and the connection portion 642 are in contact, and the material layer ML of the structure 650 and the material layer ML of the structure 660 are in contact. With such a structure, a CMOS image sensor having a stacked structure can be formed.

[0072] In this bonding process, high flatness is required for the surfaces of the structure 650 and the structure 660 that constitute the bonding surface BP. Since the upper surface of the material IM after planarization has high flatness, the flatness of the surfaces of the structure 650 and the structure 660 can also be improved. Bonding surfaces with high flatness makes it possible to improve the bonding strength.

[0073] Furthermore, by selecting materials that are easy to bond, such as using the same material for the material layers ML of the structures 650 and 660, it is possible to improve the bonding strength.

[0074] Fifth Embodiment A method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 10A to 10D and 11A to 11I. The manufacturing method shown in Figures 10A to 10D and 11A to 11I differs from the manufacturing method described in Figures 4A to 4F in that insulating layer 313 is replaced by insulating layers 401 and 402, and further includes a step of forming another layer after the step of hardening material IM. In the following description, detailed description of the same configurations and steps as those shown in Figures 4A to 4F will be omitted.

[0075] 10A shows a state in which an opening 403 to become a via hole is formed in insulating layer 401 and insulating layer 402, similar to FIG. 4A . Insulating layer 401 may include, for example, a film made of silicon oxide and a film made of silicon oxide carbide. Insulating layer 402 may include, for example, a film made of silicon oxide and a film made of silicon oxide carbide. Opening 403 is an opening that exposes wiring layer 322.

[0076] FIG. 10B shows the process of applying material IM, similar to FIG. 4A. Here, material IM is applied so that the amount applied to the opening 403 is greater than the amount applied to the surrounding flat upper surface. This can be achieved, for example, by changing the number of droplets of the precursor (liquid) of material IM ejected by the inkjet method or by changing the droplet size. Then, similar to FIG. 4B, the material IM is planarized and cured using a plate 9. Finally, a material layer ML having a highly flat upper surface is formed, as shown in FIG. 10C.

[0077] 10D shows a step of forming a film 405 on the material layer ML. The film 405 may be a film made of a material different from that of the material layer ML. The film 405 may be formed of a single layer or multiple layers of any insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxide carbide, spin-on glass (SOG), or a low-k material. Alternatively, the film 405 may be formed to include a conductive material, such as Ti.

[0078] 11A, a photoresist film 406 is formed on a film 405. Since the photoresist film 406 is formed on the film 405 on the material layer ML, which has a highly flat upper surface, the flatness of the upper surface of the photoresist film 406 is also high. Then, as shown in FIG. 11B, a resist pattern 407 is formed from the photoresist film 406 by exposure using, for example, an EUV exposure apparatus, using a manufacturing method similar to that of the other embodiments. The resist pattern 407 has an opening 408. The opening 408 is an opening for forming a wiring trench.

[0079] In the state shown in FIG. 11B , etching is performed to remove a portion of the film 405, forming a pattern 410 from the film 405. The film 405 can be removed by, for example, anisotropic etching using a reactive ion etching apparatus. The pattern 410 can function as a so-called hard mask. As shown in FIG. 11C , the pattern 410 has an opening 409. The opening 409 communicates with the resist pattern 407 and the pattern 410. Next, etching is performed through the opening 409 to remove a portion of the material layer ML, which becomes the material layer ML 412 shown in FIG. 11D . Thereafter, the resist pattern 407 is removed. Note that the resist pattern 407 may be removed by etching simultaneously with a portion of the material layer ML. In FIG. 11D , a remaining portion 413 is a portion of the material layer ML that remains unetched.

[0080] Next, etching is performed using pattern 410 as a hard mask to remove the insulating layer 402 in the portion corresponding to opening 411. At this time, remaining portion 413 may also be removed at the same time as insulating layer 402. Opening 411 becomes deeper through etching, changing from the state of opening 414 shown in FIG. 11E to opening 417 shown in FIG. 11F. Here, etching may be stopped at the state shown in FIG. 11E and proceed to the next step. In FIG. 11E, insulating layer 402 becomes insulating layer 415, and remaining portion 413 becomes remaining portion 416.

[0081] Here, by forming insulating layer 401 and insulating layer 402 as multilayer films made of different materials, it is possible to adjust the etching rate in the groove forming process in Figures 11E and 11F and improve the accuracy of groove formation.

[0082] 11F, the remaining portion 419 and the material layer 412 remaining in the insulating layer 401 can be removed by ashing, etching, or the like. The trench 420 thus formed is a trench for dual damascene, having a wiring trench and a via hole.

[0083] 11H, a conductive film 421 that will become wiring and vias is formed. As in the other embodiments, the conductive film 421 can be formed of a conductive material including aluminum, copper, or the like. Furthermore, the conductive film 421 can include a barrier metal or the like to reduce the diffusion of the conductive material. The conductive film 421 that overflows from the trench 420 and is formed on the insulating layer 418 is removed by a method such as CMP, and a dual damascene structure wiring 422 shown in FIG. 11I is formed.

[0084] According to the manufacturing method of this embodiment, since a hard mask can be used, it becomes possible to form finer patterns with high precision. In particular, fine wiring structures using an EUV exposure apparatus may have insulating layers with a complex layer structure, such as those having a low dielectric film formed between wiring layers to reduce capacitance between wiring layers. According to the manufacturing method of this embodiment, when etching is performed on a complex layer structure, a hard mask can be used as a mask with sufficient etching resistance.

[0085] Sixth Embodiment A method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 12A to 12D. The manufacturing method shown in Figures 12A to 12D corresponds to that shown in Figures 10A to 10D. The manufacturing method according to this embodiment differs from the manufacturing method described with reference to Figures 10A to 10D in that it includes a step of forming a spin-on carbon (SOC) film 430 after the step of applying material IM. This embodiment will be described below with reference to Figures 12A to 12D, but detailed descriptions of configurations and steps similar to those shown in Figures 10A to 10D will be omitted.

[0086] Figures 12A and 12B show the same processes as Figures 10A and 10B. After applying and curing the material IM to form the material layer ML, the SOC film 430 is formed (Figure 12C). Since it is formed on the material layer ML having high flatness, the SOC film 430 also has high flatness as well. Next, as shown in Figure 12D, a film 431 serving as a hard mask is formed on the SOC film 430. This film 431 has the same function as the film 405 in Figure 10D. And after the process in Figure 12D, the same configuration as in Figures 11A to 11I is performed. Note that the SOC film can be removed together with the material layer ML in the process of Figure 11G.

[0087] Note that the film 431 serving as a hard mask formed in Figure 12D can also be omitted. Furthermore, by making the SOC film of the present embodiment function as a hard mask, highly accurate etching can be performed even when the etching selectivity between the material layer ML and the photoresist cannot be sufficiently achieved. Also, the SOC film can be appropriately changed to a film formed by spin coating that is not carbon, i.e., a so-called coating film.

[0088] <Seventh Embodiment> The manufacturing method of the semiconductor device of the present embodiment will be described using Figures 13A to 13D. The manufacturing method shown in Figures 13A to 13D is a manufacturing method corresponding to Figures 10A to 10D. The difference from Figures 10A to 10D is that it has a process of forming the SOC film 440 before the process of applying the material IM. Hereinafter, the description will be made using Figures 13A to 13D, but the detailed description of the same configuration and process as in Figures 10A to 10D will be omitted.

[0089] FIG. 13A shows a process similar to that shown in FIG. 10A. In FIG. 13B, an SOC film 440 is formed to fill the opening 403. The upper surface of the SOC film 440 may have a recess 441 corresponding to the position of the opening 403. Forming photoresist on such a recess 441 may result in poor resolution. Next, as shown in FIG. 13C, a material IM is applied to the SOC film 440. At this time, a larger amount is applied to the portion corresponding to the recess 441 than to the other portions. Then, as in the previous embodiments, the material IM is planarized and hardened to form a material layer ML with high flatness. Then, a film 442 is formed on the material layer ML (FIG. 13D). This film 442 has the same function as the film 405 in FIG. 10D. After the process shown in FIG. 13D, the same configuration as that shown in FIGS. 11A to 11I is performed. Note that the SOC film can be removed together with the material layer ML in the process shown in FIG. 11G.

[0090] According to the manufacturing method of this embodiment, the deep opening 403 is filled with the SOC film 440, and the recess 441 shallower than the opening 403 is planarized. This facilitates the planarization process and the exposure process when forming the material layer ML.

[0091] 13D, the film 442 serving as a hard mask may be omitted. By adjusting the etching selectivity between the SOC film 440 and the material IM, the material layer ML of this embodiment may also function as a hard mask.

[0092] Eighth Embodiment A method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 14A to 14D and 15A to 15I. The manufacturing method shown in Figures 14A to 14D and 15A to 15I differs from the manufacturing method described in Figures 5A to 5F in that insulating layer 313 is replaced by insulating layers 501 and 502, and further includes a step of forming another layer after the step of hardening material IM. The manufacturing method shown in Figures 14A to 14D and 15A to 15I also differs from the manufacturing method described in Figures 10A to 10D and 11A to 11I in that it is trench-first.

[0093] The following explanation will be given using Figures 14A to 14D and Figures 15A to 15I, but detailed explanations will be omitted for configurations and steps similar to those in Figures 5A to 5F, or configurations and steps similar to those in Figures 10A to 10D and Figures 11A to 11I.

[0094] FIG. 14A shows a state in which a wiring trench 500 is formed in an insulating layer 502 disposed on an insulating layer 501, similar to FIG. 5A . The insulating layer 501 may include, for example, a film made of silicon oxide and a film made of silicon carbide oxide. The insulating layer 502 may include, for example, a film made of silicon oxide and a film made of silicon carbide oxide. FIG. 14B shows a step of applying the material IM shown in FIG. 5A . The amount of material IM applied is adjusted according to the shape of the upper surface of the insulating layer 502. Here, the material IM is supplied so that the amount applied in the wiring trench 500 is greater. The material IM is then planarized and hardened to form a material layer ML ( FIG. 14C ).

[0095] 14D shows a step of forming a film 503 on the material layer ML. The film 503 can be a film made of a material different from the material layer ML. The film 503 can be formed of a single layer or multiple layers of any insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxide carbide, spin-on glass (SOG), or a low-k material. Alternatively, the film 503 can be formed to include a conductive material, such as Ti. The film 503 has the same function as the film 405 in FIG. 10D.

[0096] 15A, a photoresist film 504 is formed on the film 503. Since the photoresist film 504 is formed on the film 503 on the material layer ML, which has a highly flat upper surface, the flatness of the upper surface of the photoresist film 504 is also high. Then, as shown in FIG. 15B, a resist pattern 506 is formed from the photoresist film 504 by exposure using, for example, an EUV exposure apparatus, using a manufacturing method similar to that of the other embodiments. The resist pattern 506 has an opening 505. The opening 505 is an opening for forming a via hole.

[0097] Etching is performed in the state shown in FIG. 15B to remove a portion of the film 503, thereby forming a pattern 508 from the film 503. The film 503 can be removed by, for example, anisotropic etching using a reactive ion etching apparatus. The pattern 508 can function as a so-called hard mask. As shown in FIG. 15C, the pattern 508 has an opening 507. The opening 507 communicates with the resist pattern 506 and the pattern 508. Next, etching is performed through the opening 507 to remove a portion of the material layer ML, and the material layer ML becomes the material layer 510 shown in FIG. 15D. Thereafter, the resist pattern 506 is removed. Note that the resist pattern 506 may be removed by etching simultaneously with a portion of the material layer ML.

[0098] Next, etching is performed using the pattern 508 as a hard mask to remove the insulating layer 501 in the portion corresponding to the opening 509. At this time, the pattern 508 can be etched simultaneously with the insulating layer 501. The opening 509 becomes deeper through etching, and changes from the state of opening 511 shown in FIG. 15E to opening 513 shown in FIG. 15F. The opening 513 exposes the wiring layer 322.

[0099] 15F, the material layer 510 can be removed by a method such as ashing, etching, etc. The trench 515 thus formed is a trench for dual damascene having a wiring trench and a via hole.

[0100] 15H, a conductive film 516 that will become wiring and vias is formed. As in the other embodiments, the conductive film 516 can be formed of a conductive material including aluminum, copper, or the like. Furthermore, the conductive film 516 can include a barrier metal or the like to reduce the diffusion of the conductive material. The conductive film 516 that overflows from the trench 515 and is formed on the insulating layer 502 is removed by a method such as CMP, thereby forming wiring 517 with a dual damascene structure as shown in FIG. 15I.

[0101] The manufacturing method of this embodiment allows the use of a hard mask, which makes it possible to form finer patterns with high precision, which is particularly useful when the etching selectivity between the resist pattern 506 and the material layer ML cannot be ensured in the step of forming a via hole.

[0102] Ninth Embodiment A method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 16A to 16D. The manufacturing method shown in Figures 16A to 16D corresponds to that shown in Figures 14A to 14D. The manufacturing method according to this embodiment differs from the manufacturing method described with reference to Figures 14A to 14D in that it includes a step of forming an SOC film 530 after the step of applying material IM. This embodiment will be described below with reference to Figures 16A to 16D, but detailed descriptions of configurations and steps similar to those shown in Figures 14A to 14D will be omitted.

[0103] 16A and 16B show the same process steps as those shown in FIGS. 14A and 14B. After applying and curing the material IM to form the material layer ML, the SOC film 530 is formed (FIG. 16C). Because the SOC film 530 is formed on the highly planar material layer ML, it also has high planarity. Next, as shown in FIG. 16D, a film 531 serving as a hard mask is formed on the SOC film 530. This film 531 has the same function as the film 503 shown in FIG. 14D. After the process shown in FIG. 16D, the same process steps as those shown in FIGS. 15A to 15I are performed. The SOC film can be removed together with the material layer ML in the process shown in FIG. 15G.

[0104] 16D, the film 531 serving as the hard mask may be omitted. Furthermore, by making the SOC film of this embodiment function as a hard mask, highly accurate etching can be performed even when a sufficient etching selectivity between the material layer ML and the photoresist cannot be obtained.

[0105] Tenth Embodiment A method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 17A to 17D. The manufacturing method shown in Figures 17A to 17D corresponds to that shown in Figures 14A to 14D. The manufacturing method according to this embodiment differs from the manufacturing method described with reference to Figures 14A to 14D in that it includes a step of forming an SOC film 540 before the step of applying material IM. The following description will be given with reference to Figures 17A to 17D, but detailed descriptions of configurations and steps similar to those shown in Figures 14A to 14D will be omitted.

[0106] FIG. 17A shows a process similar to that shown in FIG. 14A. Next, in FIG. 17B, an SOC film 540 is formed to fill the opening 503. The upper surface of the SOC film 540 may have a recess 541 corresponding to the position of the opening 503. Forming photoresist on such a recess 541 may result in poor resolution. Next, as shown in FIG. 17C, a material IM is applied to the SOC film 540. At this time, a larger amount is applied to the portion corresponding to the recess 541 than to the other portions. Then, as in the previous embodiments, the material IM is planarized and hardened to form a material layer ML with high flatness. Then, a film 542 is formed on the material layer ML (FIG. 17D). This film 542 has the same function as the film 503 in FIG. 14D. After the process shown in FIG. 17D, the same configuration as that shown in FIGS. 15A to 15I is performed. Note that the SOC film can be removed together with the material layer ML in the process shown in FIG. 15G.

[0107] According to the manufacturing method of this embodiment, the deep opening 503 is filled with the SOC film 540, and the recess 541 shallower than the opening 503 is planarized. This facilitates the planarization process and the exposure process when forming the material layer ML.

[0108] 17D, the film 542 serving as a hard mask may be omitted. By adjusting the etching selectivity between the SOC film 540 and the material IM, the material layer ML of this embodiment may also function as a hard mask.

[0109] Eleventh Embodiment This embodiment describes an application example using a semiconductor device manufactured by the manufacturing method of any one of the first to tenth embodiments. The semiconductor device 910 is, for example, a CMOS image sensor.

[0110] 18A is a schematic diagram illustrating a device 9191 as an application example. The device 9191 has an imaging device 930. The imaging device 930 includes a semiconductor device 910 and a package 920 that houses the semiconductor device 910. The semiconductor device 910 can be manufactured by the manufacturing method of another embodiment. The package 920 can include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910.

[0111] The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the base and terminals provided on the semiconductor device 910 .

[0112] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the imaging device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the imaging device 930. The control device 950 controls the imaging device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0113] The processing device 960 processes the signal output from the imaging device 930. The processing device 960 is a semiconductor processing device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the imaging device 930. The storage device 980 is a magnetic device or other semiconductor device that stores information (images) obtained by the imaging device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0114] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the imaging device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a storage device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the imaging device 930. The mechanical device 990 may be controlled based on the signal output from the imaging device 930.

[0115] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the imaging device 930 for vibration isolation operations.

[0116] Furthermore, the equipment 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The equipment 9191 as transportation equipment is suitable for transporting the imaging device 930 or for assisting and / or automating driving (piloting) using an imaging function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device 990 as a moving device based on information obtained by the imaging device 930. Alternatively, the equipment 9191 may be a medical device such as an endoscope, a measuring device such as a distance sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0117] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0118] Therefore, using the imaging device 930 according to this embodiment in the equipment 9191 can also improve the value of the equipment. For example, by installing the imaging device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the imaging device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0119] Next, a moving object will be described as another application example. FIG. 18B shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 800 includes a semiconductor device 80. The semiconductor device 80 is, for example, a photoelectric conversion device (image capture device). The photoelectric conversion system 800 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the semiconductor device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 800. Here, the photoelectric conversion system 800 may include an optical system (not shown) that guides light to the semiconductor device 80, such as a lens, shutter, or mirror. Furthermore, multiple photoelectric conversion units that are approximately conjugate with the pupil of the optical system may be arranged in pixels of the semiconductor device 80. For example, the multiple photoelectric conversion units that are approximately conjugate with the pupil are arranged corresponding to one microlens. The multiple photoelectric conversion units receive light beams that have passed through different positions of the pupil of the optical system, and the semiconductor device 80 outputs image data corresponding to the light beams that have passed through different positions. The parallax acquisition unit 802 may then calculate parallax using the output image data. The photoelectric conversion system 800 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to the object. In other words, the distance information includes information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may use any of this distance information to determine the possibility of a collision. The distance information may be acquired by ToF (Time of Flight). The distance information acquisition means may be implemented by dedicated hardware or a software module. It may also be realized by a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), or by a combination of these.

[0120] The photoelectric conversion system 800 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 800 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 800 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0121] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 800. Fig. 18C shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 800 or the semiconductor device 80. This configuration can further improve the accuracy of distance measurement.

[0122] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles or automatic driving to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system 800 can be applied not only to vehicles such as automobiles, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generating unit that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generating unit can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, an aircraft's propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0123] The equipment of this embodiment may be transportation equipment such as a vehicle, a ship, or an aircraft. A mechanical device in transportation equipment can be used as a moving device. Equipment as transportation equipment is suitable for transporting semiconductor devices and for assisting and / or automating driving (piloting) using a photographing function. A processing device for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device as a moving device based on information obtained from the semiconductor device.

[0124] In this embodiment, a photoelectric conversion device has been described as an example of a semiconductor device, but other semiconductor devices may be used, or both may be used.

[0125] As described above, according to the present disclosure, it is possible to improve the accuracy of forming at least one of the wiring trench and the via hole.

[0126] The configurations described in this disclosure can be combined as appropriate.

[0127] The present invention is not limited to the above-described embodiments, and various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the following claims are appended to apprise the public of the scope of the present invention.

[0128] This application claims priority based on Japanese Patent Application No. 2024-118657 filed on July 24, 2024 and Japanese Patent Application No. 2025-083253 filed on May 19, 2025, the entire contents of which are incorporated herein by reference.

Claims

1. A method for forming dual damascene wiring trenches and via holes, comprising the steps of: applying a precursor to at least one insulating layer having a hole formed therein that will become the via hole, so that the amount applied to the hole is greater than that to other parts, thereby forming a first film having a flat upper surface; and patterning the first film when forming a groove in the insulating layer that will become the wiring trench.

2. A method for forming dual damascene wiring trenches and via holes, comprising the steps of: applying a precursor to at least one insulating layer in which a groove that will become the wiring trench is formed, so that the amount applied to the groove is greater than that to other parts, to form a first film having a flat upper surface; and patterning the first film when forming a hole that will become the via hole in the insulating layer.

3. The method for forming dual damascene wiring trenches and via holes according to claim 1 or 2, characterized in that in the step of forming the first film, the upper surface of the precursor is planarized and hardened to have a flat upper surface.

4. A method for forming dual damascene wiring trenches and via holes according to any one of claims 1 to 3, characterized in that it comprises the steps of forming a photoresist film on the first film and exposing it to EUV to form a resist pattern, etching the first film using the resist pattern as a mask, and further etching the insulating layer.

5. A method for forming a dual damascene wiring trench and via hole according to any one of claims 1 to 3, characterized in that it comprises the steps of: forming a second film after the step of forming the first film; forming a photoresist film on the second film and exposing it to EUV to form a resist pattern; etching the second film using the resist pattern as a mask; and etching the insulating layer using the second film as a mask.

6. The method for forming dual damascene wiring trenches and via holes according to claim 4 or 5, wherein the numerical aperture NA of the EUV exposure is greater than 0.

55.

7. A method for forming dual damascene wiring trenches and via holes as described in any one of claims 1 to 6, characterized in that after the step of forming the first film, a step of forming a third film on the first film by spin coating is included.

8. A method for manufacturing a semiconductor device, comprising the steps of: applying a precursor onto an insulating layer disposed on a semiconductor layer, with the amount of precursor increasing according to the depressions in the upper surface of the insulating layer, flattening the upper surface, and hardening the precursor to form a first film; and patterning the first film to form wiring grooves in the insulating layer.

9. A method for manufacturing a semiconductor device as described in claim 8, characterized by comprising the steps of: forming a conductive film on the first film so as to fill the wiring groove; and removing the conductive film disposed on the first film, and forming a first wiring disposed on the first film.

10. A method for manufacturing a semiconductor device according to claim 9, comprising the steps of: applying a precursor onto a second insulating layer disposed on a semiconductor layer other than the semiconductor layer, with the amount of precursor increasing according to the depression in the upper surface of the second insulating layer, planarizing the upper surface, and curing the precursor to form a second film; patterning the second film to form a second wiring groove in the second insulating layer; forming a conductive film on the second film so as to fill the second wiring groove; removing the conductive film disposed on the second film and forming a second wiring disposed on the second film; and, after the steps of forming the first wiring disposed on the first film and forming the second wiring disposed on the second film, aligning and bonding the exposed surface of the first wiring and the exposed surface of the second wiring.

11. A method for forming dual damascene wiring trenches and via holes, comprising the steps of: forming a coating film on at least one insulating layer in which a groove that will become the wiring trench or a hole that will become the via hole has been formed; applying a precursor to the coating film so that the amount applied to recesses in the upper surface of the coating film is greater than that applied to other portions, thereby forming a first film having a flat upper surface; and patterning the first film when forming holes that will become the via holes or grooves that will become the wiring trenches in the insulating layer.

12. The method for forming a dual damascene wiring trench and via hole according to claim 11, wherein the coating film is formed by spin coating.

13. A method for forming dual damascene wiring trenches and via holes as described in claim 11 or 12, characterized in that it comprises the steps of forming a photoresist film on the first film and exposing it to EUV to form a resist pattern, etching the first film using the resist pattern as a mask, and further etching the insulating layer.

14. The method for forming a dual damascene wiring trench and via hole according to claim 13, wherein the EUV exposure has a numerical aperture NA greater than 0.55.

Images