Method for manufacturing circuit board for semiconductor package

Abstract

Provided is a novel method for manufacturing a circuit board for a semiconductor package capable of forming a conductor circuit with good insulation reliability in a fine pattern on a semiconductor chip mounting surface. The manufacturing method comprises (X) a step for performing the following steps (X1) through (X3) in this order: (X1) forming a first conductor circuit on a metal layer of a base material with the metal layer; (X2) forming a barrier film on a surface of the first conductor circuit formed on the metal layer to form the first conductor circuit with the barrier film; and (X3) forming a resin composition layer from a resin composition containing a curable resin so as to embed the first conductor circuit with the barrier film formed on the metal layer, and forming an insulation layer by curing the resin composition layer, thereby forming a first circuit board, which has, on the first main surface side thereof, the first conductor circuit with the barrier film, on the base material with the metal layer, (Y) a step for performing the following steps (Y1) and (Y2) in this order: (Y1) removing the base material with the metal layer to form the first circuit board having the first main surface on which the first conductor circuit is exposed; and (Y2) forming a barrier film on the exposed surface of the first conductor circuit, thereby forming the first circuit board having the first conductor circuit covered with the barrier film on the first main surface side, and (Z) a step for joining a core circuit board and the first circuit board so that a second main surface of the first circuit board opposite to the first main surface faces a first main surface of the core circuit board.

Description

Manufacturing method of circuit board for semiconductor package

[0001] The present invention relates to a method for manufacturing a circuit board for a semiconductor package.

[0002] 2. Description of the Related Art With the aim of improving the functionality and performance of semiconductor devices, packaging techniques relating to semiconductor packages (multi-chip packages) in which multiple semiconductor chips are mounted on a single substrate have been proposed.

[0003] For example, a technology related to so-called 2.5D packaging is known, in which multiple semiconductor chips are integrated on a silicon interposer and the silicon interposer is mounted on a package circuit board. The silicon interposer has fine circuits manufactured by a semiconductor process on its surface, on which the semiconductor chips are mounted, and has connection terminals and circuits on its back surface, which is bonded to the package circuit board. These circuits on the surface and back surface are electrically connected by through-silicon vias (TSVs) that penetrate the silicon substrate. 2.5D packaging using a silicon interposer has problems such as high component costs and poor manufacturing efficiency when manufacturing a rectangular silicon interposer, due to the fact that the silicon interposer is manufactured from a circular silicon wafer.

[0004] Therefore, a technology related to so-called 2.1D mounting, which uses an organic interposer manufactured using an extension technology of conventional organic substrates instead of a silicon interposer, is expected to reduce costs and improve manufacturing efficiency (for example, Patent Document 1).

[0005] International Publication No. 2017 / 163743

[0006] The challenge in 2.1D packaging technology is to form fine circuits similar to those of silicon interposers on the semiconductor chip mounting surface of an organic interposer. Specifically, fine circuits with a minimum line and space (L / S) of 5 / 5 μm or less are required.

[0007] However, conventional organic substrate manufacturing techniques, in which a conductor layer is formed on an insulating layer, can sometimes make it difficult to achieve finer wiring.

[0008] Furthermore, in organic substrates, the conductive metal material constituting the circuit may diffuse into the organic insulating layer. Therefore, when forming a fine circuit with a low L / S ratio, the diffused conductive metal material may cause a short circuit in the circuit, raising concerns about insulation reliability. To prevent short circuits in the fine circuit, a technique for forming a fine circuit using the damascene method involves forming a groove for the circuit in the organic insulating layer, providing a barrier film (a film that prevents the conductive metal material constituting the circuit from diffusing into the organic insulating layer), depositing the conductive metal material by plating or the like, and then polishing the surface to leave the conductive metal material only in the groove, thereby forming a circuit with a barrier film. However, considering the application of the damascene method to later semiconductor processes, the process is somewhat complicated, and a simpler method is desired. In this regard, although it is possible to provide a barrier film when forming a circuit using the semi-additive method, the following constraints may be imposed. In other words, when forming circuits using the semi-additive process, a barrier film is formed on the surface of an organic insulating layer after a conductor circuit is formed on the organic insulating layer. However, if a barrier film with low conductivity, such as a metal oxide, is formed, the barrier film will also be present on the surface of the conductor circuit corresponding to the via opening during subsequent interlayer connection, which may cause concerns about electrical conductivity reliability. Even when a barrier film made of a metal exhibiting sufficient conductivity is formed, there are only limited metals that can be preferentially and selectively deposited only on the surface of the conductor circuit formed on the organic insulating layer, leaving room for improvement in terms of the flexibility of material selection. Furthermore, NiP is a typical metal material that can be preferentially and selectively deposited only on the surface of the conductor circuit, but because Ni is a magnetic material, it may have a negative impact on signal quality when forming fine circuits with low L / S.

[0009] The present invention provides a novel method for manufacturing a circuit board for a semiconductor package, which enables a conductor circuit with excellent insulation reliability to be formed in a fine pattern on a semiconductor chip mounting surface in a simple manner with a high degree of freedom.

[0010] As a result of extensive research into solving the above problems, the present inventors have found that the above problems can be solved by a method for manufacturing a circuit board having the following configuration, and have thus completed the present invention.

[0011] That is, the present invention includes the following. <1> (X) a step of forming a first circuit board on a first main surface of a substrate with a metal layer, the step of forming a first conductive circuit on the first main surface of the substrate with a metal layer, the step of forming a first conductive circuit on the first main surface of the substrate with a barrier film by forming a barrier film on the surface of the first conductive circuit formed on the metal layer, and the step of curing the resin composition layer to form an insulating layer, in this order; (Y) a step of forming a first circuit board on a substrate with a metal layer, the step of forming a first conductive circuit on the first main surface of the substrate with a barrier film by forming a first conductive circuit on the first main surface of the ... (Z) joining a core circuit board and a first circuit board so that a second main surface of the first circuit board, the second main surface being opposite to the first main surface of the core circuit board, faces the first main surface of the core circuit board. <2> The method according to <1>, in which step (Z) is performed after step (Y). <3> The method according to <1>, in which step (Z) is performed between step (X) and step (Y). <4> The method according to any one of <1> to <3>, in which the curable resin is a thermosetting resin. <5> The method according to any one of <1> to <4>, in which the thermosetting resin is an epoxy resin. <6> The method according to any one of <1> to <5>, in which the resin composition contains a curing agent. <7> The method according to any one of <1> to <6>, in which the resin composition contains an inorganic filler. <8> The method according to any one of <1> to <7>, wherein the content of the inorganic filler in the resin composition is 20% by mass or more and 75% by mass or less, when the total amount of non-volatile components in the resin composition is 100% by mass. <9> The method according to any one of <1> to <8>, wherein the thickness of the metal layer is less than 1 μm. <10> The method according to any one of <1> to <9>, wherein, in the substrate with a metal layer, the substrate is selected from a metal substrate, an inorganic substrate, and an organic substrate having a composition different from that of the metal layer.<11> The method according to any one of <1> to <10>, wherein the barrier film is a barrier film made of one or more materials selected from the group consisting of metals and metal oxides. <12> The method according to any one of <1> to <11>, wherein (Y1) is carried out by removing the substrate and then removing the metal layer. <13> The method according to any one of <1> to <12>, wherein (X1) comprises: (X1-1) providing a photoresist on the metal layer, and exposing and developing the photoresist to expose the metal layer in a manner corresponding to the circuit pattern of the first conductive circuit to be formed, and (X1-2) forming a conductor layer on the exposed metal layer to form the first conductor circuit. <14> The method according to any one of <1> to <13>, wherein the first conductor circuit comprises a trench-type conductor circuit. <15> The method according to any one of <1> to <14>, wherein (X3) comprises laminating a resin sheet comprising a support film and a resin composition layer provided on the support film onto the substrate such that the resin composition layer is bonded to the barrier film-covered first conductor circuit. <16> The method according to any one of <1> to <15>, comprising, after (X3), (i) forming a second conductor circuit on the surface of the insulating layer, and (ii) forming a resin composition layer so as to embed the second conductor circuit, and curing the resin composition layer to form an insulating layer. <17> The method according to any one of <1> to <16>, comprising, after (Y2), (Y3) forming a resin insulating layer on the first main surface of the first circuit board, and (Y4) forming an electrode pattern on the resin insulating layer, thereby forming a semiconductor chip mounting surface on the first main surface side of the first circuit board. <18> The method according to any one of <1> to <17>, wherein the minimum line and space (L / S) of the first conductor circuit is 2 / 2 μm or less. <19> The method according to any one of <1> to <18>, wherein the core circuit board is selected from the group consisting of a copper-clad laminate, a glass substrate, a ceramic substrate, a metal substrate, a flexible substrate, and a component-embedded substrate. <20> The method according to any one of <1> to <19>, wherein in step (Z), the core circuit board and the first circuit board are joined by one or more joining methods selected from the group consisting of solder joining, adhesive joining, and hybrid bonding. <21> The method according to any one of <1> to <20>, for producing a circuit board for a multi-chip package.

[0012] According to the present invention, it is possible to provide a novel method for manufacturing a circuit board for a semiconductor package, which is capable of easily and with a high degree of freedom forming a conductor circuit with good insulation reliability in a fine pattern on the semiconductor chip mounting surface.

[0013] FIG. 1 is a schematic diagram (1) for explaining a manufacturing method of a circuit board for a semiconductor package in one embodiment of the present invention (hereinafter simply referred to as the "manufacturing method of the present invention"). FIG. 2 is a schematic diagram (2) for explaining the manufacturing method of the present invention. FIG. 3 is a schematic diagram (3) for explaining the manufacturing method of the present invention. FIG. 4 is a schematic diagram (4) for explaining the manufacturing method of the present invention. FIG. 5 is a schematic diagram (5) for explaining the manufacturing method of the present invention. FIG. 6 is a schematic diagram (6) for explaining the manufacturing method of the present invention. FIG. 7 is a schematic diagram (7) for explaining the manufacturing method of the present invention. FIG. 8 is a schematic diagram (8) for explaining the manufacturing method of the present invention. FIG. 9 is a schematic diagram (9) for explaining the manufacturing method of the present invention. FIG. 10 is a schematic diagram (10) for explaining the manufacturing method of the present invention. FIG. 11 is a schematic diagram (11) for explaining the manufacturing method of the present invention. FIG. 12 is a schematic diagram (12) for explaining the manufacturing method of the present invention. FIG. 13 is a schematic diagram (13) for explaining the manufacturing method of the present invention. FIG. 14 is a schematic diagram (14) for explaining the manufacturing method of the present invention. FIG. 15 is a schematic diagram (15) for explaining the manufacturing method of the present invention. FIG. 16 is a schematic diagram (16) for explaining the manufacturing method of the present invention. FIG. 17 is a schematic diagram (17) for explaining the manufacturing method of the present invention. FIG. 18 is a schematic diagram (18) for explaining the manufacturing method of the present invention. FIG. 19 is a schematic diagram (19) for explaining the manufacturing method of the present invention. FIG. 20 is a schematic diagram (20) for explaining the manufacturing method of the present invention. FIG. 21 is a schematic diagram (21) for explaining the manufacturing method of the present invention. FIG. 22 is a schematic diagram (22) for explaining the manufacturing method of the present invention. FIG. 23 is a schematic diagram (23) for explaining the manufacturing method of the present invention. FIG. 24 is a schematic diagram (24) for explaining the manufacturing method of the present invention. FIG. 25 is a schematic diagram (25) for explaining the manufacturing method of the present invention. FIG. 26 is a schematic diagram (26) for explaining the manufacturing method of the present invention. Fig. 27 is a schematic diagram (27) for explaining the manufacturing method of the present invention. Fig. 28 is a schematic diagram (28) for explaining the manufacturing method of the present invention. Fig. 29 is a schematic diagram (29) for explaining the manufacturing method of the present invention. Fig. 30 is a schematic diagram (30) for explaining the manufacturing method of the present invention.Figure 30 is also a schematic diagram for explaining a circuit board for a semiconductor package according to one embodiment of the present invention. Figure 31 is a schematic diagram (31) for explaining the manufacturing method of the present invention. Figure 31 is also a schematic diagram for explaining a semiconductor package according to one embodiment of the present invention. Figure 32 is a schematic diagram (32) for explaining the manufacturing method of the present invention. Figure 33 is a schematic diagram (33) for explaining the manufacturing method of the present invention. Figure 34 is a schematic diagram (34) for explaining the manufacturing method of the present invention. Figure 35 is a schematic diagram (35) for explaining the manufacturing method of the present invention. Figure 36 is a schematic diagram (36) for explaining the manufacturing method of the present invention. Figure 37 is a schematic diagram (37) for explaining the manufacturing method of the present invention. Figure 38 is a schematic diagram (38) for explaining the manufacturing method of the present invention. Figure 39 is a schematic diagram (39) for explaining the manufacturing method of the present invention. Figure 40 is a schematic diagram (40) for explaining the manufacturing method of the present invention.

[0014] Before describing in detail the method for producing a circuit board for a semiconductor package of the present invention, the "resin composition" used in the production method of the present invention will be described.

[0015] <Resin Composition> In the method for manufacturing a circuit board for a semiconductor package of the present invention, a resin composition layer is formed so as to embed the barrier film-covered first conductor circuit, and the resin composition layer is cured to form an insulating layer. Here, the resin composition layer is formed using a resin composition containing one or more resins selected from the group consisting of a curable resin, preferably a thermosetting resin and a radically polymerizable resin. From the viewpoints of being able to form the resin composition layer so as to embed the barrier film-covered first conductor circuit and exhibiting sufficient insulating properties after curing, the resin composition layer is preferably formed using a resin composition containing a thermosetting resin, more preferably formed using a resin composition containing a thermosetting resin and one or more inorganic fillers in addition to the thermosetting resin, and even more preferably formed using a resin composition containing an epoxy resin, a curing agent, and an inorganic filler.

[0016] -Curable Resin- As the curable resin, a known resin used in forming an insulating layer of a semiconductor chip package may be used, but it is preferably one or more selected from the group consisting of thermosetting resins and radically polymerizable resins. Furthermore, one type of curable resin may be used alone, or two or more types may be used in combination.

[0017] -Thermosetting Resin- As the thermosetting resin, a resin that can be cured when heat is applied can be used. Examples of thermosetting resins include epoxy resins, benzocyclobutene resins, epoxy acrylate resins, urethane acrylate resins, urethane resins, cyanate resins, polyimide resins, benzoxazine resins, unsaturated polyester resins, phenolic resins, melamine resins, and silicone resins. The thermosetting resins may be used alone or in combination of two or more. Among these, from the viewpoint of significantly achieving the effects of the present invention, it is preferable that the thermosetting resin contains an epoxy resin.

[0018] -Epoxy Resin- Examples of epoxy resins include bixylenol type epoxy resins, bisphenol A type epoxy resins, bisphenol F type epoxy resins, bisphenol S type epoxy resins, bisphenol AF type epoxy resins, dicyclopentadiene type epoxy resins, trisphenol type epoxy resins, naphthol novolac type epoxy resins, phenol novolac type epoxy resins, tert-butyl-catechol type epoxy resins, naphthalene type epoxy resins, naphthol type epoxy resins, anthracene type epoxy resins, glycidylamine type epoxy resins, glycidyl ester type epoxy resins, cresol novolac type epoxy resins, biphenyl type epoxy resins, linear aliphatic epoxy resins, epoxy resins having a butadiene structure, alicyclic epoxy resins, heterocyclic epoxy resins, spiro ring-containing epoxy resins, cyclohexane type epoxy resins, cyclohexane dimethanol type epoxy resins, naphthylene ether type epoxy resins, trimethylol type epoxy resins, and tetraphenylethane type epoxy resins. These epoxy resins may be used alone or in combination of two or more.

[0019] The curable resin preferably contains an epoxy resin having two or more epoxy groups per molecule as the epoxy resin. From the viewpoint of significantly achieving the desired effects of the present invention, the proportion of the epoxy resin having two or more epoxy groups per molecule is preferably 50% by mass or more, more preferably 60% by mass or more, and particularly preferably 70% by mass or more, relative to 100% by mass of the non-volatile components of the epoxy resin.

[0020] Epoxy resins are classified into epoxy resins that are liquid at a temperature of 20°C (hereinafter referred to as "liquid epoxy resins") and epoxy resins that are solid at a temperature of 20°C (hereinafter referred to as "solid epoxy resins"). The resin composition may contain only a liquid epoxy resin or only a solid epoxy resin as the epoxy resin, but from the viewpoint of significantly achieving the effects of the present invention, it is preferable to contain a combination of a liquid epoxy resin and a solid epoxy resin.

[0021] The liquid epoxy resin is preferably a liquid epoxy resin having two or more epoxy groups in one molecule.

[0022] Preferred liquid epoxy resins include bisphenol A type epoxy resins, bisphenol F type epoxy resins, bisphenol AF type epoxy resins, naphthalene type epoxy resins, glycidyl ester type epoxy resins, glycidyl amine type epoxy resins, phenol novolac type epoxy resins, alicyclic epoxy resins having an ester skeleton, cyclohexane type epoxy resins, cyclohexanedimethanol type epoxy resins, glycidyl amine type epoxy resins, and epoxy resins having a butadiene structure, and more preferred are bisphenol A type epoxy resins and bisphenol F type epoxy resins.

[0023] Specific examples of liquid epoxy resins include "HP4032," "HP4032D," and "HP4032SS" (naphthalene type epoxy resins) manufactured by DIC Corporation; "828US," "jER828EL," "825," and "Epikote 828EL" (bisphenol A type epoxy resins) manufactured by Mitsubishi Chemical Corporation; "jER807" and "1750" (bisphenol F type epoxy resins) manufactured by Mitsubishi Chemical Corporation; "jER152" (phenol novolac type epoxy resin) manufactured by Mitsubishi Chemical Corporation; and "630" and "630LSD" (glycidylamine type epoxy resins) manufactured by Mitsubishi Chemical Corporation. ); "ZX1059" (a mixture of bisphenol A epoxy resin and bisphenol F epoxy resin) manufactured by Nippon Steel Chemical & Material Corporation; "EX-721" (glycidyl ester epoxy resin) manufactured by Nagase ChemteX Corporation; "Celloxide 2021P" (alicyclic epoxy resin having an ester skeleton) manufactured by Daicel Corporation; "PB-3600" (epoxy resin having a butadiene structure) manufactured by Daicel Corporation; and "ZX1658" and "ZX1658GS" (liquid 1,4-glycidylcyclohexane epoxy resin) manufactured by Nippon Steel Chemical & Material Corporation. These may be used alone or in combination of two or more.

[0024] As the solid epoxy resin, a solid epoxy resin having three or more epoxy groups in one molecule is preferred, and an aromatic solid epoxy resin having three or more epoxy groups in one molecule is more preferred.

[0025] As the solid epoxy resin, bixylenol type epoxy resin, naphthalene type epoxy resin, naphthalene type tetrafunctional epoxy resin, cresol novolac type epoxy resin, dicyclopentadiene type epoxy resin, trisphenol type epoxy resin, naphthol type epoxy resin, biphenyl type epoxy resin, naphthylene ether type epoxy resin, anthracene type epoxy resin, bisphenol A type epoxy resin, bisphenol AF type epoxy resin, and tetraphenylethane type epoxy resin are preferred, and bixylenol type epoxy resin, naphthalene type epoxy resin, naphthylene ether type epoxy resin, and bisphenol AF type epoxy resin are more preferred.

[0026] Specific examples of solid epoxy resins include "HP4032H" (naphthalene type epoxy resin), "HP-4700", "HP-4710" (naphthalene type tetrafunctional epoxy resin), "N-690" (cresol novolac type epoxy resin), "N-695" (cresol novolac type epoxy resin), "HP-7200", "HP-7200HH", and "HP-7200H" (dicyclopentadiene type epoxy resin), all manufactured by DIC Corporation. "EXA-7311", "EXA-7311-G3", "EXA-7311-G4", "EXA-7311-G4S", "HP6000", "HP6000L" (naphthylene ether type epoxy resins); "EPPN-502H" (trisphenol type epoxy resin), "NC7000L" (naphthol novolac type epoxy resin), "NC3000H" manufactured by Nippon Kayaku Co., Ltd.; Examples include "NC3000," "NC3000L," and "NC3100" (biphenyl-type epoxy resins); "ESN475V" (naphthalene-type epoxy resin) and "ESN485" (naphthol novolac-type epoxy resin) manufactured by Nippon Steel Chemical & Material Co., Ltd.; "YX4000H," "YL6121" (biphenyl-type epoxy resin), "YX4000HK" (bixylenol-type epoxy resin), and "YX8800" (anthracene-type epoxy resin) manufactured by Mitsubishi Chemical Corporation; "PG-100" and "CG-500" manufactured by Osaka Gas Chemicals Co., Ltd.; and "YX7760" (bisphenol AF-type epoxy resin), "YL7800" (fluorene-type epoxy resin), "jER1010" (solid bisphenol A-type epoxy resin), and "jER1031S" (tetraphenylethane-type epoxy resin) manufactured by Mitsubishi Chemical Corporation. These may be used alone or in combination of two or more.

[0027] When a liquid epoxy resin and a solid epoxy resin are used in combination as the epoxy resin, the ratio by mass of the liquid epoxy resin to the solid epoxy resin (liquid epoxy resin:solid epoxy resin) is preferably 1:0.1 to 1:20, more preferably 1:0.3 to 1:15, and particularly preferably 1:0.5 to 1:10. When the ratio of the liquid epoxy resin to the solid epoxy resin is within this range, the desired effects of the present invention can be significantly achieved. Furthermore, when used in the form of a resin sheet, appropriate adhesiveness is typically imparted. Furthermore, when used in the form of a resin sheet, sufficient flexibility is typically obtained, improving handleability. Furthermore, a cured product having sufficient breaking strength can typically be obtained.

[0028] The epoxy equivalent of the epoxy resin is preferably 50 g / eq. to 5000 g / eq., more preferably 50 g / eq. to 3000 g / eq., even more preferably 80 g / eq. to 2000 g / eq., and even more preferably 110 g / eq. to 1000 g / eq. By having it within this range, a cured product of the resin composition can be obtained with sufficient crosslinking density. The epoxy equivalent is the mass of an epoxy resin containing one equivalent of epoxy groups. This epoxy equivalent can be measured in accordance with JIS K7236.

[0029] From the viewpoint of significantly achieving the desired effects of the present invention, the weight average molecular weight (Mw) of the epoxy resin is preferably 100 to 5000, more preferably 250 to 3000, and even more preferably 400 to 1500. The weight average molecular weight of the epoxy resin is a weight average molecular weight in terms of polystyrene measured by gel permeation chromatography (GPC).

[0030] -Radical Polymerizable Resin- The type of radical polymerizable resin is not particularly limited, as long as it has one or more (preferably two or more) radical polymerizable unsaturated groups per molecule. Examples of the radical polymerizable resin include resins having, as the radical polymerizable unsaturated group, one or more selected from a maleimide group, a vinyl group, an allyl group, a styryl group, a vinylphenyl group, an acryloyl group, a methacryloyl group, a fumaroyl group, and a maleoyl group. Among these, from the viewpoint of significantly achieving the effects of the present invention, it is preferable that the radical polymerizable resin contains one or more selected from a maleimide resin, a (meth)acrylic resin, and a styryl resin.

[0031] The type of maleimide resin is not particularly limited as long as it has one or more (preferably two or more) maleimide groups (2,5-dihydro-2,5-dioxo-1H-pyrrol-1-yl groups) in one molecule. Examples of maleimide resins include maleimide resins containing an aliphatic skeleton having 36 carbon atoms derived from dimer diamine, such as "BMI-3000J," "BMI-5000," "BMI-1400," "BMI-1500," "BMI-1700," and "BMI-689" (all manufactured by DigiCner Molecules, Inc.); maleimide resins containing an indane skeleton, as described in the Japan Institute of Invention and Innovation Disclosure Technical Bulletin No. 2020-500211; and maleimide resins containing an aromatic ring skeleton directly bonded to the nitrogen atom of the maleimide group, such as "MIR-3000-70MT" (manufactured by Nippon Kayaku Co., Ltd.), "BMI-4000" (manufactured by Daiwa Kasei Co., Ltd.), and "BMI-80" (manufactured by Keiai Kasei Co., Ltd.).

[0032] The (meth)acrylic resin is not particularly limited in type, and may be a monomer or oligomer, as long as it has one or more (preferably two or more) (meth)acryloyl groups in one molecule. Here, the term "(meth)acryloyl group" is a general term for acryloyl groups and methacryloyl groups. Examples of methacrylic resins include (meth)acrylic resins such as "A-DOG" (manufactured by Shin-Nakamura Chemical Co., Ltd.), "DCP-A" (manufactured by Kyoeisha Chemical Co., Ltd.), "NPDGA", "FM-400", "R-687", "THE-330", "PET-30", and "DPHA" (all manufactured by Nippon Kayaku Co., Ltd.).

[0033] The styryl resin is not particularly limited in type, and may be a monomer or oligomer, as long as it has one or more (preferably two or more) styryl groups or vinylphenyl groups in one molecule. Examples of the styryl resin include styryl resins such as "OPE-2St," "OPE-2St 1200," and "OPE-2St 2200" (all manufactured by Mitsubishi Gas Chemical Company, Inc.).

[0034] In the resin composition, the curable resin may contain only a thermosetting resin, may contain only a radical polymerizable resin, or may contain a combination of a thermosetting resin and a radical polymerizable resin.

[0035] From the viewpoint of obtaining a cured product exhibiting good mechanical strength and insulation reliability, the content of the curable resin is preferably 10% by mass or more, more preferably 15% by mass or more, and even more preferably 20% by mass or more, where the non-volatile components in the resin composition are taken as 100% by mass. From the viewpoint of significantly obtaining the desired effects of the present invention, the upper limit is preferably 90% by mass or less, more preferably 85% by mass or less, and particularly preferably 45% by mass or less, 40% by mass or less, or 35% by mass or less.

[0036] From the viewpoint of obtaining the effects of the present invention remarkably, the content of the curable resin is preferably 20% by mass or more, more preferably 30% by mass or more, even more preferably 40% by mass or more or 50% by mass or more, and is preferably 90% by mass or less, more preferably 85% by mass or less, even more preferably 80% by mass or less, when the resin component in the resin composition is taken as 100% by mass. In the present invention, the "resin component" in the resin composition refers to the non-volatile components constituting the resin composition, excluding the inorganic filler described below.

[0037] -Curing Agent- From the viewpoint of significantly achieving the effects of the present invention, the resin composition preferably contains a compound capable of reacting with the curable resin to cure the resin composition. A compound capable of reacting with the curable resin to cure the resin composition will be referred to as a "curing agent" hereinafter. Examples of such curing agents include active ester-based curing agents, phenol-based curing agents, naphthol-based curing agents, benzoxazine-based curing agents, cyanate ester-based curing agents, carbodiimide-based curing agents, amine-based curing agents, and acid anhydride-based curing agents. One type of curing agent may be used alone, or two or more types may be used in combination.

[0038] As the active ester curing agent, a compound having one or more active ester groups per molecule can be used. Among them, as the active ester curing agent, a compound having two or more highly reactive ester groups per molecule, such as phenol esters, thiophenol esters, N-hydroxyamine esters, and esters of heterocyclic hydroxy compounds, is preferred. The active ester curing agent is preferably one obtained by a condensation reaction between a carboxylic acid compound and / or a thiocarboxylic acid compound and a hydroxy compound and / or a thiol compound. In particular, from the viewpoint of improving heat resistance, an active ester curing agent obtained from a carboxylic acid compound and a hydroxy compound is preferred, and an active ester curing agent obtained from a carboxylic acid compound and a phenol compound and / or a naphthol compound is more preferred.

[0039] Examples of the carboxylic acid compound include benzoic acid, acetic acid, succinic acid, maleic acid, itaconic acid, phthalic acid, isophthalic acid, terephthalic acid, and pyromellitic acid.

[0040] Examples of phenol compounds or naphthol compounds include hydroquinone, resorcinol, bisphenol A, bisphenol F, bisphenol S, phenolphthalene, methylated bisphenol A, methylated bisphenol F, methylated bisphenol S, phenol, o-cresol, m-cresol, p-cresol, catechol, α-naphthol, β-naphthol, 1,5-dihydroxynaphthalene, 1,6-dihydroxynaphthalene, 2,6-dihydroxynaphthalene, dihydroxybenzophenone, trihydroxybenzophenone, tetrahydroxybenzophenone, phloroglucin, benzenetriol, dicyclopentadiene-type diphenol compounds, phenol novolak, etc. Here, "dicyclopentadiene-type diphenol compounds" refers to diphenol compounds obtained by condensing one dicyclopentadiene molecule with two phenol molecules.

[0041] Specific preferred examples of the active ester curing agent include active ester curing agents containing a dicyclopentadiene-type diphenol structure, active ester curing agents containing a naphthalene structure, active ester curing agents containing an acetylated product of phenol novolac, and active ester curing agents containing a benzoylated product of phenol novolac. Among these, active ester curing agents containing a naphthalene structure and active ester curing agents containing a dicyclopentadiene-type diphenol structure are more preferred. The "dicyclopentadiene-type diphenol structure" refers to a divalent structural unit consisting of phenylene-dicyclopentylene-phenylene.

[0042] Commercially available active ester curing agents include active ester curing agents containing a dicyclopentadiene-type diphenol structure, such as "EXB9451," "EXB9460," "EXB9460S," "HPC-8000-65T," "HPC-8000H-65TM," and "EXB-8000L-65TM" (manufactured by DIC Corporation); and naphthalene-type active ester curing agents containing a naphthalene structure, such as "EXB9416-70BK," "EXB-8100L-65T," "EXB-8150L-65T," "EXB-8150-65T," "HPC-8150-60T," "HPC-8150-62T," and "HPB-8151-62T" (manufactured by DIC Corporation), and "PC1300-02- 65T" (manufactured by Air Water Inc.); "DC808" (manufactured by Mitsubishi Chemical Corporation) as an active ester-based curing agent containing an acetylated product of phenol novolac; "YLH1026" (manufactured by Mitsubishi Chemical Corporation) as an active ester-based curing agent containing a benzoylated product of phenol novolac; "DC808" (manufactured by Mitsubishi Chemical Corporation) as an active ester-based curing agent which is an acetylated product of phenol novolac; "YLH1026" (manufactured by Mitsubishi Chemical Corporation), "YLH1030" (manufactured by Mitsubishi Chemical Corporation), "YLH1048" (manufactured by Mitsubishi Chemical Corporation) as active ester-based curing agents which are benzoylated products of phenol novolac; and "EXB-8500-65T" (manufactured by DIC Corporation).

[0043] From the viewpoint of significantly obtaining the effects of the present invention, the content of the active ester curing agent is preferably 1% by mass or more, more preferably 2% by mass or more, and even more preferably 4% by mass or more, relative to 100% by mass of the non-volatile components in the resin composition, and is preferably 50% by mass or less, more preferably 40% by mass or less, and even more preferably 30% by mass or less.

[0044] From the viewpoint of significantly obtaining the effects of the present invention, the content of the active ester-based curing agent is preferably 5% by mass or more, more preferably 10% by mass or more, and even more preferably 15% by mass or more, and is preferably 70% by mass or less, more preferably 60% by mass or less, and even more preferably 50% by mass or less, when the resin component in the resin composition is taken as 100% by mass.

[0045] As the phenol-based curing agent and naphthol-based curing agent, those having a novolac structure are preferred from the viewpoint of heat resistance and water resistance. Furthermore, from the viewpoint of adhesion to the conductor layer, nitrogen-containing phenol-based curing agents and nitrogen-containing naphthol-based curing agents are preferred, and triazine skeleton-containing phenol-based curing agents and triazine skeleton-containing naphthol-based curing agents are more preferred.

[0046] Specific examples of phenol-based curing agents and naphthol-based curing agents include "MEH-7700", "MEH-7810", and "MEH-7851" manufactured by Meiwa Chemical Industry Co., Ltd.; "NHN", "CBN", and "GPH" manufactured by Nippon Kayaku Co., Ltd.; "SN170", "SN180", "SN190", "SN475", "SN485", "SN495", "SN-495V", "SN375", and "SN395" manufactured by Nippon Steel Chemical & Material Co., Ltd.; and "TD-2090", "LA-7052", "LA-7054", "LA-1356", "LA-3018-50P", and "EXB-9500" manufactured by DIC Corporation.

[0047] Specific examples of benzoxazine-based curing agents include "JBZ-OD100" (benzoxazine ring equivalent 218 g / eq.), "JBZ-OP100D" (benzoxazine ring equivalent 218 g / eq.), and "ODA-BOZ" (benzoxazine ring equivalent 218 g / eq.), all manufactured by JFE Chemical Corporation; "P-d" (benzoxazine ring equivalent 217 g / eq.) and "F-a" (benzoxazine ring equivalent 217 g / eq.), all manufactured by Shikoku Chemicals Corporation; and "HFB2006M" (benzoxazine ring equivalent 432 g / eq.), all manufactured by Showa Polymer Co., Ltd.

[0048] Examples of cyanate ester curing agents include bifunctional cyanate compounds such as bisphenol A dicyanate, polyphenol cyanate, oligo(3-methylene-1,5-phenylene cyanate), 4,4'-methylenebis(2,6-dimethylphenyl cyanate), 4,4'-ethylidene diphenyl dicyanate, hexafluorobisphenol A dicyanate, 2,2-bis(4-cyanate)phenylpropane, 1,1-bis(4-cyanatephenylmethane), bis(4-cyanate-3,5-dimethylphenyl)methane, 1,3-bis(4-cyanatephenyl-1-(methylethylidene))benzene, bis(4-cyanatephenyl)thioether, and bis(4-cyanatephenyl)ether; polyfunctional cyanate compounds derived from phenol novolac, cresol novolac, and the like; and prepolymers in which these cyanate compounds are partially triazinated. Specific examples of cyanate ester compounds include "PT30," "PT30S," and "PT60" (phenol novolac-type multifunctional cyanate esters), "ULL-950S" (multifunctional cyanate ester), "BA230," and "BA230S75" (prepolymers in which part or all of bisphenol A dicyanate has been triazinated to form a trimer), all of which are manufactured by Arxada.

[0049] Specific examples of carbodiimide curing agents include Carbodilite (registered trademark) V-03 (carbodiimide group equivalent: 216 g / eq.), V-05 (carbodiimide group equivalent: 216 g / eq.), V-07 (carbodiimide group equivalent: 200 g / eq.), and V-09 (carbodiimide group equivalent: 200 g / eq.), all manufactured by Nisshinbo Chemical Inc.; and Stavaxol (registered trademark) P (carbodiimide group equivalent: 302 g / eq.) manufactured by Lanxess AG.

[0050] Examples of the amine-based curing agent include resins having one or more amino groups in one molecule, such as aliphatic amines, polyether amines, alicyclic amines, and aromatic amines. Of these, aromatic amines are preferred from the viewpoint of achieving the desired effects of the present invention. The amine-based curing agent is preferably a primary amine or a secondary amine, and more preferably a primary amine. Specific examples of the amine-based curing agent include 4,4'-methylenebis(2,6-dimethylaniline), diphenyldiaminosulfone, 4,4'-diaminodiphenylmethane, 4,4'-diaminodiphenylsulfone, 3,3'-diaminodiphenylsulfone, m-phenylenediamine, m-xylylenediamine, diethyltoluenediamine, 4,4'-diaminodiphenyl ether, 3,3'-dimethyl-4,4'-diaminobiphenyl, 2,2'-dimethyl-4,4'-diaminobiphenyl, 3,3'-dihydroxybenzidine, 2,2-bis(3-amino-4-hydroxybenzoyl) bis(4-aminophenoxy)phenyl)propane, 3,3-dimethyl-5,5-diethyl-4,4-diphenylmethanediamine, 2,2-bis(4-aminophenyl)propane, 2,2-bis(4-(4-aminophenoxy)phenyl)propane, 1,3-bis(3-aminophenoxy)benzene, 1,3-bis(4-aminophenoxy)benzene, 1,4-bis(4-aminophenoxy)benzene, 4,4'-bis(4-aminophenoxy)biphenyl, bis(4-(4-aminophenoxy)phenyl)sulfone, bis(4-(3-aminophenoxy)phenyl)sulfone, and the like. Commercially available amine-based curing agents may be used, and examples thereof include "KAYABOND C-200S," "KAYABOND C-100," "KAYAHARD A-A," "KAYAHARD A-B," and "KAYAHARD A-S" manufactured by Nippon Kayaku Co., Ltd., and "Epicure W" manufactured by Mitsubishi Chemical Corporation.

[0051] Examples of acid anhydride curing agents include compounds having one or more acid anhydride groups in one molecule. Specific examples of acid anhydride curing agents include phthalic anhydride, tetrahydrophthalic anhydride, hexahydrophthalic anhydride, methyltetrahydrophthalic anhydride, methylhexahydrophthalic anhydride, methylnadic anhydride, hydrogenated methylnadic anhydride, trialkyltetrahydrophthalic anhydride, dodecenylsuccinic anhydride, 5-(2,5-dioxotetrahydro-3-furanyl)-3-methyl-3-cyclohexene-1,2-dicarboxylic anhydride, trimellitic anhydride, pyromellitic anhydride, and benzophenonetetracarboxylic acid. dianhydride, biphenyltetracarboxylic dianhydride, naphthalenetetracarboxylic dianhydride, oxydiphthalic dianhydride, 3,3'-4,4'-diphenylsulfonetetracarboxylic dianhydride, 1,3,3a,4,5,9b-hexahydro-5-(tetrahydro-2,5-dioxo-3-furanyl)-naphtho[1,2-C]furan-1,3-dione, ethylene glycol bis(anhydrotrimellitate), polymeric acid anhydrides such as styrene-maleic acid resins in which styrene and maleic acid are copolymerized, and the like.

[0052] When an epoxy resin is used as the curable resin, the ratio of the amount of epoxy resin to the curing agent, expressed as the ratio of [total number of epoxy groups in the epoxy resin] to [total number of reactive groups in the curing agent], is preferably in the range of 1:0.01 to 1:5, more preferably 1:0.05 to 1:3, and even more preferably 1:0.1 to 1:2. Here, the "number of epoxy groups in the epoxy resin" refers to the sum of all values ​​obtained by dividing the mass of the non-volatile components of the epoxy resin present in the resin composition by the epoxy equivalent. Furthermore, the "number of active groups in the curing agent" refers to the sum of all values ​​obtained by dividing the mass of the non-volatile components of the curing agent present in the resin composition by the active group equivalent. By keeping the ratio of the epoxy resin to the curing agent within this range, a cured product with excellent flexibility can be obtained.

[0053] From the viewpoint of significantly obtaining the effects of the present invention, the content of the curing agent is preferably 1% by mass or more, more preferably 3% by mass or more, and even more preferably 5% by mass or more, relative to 100% by mass of the non-volatile components in the resin composition, and is preferably 50% by mass or less, more preferably 40% by mass or less, and even more preferably 30% by mass or less.

[0054] From the viewpoint of significantly obtaining the effects of the present invention, the content of the curing agent is preferably 5% by mass or more, more preferably 10% by mass or more, even more preferably 15% by mass or more or 20% by mass or more, and is preferably 70% by mass or less, more preferably 60% by mass or less, even more preferably 50% by mass or less, when the resin component in the resin composition is taken as 100% by mass.

[0055] -Inorganic Filler- The resin composition preferably contains an inorganic filler to improve properties such as the coefficient of thermal expansion and dielectric loss tangent. Examples of such inorganic fillers include silica, alumina, aluminosilicate, glass, cordierite, silicon oxide, barium sulfate, barium carbonate, talc, clay, mica powder, zinc oxide, hydrotalcite, boehmite, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, magnesium oxide, boron nitride, aluminum nitride, manganese nitride, aluminum borate, strontium carbonate, strontium titanate, calcium titanate, magnesium titanate, bismuth titanate, titanium oxide, zirconium oxide, barium titanate, barium titanate zirconate, barium zirconate, calcium zirconate, zirconium phosphate, and zirconium tungstate phosphate. Among these, calcium carbonate and silica are preferred, and silica is particularly preferred. Examples of silica include amorphous silica, fused silica, crystalline silica, synthetic silica, and hollow silica. The silica is preferably spherical silica. The inorganic filler may be used alone or in combination of two or more.

[0056] Examples of commercially available inorganic fillers include "UFP-30" manufactured by Denka; "SP60-05", "SP507-05", and "SPH516-05" manufactured by Nippon Steel Chemical & Material Co., Ltd.; "YC100C", "YA050C", "YA050C-MJE", and "YA010C" manufactured by Admatechs; "Silfil NSS-3N", "Silfil NSS-4N", and "Silfil NSS-5N" manufactured by Tokuyama Corporation; and "SC2500SQ" manufactured by Admatechs.

[0057] From the viewpoint of exhibiting excellent insulating properties in extremely fine patterns such as a minimum line and space (L / S) of 2 / 2 μm or less, the average particle diameter of the inorganic filler is preferably 0.6 μm or less, more preferably 0.5 μm or less, even more preferably 0.4 μm or less, and is preferably 0.01 μm or more, more preferably 0.02 μm or more, even more preferably 0.03 μm or more.

[0058] The specific surface area of ​​the inorganic filler is preferably 1 m ２ / g or more, more preferably 2m ２ / g or more, more preferably 3m ２ / g or more. There is no particular upper limit, but it is preferably 60 m ２ / g or less, 50m ２ / g or less or 40m ２ The specific surface area can be calculated according to the BET method by adsorbing nitrogen gas onto the surface of a sample using a specific surface area measuring device (Macsorb HM-1210 manufactured by Mountech Co., Ltd.) and then using the BET multipoint method.

[0059] In order to improve moisture resistance and dispersibility, the inorganic filler is preferably treated with a surface treatment agent. Examples of the surface treatment agent include vinylsilane coupling agents, (meth)acrylic coupling agents, fluorine-containing silane coupling agents, aminosilane coupling agents, epoxysilane coupling agents, mercaptosilane coupling agents, silane coupling agents, alkoxysilanes, organosilazane compounds, and titanate coupling agents. Among these, in order to significantly achieve the effects of the present invention, vinylsilane coupling agents, (meth)acrylic coupling agents, and aminosilane coupling agents are preferred, and aminosilane coupling agents are more preferred. Furthermore, the surface treatment agent may be used alone or in any combination of two or more.

[0060] Commercially available surface treatment agents include, for example, "KBM1003" (vinyltriethoxysilane), "KBM503" (3-methacryloxypropyltriethoxysilane), "KBM403" (3-glycidoxypropyltrimethoxysilane), "KBM803" (3-mercaptopropyltrimethoxysilane), "KBE903" (3-aminopropyltriethoxysilane), "KBM573" (N-phenyl-3-aminopropyltrimethoxysilane), "SZ-31" (hexamethyldisilazane), "KBM103" (phenyltrimethoxysilane), "KBM-4803" (long-chain epoxy-type silane coupling agent), and "KBM-7103" (3,3,3-trifluoropropyltrimethoxysilane), all manufactured by Shin-Etsu Chemical Co., Ltd.

[0061] The degree of surface treatment with the surface treatment agent is preferably within a predetermined range from the viewpoint of improving the dispersibility of the inorganic filler. Specifically, 100 parts by mass of the inorganic filler is preferably surface-treated with 0.2 to 5 parts by mass of the surface treatment agent, more preferably 0.2 to 3 parts by mass, and even more preferably 0.3 to 2 parts by mass.

[0062] The degree of surface treatment with the surface treatment agent can be evaluated by the amount of carbon per unit surface area of ​​the inorganic filler. From the viewpoint of improving the dispersibility of the inorganic filler, the amount of carbon per unit surface area of ​​the inorganic filler is 0.02 mg / m ２ More than 0.1 mg / m ２ More preferably, 0.2 mg / m or more ２ On the other hand, from the viewpoint of suppressing an increase in the melt viscosity of the resin varnish and the melt viscosity in the form of a sheet, it is more preferable that the content be 1 mg / m ２ Preferably, 0.8 mg / m or less ２ More preferably, 0.5 mg / m or less ２ The following is even more preferred:

[0063] The carbon amount per unit surface area of ​​the inorganic filler can be measured after the surface-treated inorganic filler is washed with a solvent (e.g., methyl ethyl ketone (MEK)). Specifically, a sufficient amount of MEK as a solvent is added to the inorganic filler that has been surface-treated with a surface treatment agent, and ultrasonic cleaning is performed at 25°C for 5 minutes. After removing the supernatant and drying the solid content, the carbon amount per unit surface area of ​​the inorganic filler can be measured using a carbon analyzer. As the carbon analyzer, an "EMIA-320V" manufactured by Horiba, Ltd. or the like can be used.

[0064] The content of the inorganic filler in the resin composition (and thus the content of the inorganic filler in the resin composition layer and insulating layer) is preferably 20% by mass or more, more preferably 30% by mass or more, and even more preferably 40% by mass or more, based on 100% by mass of the non-volatile components in the resin composition, from the viewpoint of sufficiently reducing the thermal expansion coefficient and dielectric loss tangent of the insulating layer. As described below, when the insulating layer contains an inorganic filler, it has been difficult to form a trench-type conductor circuit in a fine pattern. In contrast, according to the method of the present invention, even when the inorganic filler content is even higher, it is possible to form a trench-type conductor circuit in an extremely fine pattern. For example, the content of the inorganic filler in the resin composition may be increased to 45% by mass or more, 50% by mass or more, or 55% by mass or more. The upper limit of the content of the inorganic filler is preferably 75% by mass or less, more preferably 70% by mass or less, and even more preferably 65% ​​by mass or less. Therefore, in one embodiment, the content of the inorganic filler in the resin composition is 20% by mass or more and 75% by mass or less, when the nonvolatile components in the resin composition are taken as 100% by mass.

[0065] As mentioned above, so-called 2.1D packaging technology, which uses organic interposers manufactured using conventional organic substrate extension techniques instead of silicon interposers, is expected to reduce costs and improve manufacturing efficiency. However, forming fine circuits similar to those of silicon interposers on the semiconductor chip mounting surface of the organic interposer remains a challenge. However, conventional organic substrate manufacturing techniques, which form a conductor layer on an insulating layer, can sometimes make it difficult to achieve fine wiring. In particular, the insulating layer used in organic interposers may contain inorganic fillers such as silica to achieve properties such as a low thermal expansion coefficient and a low dielectric loss tangent. In such cases, fine wiring can be even more difficult. In contrast, according to the present invention, even when the insulating layer used in the organic interposer contains an inorganic filler, it is possible to easily and flexibly form conductor circuits with excellent insulation reliability in fine patterns on the semiconductor chip mounting surface.

[0066] The resin composition may further contain other components. Examples of such other components include a curing accelerator, a thermoplastic resin, other additives, etc. Each component will be described below.

[0067] -Curing accelerator- The resin composition may contain a curing accelerator. Examples of the curing accelerator include phosphorus-based curing accelerators, amine-based curing accelerators, imidazole-based curing accelerators, guanidine-based curing accelerators, and metal-based curing accelerators. Amine-based curing accelerators and imidazole-based curing accelerators are preferred, and amine-based curing accelerators are more preferred. One type of curing accelerator may be used alone, or two or more types may be used in combination.

[0068] Examples of the phosphorus-based curing accelerator include triphenylphosphine, phosphonium borate compounds, tetraphenylphosphonium tetraphenylborate, n-butylphosphonium tetraphenylborate, tetrabutylphosphonium decanoate, (4-methylphenyl)triphenylphosphonium thiocyanate, tetraphenylphosphonium thiocyanate, and butyltriphenylphosphonium thiocyanate, with triphenylphosphine and tetrabutylphosphonium decanoate being preferred.

[0069] Examples of the amine curing accelerator include trialkylamines such as triethylamine and tributylamine, 4-dimethylaminopyridine, benzyldimethylamine, 2,4,6-tris(dimethylaminomethyl)phenol, and 1,8-diazabicyclo(5,4,0)-undecene, with 4-dimethylaminopyridine and 1,8-diazabicyclo(5,4,0)-undecene being preferred.

[0070] Examples of the imidazole curing accelerator include 2-methylimidazole, 2-undecylimidazole, 2-heptadecylimidazole, 1,2-dimethylimidazole, 2-ethyl-4-methylimidazole, 1,2-dimethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-phenyl-4-methylimidazole, 1-benzyl-2-methylimidazole, and 1-benzyl-2-phenylimidazole. 1-cyanoethyl-2-methylimidazole, 1-cyanoethyl-2-undecylimidazole, 1-cyanoethyl-2-ethyl-4-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazolium trimellitate, 1-cyanoethyl-2-phenylimidazolium trimellitate, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine, 2, 4-Diamino-6-[2'-undecylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-ethyl-4'-methylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine isocyanuric acid adduct, 2-phenylimidazole isocyanuric acid adduct, 2-phenyl-4,5-dihydroxymethylimidazole, 2-phenyl-4,5-dihydroxymethylimidazole, Examples of the imidazole curing accelerator include imidazole compounds such as phenyl-4-methyl-5-hydroxymethylimidazole, 2,3-dihydro-1H-pyrrolo[1,2-a]benzimidazole, 1-dodecyl-2-methyl-3-benzylimidazolium chloride, 2-methylimidazoline, and 2-phenylimidazoline, as well as adducts of imidazole compounds with epoxy resins, with 2-ethyl-4-methylimidazole and 1-benzyl-2-phenylimidazole being preferred. Commercially available imidazole curing accelerators may also be used, such as "P200-H50" manufactured by Mitsubishi Chemical Corporation.

[0071] Examples of guanidine curing accelerators include dicyandiamide, 1-methylguanidine, 1-ethylguanidine, 1-cyclohexylguanidine, 1-phenylguanidine, 1-(o-tolyl)guanidine, dimethylguanidine, diphenylguanidine, trimethylguanidine, tetramethylguanidine, pentamethylguanidine, 1,5,7-triazabicyclo[4.4.0]dec-5-ene, and 7-methyl-1,5,7-triazabicyclo[4.4.0]dec-5-ene. Examples of suitable biguanide include 1-methylbiguanide, 1-ethylbiguanide, 1-n-butylbiguanide, 1-n-octadecylbiguanide, 1,1-dimethylbiguanide, 1,1-diethylbiguanide, 1-cyclohexylbiguanide, 1-allylbiguanide, 1-phenylbiguanide, and 1-(o-tolyl)biguanide. Of these, dicyandiamide and 1,5,7-triazabicyclo[4.4.0]dec-5-ene are preferred.

[0072] Examples of metal-based curing accelerators include organometallic complexes or organometallic salts of metals such as cobalt, copper, zinc, iron, nickel, manganese, and tin. Specific examples of organometallic complexes include organic cobalt complexes such as cobalt(II) acetylacetonate and cobalt(III) acetylacetonate, organic copper complexes such as copper(II) acetylacetonate, organic zinc complexes such as zinc(II) acetylacetonate, organic iron complexes such as iron(III) acetylacetonate, organic nickel complexes such as nickel(II) acetylacetonate, and organic manganese complexes such as manganese(II) acetylacetonate. Examples of organometallic salts include zinc octoate, tin octoate, zinc naphthenate, cobalt naphthenate, tin stearate, and zinc stearate.

[0073] From the viewpoint of significantly obtaining the effects of the present invention, the content of the curing accelerator is preferably 0.01% by mass or more, more preferably 0.02% by mass or more, and particularly preferably 0.03% by mass or more, and is preferably 3% by mass or less, more preferably 1% by mass or less, and particularly preferably 0.5% by mass or less, when the non-volatile content in the resin composition is taken as 100% by mass.

[0074] From the viewpoint of significantly obtaining the effects of the present invention, the content of the curing accelerator is preferably 0.01% by mass or more, more preferably 0.05% by mass or more, and even more preferably 0.1% by mass or more, and is preferably 3% by mass or less, more preferably 2% by mass or less, and even more preferably 1% by mass or less, when the resin component in the resin composition is taken as 100% by mass.

[0075] -Thermoplastic Resin- The resin composition may contain a thermoplastic resin. Examples of the thermoplastic resin include phenoxy resin, polyvinyl acetal resin, polyolefin resin, polyimide resin, polyamideimide resin, polyetherimide resin, polysulfone resin, polyethersulfone resin, polyphenylene ether resin, polyetheretherketone resin, and polyester resin, with phenoxy resin being preferred. The thermoplastic resin may be used alone or in combination of two or more.

[0076] The polystyrene-equivalent weight average molecular weight of the thermoplastic resin is preferably 38,000 or more, more preferably 40,000 or more, and even more preferably 42,000 or more. The upper limit is preferably 100,000 or less, more preferably 70,000 or less, and even more preferably 60,000 or less. The polystyrene-equivalent weight average molecular weight of the thermoplastic resin is measured by gel permeation chromatography (GPC). Specifically, the polystyrene-equivalent weight average molecular weight of the thermoplastic resin is measured using a Shimadzu Corporation LC-9A / RID-6A measuring device, a Showa Denko Corporation Shodex K-800P / K-804L / K-804L column, and chloroform or the like as the mobile phase at a column temperature of 40°C, and can be calculated using a standard polystyrene calibration curve.

[0077] Examples of phenoxy resins include phenoxy resins having one or more skeletons selected from the group consisting of bisphenol A skeleton, bisphenol F skeleton, bisphenol S skeleton, bisphenolacetophenone skeleton, novolac skeleton, biphenyl skeleton, fluorene skeleton, dicyclopentadiene skeleton, norbornene skeleton, naphthalene skeleton, anthracene skeleton, adamantane skeleton, terpene skeleton, and trimethylcyclohexane skeleton. The terminal of the phenoxy resin may be any functional group such as a phenolic hydroxyl group or an epoxy group. One type of phenoxy resin may be used alone, or two or more types may be used in combination. Specific examples of phenoxy resins include "1256" and "4250" (both phenoxy resins containing a bisphenol A skeleton), "YX8100" (phenoxy resin containing a bisphenol S skeleton), and "YX6954" (phenoxy resin containing a bisphenol acetophenone skeleton), all manufactured by Mitsubishi Chemical Corporation. Other examples include "FX280" and "FX293" manufactured by Nippon Steel Chemical & Material Co., Ltd., and "YX7800BH40," "YL7500BH30," "YX6954BH30," "YX7553," "YX7553BH30," "YL7769BH30," "YL6794," "YL7213," "YL7290," and "YL7482" manufactured by Mitsubishi Chemical Corporation.

[0078] Examples of polyvinyl acetal resins include polyvinyl formal resins and polyvinyl butyral resins, with polyvinyl butyral resins being preferred. Specific examples of polyvinyl acetal resins include the S-LEC BH series, BX series (e.g., BX-5Z), KS series (e.g., KS-1), BL series, and BM series manufactured by Sekisui Chemical Co., Ltd.

[0079] Specific examples of polyimide resins include "Rikacoat SN20" and "Rikacoat PN20" manufactured by New Japan Chemical Co., Ltd. Specific examples of polyimide resins also include modified polyimides such as linear polyimides obtained by reacting bifunctional hydroxyl group-terminated polybutadiene, a diisocyanate compound, and a tetrabasic acid anhydride (polyimides described in JP-A-2006-37083), and polysiloxane skeleton-containing polyimides (polyimides described in JP-A-2002-12667 and JP-A-2000-319386, etc.).

[0080] Specific examples of polyamide-imide resins include "Vylomax HR11NN" and "Vylomax HR16NN" manufactured by Toyobo Co., Ltd. Specific examples of polyamide-imide resins also include modified polyamide-imides such as "KS9100" and "KS9300" (polysiloxane skeleton-containing polyamide-imides) manufactured by Resonac Corporation.

[0081] A specific example of a polyethersulfone resin is "PES5003P" manufactured by Sumitomo Chemical Co., Ltd. A specific example of a polyphenylene ether resin is "OPE-2St 1200" oligophenylene ether styrene resin manufactured by Mitsubishi Gas Chemical Company, Inc. A specific example of a polyetheretherketone resin is "Sumiploy K" manufactured by Sumitomo Chemical Co., Ltd. A specific example of a polyetherimide resin is "Ultem" manufactured by GE Corporation.

[0082] Specific examples of polysulfone resins include polysulfone "P1700" and "P3500" manufactured by Solvay Advanced Polymers.

[0083] Examples of polyolefin resins include ethylene copolymer resins such as low-density polyethylene, very low-density polyethylene, high-density polyethylene, ethylene-vinyl acetate copolymer, ethylene-ethyl acrylate copolymer, and ethylene-methyl acrylate copolymer; and polyolefin elastomers such as polypropylene and ethylene-propylene block copolymer.

[0084] Examples of polyester resins include polyethylene terephthalate resin, polyethylene naphthalate resin, polybutylene terephthalate resin, polybutylene naphthalate resin, polytrimethylene terephthalate resin, polytrimethylene naphthalate resin, and polycyclohexane dimethyl terephthalate resin.

[0085] Among these, phenoxy resins and polyvinyl acetal resins are preferred as the thermoplastic resin. Therefore, in a preferred embodiment, the resin composition contains one or more thermoplastic resins selected from the group consisting of phenoxy resins and polyvinyl acetal resins. Among these, phenoxy resins are preferred as the thermoplastic resin, and phenoxy resins having a weight average molecular weight of 40,000 or more are particularly preferred.

[0086] From the viewpoint of achieving the remarkable effects of the present invention, the content of the thermoplastic resin is preferably 0.1% by mass or more, more preferably 0.3% by mass or more, and even more preferably 0.5% by mass or more, based on 100% by mass of the nonvolatile components in the resin composition, and the upper limit is preferably 5% by mass or less, more preferably 4% by mass or less, and even more preferably 3% by mass or less.

[0087] From the viewpoint of significantly obtaining the effects of the present invention, the content of the thermoplastic resin is preferably 0.5% by mass or more, more preferably 1% by mass or more, and even more preferably 1.5% by mass or more, when the resin component in the resin composition is taken as 100% by mass, and is preferably 10% by mass or less, more preferably 8% by mass or less, and even more preferably 5% by mass or less.

[0088] Other Additives The resin composition may further contain other additives. Examples of such additives include organic fillers such as rubber particles; organometallic compounds such as organocopper compounds, organozinc compounds, and organocobalt compounds; colorants such as phthalocyanine blue, phthalocyanine green, iodine green, diazo yellow, crystal violet, titanium oxide, and carbon black; leveling agents such as silicone-based leveling agents and acrylic polymer-based leveling agents; thickeners such as bentone and montmorillonite; antifoaming agents such as silicone-based antifoaming agents, acrylic-based antifoaming agents, fluorine-based antifoaming agents, and vinyl resin-based antifoaming agents; adhesion improvers such as urea silane; adhesion imparting agents such as triazole-based adhesion imparting agents, tetrazole-based adhesion imparting agents, and triazine-based adhesion imparting agents; and hindered phenol-based oxides. Examples of suitable additives include antioxidants such as antioxidants; fluorescent brighteners such as stilbene derivatives; surfactants such as fluorine-based surfactants and silicone-based surfactants; flame retardants such as phosphorus-based flame retardants (e.g., phosphate ester compounds, phosphazene compounds, phosphinic acid compounds, and red phosphorus), nitrogen-based flame retardants (e.g., melamine sulfate), halogen-based flame retardants, and inorganic flame retardants (e.g., antimony trioxide); dispersants such as phosphate ester-based dispersants, polyoxyalkylene-based dispersants, acetylene-based dispersants, silicone-based dispersants, anionic dispersants, and cationic dispersants; and stabilizers such as borate-based stabilizers, titanate-based stabilizers, aluminate-based stabilizers, zirconate-based stabilizers, isocyanate-based stabilizers, carboxylic acid-based stabilizers, and carboxylic anhydride-based stabilizers. These additives may be used alone or in combination of two or more. The content of such additives may be determined depending on the properties required of the insulating layer.

[0089] The method for preparing the resin composition is not particularly limited, and examples thereof include a method in which the ingredients are mixed and dispersed, if necessary, together with a solvent, using a rotary mixer or the like.

[0090] The minimum melt viscosity of the resin composition (and thus the resin composition layer) is preferably 5,000 poise or less, more preferably 4,500 poise or less, and even more preferably 4,000 poise or less, from the viewpoints of embedding the conductor circuit and maintaining the conductor circuit without collapse. Furthermore, from the viewpoints of preventing exudation during the formation of the resin composition layer and improving processability, it is preferably 100 poise or more, more preferably 200 poise or more, and even more preferably 300 poise or more. The minimum melt viscosity of the resin composition can be determined by measuring the melt viscosity using a dynamic viscoelasticity method. Specifically, using parallel plates with a diameter of 18 mm, 1 g of a sample resin composition is heated from a starting temperature of 60°C to 200°C at a heating rate of 5°C / min, and the dynamic viscoelastic modulus is measured under measurement conditions of a measurement temperature interval of 2.5°C, an oscillation frequency of 1 Hz, and a strain of 1 deg. The minimum melt viscosity (poise) can be determined from the minimum value of the melt viscosity. An example of a dynamic viscoelasticity measuring device is the "Rheosol-G3000" manufactured by UBM.

[0091] The present invention will be described in detail below with reference to preferred embodiments. While the description may refer to drawings, each drawing merely shows the shape, size, and arrangement of components to the extent that the invention can be understood. The present invention is not limited by the following description, and each component can be modified as appropriate without departing from the spirit of the present invention.

[0092] [Method for manufacturing a circuit board for a semiconductor package] The method for manufacturing a circuit board for a semiconductor package of the present invention (hereinafter also simply referred to as the "manufacturing method of the present invention" or "method of the present invention") is characterized by including the following steps (X), (Y), and (Z). (X) (X1) to (X3) below: (X1) forming a first conductive circuit on the metal layer of a substrate with a metal layer; (X2) forming a barrier film on the surface of the first conductive circuit formed on the metal layer to form a first conductive circuit with a barrier film; (X3) forming a resin composition layer from a resin composition containing a curable resin so as to embed the first conductive circuit with a barrier film formed on the metal layer, and curing the resin composition layer to form an insulating layer, in this order, to form a first circuit board on the substrate with a metal layer, the first circuit board having a first conductive circuit with a barrier film on its first main surface; (Y) (Y1) and (Y2) below: (Y1) removing the substrate with a metal layer to form a first circuit board having a first main surface on which the first conductive circuit is exposed; and (Y2) forming a barrier film on the surface of the exposed first conductive circuit, in this order, to form a first circuit board having a first conductive circuit covered with a barrier film on its first main surface; (Z) a step of joining the core circuit board and the first circuit board so that a second main surface of the first circuit board opposite to the first main surface faces the first main surface of the core circuit board;

[0093] In the present invention, the phrase "performed in this order" with respect to (X1) to (X3) does not preclude the inclusion of other steps, as long as it includes steps (X1) to (X3) and steps (X1) to (X3) are performed in this order. Similarly, the phrase "performed in this order" with respect to (Y1) and (Y2) does not preclude the inclusion of other steps, as long as it includes steps (Y1) and (Y2) and steps (Y1) and (Y2) are performed in this order.

[0094] The method of the present invention is advantageous because it does not require a process for selectively removing the metal layer (seed layer) in areas where conductor circuits are not formed by etching, preventing the conductor circuits from being affected by etching, and thus enabling the formation of wiring (conductor circuits) in a fine pattern. Furthermore, it is possible to form conductor circuits with excellent electrical properties by maintaining the cross-sectional area of ​​the conductor circuit. Furthermore, it is possible to form conductor circuits with a high aspect ratio, which is advantageous for improving the reliability of the joint with the semiconductor chip and reducing the connection pitch. The method of the present invention also enables the entire surface of such a fine circuit (the surface in contact with the insulating layer and the semiconductor chip mounting surface) to be covered with a barrier film, thereby realizing a fine circuit with excellent insulation reliability. Here, the term "barrier film" refers to a film that has the function of suppressing the diffusion of the conductor metal material constituting the circuit into the insulating layer, and is described in detail below. Furthermore, the method of the present invention forms a circuit board (first circuit board) with excellent surface flatness, and then bonds the circuit board to a core circuit board, allowing for a high degree of freedom in selecting a core circuit board depending on the characteristics required of the semiconductor package.

[0095] In this regard, in conventional techniques, when forming a trench-type conductor circuit, an insulating layer is generally laser-processed to form a trench (groove), and the trench is then filled with a conductor using a method such as sputtering to form the trench-type conductor circuit. Such techniques can sometimes make it difficult to achieve finer wiring, and this is particularly true when the insulating layer contains an inorganic filler. In contrast, the method of the present invention makes it possible to form a trench-type conductor circuit in an extremely fine pattern, such as one with a minimum line and space (L / S) of 2 / 2 μm or less, even when the insulating layer contains an inorganic filler.

[0096] Furthermore, when forming a circuit with a low L / S, the conductive metal material constituting the circuit is likely to diffuse into the insulating layer, causing short circuits and raising concerns about insulation reliability. In contrast, the method of the present invention makes it possible to cover the entire surface of a fine circuit with a barrier film easily and with a high degree of freedom, as described below, thereby realizing a fine circuit with good insulation reliability.

[0097] Furthermore, in conventional 2.1D mounting techniques in which an organic fine wiring layer is formed on a core circuit board, the core circuit board is usually selected with emphasis on the process reliability when the organic fine wiring layer is formed thereon. However, in the method of the present invention in which a circuit board (first circuit board) equipped with fine circuits is formed and then this circuit board is joined to a core circuit board to manufacture a circuit board for a semiconductor package, the core circuit board can be selected with emphasis on product reliability, and therefore the core circuit board can be selected with a high degree of freedom depending on the characteristics required for the semiconductor package.

[0098] Therefore, the present invention significantly contributes to the finer wiring and improved reliability of circuit boards for semiconductor packages, and in turn to the higher performance of semiconductor packages.

[0099] <Step (X)> In step (X), a first circuit board having a first conductive circuit with a barrier film on its first main surface is formed on a substrate with a metal layer.

[0100] Specifically, the following steps (X1) to (X3) are carried out in this order: (X1) forming a first conductive circuit on the metal layer of a substrate with a metal layer, (X2) forming a barrier film on the surface of the first conductive circuit formed on the metal layer to form a barrier film-containing first conductive circuit, and (X3) forming a resin composition layer from a resin composition containing a curable resin so as to embed the barrier film-containing first conductive circuit formed on the metal layer, and curing the resin composition layer to form an insulating layer.

[0101] Each of (X1) to (X3) will be explained below.

[0102] -(X1)- In (X1), a first conductive circuit is formed on the metal layer of the substrate with a metal layer.

[0103] The substrate with a metal layer used in (X1) is not particularly limited as long as it includes a substrate and a metal layer provided on the substrate.

[0104] In the substrate with a metal layer, the metal layer functions as a seed layer for forming the first conductive circuit, and the substrate functions as a support for the metal layer. The constituent material of the substrate is not particularly limited, and any substrate selected from a metal substrate, an inorganic substrate, and an organic substrate may be used. In a preferred embodiment, the substrate is selected from a metal substrate, an inorganic substrate, and an organic substrate having a different composition from that of the metal layer.

[0105] The metal substrate, which has a different composition from the metal layer, is not particularly limited in its constituent material (metal material) as long as it has a different composition from the metal layer. Examples of metal materials include copper, aluminum, and alloys of these with other metals (e.g., tin, chromium, silver, magnesium, nickel, zirconium, silicon, titanium, etc.). The thickness of the metal substrate is not particularly limited and may be, for example, in the range of 0.1 mm to 5 mm.

[0106] Examples of inorganic substrates include glass substrates and ceramic substrates, while examples of organic substrates include substrates made of plastic materials. The material of the glass substrate is not particularly limited, and various glass materials such as borosilicate glass, quartz glass, lead glass, and soda-lime glass may be used. The material of the ceramic substrate is not particularly limited, and various ceramic materials such as alumina and zirconia may be used. Examples of plastic materials include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), acrylics such as polycarbonate (PC), polymethyl methacrylate (PMMA), cyclic polyolefins, triacetyl cellulose (TAC), polyether sulfide (PES), polyether ketone, and polyimide. Composite materials such as fiber-reinforced plastics may also be used. The thickness of these inorganic and organic substrates is not particularly limited and may be determined appropriately depending on the type of substrate, but may be, for example, in the range of 0.1 mm to 5 mm.

[0107] The substrate with a metal layer includes a metal layer provided on the substrate. The surface of the substrate on which the metal layer is provided is preferably smooth and flat. The metal material constituting the metal layer is not particularly limited as long as it can form a conductor layer on the metal layer surface, but examples include copper, palladium, gold, platinum, silver, aluminum, and alloys of these with other metals (e.g., tin, chromium, magnesium, nickel, zirconium, silicon, titanium, etc.). The metal layer can be formed on the substrate by methods such as sputtering, electroless plating, and attaching an ultrathin metal foil, and sputtering is particularly preferred.

[0108] In the substrate with a metal layer, the thickness of the metal layer is preferably less than 1 μm, less than 0.9 μm, less than 0.8 μm, less than 0.75 μm, less than 0.7 μm, less than 0.68 μm, less than 0.66 μm, or 0.65 μm or less, from the viewpoint of forming a uniform recessed shape in the opening of the first conductive circuit after removing the metal layer by etching or the like and improving yield. The thickness of the metal layer may be even thinner, for example, less than 0.5 μm, less than 0.45 μm, less than 0.4 μm, less than 0.35 μm, less than 0.3 μm, less than 0.25 μm, or less than 0.2 μm, as long as the effects of the present invention are not impaired. The lower limit of the thickness of the metal layer is not particularly limited, but may be, for example, 0.01 μm or more, 0.02 μm or more, or 0.03 μm or more, from the viewpoint of facilitating the formation of the first conductive circuit described below.

[0109] In the present invention, the phrase "a metal layer is provided on a substrate" includes not only a case where the metal layer is provided in contact with (directly on) the substrate, but also a case where the metal layer is provided on the substrate via another layer.

[0110] Here, the other layer is not particularly limited as long as it does not impair the effects of the present invention, and examples thereof include an adhesive layer that allows a metal layer to be provided on a substrate with good adhesion, and a release layer that allows the substrate to be peeled from the metal layer. Any conventionally known adhesive layer or release layer may be used as long as it exhibits the desired function. When the substrate with a metal layer has a release layer between the metal layer and the substrate, this makes it possible to peel and remove the substrate in (Y1) described below, which is preferable because it allows for the easy formation of a circuit board having a first main surface on which the first conductor circuit (trench-type conductor circuit) is exposed. Therefore, in a preferred embodiment, the substrate with a metal layer includes a release layer between the substrate and the metal layer.

[0111] The release layer is not particularly limited as long as it can release the substrate from the metal layer, and examples thereof include an alloy layer of an element selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, and P; and an organic coating that evaporates (sublimes) when exposed to active energy rays (WO2018 / 025957).

[0112] In the substrate with a metal layer, the arithmetic mean roughness Ra of the metal layer surface on which the conductor circuit is formed is preferably 200 nm or less, more preferably 150 nm or less, and even more preferably 100 nm or less, 80 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 20 nm or less, from the viewpoint of being able to form the first conductor circuit in a fine pattern. The lower limit of Ra is not particularly limited and may be, for example, 1 nm or more, 2 nm or more, 3 nm or more, etc. Therefore, in one embodiment, the arithmetic mean roughness Ra of the metal layer surface is 200 nm or less. The arithmetic mean roughness Ra is a value measured in accordance with ISO 25178 and can be measured using a non-contact surface roughness meter. An example of a non-contact surface roughness meter is the "WYKO NT3300" manufactured by Veeco Instruments.

[0113] In a substrate with a metal layer, the difference TTV (Total Thickness Variation) between the maximum and minimum heights of the metal layer surface measured in the thickness direction of the substrate with a metal layer is preferably 50 μm or less, more preferably 40 μm or less, and even more preferably 30 μm or less, 20 μm or less, 15 μm or less, 10 μm or less, 7 μm or less, or 5 μm or less, from the viewpoint of being able to form a first conductive circuit in a fine pattern. The lower limit of the TTV is not particularly limited and can be, for example, 1 μm or more, 2 μm or more, 3 μm or more, etc. Therefore, in one embodiment, the difference TTV between the maximum and minimum heights of the metal layer surface measured in the thickness direction of the substrate with a metal layer is 50 μm or less.

[0114] In the present invention, a first conductive circuit is formed on the metal layer of the substrate having a metal layer.

[0115] The first conductive circuit may be formed in accordance with known circuit formation methods such as semi-additive methods, full-additive methods, etc. Thus, in one embodiment, (X1) includes: (X1-1) providing a photoresist on a metal layer, exposing and developing the photoresist to expose the metal layer in a manner corresponding to the circuit pattern of the first conductive circuit to be formed, and (X1-2) forming a conductor layer on the exposed metal layer to form the first conductive circuit.

[0116] As the photoresist, any known photoresist that can be developed into a desired conductor circuit pattern may be used, and either a film photoresist (dry film photoresist) or a liquid photoresist may be used.

[0117] In particular, from the viewpoint of being able to fully enjoy the effect of the present invention of being able to form first conductive circuits in a fine pattern, it is preferable to form the first conductive circuits using a semi-additive method. Therefore, in the above (X1-2), it is preferable to form the conductor layer by electrolytic plating using the exposed metal layer as a plating seed layer.

[0118] In the method of the present invention, the substrate with a metal layer is removed by (Y1) described below, eliminating the need for etching to remove the metal layer (seed layer) from the circuit-free portion, as is typically done in semi-additive processes. In previous techniques, such etching could result in the removal of even a portion of the conductor circuit, making it impossible to maintain the cross-sectional area of ​​the conductor circuit. This problem was particularly pronounced when forming conductor circuits with a small L / S ratio, hindering the formation of conductor circuits in fine patterns. In contrast, the method of the present invention involves forming a conductor circuit on the metal layer of a substrate with a metal layer, forming a barrier film on the conductor circuit, and forming an insulating layer to embed the barrier film-coated conductor circuit. The substrate with a metal layer is then removed to expose the conductor circuit. This prevents the conductor circuit from being affected by etching, making it possible to form a first conductor circuit with a desired cross-sectional area in a fine pattern.

[0119] In the present invention, it is possible to form first conductive circuits in a fine pattern. Specifically, it is possible to form conductive circuits with a minimum line and space (L / S) of preferably 5 / 5 μm or less, more preferably 3 / 3 μm or less, and even more preferably 2 / 2 μm or less, and even conductive circuits with an L / S of 1.5 / 1.5 μm or less or 1 / 1 μm or less can be formed. Thus, in a preferred embodiment, the minimum line and space (L / S) of the first conductive circuits is 2 / 2 μm or less.

[0120] The thickness of the conductor layer forming the first conductor circuit may be determined depending on the specific design of the circuit board for a semiconductor package. In the present invention, a conductor circuit can be formed in a fine pattern having an aspect ratio (the ratio T / W of the conductor layer thickness T to the conductor layer line width W) of preferably 1 or more, more preferably 1.5 or more, 2 or more, 2.5 or more, or 3 or more.

[0121] An example of (X1) will be described below with reference to FIGS.

[0122] First, a substrate with a metal layer is prepared ( FIG. 1 ). FIG. 1 shows an example of a substrate with a metal layer 10 prepared as such a substrate with a metal layer, the substrate 1 including a substrate 1 and a metal layer 2 provided on the substrate. The preferred range of the arithmetic mean roughness Ra of the surface 10a of the metal layer 2 is as described above. The surface roughness of the other main surface 10b opposite thereto is not particularly limited. Furthermore, the preferred range of the difference TTV between the maximum and minimum heights of the metal layer surface measured in the thickness direction of the substrate with a metal layer is also as described above.

[0123] Next, a first conductive circuit is formed on (the surface 10a of) the metal layer 2 of the metal layer-attached substrate 10. Specifically, photoresist 20 is provided on the metal layer 2 of the metal layer-attached substrate 10 (FIG. 2), and the photoresist is exposed and developed to expose the metal layer corresponding to the circuit pattern of the first conductive circuit to be formed (FIG. 3). Conductor layers 30 are then formed on the exposed metal layer, forming a first conductive circuit comprised of these conductor layers 30 (FIG. 4; hereinafter, the reference numeral for the first conductive circuit will also be referred to as 30 for convenience). As described above, the method of the present invention makes it possible to form a first conductive circuit in a fine pattern. After the first conductive circuit is formed, photoresist 20 is removed (FIG. 5).

[0124] The formation of conductor layers via photoresist may be performed multiple times to form desired circuit patterns or interlayer connection patterns. For example, a second photoresist 21 is provided on a metal layer on which first conductor circuits 30 are provided ( FIG. 6 ), and the photoresist is exposed and developed to expose conductor layers 30 (first conductor circuits 30) corresponding to the interlayer connection pattern ( FIG. 7 ). A conductor layer is then provided on the exposed first conductor circuits 30 to form interlayer connection conductors ( FIG. 8 ; the fourth, eighth, and twelfth conductor layers 30 from the left in the figure correspond to the interlayer connection conductors). After the interlayer connection conductors are formed, the second photoresist 21 is removed ( FIG. 9 ).

[0125] 3 to 9 show an example in which a first conductive circuit is formed using photoresist 20, and then an interlayer connection conductor is formed using photoresist 21. However, the procedure is not particularly limited as long as a first conductive circuit can be formed on a metal layer. For example, photoresist 20 may be exposed and developed to first expose the metal layer of the base material corresponding to the interlayer connection pattern, and a conductor layer (interlayer connection conductor) may be formed on the exposed metal layer. In such a case, after the interlayer connection conductor is formed, photoresist 20 may be exposed and developed without removing it to expose the metal layer of the base material corresponding to the circuit pattern of the first conductive circuit to be formed, and a conductor layer may be formed on the exposed metal layer to form the first conductive circuit.

[0126] --(X2)--In (X2), a barrier film is formed on the surface of the first conductive circuit formed on the metal layer to form a first conductive circuit with a barrier film.

[0127] As mentioned above, conductive metal materials constituting the circuit may diffuse into the organic insulating layer. For example, diffusion of metal atoms constituting the circuit may occur when current is applied to the first conductive circuit or when a circuit board for a semiconductor package is manufactured using the first circuit board. If the L / S ratio of the first conductive circuit is small, the diffused metal atoms may form unintended conductive paths, resulting in short circuits. In this regard, a technique for forming a circuit provided with a barrier film when forming a microcircuit using a damascene method to prevent short circuits in the microcircuit is known. However, considering the application of the damascene method to later semiconductor processes, the process is somewhat complicated, and as mentioned above, a simpler method is desired. Furthermore, although it is possible to form a barrier film when forming a circuit using a conventional semi-additive method, such a method involves forming a conductor circuit on an organic insulating layer and then forming a barrier film on the surface of the conductor circuit. If a barrier film with low conductivity, such as a metal oxide, is formed, this may raise concerns about the reliability of electrical continuity during subsequent interlayer connection at via openings. Furthermore, even when considering the case of providing a barrier film made of a metal exhibiting sufficient conductivity, there are only a limited number of metals that can be preferentially and selectively deposited only on the surface of a conductor circuit provided on an organic insulating layer, leaving room for improvement in terms of the degree of freedom in material selection, and while NiP is a representative metal material that can be preferentially and selectively deposited only on the surface of a conductor circuit, because Ni is a magnetic material, it may have an adverse effect on signal quality when forming fine circuits with a low L / S. In contrast, in the method of the present invention, in step (X), a barrier film is formed on the surface of a first conductor circuit formed on the metal layer of a metal layer-provided substrate, and an insulating layer is formed so as to embed the barrier film-provided first conductor circuit, thereby forming a first circuit board on the metal layer-provided substrate, the first conductor circuit having a barrier film-provided first conductor circuit on its first main surface. Then, in the subsequent step (Y), the base material with the metal layer is removed to form a first circuit board having a first main surface on which the first conductive circuit is exposed, and a barrier film is formed on the surface of the exposed first conductive circuit to form a first circuit board having the first conductive circuit covered with the barrier film on the first main surface side.The method of the present invention is simpler than the damascene method and offers the advantage of greater freedom in material selection when forming the barrier film compared to conventional semi-additive methods in which conductor circuits are formed on an organic insulating layer and then a barrier film is formed on the surface of the organic insulating layer. For example, when forming a barrier film from a material with sufficient conductivity, such as metal, in step (X), it is not necessary to selectively form the barrier film only on the surface of the first conductor circuit (because the barrier film formed on the metal layer of the metal-layer-covered substrate can be easily removed by polishing or the like in a later step). Therefore, the material is not limited to NiP or the like, and various materials may be used. When forming a barrier film from a material with low conductivity, such as metal oxide, in step (X), the barrier film present in interlayer connections such as vias can be easily removed by polishing or the like, as described below. Furthermore, when forming a barrier film on the exposed surface of the first conductor circuit in step (Y), the barrier film can be formed using a mask pattern that exposes the first conductor circuit depending on the location where the barrier film is to be formed, and the material of the barrier film is not important. For example, a barrier film made of a material with low conductivity such as metal oxide may be formed on the surface of the first conductive circuit other than the electrode pad portions corresponding to the electrodes of the semiconductor chip. Also, a barrier film made of a material with sufficient conductivity such as metal may be formed on the surface of the first conductive circuit in the electrode pad portions, or no barrier film may be formed.

[0128] By forming a barrier film on the surface of the first conductive circuit, the barrier film is interposed between the first conductive circuit and the insulating layer, thereby preventing short circuits even when the L / S ratio of the first conductive circuit is small, and achieving a circuit board with good insulation reliability. Note that in (X2), the barrier film does not need to be formed selectively only on the surface of the first conductive circuit, and may also be formed on the metal layer of the metal layer-formed substrate. Also, in (X2), it is sufficient that the barrier film is formed on at least a portion of the surface of the first conductive circuit, but from the perspective of achieving a circuit board with good insulation reliability, it is preferable that the barrier film be formed on the entire surface of the first conductive circuit.

[0129] In the present invention, the material for the barrier film is not limited as long as it can suppress the diffusion of metal atoms from the first conductive circuit to the insulating layer, but inorganic materials are typically used. Specific examples of barrier film materials include metals that have a lower diffusivity into the insulating layer than the metal atoms contained in the first conductive circuit. Examples of metals with such low diffusivity include titanium, nickel, palladium, chromium, tantalum, tungsten, cobalt, and gold, as well as alloys containing these metal elements. Specific examples of barrier film materials include inorganic oxides such as metal oxides. Examples of metal oxides include alumina (aluminum oxide), zinc oxide, silicon oxide, magnesium oxide, calcium oxide, zirconium oxide, yttrium oxide, nickel oxide, iron oxide, titanium oxide, tantalum oxide, tin oxide, vanadium oxide, cerium oxide, and chromium oxide, with silicon oxide being preferred. The barrier film material may be used alone or in combination of two or more. Therefore, in one embodiment, the barrier film is a barrier film made of one or more materials selected from metals and metal oxides.

[0130] The thickness of the barrier film is preferably 0.001 μm or more, more preferably 0.01 μm or more, from the viewpoint of obtaining a circuit board with good insulation reliability, and is preferably 1 μm or less, more preferably 0.5 μm or less, 0.3 μm or less, or 0.2 μm or less, from the viewpoint of effectively suppressing loss in signal transmission by increasing the area occupied by the insulating layer.

[0131] The method for forming the barrier film is not particularly limited, and the barrier film can be formed by an appropriate method depending on the material of the barrier film to be used.

[0132] For example, when a barrier film is formed using a metal, the barrier film can be formed by a coating method, a PVD (Physical Vapor Deposition) method such as sputtering, a printing method or a spray method using a metal paste, and a plating method. In the case of a coating method, the barrier film can be formed, for example, by applying a metal complex and then heating. In addition, when a metal paste is used, the barrier film can be formed by applying a paste containing metal particles and then sintering it.

[0133] For example, when forming a barrier film using an inorganic oxide, the barrier film can be formed by a CVD (Chemical Vapor Deposition) method, an aerosol deposition method, or the like. The CVD method can be performed using a CVD apparatus such as the SAMCO Liquid Source CVD (registered trademark) apparatus "PD-200SPT." In the aerosol deposition method, a metal oxide powder is aerosolized by a gas, and the aerosol is sprayed onto the surface of the first conductive circuit to form the barrier film.

[0134] An example of (X2) will be described below with reference to FIG.

[0135] Barrier film 30b is formed on the surface of first conductive circuit 30 ( FIG. 10 ). The barrier film may be formed on at least a portion of the surface of first conductive circuit 30, but from the perspective of realizing a circuit board with good insulation reliability, it is preferable to form it on the entire surface of first conductive circuit 30. FIG. 10 shows an embodiment in which barrier film 30b is formed on the surface of first conductive circuit 30 and the exposed surface of metal layer 2.

[0136] -(X3)- In (X3), a resin composition layer is formed from a resin composition containing a curable resin so as to embed the first conductor circuit with a barrier film formed on the metal layer, and the resin composition layer is cured to form an insulating layer.

[0137] As described above, the resin composition layer is formed using a resin composition containing at least one selected from the group consisting of a curable resin, preferably a thermosetting resin and a radically polymerizable resin. From the viewpoints of being able to form the resin composition so as to embed the barrier film-covered first conductive circuit and exhibiting sufficient insulation properties after curing, the resin composition layer is preferably formed using a resin composition containing a thermosetting resin, more preferably formed using a resin composition containing a thermosetting resin and at least one curing agent and inorganic filler, and even more preferably formed using a resin composition containing an epoxy resin, a curing agent, and an inorganic filler. The resin composition is as described above in the section <Resin Composition>.

[0138] (X3) may be carried out by applying the resin composition in a varnish state, or by forming a resin composition layer containing the resin composition in advance and laminating the resin composition layer.

[0139] In a preferred embodiment, (X3) comprises laminating a resin sheet comprising a support film and a resin composition layer provided on the support film onto a substrate with a metal layer provided with a barrier film-covered first conductor circuit, such that the resin composition layer is bonded to the barrier film-covered first conductor circuit.

[0140] Examples of the support film include a film made of a plastic material, a metal foil, and release paper, with a film made of a plastic material and a metal foil being preferred. When a film made of a plastic material is used as the support film, examples of the plastic material include polyesters such as PET and PEN, acrylics such as PC and PMMA, cyclic polyolefins, TAC, PES, polyether ketone, and polyimide. When a metal foil is used as the support film, examples of the metal foil include copper foil and aluminum foil, with copper foil being preferred. As the copper foil, a foil made of a single metal such as copper may be used, or a foil made of an alloy of copper and another metal (e.g., tin, chromium, silver, magnesium, nickel, zirconium, silicon, titanium, etc.) may be used. The support film may be subjected to a matte treatment, a corona treatment, or an antistatic treatment on the surface that will be bonded to the resin composition layer. Furthermore, as the support film, a support film with a release layer having a release layer on the surface that will be bonded to the resin composition layer may be used.

[0141] The thickness of the support film is not particularly limited, but is preferably in the range of 5 μm to 75 μm, more preferably in the range of 10 μm to 60 μm. When a support film with a release layer is used, it is preferable that the thickness of the entire support film with a release layer is in the above range.

[0142] The resin sheet can be prepared, for example, by preparing a resin varnish by dissolving the resin composition in an organic solvent or by applying the resin varnish to a support film using a die coater or the like, and then drying the varnish to form a resin composition layer.

[0143] In the resin sheet, the thickness of the resin composition layer is not particularly limited as long as it is possible to embed the first conductor circuits with a barrier film, and may be determined appropriately depending on the specific design.

[0144] The lamination of the resin sheet is not particularly limited as long as the resin composition layer can be laminated so as to embed the barrier film-attached first conductor circuit, and can be carried out, for example, by thermocompression bonding the resin sheet to the metal layer-attached substrate from the support film side. Examples of a member for thermocompression bonding the resin sheet to the metal layer-attached substrate (hereinafter also referred to as a "thermocompression bonding member") include a heated metal plate (such as a SUS panel) or a metal roll (such as a SUS roll). Note that rather than pressing the thermocompression bonding member directly onto the resin sheet, it is preferable to press it via an elastic material such as heat-resistant rubber so that the resin sheet can sufficiently conform to the surface irregularities of the metal layer-attached substrate due to the first conductor circuit and the interlayer connection conductors.

[0145] The resin sheet may be laminated by a vacuum lamination method. In the vacuum lamination method, the thermocompression temperature is preferably in the range of 60°C to 160°C, more preferably 80°C to 140°C, the thermocompression pressure is preferably in the range of 0.098 MPa to 1.77 MPa, more preferably 0.29 MPa to 1.47 MPa, and the thermocompression time is preferably in the range of 20 seconds to 400 seconds, more preferably 30 seconds to 300 seconds. The lamination is preferably carried out under reduced pressure conditions of 26.7 hPa or less. The lamination may be carried out using a vacuum laminator. Examples of commercially available vacuum laminators include a vacuum pressure laminator manufactured by Meiki Seisakusho Co., Ltd., a vacuum applicator manufactured by Nikko Materials Co., Ltd., and a batch-type vacuum pressure laminator.

[0146] After lamination, the laminated resin sheets may be smoothed under normal pressure (atmospheric pressure), for example, by pressing a thermocompression member from the support film side. The pressing conditions for the smoothing treatment may be the same as the thermocompression conditions for lamination. Lamination and smoothing treatment may be performed consecutively using a vacuum laminator.

[0147] The resin composition layer is then cured to form an insulating layer, which embeds the first conductive circuits with a barrier film.

[0148] The curing conditions for the resin composition layer are not particularly limited, and conditions that are usually employed when forming an insulating layer for a circuit board may be used.

[0149] The thermal curing conditions for the resin composition layer vary depending on the type of resin composition, but in one embodiment, the curing temperature is preferably 120° C. to 250° C., more preferably 150° C. to 240° C. The curing time is preferably 5 minutes to 240 minutes, more preferably 10 minutes to 150 minutes.

[0150] When a resin composition layer (insulating layer) is formed using a resin sheet, the support film may be removed before or after the resin composition layer is cured.

[0151] An example of (X3) will be described below with reference to FIGS.

[0152] A resin composition layer 50 is formed to embed first conductive circuits 30 provided with barrier film 30b, and the resin composition layer is cured to form insulating layer 51 ( FIG. 11 ). It is preferable to form insulating layer 51 thick enough to embed first conductive circuits 30 provided with barrier film and interlayer connection conductors, and then remove excess insulating layer 51 by polishing to expose the interlayer connection conductors, thereby flattening and smoothing the surface ( FIG. 12 ). The polishing method is not particularly limited, and may be, for example, chemical mechanical polishing or mechanical polishing methods such as buffing, belt polishing, and roll polishing. While FIG. 12 shows an embodiment in which the barrier film provided on the surface of the interlayer connector is removed by polishing, if a material exhibiting good conductivity is used as the barrier film, insulating layer 51 may be removed by polishing to expose the interlayer connector with the barrier film (i.e., while maintaining the barrier film provided on the surface of the interlayer connector).

[0153] After (X3), a conductor circuit and an insulating layer can be formed to produce a multilayer circuit board.

[0154] Therefore, in a preferred embodiment, the method of the present invention further comprises, after (X3), the steps of: (i) forming a second conductor circuit on the surface of the insulating layer; and (ii) forming a resin composition layer so as to embed the second conductor circuit, and curing the resin composition layer to form an insulating layer.

[0155] -Step (i)- In step (i), second conductive circuits are formed on the surface of the insulating layer.

[0156] The second conductive circuit may be formed in accordance with a known circuit formation method such as a semi-additive method or a full-additive method.

[0157] For example, when forming a second conductive circuit using a semi-additive process, a metal layer is formed on the surface of an insulating layer, a photoresist is applied to the metal layer, and the photoresist is then exposed and developed to expose a portion of the metal layer corresponding to the desired circuit pattern. Next, a conductor layer is formed on the exposed metal layer using electroplating, and the photoresist is then removed. Thereafter, unnecessary metal layer other than the conductor layer-forming portion is removed by etching or the like, thereby forming a second conductive circuit having the desired circuit pattern.

[0158] When forming the second conductive circuit by a semi-additive method, the metal layer functioning as a plating seed layer may be formed by dry plating or wet plating. Examples of dry plating include physical vapor deposition (PVD) methods such as sputtering, ion plating, and vacuum deposition, and chemical vapor deposition (CVD) methods such as thermal CVD and plasma CVD. Examples of wet plating include electroless plating. The thickness of the metal layer is preferably thin in order to form a thin second conductive circuit, and may be, for example, 1 μm or less, 0.8 μm or less, 0.6 μm or less, 0.5 μm or less, 0.4 μm or less, or 0.2 μm or less. The lower limit of the thickness of the metal layer may be, for example, 0.01 μm or more, 0.02 μm or more, in order to prevent plating burn when forming the conductive layer by electroplating.

[0159] The line and space (L / S) of the second conductive circuit and the thickness of the circuit conductor layer may be determined appropriately depending on the specific design of the circuit board for a semiconductor package.

[0160] An example of step (i) will be described below with reference to Figures 13 to 18. In the illustrated embodiment, the second conductive circuits are formed by a semi-additive method.

[0161] Metal layer 31 is formed on the surface of the insulating layer obtained in (X3) ( FIG. 13 ). Next, photoresist 22 is provided on metal layer 31 ( FIG. 14 ), and photoresist 22 is exposed and developed to expose metal layer 31 in a manner corresponding to the circuit pattern of the second conductive circuit to be formed ( FIG. 15 ). Conductive layer 30 is then formed on the exposed metal layer by electrolytic plating ( FIG. 16 ), and photoresist 22 is removed ( FIG. 17 ). Thereafter, unnecessary metal layer 31 outside the area where the conductor layer will be formed is removed by etching or the like ( FIG. 18 ), thereby forming second conductive circuit 30 on the surface of the insulating layer.

[0162] -Step (ii)- In step (ii), a resin composition layer is formed so as to embed the second conductive circuits, and the resin composition layer is cured to form an insulating layer.

[0163] Step (ii) may be carried out in the same manner as in (X3) described above. The composition of the resin composition used to form the resin composition layer is as described in the above <Resin Composition> section, and the configuration of the resin sheet is as described for (X3). The resin composition used to form the resin composition layer in step (ii) may have the same composition as the resin composition used in (X3), or may have a different composition.

[0164] By repeating steps (i) and (ii) N times, a circuit board (first circuit board) having N+1 circuit layers can be manufactured. When manufacturing such a multilayer circuit board, steps of drilling holes in the insulating layer and desmearing the insulating layer may be performed after the nth step (ii) and before the n+1th step (i). These steps may be performed according to various methods known to those skilled in the art for use in manufacturing circuit boards. This allows via conductors to be formed to connect the layers together in the n+1th step (i).

[0165] An example of the step (ii) and a procedure for forming the via conductors will be described below with reference to FIGS.

[0166] Resin composition layer 50 is formed to embed second conductive circuit 30 provided on insulating layer 51, and the resin composition layer is cured to form insulating layer 51 ( FIG. 19 ). In FIG. 19 , the boundary between insulating layer 51 formed in (X3) and resin composition layer 50 (insulating layer 51) formed in step (ii) is indicated by a dotted line, but the insulating layer formed in step (ii) is integrated with the insulating layer formed in (X3) to form insulating layer 51. Next, via holes 51v are formed in the insulating layer according to the desired interlayer connection pattern ( FIG. 20 ). After desmearing, conductors can be formed in via holes 51v to form via conductors 30 ( FIG. 21 ).

[0167] 13 to 21 show an example in which step (i) and step (ii) are each performed once, but as mentioned above, by repeatedly performing step (i) and step (ii) N times, a first circuit board having N+1 circuit layers can be manufactured.

[0168] By repeating steps (i) and (ii) N times, a circuit board (first circuit board) having N+1 circuit layers is formed on the base material with a metal layer, and then it is preferable to further process the exposed surface of the first circuit board, i.e., the second main surface opposite to the first main surface, in order to realize a surface structure suitable as a bonding surface with a core circuit board.

[0169] For example, a resin insulating layer may be formed on the second main surface of the first circuit board, and an electrode pattern may be formed to correspond to the electrodes of the core circuit board, thereby forming the core circuit board bonding surface.

[0170] Therefore, in a preferred embodiment, the method of the present invention, after the Nth time of step (ii), carries out the steps of: (iii) forming a resin insulating layer on the second main surface of the first circuit board; and (iv) forming an electrode pattern on the resin insulating layer, thereby forming a core circuit board bonding surface on the second main surface side of the first circuit board.

[0171] -Step (iii)- In the step (iii), a resin insulating layer is formed on the second main surface of the first circuit board.

[0172] Step (iii) may be performed by applying a resin composition to the second main surface of the first circuit board to form a resin insulating layer. The resin composition used to form the resin insulating layer in step (iii) is not particularly limited as long as it can achieve a resin insulating layer that functions as a protective film for the conductor circuit and can form an electrode pattern on the resin insulating layer in step (iv), described below. It may be a photosensitive resin composition, a thermosetting resin composition, or a thermoplastic resin composition. Therefore, in one embodiment, step (iii) is performed by applying a resin composition selected from the group consisting of a photosensitive resin composition, a thermosetting resin composition, and a thermoplastic resin composition to the second main surface of the first circuit board to form a resin insulating layer. Furthermore, in step (iii), these resin compositions may be applied to the second main surface of the first circuit board as a liquid composition, or may be applied to the second main surface of the first circuit board as a resin sheet containing a layer of the resin composition. When a photosensitive resin composition is used, the photosensitive resin composition can be cured by exposure and appropriate heating to form a resin insulating layer. When a thermosetting resin composition is used, the thermosetting resin composition can be heated to cure the composition, thereby forming a resin insulating layer. When a thermoplastic resin composition is used, the resin insulating layer can be formed by forming the resin composition into a film.

[0173] The composition of the resin composition used to form the resin insulating layer in step (iii) is not particularly limited as long as it can realize the desired resin insulating layer as described above. In the photosensitive resin composition, it is a resin composition containing at least a photosensitive resin that can be cured by the action of light. It may be a positive photosensitive resin composition in which the exposed portion is removed by development, or a negative photosensitive resin composition in which the unexposed portion is removed by development. Any conventionally known resin composition may be used (for example, see JP 2022-184623 A and JP 2019-125629 A). In the thermosetting resin composition, it is sufficient as long as it contains at least a thermosetting resin that can be cured by the action of heat. Examples of thermosetting resins include epoxy resins, benzocyclobutene resins, epoxy acrylate resins, urethane acrylate resins, urethane resins, cyanate resins, polyimide resins, benzoxazine resins, unsaturated polyester resins, phenolic resins, melamine resins, and silicone resins. Among these, a resin composition containing an epoxy resin as the thermosetting resin is preferred, and for example, the epoxy resin composition described above in the section <Resin Composition> may be used (however, the presence or absence and content of an inorganic filler will be described later.) The thermoplastic resin composition may be any resin composition containing at least a thermoplastic resin that can be softened by the action of heat, and examples of the thermoplastic resin include phenoxy resin, polyvinyl acetal resin, polysulfone resin, polyethersulfone resin, polyphenylene ether resin, polyetheretherketone resin, and polyester resin.

[0174] The resin composition used to form the resin insulation layer in step (iii) may or may not contain an inorganic filler (the type of which is as explained in the above <Resin Composition> section) in addition to the above resin. The content of the inorganic filler in the resin composition may be, for example, 50% by mass or less, 40% by mass or less, 30% by mass or less, 20% by mass or less, 10% by mass or less, 5% by mass or less, etc., when the non-volatile components of the resin composition are taken as 100% by mass.

[0175] The resin insulation layer formed in step (iii) preferably exhibits a low coefficient of thermal expansion from the viewpoint of suppressing cracking during the manufacture and operation of the semiconductor package. For example, the linear thermal expansion coefficient α1 of the resin insulation layer in the temperature range below its glass transition temperature (Tg) is preferably less than 50 ppm / °C, more preferably 45 ppm / °C or less, or 40 ppm / °C or less. The linear thermal expansion coefficient α1 is obtained by performing thermomechanical analysis twice consecutively under measurement conditions of a load of 1 g and a heating rate of 5°C / min, and calculating the average linear thermal expansion coefficient (CTE; ppm / °C) in the range from 25°C to Tg (°C) or less in the second measurement. The first measurement is performed by heating to 200°C, and the second measurement is performed by heating to 260°C.

[0176] From a similar viewpoint, it is preferable that the resin insulation layer formed in step (iii) exhibits a low modulus of elasticity. For example, the tensile modulus of the resin insulation layer measured at 25°C in accordance with JIS K7161 is preferably less than 15 GPa, more preferably 14 GPa or less, 12 GPa or less, or 10 GPa or less.

[0177] The thickness of the resin insulation layer formed in step (iii) is preferably 2 μm or more, more preferably 4 μm or more or 5 μm, from the viewpoint of obtaining a circuit board with better insulation reliability and realizing good bonding with the core circuit board, and the upper limit is preferably 40 μm or less, more preferably 35 μm or less, 30 μm or less, 25 μm or less, or 20 μm or less.

[0178] -Step (iv)- In step (iv), an electrode pattern is formed on the resin insulating layer.

[0179] The procedure for step (iv) is not particularly limited as long as it is possible to form an electrode pattern that electrically connects the conductor circuit (N+1th conductor circuit) in the outermost layer on the second main surface side of the first circuit board to the electrodes of the core circuit board. In one embodiment, step (iv) may be performed by drilling the resin insulating layer to form via holes according to the desired electrode pattern, and then forming a conductor layer on the surface of the resin insulating layer and in the via holes to provide electrode pads.

[0180] The resin insulating layer may be drilled according to the composition of the resin composition used to form the resin insulating layer, etc. For example, when a photosensitive resin composition is used, the hole may be drilled by exposure and development, and when a thermosetting resin composition or a thermoplastic resin composition is used, the hole may be drilled using a laser, plasma, etc. The size and shape of the hole may be determined appropriately according to the design of the core circuit board bonding surface.

[0181] After forming the via holes in the resin insulating layer, a desmear treatment may be performed. The desmear treatment may be performed by a dry desmear treatment, a wet desmear treatment, or a combination of these. Examples of the dry desmear treatment include a desmear treatment using plasma and a dry sandblasting treatment in which an abrasive is sprayed from a nozzle to polish the treatment target. Examples of the wet desmear treatment include a desmear treatment using an oxidizing agent solution and a wet sandblasting treatment in which an abrasive slurry solution is sprayed to polish the treatment target.

[0182] In forming the electrode pattern, the conductor layer may be formed in accordance with a known circuit formation method such as a semi-additive method or a full-additive method.

[0183] For example, when forming an electrode pattern using a semi-additive method, a metal layer that functions as a plating seed layer is formed on the surface of an insulating resin layer, a photoresist is applied to the metal layer, and then the photoresist is exposed and developed to expose a portion of the metal layer corresponding to the desired circuit pattern. Next, a conductor layer is formed on the exposed metal layer using an electroplating method, and the photoresist is then removed. Thereafter, unnecessary metal layer other than the conductor layer formation portion is removed by etching or the like, thereby forming a conductor layer (electrode pattern) having the desired pattern.

[0184] When forming a conductor layer by a semi-additive method, the metal layer functioning as a plating seed layer may be formed by dry plating or wet plating. Examples of dry plating include physical vapor deposition (PVD) methods such as sputtering, ion plating, and vacuum deposition, and chemical vapor deposition (CVD) methods such as thermal CVD and plasma CVD. Examples of wet plating include electroless plating. The thickness of the metal layer is preferably thin in order to form a thin conductor layer, and may be, for example, 1 μm or less, 0.8 μm or less, 0.6 μm or less, 0.5 μm or less, 0.4 μm or less, or 0.2 μm or less. The lower limit of the thickness of the metal layer may be, for example, 0.01 μm or more, 0.02 μm or more, in order to prevent plating burn when forming a conductor layer by electroplating.

[0185] The conductor material used for the conductor layer is not particularly limited. In a preferred embodiment, the conductor layer contains one or more metals selected from the group consisting of gold, platinum, palladium, silver, copper, aluminum, cobalt, chromium, zinc, nickel, titanium, tungsten, iron, tin, and indium. The conductor layer may be a single metal layer or an alloy layer. Examples of the alloy layer include a layer formed from an alloy of two or more metals selected from the above group (e.g., a nickel-chromium alloy, a copper-nickel alloy, and a copper-titanium alloy). Among these, from the viewpoints of versatility, cost, ease of patterning, etc., in forming the conductor layer, a single metal layer of chromium, nickel, titanium, aluminum, zinc, gold, palladium, silver, or copper, or an alloy layer of a nickel-chromium alloy, a copper-nickel alloy, or a copper-titanium alloy is preferred. A single metal layer of chromium, nickel, titanium, aluminum, zinc, gold, palladium, silver, or copper, or an alloy layer of a nickel-chromium alloy is more preferred, and a single metal layer of copper is even more preferred.

[0186] When a conductor circuit (the (N+1)th conductor circuit) on the outermost layer on the second main surface of the first circuit board is connected to an electrode of the core circuit board with a microbump, a conductor layer is formed on a metal layer, a solder layer is then formed on the conductor layer by electrolytic plating, and then the photoresist is removed, and unnecessary metal layers other than the conductor layer-forming portion are removed by etching, etc. In such an embodiment, the solder layer may be, for example, a single metal layer of tin or an alloy layer of tin with silver, copper, antimony, bismuth, nickel, or the like, and a nickel plating layer may be provided between the conductor layer and the solder layer to impart reflow heat resistance.

[0187] In order to achieve good bonding when bonding the first circuit board and the core circuit board in the step (Z) described below, it is preferable that the resin insulation layer formed on the core circuit board bonding surface of the first circuit board has a predetermined degree of hardness. Specifically, the degree of hardness of the resin insulation layer is preferably 50% or more, more preferably 60% or more, even more preferably 70% or more, 80% or more, 90% or more, or 95% or more, and may even be 100%. By having the resin insulation layer constituting the core circuit board bonding surface of the first circuit board have such a degree of hardness prior to performing step (Z), it is possible to suppress the generation of degassing during step (Z) and significantly reduce the occurrence of bonding defects. The degree of hardness of the resin insulation layer can be measured by differential scanning calorimetry. An example of a differential scanning calorimetry device is the "DSC7020" manufactured by Hitachi High-Tech Science Corporation.

[0188] In order to achieve even better bonding, the bonding surface of the first circuit board to the core circuit board may be polished and flattened prior to bonding the first circuit board to the core circuit board in step (Z) described below. Polishing may be performed using a known technique such as chemical mechanical polishing.

[0189] By the above step (X), a first circuit board having a first conductor circuit with a barrier film on the first main surface side can be formed on a substrate with a metal layer. According to the method of the present invention, even when the insulating layer contains an inorganic filler, it is possible to form a first circuit board having a conductor circuit (first conductor circuit) with a barrier film in an extremely fine pattern, such as a minimum line and space (L / S) of 2 / 2 μm or less, on a substrate with a metal layer.

[0190] <Step (Y)> In step (Y), a first circuit board is formed that includes a first conductive circuit covered with a barrier film on the first main surface side.

[0191] Specifically, the following steps (Y1) and (Y2) are carried out in this order: (Y1) removing the metal layer-attached substrate to form a first circuit board having a first main surface on which first conductive circuits are exposed; and (Y2) forming a barrier film on the exposed surfaces of the first conductive circuits.

[0192] Hereinafter, (Y1) and (Y2) will be described separately.

[0193] -(Y1)- In (Y1), the base material with the metal layer is removed to form a first circuit board having a first main surface from which the first conductive circuits are exposed.

[0194] (Y1) can be performed by simultaneously removing the metal layer and the substrate, or by removing the substrate and then removing the metal layer, depending on the types of metal layer and substrate used. (Y1) can be performed, for example, by etching, chemical-mechanical polishing, or the like. For example, the substrate can be removed by chemical-mechanical polishing, or the like, and then the metal layer can be removed by etching, or the like. Furthermore, when a substrate with a metal layer having a release layer between the metal layer and the substrate is used, (Y1) can be performed by peeling and removing the substrate, and then removing the metal layer by etching, chemical-mechanical polishing, or the like.

[0195] An example of (Y1) will be described below with reference to Figures 21 to 24. Note that the illustrated embodiment shows a procedure for removing a substrate when a substrate with a metal layer having a release layer between the metal layer and the substrate is used.

[0196] In the substrate 10 with a metal layer, the substrate 1 is peeled from the metal layer 2 ( FIGS. 21 and 22 ; the peel layer is not shown). Next, the metal layer 2 from the substrate with a metal layer is removed by etching, chemical-mechanical polishing, or other methods ( FIGS. 23 and 24 ). While FIGS. 23 and 24 show an embodiment in which the barrier film formed on the surface of the metal layer in (X2) is also removed, if an insulating material such as a metal oxide is used as the barrier film, the metal layer may be removed by polishing so as to maintain the barrier film formed on the surface of the metal layer. In this manner, a first circuit board is formed, having a first main surface 100a from which the first conductive circuits 30 are exposed. As shown in FIG. 24 , the first circuit board includes first conductive circuits 30 as trench-type conductive circuits on the first main surface 100a.

[0197] --(Y2)--In (Y2), a barrier film is formed on the exposed surfaces of the first conductive circuits.

[0198] The material and method of forming the barrier film are as described above for (X2).

[0199] When forming a barrier film made of, for example, a metal (preferable types are as described above) on the surface of the first conductive circuit, the barrier film can be formed by electrolytic plating using the first conductive circuit as an electrode, which makes it possible to selectively form a barrier film on the surface of the first conductive circuit.

[0200] When forming a barrier film made of, for example, a metal oxide (preferable types are as described above) on the surface of the first conductive circuit, the barrier film can be formed by aerosol deposition. Aerosol deposition requires that the kinetic energy of raw material powder particles be converted into thermal energy through collisions. Therefore, a coating is easily formed on hard surfaces, but is difficult to form on soft surfaces. Generally, conductor materials have high hardness, and therefore the surface of a first conductive circuit formed from that conductor material is hard. Therefore, a barrier film made of a metal oxide can be easily formed on the surface of the first conductive circuit by aerosol deposition. On the other hand, while part or all of the surface of the insulating layer is formed from a resin material, this resin material generally has a lower hardness than the conductor material. Therefore, it is difficult to form a barrier film made of a metal oxide on the surface of the insulating layer by aerosol deposition. Therefore, aerosol deposition allows for selective formation of a barrier film on the surface of the first conductive circuit.

[0201] In step (Y), when a barrier film is formed on the exposed surface of the first conductive circuit, the barrier film may be formed using a mask pattern that exposes the first conductive circuit depending on the location where the barrier film is to be formed. When using a mask pattern, for example, a barrier film made of a low-conductivity material such as metal oxide may be formed on the surface of the first conductive circuit other than the electrode pad portions corresponding to the electrodes of the semiconductor chip. Furthermore, a barrier film made of a material with sufficient conductivity such as metal may be formed on the surface of the first conductive circuit in the electrode pad portions, or no barrier film may be formed.

[0202] In (Y2), the thickness of the barrier film formed on the surface of the first conductive circuit is preferably 0.001 μm or more, more preferably 0.01 μm or more, from the viewpoint of obtaining a circuit board with good insulation reliability, and is preferably 1 μm or less, more preferably 0.5 μm or less, 0.3 μm or less, or 0.2 μm or less, from the viewpoint of easily achieving a flat semiconductor chip mounting surface.

[0203] An example of (Y2) will be described below with reference to FIG.

[0204] Barrier film 30b is formed on the surfaces of first conductive circuits 30 exposed on first main surface 100a of first circuit board 100 (FIG. 25). The barrier film may be formed on at least a portion of the surface of first conductive circuits 30, but from the perspective of realizing a circuit board with good insulation reliability, it is preferable to form the barrier film on the entire surface of first conductive circuits 30.

[0205] After (Y2), the first main surface of the first circuit board may be further processed to achieve a surface structure suitable for use as a semiconductor chip mounting surface.

[0206] For example, a resin insulating layer may be formed on the first main surface of the first circuit board, and an electrode pattern may be formed to correspond to the electrodes of the semiconductor chip, thereby forming a semiconductor chip mounting surface.

[0207] Therefore, in a preferred embodiment, after (Y2), the method of the present invention includes (Y3) forming a resin insulating layer on the first main surface of the first circuit board, and (Y4) forming an electrode pattern on the resin insulating layer, thereby forming a semiconductor chip mounting surface on the first main surface side of the first circuit board.

[0208] -(Y3)- In (Y3), a resin insulating layer is formed on the first main surface of the first circuit board.

[0209] (Y3) may be performed in the same manner as (iii) described above in relation to the core circuit board bonding surface of the first circuit board. That is, a resin insulating layer may be formed by applying a resin composition to the first main surface of the first circuit board. The resin composition used to form the resin insulating layer in (Y3) is not particularly limited as long as it can achieve a resin insulating layer that functions as a protective film for the conductor circuit and can also form an electrode pattern on the resin insulating layer in (Y4), as described below. It may be a photosensitive resin composition or a thermosetting resin composition. Therefore, in one embodiment, (Y3) is performed by applying a resin composition selected from the group consisting of photosensitive resin compositions and thermosetting resin compositions to the first main surface of the first circuit board to form a resin insulating layer. Furthermore, in (Y3), these resin compositions may be applied to the first main surface of the first circuit board as a liquid composition, or may be applied to the first main surface of the first circuit board as a resin sheet containing a layer of the resin composition. When a photosensitive resin composition is used, the photosensitive resin composition can be cured by exposure and appropriate heating to form a resin insulating layer. When a thermosetting resin composition is used, the thermosetting resin composition can be cured by heating to form a resin insulating layer. These photosensitive resin compositions and thermosetting resin compositions may be the same as those described in (iii) above in relation to the core circuit board bonding surface of the first circuit board. The resin composition used to form the resin insulating layer in (Y3) may or may not contain an inorganic filler (the type of which is as described in the <Resin Composition> section above) in addition to the resin. The content of the inorganic filler in the resin composition may be, for example, 50% by mass or less, 40% by mass or less, 30% by mass or less, 20% by mass or less, 10% by mass or less, or 5% by mass or less, when the non-volatile components of the resin composition are taken as 100% by mass.

[0210] The resin insulating layer formed in (Y3) preferably exhibits a low thermal expansion coefficient from the viewpoint of suppressing cracks during the manufacture and operation of the semiconductor package, and for example, the linear thermal expansion coefficient α1 in a temperature range equal to or lower than the glass transition temperature (Tg) of the resin insulating layer is preferably less than 50 ppm / ° C., more preferably equal to or lower than 45 ppm / ° C. or equal to or lower than 40 ppm / ° C. The linear thermal expansion coefficient α1 can be measured in the same manner as described in (iii) above.

[0211] From a similar viewpoint, it is preferable that the resin insulation layer formed in (Y3) exhibits a low modulus of elasticity. For example, the tensile modulus of the resin insulation layer measured at 25°C in accordance with JIS K7161 is preferably less than 15 GPa, more preferably 14 GPa or less, 12 GPa or less, or 10 GPa or less.

[0212] The thickness of the resin insulating layer formed in (Y3) is preferably 1 μm or more, more preferably 2 μm or more, from the viewpoint of obtaining a circuit board with better insulation reliability and realizing good bonding with the semiconductor chip, and the upper limit is preferably 25 μm or less, more preferably 20 μm or less, 15 μm or less, 13 μm or less, or 10 μm or less.

[0213] --(Y4)--In (Y4), an electrode pattern is formed on the resin insulating layer.

[0214] The procedure for (Y4) is not particularly limited as long as it is possible to form an electrode pattern that electrically connects the first conductive circuit of the first circuit board and the electrode of the semiconductor chip. In one embodiment, (Y4) may be performed by drilling the resin insulating layer to form via holes according to the desired electrode pattern, and then forming conductors on the surface of the resin insulating layer and in the via holes to provide electrode pads.

[0215] The resin insulating layer may be drilled depending on the composition of the resin composition used to form the resin insulating layer, for example, by exposure and development when a photosensitive resin composition is used, or by using a laser, plasma, etc. when a thermosetting resin composition is used. The dimensions and shape of the holes may be determined appropriately depending on the design of the semiconductor chip mounting surface.

[0216] After forming the via holes in the resin insulating layer, a desmear treatment may be performed. The desmear treatment may be performed by a dry desmear treatment, a wet desmear treatment, or a combination of these. Examples of the dry desmear treatment include a desmear treatment using plasma and a dry sandblasting treatment in which an abrasive is sprayed from a nozzle to polish the treatment target. Examples of the wet desmear treatment include a desmear treatment using an oxidizing agent solution and a wet sandblasting treatment in which an abrasive slurry solution is sprayed to polish the treatment target.

[0217] In forming the electrode pattern, the conductor layer may be formed in accordance with a known circuit formation method such as a semi-additive method or a full-additive method, as described above in (iv).

[0218] For example, when forming an electrode pattern using a semi-additive method, a metal layer functioning as a plating seed layer is formed on the surface of an insulating resin layer, a photoresist is applied to the metal layer, and then the photoresist is exposed and developed to expose a portion of the metal layer corresponding to the desired circuit pattern. Next, a conductor layer is formed on the exposed metal layer using an electrolytic plating method, and the photoresist is then removed. Thereafter, unnecessary metal layer other than the conductor layer formation portion is removed by etching or the like to form a conductor layer (electrode pattern) having the desired pattern. The method for forming the metal layer functioning as a plating seed layer, the thickness of the metal layer, and the preferred type of conductor material used for the conductor layer are as described above in (iv) above.

[0219] When a conductor circuit (first conductor circuit) on the outermost layer of the first main surface of the first circuit board is connected to an electrode of a semiconductor chip with microbumps, a conductor layer is formed on a metal layer, a solder layer is then formed on the conductor layer by electrolytic plating, and then the photoresist is removed, and unnecessary metal layer other than the conductor layer-forming portion is removed by etching, etc. As described above in (iv) above, a preferred embodiment of the solder layer, as well as the fact that a nickel plating layer may be provided between the conductor layer and the solder layer to impart reflow heat resistance, are also suitable.

[0220] An example of the implementation procedure of (Y3) and (Y4) will be described below with reference to FIGS.

[0221] A resin composition 60 is applied to the first main surface 100a of the first circuit board 100 to form a resin insulating layer 61 ( FIG. 26 ). As previously described, the resin insulating layer can be formed by curing the resin composition by exposure and appropriate heating when using a photosensitive resin composition, or by heating when using a thermosetting resin composition. While FIG. 26 shows the boundary between the insulating layer 51 formed in step (X) and the resin composition 60 (resin insulating layer 61) formed in step (Y3), the resin insulating layer 61 formed in step (Y3) may be integrated with the insulating layer formed in step (X) to form an insulating layer. Next, the resin insulating layer is drilled to form via holes 61v according to the desired electrode pattern ( FIG. 27 ). Drilling the resin insulating layer can be performed by development when the resin insulating layer is formed using a photosensitive resin composition, or by using a laser, plasma, or the like when the resin insulating layer is formed using a thermosetting resin composition. 27 shows an embodiment in which the barrier film formed on the surface of first conductive circuit 30 in (Y2) is maintained in its entirety, but if a material with low conductivity such as metal oxide is used as the barrier film, the barrier film may be removed in areas where electrical continuity with the electrodes of the semiconductor chip is required, and holes may be drilled in the resin insulating layer to expose the first conductive circuit. After an appropriate desmearing process, conductors may be formed on the surface of resin insulating layer 61 and in via holes 61v to form conductor / electrode pads 70 (FIG. 28). The semi-additive method may be used to form the conductors, and the implementation procedure is as described above.

[0222] The above step (Y) makes it possible to form a first circuit board having a first conductive circuit covered with a barrier film on the first main surface side. According to the method of the present invention, even when the insulating layer contains an inorganic filler, it is possible to form a first circuit board having a trench-type conductive circuit (first conductive circuit) covered with a barrier film in an extremely fine pattern, such as a minimum line and space (L / S) of 2 / 2 μm or less.

[0223] <Step (Z)> In step (Z), the core circuit board and the first circuit board are joined together so that the first main surface of the core circuit board faces the second main surface of the first circuit board opposite to the first main surface.

[0224] The core circuit board may be any circuit board used as a circuit board for a semiconductor package, such as a copper-clad laminate, a glass substrate, a ceramic substrate, a metal substrate, a flexible substrate, or a substrate with built-in components, and may be selected to satisfy the various characteristics required for the semiconductor package.

[0225] For example, various copper-clad laminates with high reliability in terms of heat resistance (high Tg, etc.), mechanical properties (high modulus of elasticity, etc.), and thermal expansion properties (low CTE) may be selected, or various copper-clad laminates with high reliability in terms of compatibility with other materials, such as high elongation, may be selected. Furthermore, according to the method of the present invention, in which a first circuit board having a fine conductor circuit is formed and then the first circuit board is bonded to a core circuit board, even if a glass or ceramic substrate is selected as the core circuit board, there is an advantage in that a large substrate is not required and the risk of cracking can be reduced. Furthermore, a metal substrate with high reliability in terms of heat dissipation may be selected, or a flexible substrate with an insulating layer formed from a polyimide, liquid crystal polymer, or the like with high reliability in terms of dielectric properties may be selected. Alternatively, a component-embedded substrate with a semiconductor chip, electronic component, or the like built in may be selected as the core circuit board.

[0226] In this regard, in conventional 2.1D mounting techniques in which an organic fine wiring layer is formed on a core circuit board, the core circuit board is usually selected with emphasis on the process reliability when the organic fine wiring layer is formed thereon. However, in the method of the present invention in which a circuit board (first circuit board) equipped with fine circuits is formed and then this circuit board is joined to a core circuit board to manufacture a circuit board for a semiconductor package, the core circuit board can be selected with emphasis on product reliability, and therefore the core circuit board can be selected with a high degree of freedom depending on the characteristics required of the semiconductor package.

[0227] Thus, in one embodiment, the core circuit board is selected from the group consisting of a copper clad laminate, a glass substrate, a ceramic substrate, a metal substrate, a flexible substrate, and a substrate with embedded components.

[0228] The core circuit board and the first circuit board may be joined by any known method for electrically connecting circuit boards, such as solder bonding, adhesive bonding, and hybrid bonding.

[0229] Regarding solder bonding, solder bonding may be performed alone, or may be performed in combination with an underfill process to fill gaps in the joint, or may be performed in combination with an adhesive bonding process to bond circuit boards together. Also, an anisotropic conductive adhesive may be used as the adhesive to electrically connect and bond the circuit boards together.

[0230] The first circuit board formed by the above step (X) has excellent surface flatness, allowing it to be suitably bonded to the core circuit board by hybrid bonding. Hybrid bonding directly bonds the conductor circuit of the first circuit board (specifically, the electrode pads on the bonding surface of the first circuit board to the core circuit board; the same applies hereinafter to bonding with the core circuit board) to the conductor circuit of the core circuit board without using solder bumps like in solder bonding, which is advantageous in that it allows for a smaller connection pitch. Hybrid bonding may include a step of performing heat treatment to promote diffusion of the conductor material between the conductor circuit of the first circuit board and the conductor circuit of the core circuit board. Heat treatment promotes diffusion of the conductor material, allowing for rapid bonding of the first circuit board and the core circuit board. For example, hybrid bonding may be performed according to JP 2019-515511 A. In this case, in first conductor circuits with a small L / S ratio, the conductor metal material constituting the circuit may diffuse into the insulating layer, causing a short circuit. However, in the present invention, the first conductor circuit is covered with a barrier film, which advantageously reduces the possibility of such a short circuit while allowing for sufficient heat treatment to be performed to achieve good insulation reliability. Furthermore, prior to hybrid bonding, plasma treatment may be performed on one or both of the conductor circuits of the first circuit board and the conductor circuits of the core circuit board. Such plasma treatment may be performed according to JP 2020-4999 A. By performing such plasma treatment, the bonding efficiency can be improved while keeping the heat treatment temperature during hybrid bonding low.

[0231] An example of step (Z) will be described below with reference to FIGS.

[0232] The first circuit board 100 is placed so that its second main surface 100b, opposite the first main surface 100a, faces the first main surface 200a of the core circuit board 200 (FIG. 29). In FIG. 29, the conductor circuits of the first circuit board 100 are shown in black (the barrier film, resin insulating layer, and electrode pads covering the first conductor circuits on the first main surface 100a side are not shown). Although the conductor circuits of the core circuit board 200 are not shown in FIG. 29, they are aligned so that the conductor circuits of the first circuit board 100 and the conductor circuits of the core circuit board 200 are bonded together to form the desired circuit for a semiconductor package. Next, the first circuit board 100 and the core circuit board 200 are bonded together (FIG. 30). In this manner, a circuit board 500 for a semiconductor package is obtained. FIG. 30 shows a hybrid bonding method in which both circuit boards are bonded together without using solder bumps, but as mentioned above, both circuit boards may be bonded together by solder bonding or adhesive bonding.

[0233] As described above, in step (Z), the core circuit board and the first circuit board are joined so that the first main surface of the core circuit board and the second main surface of the first circuit board face each other. In the resulting circuit board for a semiconductor package, the first main surface of the first circuit board and the second main surface of the core circuit board are exposed, and these first main surface of the first circuit board and the second main surface of the core circuit board are also referred to as the "first main surface of the circuit board for a semiconductor package" and the "second main surface of the circuit board for a semiconductor package," respectively. The first main surface of the circuit board for a semiconductor package is the semiconductor chip mounting surface, and the second main surface is the surface connected to a printed wiring board.

[0234] In this way, it is possible to form a circuit board for a semiconductor package having a trench-type conductor circuit (first conductor circuit) covered with a barrier film on the first main surface side 100a in an extremely fine pattern, such as a minimum line and space (L / S) of 2 / 2 μm or less.

[0235] The circuit board for a semiconductor package manufactured by the method of the present invention is used by mounting a semiconductor chip 300 on first main surface (semiconductor chip mounting surface) 100a having a first conductive circuit covered with a barrier film, and is preferably used by mounting a plurality of semiconductor chips 300 on first main surface 100a (FIG. 31). Thus, in one embodiment, the circuit board for a semiconductor package of the present invention is a circuit board for a multi-chip package.

[0236] Furthermore, a second main surface 200b of the circuit board for semiconductor package opposite to the first main surface 100a is provided with board connection terminals such as bumps (not shown in FIG. 31), allowing the circuit board for semiconductor package to be mounted on a printed wiring board.

[0237] The above describes an embodiment in which step (Z) is performed after step (Y). In the method of the present invention, the order of step (Y) and step (Z) is not limited to this order, and step (Z) may be performed between step (X) and step (Y). Therefore, in one embodiment, step (Z) is performed after step (Y). In another embodiment, step (Z) is performed between step (X) and step (Y).

[0238] Hereinafter, an example of the procedure for performing each step will be described with reference to FIGS. 32 to 39 regarding an embodiment in which step (Z) is performed between step (X) and step (Y).

[0239] Step (X) may be carried out as described above with reference to Figures 1 to 21, thereby forming a first circuit board 100 having first conductor circuits (30 and 30b) with a barrier film on the first main surface side on a substrate 10 with a metal layer (Figure 21).

[0240] Next, step (Z) is performed. Specifically, the first circuit board 100 is disposed so that its second main surface 100b, which is opposite to the first main surface 200a of the core circuit board 200, faces the first main surface 200a (FIG. 32). In FIG. 32, the first circuit board 100 is shown schematically (the resin insulating layer and electrode pads provided on the second main surface 100b are not shown). Although the conductor circuits of the core circuit board 200 are not shown in FIG. 32, they are aligned so that the conductor circuits of the first circuit board 100 and the conductor circuits of the core circuit board 200 are bonded to each other to form the intended circuit for a semiconductor package. Next, the first circuit board 100 and the core circuit board 200 are bonded together (FIG. 33). While FIG. 33 shows a hybrid bonding method in which the two circuit boards are bonded together without solder bumps, as previously described, the two circuit boards may also be bonded together by solder bonding or adhesive bonding.

[0241] Step (Y) is then performed. First, an example of step (Y1) will be described with reference to FIGS. 33 to 36 . In the substrate 10 with a metal layer, the substrate 1 is peeled from the metal layer 2 ( FIGS. 33 and 34 ; the peel layer is not shown). Next, the metal layer 2 from the substrate with a metal layer is removed by etching, chemical-mechanical polishing, or other methods ( FIGS. 35 and 36 ). While FIGS. 35 and 36 show an embodiment in which the barrier film formed on the surface of the metal layer in step (X2) is also removed, if a material with low conductivity, such as a metal oxide, is used as the barrier film, the metal layer may be removed by polishing so as to maintain the barrier film formed on the surface of the metal layer. In this way, a first circuit board having a first main surface 100a from which the first conductive circuits 30 are exposed is formed on the core circuit board 200. As shown in FIG. 36 , the first circuit board includes first conductive circuits 30 as trench-type conductive circuits on the first main surface 100a.

[0242] An example of (Y2) will be described below with reference to Fig. 37. Barrier film 30b is formed on the surfaces of first conductive circuits 30 exposed on first main surface 100a of first circuit board 100 (Fig. 37). The barrier film may be formed on at least a portion of the surface of first conductive circuits 30, but from the perspective of achieving a circuit board with good insulation reliability, it is preferable to form the barrier film on the entire surface of first conductive circuits 30.

[0243] An example of the procedure for (Y3) and (Y4) will be described below with reference to FIGS. 38 to 40 . A resin insulating layer 61 is formed by applying a resin composition 60 to the first main surface 100a of the first circuit board 100 ( FIG. 38 ). While FIG. 38 shows the boundary between the insulating layer 51 formed in step (X) and the resin composition 60 (resin insulating layer 61) formed in step (Y3), the resin insulating layer 61 formed in step (Y3) may be integrated with the insulating layer formed in step (X) to form an insulating layer. Next, the resin insulating layer is drilled to form via holes 61v according to the desired electrode pattern ( FIG. 39 ). While FIG. 39 shows an embodiment in which the barrier film formed on the surface of the first conductive circuit 30 in step (Y2) is entirely maintained, in cases where a low-conductivity material such as a metal oxide is used as the barrier film, the resin insulating layer may be drilled to expose the first conductive circuit at locations where electrical continuity with the electrodes of the semiconductor chip is required. After a suitable desmearing process, a conductor is formed on the surface of the resin insulating layer 61 and in the via hole 61v, thereby forming the conductor / electrode pad 70 (FIG. 40).

[0244] As described above, the circuit board for a semiconductor package obtained in this manner is used by mounting a semiconductor chip 300 on first main surface (semiconductor chip mounting surface) 100a, and preferably by mounting a plurality of semiconductor chips 300 on first main surface 100a (FIGS. 30 and 31). Also, board connection terminals such as bumps (not shown in FIG. 31) are provided on second main surface 200b opposite first main surface 100a of the circuit board for a semiconductor package, so that the circuit board can be mounted on a printed wiring board, as described above.

[0245] [Circuit Board for Semiconductor Package] The method of the present invention makes it possible to easily and flexibly manufacture a circuit board for semiconductor package having a conductor circuit with excellent insulation reliability in a fine pattern on the semiconductor chip mounting surface. The present invention also provides such a circuit board for semiconductor package.

[0246] In one embodiment, the circuit board for a semiconductor package of the present invention includes: a first circuit board having a first main surface and a second main surface; and a core circuit board having the first main surface and the second main surface, the first circuit board and the core circuit board being joined together so that the second main surface of the first circuit board faces the first main surface of the core circuit board; the first circuit board includes a trench-type conductor circuit on the first main surface, the minimum line and space (L / S) of the trench-type conductor circuit being 2 / 2 μm or less; an insulating layer defining the first main surface together with the trench-type conductor circuit being made of a cured product of a resin composition containing a curable resin; and the joint surface of the trench-type conductor circuit with the insulating layer and the surface of the trench-type conductor circuit on the first main surface are covered with a barrier film. The resin composition preferably contains one or more resins selected from the group consisting of thermosetting resins and radically polymerizable resins, and more preferably contains a thermosetting resin, particularly from the viewpoint of exhibiting sufficient insulating properties after curing. It is even more preferable to contain one or more of a curing agent and an inorganic filler in addition to the thermosetting resin, and it is even more preferable to contain an epoxy resin, a curing agent, and an inorganic filler.

[0247] The first circuit board and the core circuit board, including their respective preferred embodiments and joining modes, are as explained above in the section [Method for manufacturing a circuit board for a semiconductor package].

[0248] The features of the circuit board for a semiconductor package of the present invention will be described below with reference to FIGS.

[0249] 30 (also see FIGS. 25 to 29 for the configurations of the first circuit board and the core circuit board), a circuit board for a semiconductor package according to one embodiment of the present invention includes a first circuit board 100 having a first main surface 100a and a second main surface 100b, and a core circuit board 200 having a first main surface 200a and a second main surface 200b, and the first circuit board 100 and the core circuit board 200 are bonded together so that the second main surface 100b of the first circuit board 100 faces the first main surface 200a of the core circuit board 200 ( FIGS. 29 and 30 ). As mentioned above, FIG. 30 shows a hybrid bonding mode in which the two circuit boards are bonded together without using solder bumps, but as mentioned above, the two circuit boards may also be bonded together by solder bonding or adhesive bonding.

[0250] In the circuit board for a semiconductor package of the present invention, first circuit board (100) includes first conductive circuits 30 on its first main surface (100a). First circuit board (100) also includes an insulating layer (51) that, together with first conductive circuits 30, defines first main surface (100a) and is disposed so as to embed first conductive circuits 30. That is, in the circuit board for a semiconductor package according to one embodiment of the present invention, first circuit board (100) includes trench-type conductive circuits 30 (first conductive circuits 30) on first main surface (100a). Note that in Figures 25 to 30, the trench-type conductive circuits exposed on the first main surface extend from the front to the back of the paper (i.e., in the Z direction when the paper is taken as the X-Y plane). In the circuit board for a semiconductor package of the present invention, the bonding surface of trench-type conductor circuit 30 (first conductor circuit 30) with insulating layer 51 and the surface of trench-type conductor circuit 30 on first main surface 100a are covered with barrier film 30b.

[0251] In a circuit board for a semiconductor package according to one embodiment of the present invention, trench-type conductor circuit 30 (first conductor circuit 30) provided on first main surface 100a has an extremely fine pattern, and its minimum line and space (L / S) is 2 / 2 μm or less, and more preferably 1 / 1 μm or less.

[0252] In the circuit board for semiconductor packages of the present invention, insulating layer 51, which defines first main surface 100a together with trench-type conductor circuits 30 (first conductor circuits 30), is composed of a cured product of a resin composition containing a curable resin. The resin composition is as described above in the <Resin Composition> section. However, from the viewpoint of achieving properties such as a low thermal expansion coefficient and a low dielectric loss tangent, the insulating layer preferably contains an inorganic filler. As mentioned above, when an insulating layer contains an inorganic filler, it can be difficult to form a trench-type conductor circuit in a fine pattern. In contrast, the method of the present invention makes it possible to form a trench-type conductor circuit in an extremely fine pattern, even when the insulating layer contains an inorganic filler, or even when the inorganic filler content is high. When the insulating layer contains an inorganic filler, the content of the inorganic filler in the insulating layer is preferably 20% by mass or more, more preferably 30% by mass or more, and even more preferably 40% by mass or more. It is also preferably 75% by mass or less, more preferably 70% by mass or less, and even more preferably 65% ​​by mass or less. Therefore, in a preferred embodiment, the content of inorganic filler in the insulating layer that defines the first main surface together with the trench-type conductor circuit is 20 mass % or more. Although the content and amount of inorganic filler have been described above for the insulating layer that is arranged to embed the trench-type conductor circuit, as explained above in [Method for manufacturing a circuit board for a semiconductor package], the same configuration may be used for all insulating layers that make up the circuit board.

[0253] In the circuit board for a semiconductor package of the present invention, the first circuit board 100 preferably has a multilayer structure with two or more circuit layers (including the first conductor circuit). The number of circuit layers may be determined depending on the specific design of the circuit board for a semiconductor package, but is preferably three or more, four or more, or five or more. The upper limit of the number of circuit layers is not particularly limited and may be, for example, 50 or less, 40 or less, 30 or less, etc. The method for manufacturing the first circuit board with a multilayer structure is as described above in "Method for manufacturing a circuit board for a semiconductor package."

[0254] - Cross-sectional shape of trench-type conductive circuit - The method of the present invention makes it possible to form trench-type conductive circuits with an excellent cross-sectional shape. Specifically, in a cross section in direction Y that is perpendicular to first main surface 100a and also perpendicular to the direction in which trench-type conductive circuit 30 extends (i.e., the cross section shown in Figures 25 to 30; direction Y is the up-and-down direction in Figures 25 to 30), the angle between direction y1 of a straight line defined by the sidewall of trench-type conductive circuit 30 and direction Y is 20° or less.

[0255] The angular difference between the direction y1 and the direction Y is preferably 15° or less, more preferably 10° or less, and even more preferably 8° or less, 6° or less, 5° or less, 4° or less, 2° or less, or 1° or less, and even a trench-type conductor circuit in which the angular difference is substantially 0° can be formed.

[0256] In this regard, when trench-type conductor circuits are provided using conventional techniques for forming conductor circuits on an insulating layer, the resulting conductor circuits tend to have a tapered shape, with the width decreasing from the main surface (first main surface) on which the conductor circuit is provided toward the depth of the circuit board. This tendency (such as the degree of taper angle) is more pronounced when the insulating layer contains an inorganic filler (especially when the inorganic filler content is high). In contrast, with the circuit board manufactured by the method of the present invention, trench-type conductor circuits with a good cross-sectional shape can be formed, as described above, even when the insulating layer contains an inorganic filler, or even when the inorganic filler content is high. Unlike circuit boards manufactured by conventional techniques for forming conductor circuits on an insulating layer, the circuit board for semiconductor package manufactured by the method of the present invention tends to have a reverse tapered shape, with the width increasing from the first main surface toward the depth of the circuit board. Therefore, in one embodiment, the trench-type conductor circuit has a reverse tapered shape, with the width increasing from the first main surface toward the depth of the circuit board.

[0257] -Surface Characteristics of First Main Surface- In the circuit board for a semiconductor package of the present invention, the arithmetic mean roughness Ra of the first main surface is preferably 200 nm or less, more preferably 150 nm or less, and even more preferably 100 nm or less, 80 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 20 nm or less. The lower limit of Ra is not particularly limited and can be, for example, 1 nm or more, 2 nm or more, 3 nm or more, etc. Therefore, in a preferred embodiment, the arithmetic mean roughness Ra of the first main surface of the circuit board for a semiconductor package of the present invention is 200 nm or less.

[0258] In the circuit board for a semiconductor package of the present invention, the difference TTV between the maximum and minimum heights of the first main surface measured in the thickness direction of the first circuit board is preferably 50 μm or less, more preferably 40 μm or less, and even more preferably 30 μm or less, 20 μm or less, 15 μm or less, 10 μm or less, 7 μm or less, or 5 μm or less, from the viewpoint of being able to form first conductive circuits in a fine pattern. The lower limit of the TTV is not particularly limited and may be, for example, 1 μm or more, 2 μm or more, 3 μm or more, etc. Therefore, in one embodiment, the difference TTV between the maximum and minimum heights of the first main surface measured in the thickness direction of the first circuit board is 50 μm or less.

[0259] In the manufacture of a semiconductor package, a semiconductor chip is mounted on the first main surface of the circuit board for a semiconductor package of the present invention (more specifically, electrically connected to the first conductive circuit). The circuit board for a semiconductor package of the present invention allows for easy and accurate connection of the semiconductor chip.

[0260] -Aspect Ratio of Trench-Type Conductive Circuit- According to the method of the present invention, trench-type conductive circuits with a high aspect ratio can be formed in a fine pattern. Specifically, in a cross section in direction Y (i.e., the cross section shown in FIGS. 25 to 30 ) perpendicular to first main surface 100a and perpendicular to the extension direction of trench-type conductive circuit 30, the ratio (T / W) of the thickness T to the width W of the trench-type conductive circuit is preferably 1 or greater, more preferably 1.5 or greater, 2 or greater, 2.5 or greater, or 3 or greater. The upper limit of the aspect ratio (T / W) can be, for example, 10 or less, 8 or less, etc. Here, when the width W changes in the depth direction in the cross section in direction Y, such as when the trench-type conductive circuit has an inverse tapered shape as described above, the maximum value of the width W is used when calculating the aspect ratio (T / W).

[0261] Therefore, in a preferred embodiment, the circuit board for a semiconductor package of the present invention has a trench-type conductor circuit with a high aspect ratio on a flat and smooth first main surface (semiconductor chip mounting surface), as described above, and has a structure in which the entire surface of the trench-type conductor circuit (the joint surface with the insulating layer and the surface on the first main surface) is covered with a barrier film.

[0262] As described above, the circuit board for a semiconductor package of the present invention has a semiconductor chip, preferably a plurality of semiconductor chips, mounted on its first main surface, and therefore can be suitably used as a circuit board for a multi-chip package.

[0263] As explained above in the "Method for Manufacturing a Circuit Board for a Semiconductor Package," the second main surface of the first circuit board opposite the first main surface may be further processed to achieve a surface structure suitable for use as a core circuit board bonding surface. For example, the second main surface of the first circuit board may have a core circuit board bonding surface formed by forming a resin insulating layer on the second main surface and further forming an electrode pattern corresponding to the electrodes of the core circuit board. The first main surface of the first circuit board may also be further processed to achieve a surface structure suitable for use as a semiconductor chip mounting surface. For example, the first main surface of the first circuit board may have a semiconductor chip mounting surface formed by forming a resin insulating layer on the first main surface and further forming an electrode pattern corresponding to the electrodes of the semiconductor chip. The core circuit board bonding surface and the semiconductor chip mounting surface are as explained above in the "Method for Manufacturing a Circuit Board for a Semiconductor Package," and the preferred aspects and characteristics of the resin insulating layer constituting the core circuit board bonding surface and the preferred aspects and characteristics of the resin insulating layer constituting the semiconductor chip mounting surface are also as explained above.

[0264] Therefore, in one such embodiment, the circuit board for a semiconductor package of the present invention comprises: a first circuit board having a first main surface and a second main surface; and a core circuit board having a first main surface and a second main surface, wherein the first circuit board is provided with a first conductive circuit having a minimum line and space (L / S) of 2 / 2 μm or less on the first main surface side, the surface of the first conductive circuit being covered with a barrier film, and having a core circuit board bonding surface formed on the second main surface with a resin insulating layer and an electrode pattern formed to correspond to the electrodes of the core circuit board (more preferably having a semiconductor chip mounting surface formed on the first main surface with a resin insulating layer and an electrode pattern formed to correspond to the electrodes of the semiconductor chip), and the first circuit board and the core circuit board are bonded together so that the core circuit board bonding surface of the first circuit board faces the first main surface of the core circuit board.

[0265] Furthermore, the circuit board for a semiconductor package of the present invention has board connection terminals such as bumps formed on its second main surface (200b in FIG. 30).

[0266] [Semiconductor Package] A semiconductor package can be manufactured using the circuit board for a semiconductor package of the present invention, and the present invention also provides such a semiconductor package.

[0267] In one embodiment, a semiconductor package of the present invention includes the circuit board for a semiconductor package of the present invention and a semiconductor chip mounted on a first main surface of the circuit board.

[0268] The configuration and manufacturing procedure of the semiconductor package of the present invention will be described with reference to FIG.

[0269] A semiconductor package according to one embodiment of the present invention is manufactured by providing a semiconductor chip 300 on the first main surface 100a of the circuit board for a semiconductor package of the present invention ( FIG. 31 ). The semiconductor chip may be mounted by any known method for electrically connecting the semiconductor chip to an organic interposer or package substrate. Examples of such bonding methods include solder bonding, adhesive bonding, and hybrid bonding, which may be performed in the same manner as described above for step (Z). As described above, the first main surface of the circuit board for a semiconductor package of the present invention has excellent flatness, allowing for suitable bonding to the semiconductor chip by hybrid bonding. Hybrid bonding directly bonds the conductive circuit of the first circuit board to the electrodes of the semiconductor chip without using solder bumps, thereby enabling a smaller connection pitch and thereby further enhancing the benefits of using the circuit board for a semiconductor package of the present invention. During hybrid bonding, it is preferable to perform heat treatment to promote diffusion of the conductive material between the conductor circuit of the circuit board for semiconductor packages and the electrodes of the semiconductor chip, but as mentioned above, there is a possibility of short circuits occurring in conductor circuits with a small L / S ratio. In this regard, the circuit board for semiconductor packages of the present invention has the advantage that the fine trench-type conductor circuits (first conductor circuits) are covered with a barrier film, which makes it possible to perform heat treatment sufficient to achieve good insulation reliability while reducing the possibility of such short circuits.

[0270] As explained above in the "Method for Manufacturing a Circuit Board for a Semiconductor Package," the first main surface of the first circuit board may be further processed to achieve a surface structure suitable for mounting a semiconductor chip. For example, the first main surface of the first circuit board may have a semiconductor chip mounting surface formed by forming a resin insulating layer on the first main surface and further forming an electrode pattern corresponding to the electrodes of the semiconductor chip. Therefore, in one such embodiment, the semiconductor package of the present invention includes the circuit board for a semiconductor package of the present invention and a semiconductor chip mounted on the semiconductor chip mounting surface of the circuit board.

[0271] The semiconductor package of the present invention also has board connection terminals such as bumps on the second main surface 200b (not shown in FIG. 31).

[0272] DESCRIPTION OF SYMBOLS 1 Substrate 2 Metal layer 10 Substrate with metal layer 10a Metal layer (first main surface) 10b Second main surface 20, 21, 22 Photoresist 30 Conductor layer (conductor circuit) 30b Barrier film 31 Metal layer (plating seed layer) 50, 60 Resin composition layer 51 Insulating layer 61 Resin insulating layer 51v, 61v Via 70 Via conductor, electrode pad 100 First circuit board 100a First main surface of first circuit board (first main surface of circuit board for semiconductor package) 100b Second main surface of first circuit board 200 Core circuit board 200a First main surface of core circuit board 200b Second main surface of core circuit board (second main surface of circuit board for semiconductor package) 300 Semiconductor chip 500 Circuit board for semiconductor package

Claims

(X) The following (X1) to (X3): (X1) Forming a first conductive circuit on the metal layer of a substrate with a metal layer. (X2) forming a barrier film on the surface of the first conductive circuit formed on the metal layer to form a first conductive circuit with a barrier film; (X3) forming a resin composition layer from a resin composition containing a curable resin so as to embed the barrier film-covered first conductive circuit formed on the metal layer, and curing the resin composition layer to form an insulating layer. a step of performing the above steps in this order to form a first circuit board on a base material with a metal layer, the first circuit board having a first conductive circuit with a barrier film on the first main surface side; (Y) The following (Y1) and (Y2): (Y1) Removing the base material with the metal layer to form a first circuit board having a first main surface on which the first conductive circuit is exposed. (Y2) Forming a barrier film on the exposed surface of the first conductive circuit. a step of performing the above steps in this order to form a first circuit board having a first conductive circuit covered with a barrier film on the first main surface side; and (Z) joining the core circuit board and the first circuit board so that a second main surface of the first circuit board opposite to the first main surface faces a first main surface of the core circuit board; A method for manufacturing a circuit board for a semiconductor package, comprising: 　 The method according to claim 1, wherein step (Z) is carried out after step (Y). 　 The method according to claim 1, wherein step (Z) is carried out between step (X) and step (Y). 　 The method of claim 1 , wherein the curable resin is a thermosetting resin. 　 The method of claim 1 , wherein the thermosetting resin is an epoxy resin. 　 The method of claim 1 , wherein the resin composition includes a curing agent. 　 The method of claim 1 , wherein the resin composition comprises an inorganic filler. 　 The method according to claim 7, wherein the content of the inorganic filler in the resin composition is 20% by mass or more and 75% by mass or less, when the nonvolatile components in the resin composition are taken as 100% by mass. 　 The method of claim 1 , wherein the metal layer has a thickness of less than 1 μm. 　 The method according to claim 1, wherein the substrate with the metal layer is selected from a metal substrate having a composition different from that of the metal layer, an inorganic substrate, and an organic substrate. 　 The method according to claim 1, wherein the barrier film is made of at least one material selected from the group consisting of metals and metal oxides. 　 The method of claim 1 , wherein (Y1) is carried out by removing the substrate and then removing the metal layer. (X1) is (X1-1) providing a photoresist on a metal layer, exposing and developing the photoresist, exposing the metal layer in accordance with the circuit pattern of the first conductive circuit to be formed; and (X1-2) Forming a conductor layer on the exposed metal layer to form a first conductor circuit The method of claim 1 , comprising: 　 The method of claim 1 , wherein the first conductive circuit comprises a trench-type conductive circuit. 　 The method according to claim 1, wherein (X3) comprises laminating a resin sheet comprising a support film and a resin composition layer provided on the support film onto a substrate such that the resin composition layer is bonded to the barrier film-covered first conductor circuit. 　 After (X3), (i) forming a second conductive circuit on the surface of the insulating layer; and (ii) forming a resin composition layer so as to embed the second conductive circuit, and curing the resin composition layer to form an insulating layer; The method of claim 1 , comprising: 　 After (Y2), (Y3) forming a resin insulating layer on the first main surface of the first circuit board; and (Y4) Forming an electrode pattern on the resin insulating layer 2. The method according to claim 1, further comprising the steps of: forming a semiconductor chip mounting surface on the first main surface side of the first circuit board; 　 The method of claim 1 , wherein the first conductive circuit has a minimum line and space (L / S) of 2 / 2 μm or less. 　 The method of claim 1 , wherein the core circuit board is selected from the group consisting of a copper-clad laminate, a glass substrate, a ceramic substrate, a metal substrate, a flexible substrate, and a substrate with embedded components. 　 The method according to claim 1, wherein in step (Z), the core circuit board and the first circuit board are joined by one or more joining methods selected from the group consisting of solder joining, adhesive joining, and hybrid bonding.

10. The method of claim 1 for manufacturing a circuit board for a multi-chip package.

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