Display apparatus and electronic device comprising same

Abstract

This display apparatus comprises: a driving voltage line extending in a first direction; a conductive pattern which is disposed on the driving voltage line and which at least partially overlaps the driving voltage line; a driving transistor which is disposed on the conductive pattern, and which includes a first semiconductor layer that is electrically connected to the conductive pattern and includes a channel area, and a first gate electrode that is disposed on the first semiconductor layer and overlaps the channel area; and a data line extending in a second direction perpendicular to the first direction. The driving voltage line includes a shielding part that includes a side surface facing the data line on a plane. On the plane, the distance between the side surface of the shielding part and the data line is shorter than the distance between the conductive pattern and the data line.

Description

Display device and electronic device including same

[0001] The present invention relates to a display device and a structure of an electronic device including the same.

[0002] In recent years, electronic devices containing display devices have become increasingly diverse in their applications. Furthermore, the thinner and lighter these devices are, the broader their range of applications is expanding.

[0003] As electronic devices including display devices are utilized in various ways, there are various methods for designing the shape of the display panel, and the functions that can be grafted or linked to the display device are increasing.

[0004] The content described in the above background art is intended to help understand the background of the present invention and may contain information that does not correspond to prior art.

[0005] Embodiments of the present invention can provide a display device with improved display quality and an electronic device including the same. However, these aspects and features are exemplary and are not intended to limit the scope of the present invention. Additional aspects and features may be described in the following description, may become apparent from the description, or may be learned by practicing one or more of the embodiments presented herein.

[0006] A display device according to embodiments of the present invention includes a substrate including a display area including a plurality of pixels and a non-display area disposed outside the display area, a driving voltage line extending in a first direction on the substrate and transmitting a driving voltage, a conductive pattern disposed on the driving voltage line and at least partially overlapping the driving voltage line, a driving transistor including a first semiconductor layer disposed on the conductive pattern and electrically connected to the conductive pattern and including a channel area, and a first gate electrode disposed on the first semiconductor layer and overlapping the channel area, a first capacitor including a first electrode integrally provided with the first gate electrode and a second lower electrode overlapping the first electrode and included in the conductive pattern, a second capacitor including a third electrode included in the driving voltage line and a fourth electrode overlapping the third electrode and included in the conductive pattern, and a data line extending in a second direction perpendicular to the first direction. The above driving voltage line includes a shielding portion including a side surface facing the data line on a plane, and a distance between the side surface of the shielding portion and the data line on a plane is smaller than a distance between the conductive pattern and the data line.

[0007] In one embodiment, the first capacitor may further include a second upper electrode disposed on the first electrode and electrically connected to the second lower electrode.

[0008] In one embodiment, the third electrode may be at least a portion of the shield.

[0009] In one embodiment, the shielding member may include a first portion extending in the second direction and including a side surface facing the data line, a second portion extending in the second direction and spaced apart from the first portion in the first direction, and a third portion extending in the first direction and connecting the first portion and the second portion.

[0010] In one embodiment, the distance between the side surface of the first portion of the shield facing the data line and the data line may be smaller than the distance between the conductive pattern and the data line.

[0011] In one embodiment, the shielding portion may be spaced apart from the channel region of the first semiconductor layer on a plane.

[0012] In one embodiment, the channel region of the first semiconductor layer on the plane may be disposed between the first portion and the second portion of the shielding portion, and may be spaced apart from the third portion of the shielding portion.

[0013] In one embodiment, the shielding portion may overlap the entire channel region of the first semiconductor layer.

[0014] A display device according to embodiments of the present invention comprises a substrate including a display area including a first subpixel circuit of an adjacent first subpixel and a second subpixel circuit of a second subpixel, and a peripheral area disposed outside the display area, a driving voltage line that transmits a driving voltage and extends in a first direction on the substrate and passes through a first subpixel circuit area including the first subpixel circuit and a second subpixel circuit area including the second subpixel circuit, a first conductive pattern that is disposed on the driving voltage line in the first subpixel circuit area and at least partially overlaps the driving voltage line, a second conductive pattern that is disposed on the driving voltage line in the second subpixel circuit area and at least partially overlaps the driving voltage line, a first semiconductor layer that is disposed on the first conductive pattern and is electrically connected to the first conductive pattern and includes a first channel area, and a first gate electrode that is disposed on the first semiconductor layer and overlaps the first channel area, and the first A display device comprising: a first driving transistor disposed in a subpixel circuit region; a second semiconductor layer disposed on the second conductive pattern and electrically connected to the second conductive pattern, the second semiconductor layer including a second channel region; and a second gate electrode disposed on the second semiconductor layer and overlapping the second channel region; a second driving transistor disposed in the second subpixel circuit region; a first data line extending in a second direction perpendicular to the first direction and transmitting a data voltage to the first subpixel circuit; and a second data line extending in the second direction and transmitting a data voltage to the second subpixel circuit. The driving voltage line includes a first shielding portion disposed in the first subpixel circuit region and including a first side surface facing the first data line and a second side surface facing the second data line on a plane.On a plane, a distance between the first side of the first shielding portion and the first data line is smaller than a distance between the first conductive pattern and the first data line, and on a plane, the first shielding portion is spaced apart from the first channel region of the first semiconductor layer.

[0015] In one embodiment, the distance between the second side of the first shielding portion and the second data line may be smaller than the distance between the first conductive pattern and the second data line.

[0016] In one embodiment, the driving voltage line may further include a second shielding portion arranged in the second subpixel circuit area and including a third side surface facing the second data line on a plane, and a connecting portion connecting the first shielding portion and the second shielding portion.

[0017] In one embodiment, the third side of the second shielding portion may be such that the distance between the second data line is smaller than the distance between the second conductive pattern and the second data line.

[0018] In one embodiment, a portion of the second data line may overlap the connecting portion, and the second shielding portion may overlap the entire second channel region of the second semiconductor layer.

[0019] In one embodiment, the first shielding portion may include a first portion extending in the second direction and including a side facing the first data line, a second portion extending in the second direction and spaced apart from the first portion in the first direction and including a side facing the second data line, and a third portion extending in the first direction and connecting the first portion and the second portion.

[0020] In one embodiment, the first channel region of the first semiconductor layer on the plane may be disposed between the first portion and the second portion of the first shielding portion, and may be spaced apart from the third portion of the first shielding portion.

[0021] In one embodiment, the display device may further include a first capacitor including a first electrode and a second lower electrode overlapping the first electrode. The first electrode and the first gate electrode may be provided integrally with each other, and the second lower electrode may be included in the first conductive pattern.

[0022] In one embodiment, the first capacitor may further include a second upper electrode disposed on the first electrode and electrically connected to the second lower electrode.

[0023] In one embodiment, the display device may further include a second capacitor including a third electrode and a fourth electrode overlapping the third electrode. The third electrode may be included in the first shielding portion, and the fourth electrode may be included in the first conductive pattern.

[0024] An electronic device according to embodiments of the present invention includes a display device and a housing for accommodating the display device, the display device including a substrate including a display area including a plurality of pixels and a non-display area disposed outside the display area; a driving voltage line extending in a first direction on the substrate and transmitting a driving voltage, a conductive pattern disposed on the driving voltage line and at least partially overlapping the driving voltage line, a driving transistor including a first semiconductor layer disposed on the conductive pattern and electrically connected to the conductive pattern and including a channel area, and a first gate electrode disposed on the first semiconductor layer and overlapping the channel area; and a data line extending in a second direction perpendicular to the first direction. The driving voltage line includes a shielding portion including a side surface facing the data line in a plane. A distance between the side surface of the shielding portion and the data line in a plane is smaller than a distance between the conductive pattern and the data line.

[0025] In one embodiment, the electronic device may further include a processor, and the display device may further include a controller that receives a control signal from the processor and outputs a power control signal based on the control signal, and a power supply circuit that generates the driving voltage based on the power control signal of the controller. The driving voltage line may be electrically connected to the power supply circuit to receive the driving voltage.

[0026] However, the present invention is not limited to the above-described aspects and features, and these and additional aspects and features may be described in part in the subsequent detailed description with reference to the drawings, or may become apparent therefrom, or may be learned by practicing one or more embodiments set forth herein.

[0027] According to embodiments of the present invention, a display device with improved display quality and an electronic device including the same can be provided. Of course, the scope of the present invention is not limited by these effects.

[0028] The above and other aspects and features of the present invention will be more clearly understood through the following detailed description of exemplary and non-limiting embodiments illustrated with reference to the accompanying drawings.

[0029] FIG. 1A is a schematic perspective view of an electronic device according to one embodiment of the present invention.

[0030] FIG. 1b is an exploded perspective view of an electronic device according to one embodiment of the present invention.

[0031] Figure 2 is a schematic plan view of a display device according to one embodiment of the present invention.

[0032] Figure 3 is a schematic block diagram of a display device according to one embodiment of the present invention.

[0033] FIG. 4 is an equivalent circuit diagram showing a subpixel circuit of one subpixel and a light-emitting diode electrically connected to the subpixel circuit of one subpixel of a display device according to one embodiment of the present invention.

[0034] FIG. 5 is a cross-sectional view of a portion of a display area of ​​a display device according to one embodiment of the present invention.

[0035] FIG. 6 is a plan view showing the first to third sub-pixel circuit regions of the first to third sub-pixels of the display device according to one embodiment of the present invention.

[0036] Figures 7 to 11 are plan views according to the stacking order of the components of each layer constituting the first to third subpixels of the display device illustrated in Figure 6.

[0037] FIG. 12 is a schematic plan view of the driving voltage lines, the first conductive pattern, and the data lines in the display device illustrated in FIG. 6.

[0038] Hereinafter, embodiments will be described in more detail with reference to the attached drawings, and like reference numerals represent like elements throughout the drawings. However, the present invention may be implemented in various forms and should not be construed as limited to the embodiments illustrated in this specification. Rather, these embodiments are provided as examples to thoroughly and completely explain the present invention and to enable those skilled in the art to fully understand the aspects and features of the present invention. Therefore, unnecessary processes, components, techniques, etc. for those skilled in the art to fully understand the aspects and features of the present invention may not be described separately. Unless otherwise stated, like reference numerals represent like elements throughout the attached drawings and this specification, and repetitive descriptions thereof may be omitted.

[0039] Since a particular embodiment can be implemented in various ways, the order of specific processes may differ from the order described. For example, two processes described in succession may be performed simultaneously or nearly simultaneously, or in the reverse order described.

[0040] Furthermore, when considering this specification as a whole, unless otherwise stated or implied, those skilled in the art will appreciate that suitable features of the various embodiments of the present invention may be partially or wholly combined or combined with one another and may be technically interoperable to operate in various ways, and that each embodiment may be implemented separately or in any suitable combination.

[0041] In the drawings, the relative sizes, thicknesses, and proportions of components, layers, and areas may be exaggerated or simplified for clarity. Spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used for convenience of explanation to describe the relationship of one element or feature to other element(s) or feature(s) as depicted in the drawings. It should be understood that these spatially relative terms are intended to encompass various orientations in which the device is actually used or operated, in addition to the orientations depicted in the drawings. For example, if a device in a drawing is turned over, a description of an element as being "below" or "below" another element may also mean that the element is located "above" the other element. Therefore, terms such as "below," "below," etc. may encompass both the up and down orientations. Furthermore, since the device may be rotated 90 degrees or positioned in other orientations, these spatially relative terms should be interpreted in context.

[0042] Furthermore, the shapes depicted in the drawings may differ during actual implementation due to, for example, tolerances or manufacturing techniques. Therefore, the embodiments of the present invention should not be interpreted as being limited to the specific shapes depicted in the drawings, but should also take into account shape variations that may occur, for example, due to the manufacturing process. In other words, the shapes depicted in the drawings may not accurately reflect the actual shape of the device, and thus the present invention is not limited to the shapes depicted in these drawings.

[0043] The x-axis, y-axis, and z-axis depicted in the drawing are not limited to the three axes of the Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular or nearly perpendicular to each other, or may indicate different directions that are not perpendicular to each other.

[0044] Although terms such as "first," "second," and "third" are used to describe various components, parts, regions, layers, and / or sections, it should be understood that these terms are not intended to be limiting. These terms are intended to distinguish one component, part, region, layer, or section from another. Accordingly, the first component described below may be referred to as the second component without departing from the technical spirit and scope of the present invention.

[0045] When a component or layer is referred to as being “on,” “connected to,” or “coupled to” another component or layer, it means that the component or layer may be directly positioned, directly connected to, or directly coupled to the other component or layer, or there may be one or more intervening components or layers. Similarly, when a layer, region, or component is referred to as being “electrically connected” to another layer, region, or component, it means that the two elements may be directly electrically connected, or there may be one or more intervening layers, regions, or components. Furthermore, when a component or layer is referred to as being “between” two components or layers, it may be solely between the two elements, or there may be one or more intervening components or layers.

[0046] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the present invention. As used herein, the singular forms “a” or “an” should be construed to include the plural forms as well, unless the context clearly dictates otherwise. Furthermore, terms such as “comprises,” “comprising,” and the like, as used herein, specify the presence of stated features, components, steps, operations, components, and / or parts, but do not preclude the presence or addition of one or more other features, components, steps, operations, components, and / or parts, or any combination thereof. As used herein, “and / or” means any combination that includes at least one of the listed items. For example, “A and / or B” means A, B, or A and B. Furthermore, when an expression such as “at least one” precedes a list of elements, it applies to the list as a whole and not to individual elements. For example, “at least one of a, b, or c,” “at least one of a, b, and c,” or “at least one of the group consisting of a, b, and c” means including a alone, b alone, c alone, a and b, a and c, b and c, or all of a, b, and c, or variations thereof.

[0047] As used herein, the terms “substantially,” “about,” and the like indicate approximations rather than precise numbers, and are intended to encompass the inherent variability of measurements or calculations generally recognized in the art. Furthermore, the term “may” as used herein means “one or more embodiments of the invention.” As used herein, “use,” “using,” and “used” may be considered synonymous with “utilize,” “utilizing,” and “utilized,” respectively.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the relevant art. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with the relevant technology and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless specifically stated otherwise.

[0049] FIG. 1A is a schematic perspective view of an electronic device according to one embodiment of the present invention. FIG. 1B is an exploded perspective view of an electronic device according to one embodiment of the present invention.

[0050] An electronic device (1) according to one embodiment is a device that displays a moving image and / or a still image, and may be a portable electronic device (e.g., a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an Ultra Mobile PC (UMPC)), as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT), or a part thereof. An electronic device (1) according to one embodiment may be a wearable device, such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD), or a part thereof. An electronic device (1) according to one embodiment may be a dashboard of a vehicle, a CID (Center Information Display) placed on a center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, a display placed on the rear seat entertainment of a vehicle or the back of a front seat, a head-up display (HUD) installed at the front of a vehicle or projected on a front window glass, or a holographic augmented reality head-up display (CGH AR HUD).

[0051] For example, the electronic device (1) may be one of a flat panel display, a curved display, a computer monitor, a medical monitor, a television, a billboard, an indoor or outdoor lighting and / or signal light, a head-up display, a fully or partially transparent display, a flexible display, a rollable display, a foldable display, a stretchable display, a laser printer, a telephone, a mobile phone, a tablet, a phablet, a personal digital assistant (PDA), a wearable device, a laptop computer, a digital camera, a camcorder, a viewfinder, a microdisplay, a 3D display, a virtual reality or augmented reality display, a vehicle, a video wall including multiple displays tiled together, a theater or stadium screen, a light therapy device, or a signage.

[0052] Referring to FIGS. 1A and 1B, the electronic device (1) can display an image in a third direction (e.g., the z direction) that is perpendicular or substantially perpendicular to a first direction (e.g., the x direction) and a second direction (e.g., the y direction). The image can include a dynamic image and / or a still image.

[0053] An electronic device (1) can detect user input applied from the outside. The user input may include various forms of external input, such as a part of the user's body, light, heat, or pressure. The user input may be provided in various forms, and the electronic device (1) may also detect user input applied to the side or back of the electronic device (1) depending on the target structure of the electronic device (1).

[0054] An electronic device (1) may include a cover window (CW), a housing (HU), and a display device (10). In one embodiment, the cover window (CW) and the housing (HU) may be combined to form the exterior of the electronic device (1).

[0055] The cover window (CW) may include a light-transmitting area (LTA) and a bezel area (BZA). The light-transmitting area (LTA) may be an optically transparent area. For example, the light-transmitting area (LTA) may be an area with a visible light transmittance of about 90% or greater.

[0056] A bezel area (BZA) can define a shape of a light-transmitting area (LTA). The bezel area (BZA) can be adjacent to the light-transmitting area (LTA) and can surround the light-transmitting area (LTA) (e.g., along an edge). The bezel area (BZA) can be an area having relatively low light transmittance compared to the light transmittance of the light-transmitting area (LTA). The bezel area (BZA) can include an opaque material that blocks light. The bezel area (BZA) can have an intended color (e.g., a specific color or a predetermined color). The bezel area (BZA) can be defined by a bezel layer provided separately from a transparent substrate defining the light-transmitting area (LTA), or by an ink layer formed by inserting or coloring the transparent substrate.

[0057] A housing (HU) can be coupled with a cover window (CW). The housing (HU) can accommodate a display device (10). The housing (HU) can include a rear surface and a side surface. A cover window (CW) can be arranged on a front surface of the housing (HU). That is, the cover window (CW) can be arranged above the housing (HU). The housing (HU) can be coupled with the cover window (CW) to provide an accommodation space. The display device (10) can be accommodated in the accommodation space provided between the housing (HU) and the cover window (CW).

[0058] The housing (HU) may include a material having relatively high rigidity. For example, the housing (HU) may include glass, plastic, or metal. For example, the housing (HU) may include a plurality of frames and / or plates made of a combination of glass, plastic, or metal. The housing (HU) may reliably protect the components of the electronic device (1) accommodated in the accommodation space (e.g., the interior space) from external impact.

[0059] The display device (10) can display an image. The display device (10) can include a display area (DA) and a non-display area (NDA). Since the display device (10) includes a substrate (100, see FIG. 5), it can be said that the substrate (100) has a display area (DA) and a non-display area (NDA).

[0060] The display area (DA) may be an active area that is activated according to an electrical signal. In one embodiment, the display area (DA) may be an area where an image is displayed and, at the same time, an area where a user's input is detected. The display area (DA) may be an area where a plurality of subpixels (P) are arranged. The plurality of subpixels (P) may be repeatedly arranged along a first direction (e.g., x direction) and a second direction (e.g., y direction).

[0061] The display area (DA) may overlap at least partially with the light-transmitting area (LTA) of the cover window (CW). For example, the display area (DA) may partially or entirely overlap with the light-transmitting area (LTA). Accordingly, a user may view an image or provide an external input through the light-transmitting area (LTA). However, the present invention is not limited thereto. For example, the area where an image is displayed and the area where a user's input is detected within the display area (DA) may be spaced apart from each other (e.g., separated).

[0062] The non-display area (NDA) may overlap at least partially with the bezel area (BZA) of the cover window (CW). The non-display area (NDA) may be an area covered by the bezel area (BZA). The non-display area (NDA) may be adjacent to the display area (DA). The non-display area (NDA) may be an area where no image is displayed. A driving circuit or driving wiring for driving the display area (DA) may be arranged in the non-display area (NDA).

[0063] Figure 2 is a schematic plan view of a display device according to one embodiment of the present invention.

[0064] Referring to FIG. 2, the display device (10) may include a display area (DA) and a non-display area (NDA) outside the display area (DA). At least a portion of the display area (DA) may be surrounded by the non-display area (NDA) (e.g., along an edge).

[0065] When the display area (DA) is viewed in a planar shape (e.g., on a plane), the display area (DA) may have a rectangular shape. In another embodiment, the display area (DA) may have a polygonal shape such as a triangle, a pentagon, a hexagon, a circular shape, an oval shape, an irregular shape, etc. The display area (DA) may have a rounded corner at an edge. In one embodiment, the display device (10) may have a display area (DA) of a shape in which a length in a first direction (e.g., an x-direction) is longer than a length in a second direction (e.g., a y-direction), as illustrated in FIG. 2. In another embodiment, the display device (10) may have a display area (DA) of a shape in which a length in a second direction (e.g., an y-direction) is longer than a length in the first direction (e.g., an x-direction).

[0066] Figure 3 is a schematic block diagram of an electronic device according to one embodiment of the present invention.

[0067] Referring to FIG. 3, an electronic device (1) may include a display device (10) and a processor (20). The display device (10) according to one embodiment may include a pixel unit (e.g., pixel area) (11), a gate driving circuit (13), a data driving circuit (15), a power supply circuit (17), and a controller (19).

[0068] The pixel unit (11) may be provided in the display area (DA, FIG. 2). In the non-display area (NDA, FIG. 2), various conductive lines for transmitting electrical signals to be applied to the display area (DA), external circuits electrically connected to sub-pixel circuits, and pads to which a printed circuit board or driver IC chip is attached may be located. For example, the non-display area (NDA) may be provided with a gate driving circuit (13), a data driving circuit (15), a power supply circuit (17), and a controller (19).

[0069] As illustrated in FIGS. 2 and 3, a plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of subpixels (P) connected thereto may be arranged in a display area (DA). The plurality of subpixels (P) may be arranged in various configurations, such as a stripe arrangement, an RGBG arrangement (e.g., a PENTILE® arrangement, PENTILE® is an official registered trademark of Samsung Display Co., Ltd.), a diamond arrangement, or a mosaic arrangement, to implement an image. Each subpixel (P) may include a subpixel circuit and a display element (e.g., a light-emitting diode) connected to the subpixel circuit. For example, the display element may include an organic light-emitting diode. The subpixel (P) may emit light of, for example, red, green, blue, or white through the display element. Each subpixel (P) can be connected to at least one corresponding gate line among a plurality of gate lines (GL) and a corresponding data line among a plurality of data lines (DL).

[0070] The gate lines (GL) may each extend in a first direction (e.g., the x direction or the row direction) and be connected to subpixels (P) positioned in the same row. The gate lines (GL) may transmit a gate signal to the subpixels (P) in the same row. The data lines (DL) may each extend in a second direction (e.g., the y direction or the column direction) and be connected to subpixels (P) positioned in the same column. The data lines (DL) may each transmit a data signal to the corresponding subpixels (P) positioned in the same column in synchronization with the gate signal.

[0071] In one embodiment, the non-display area (NDA) may be a type of non-display area in which subpixels (P) are not arranged.

[0072] The gate driving circuit (13) is connected to a plurality of gate lines (GL), and can generate a gate signal in response to a scan control signal (GCS) from a controller (19), and sequentially supply the gate signal to the gate lines (GL). The gate line (GL) can be connected to a gate electrode of a transistor included in a subpixel (P). The gate signal can be a gate control signal that controls the turn-on and turn-off of a transistor whose gate is connected to the gate line (GL). The gate signal can include a gate-on voltage that can turn on the transistor and a gate-off voltage that can turn off the transistor. In one embodiment, the gate-on voltage can be a high-level voltage (e.g., a first-level voltage) or a low-level voltage (e.g., a second-level voltage).

[0073] In FIGS. 2 and 3, the subpixel (P) is illustrated as being connected to one gate line (GL), but the present invention is not limited thereto, and the subpixel (P) may be connected to two or more gate lines. In this case, the gate driving circuit (13) may supply two or more gate signals having different timings at which the gate-on voltage is applied to the corresponding gate lines (GL).

[0074] The data driving circuit (15) is connected to a plurality of data lines (DL) and can supply a data signal (DATA) to the data lines (DL) in response to a data control signal (DCS) from the controller (19). The data signal (DATA) supplied to the data line (DL) can be supplied to a subpixel (P) to which a gate signal is supplied. The data driving circuit (15) can convert input image data having a grayscale input from the controller (19) into a data signal (DATA) in the form of a voltage or current.

[0075] The power supply circuit (17) can generate signals (e.g., voltage and current) used for driving the subpixel (P) in response to a power control signal (PCS) from the controller (19). The power supply circuit (17) can generate a driving voltage (ELVDD) and a common voltage (ELVSS) and supply them to the subpixels (P). For example, the power supply circuit (17) can generate the driving voltage (ELVDD) based on the power control signal (PCS) and supply it to a driving voltage line (PL, see FIG. 6). The driving voltage (ELVDD) can be a high-level voltage provided to a first terminal of a driving transistor connected to a first electrode (e.g., a pixel electrode or an anode) of a display element included in the subpixel (P). The common voltage (ELVSS) can be a low-level voltage provided to a second electrode (e.g., a counter electrode or a cathode) of a display element included in the subpixel (P). The power supply circuit (17) can generate a high-level high voltage and a low-level low voltage and supply them to the gate driving circuit (13).

[0076] The controller (19) can receive a control signal (CS) and input data (IDAT) from a processor (20) (e.g., an application processor (AP), a graphic processing unit (GPU), a central processing unit (CPU), an image signal processor, a sensor hub processor, or a communication processor, etc.). In one embodiment, the control signal (CS) may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. For example, the controller (19) can output a scan control signal (GCS), a data control signal (DCS), and a power control signal (PCS) based on the control signal (CS) and the input data (IDAT) transmitted from the processor (20). The scan control signal (GCS), the data control signal (DCS), and the power control signal (PCS) generated by the controller (19) can be transmitted to a gate driving circuit (13), a data driving circuit (15), and a power supply circuit (17), respectively. The scan control signal (GCS) output to the gate drive circuit (13) may include a plurality of clock signals and a gate start signal. The data control signal (DCS) output to the data drive circuit (15) may include a source start signal and clock signals.

[0077] Since the display device (10) includes a substrate (100, see FIG. 5), it can be said that the substrate (100, see FIG. 5) includes a display area (DA) and a non-display area (NDA). For example, sub-pixels (P) may be arranged in the display area (DA) of the substrate (100, see FIG. 5). Part or all of the gate driving circuit (13) may be formed directly in the non-display area (NDA) of the substrate (100, see FIG. 5) during the process of forming transistors constituting the sub-pixel circuit in the display area (DA) of the substrate (100, see FIG. 5). The data driving circuit (15), the power supply circuit (17), and the controller (19) may be formed in the form of separate integrated circuit chips or a single integrated circuit chip, respectively, and may be arranged on an FPCB (flexible printed circuit board) electrically connected to pads arranged on one side of the substrate. In another embodiment, the data drive circuit (15), power supply circuit (17), and controller (19) may be directly placed on the substrate (100, see FIG. 5) in a COG (Chip On Glass) manner or a COP (Chip On Plastic) manner.

[0078] FIG. 4 is an equivalent circuit diagram showing a subpixel circuit of one subpixel and a light-emitting diode electrically connected to the subpixel circuit of one subpixel of a display device according to one embodiment of the present invention.

[0079] Referring to FIG. 4, a subpixel circuit (PC) may be electrically connected to a first gate line (GWL) for transmitting a first gate signal (GW), a second gate line (GRL) for transmitting a second gate signal (GR), a third gate line (EML) for transmitting a third gate signal (EM), a fourth gate line (GIL) for transmitting a fourth gate signal (GI), a fifth gate line (EMBL) for transmitting a fifth gate signal (EMB), and a data line (DL) for transmitting a data signal (DATA). The first gate signal (GW) may be a write gate signal, and the first gate line (GWL) may be referred to as a write gate line. Since the light emission of a light emitting diode (LED) is controlled by the third gate signal (EM) and the fifth gate signal (EMB), the third gate signal (EM) and the fifth gate signal (EMB) may be light emission control signals, and the third gate line (EML) and the fifth gate line (EMBL) may be referred to as light emission control lines. The subpixel circuit (PC) can be electrically connected to a driving voltage line (PL) that transmits a driving voltage (ELVDD), a reference voltage line (VRL) that transmits a reference voltage (Vref), and an initialization voltage line (VAL) that transmits an initialization voltage (Vaint).

[0080] In one embodiment, each of the plurality of transistors included in the subpixel circuit (PC) may be an NMOS transistor (n-channel MOSFET) including an oxide semiconductor layer. However, the present invention is not limited thereto, and the transistors are not limited thereto. In one embodiment, some of the plurality of transistors, for example, the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors (T1, T2, T3, T4, T5, T6, T7, T8), may be PMOS transistors (p-channel MOSFETs), and the remaining some of the plurality of transistors may be NMOS transistors (n-channel MOSFETs). For example, the fifth transistor (T5) and / or the sixth transistor (T6) of the plurality of transistors may be PMOS transistors, and the remaining transistors may be NMOS transistors. For example, for example, the PMOS transistor (e.g., the fifth transistor (T5) and / or the sixth transistor (T6)) may include an inorganic semiconductor (e.g., amorphous silicon, polysilicon) or an organic semiconductor.

[0081] The subpixel circuit (PC) may include first to sixth transistors (T1, T2, T3, T4, T5, T6), a first capacitor (C1), a second capacitor (C2), and an auxiliary capacitor (Ca). The first transistor (T1) is a driving transistor that outputs a driving current corresponding to a data signal (DATA). The second to sixth transistors (T2 to T6) may be switching transistors that transmit signals. The first transistor (T1) may be referred to as a driving transistor, the second transistor (T2) as a data writing transistor, the third transistor (T3) as a compensation transistor, the fourth transistor (T4) as an initialization transistor, the fifth transistor (T5) as an operation control transistor, and the sixth transistor (T6) as an emission control transistor.

[0082] The first terminal (e.g., the first electrode) and the second terminal (or the second electrode) of each of the first to sixth transistors (T1, T2, T3, T4, T5, and T6) may be a source (e.g., a source electrode) or a drain (e.g., a drain electrode) depending on the voltage of the first terminal and the second terminal. For example, depending on the voltage of the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. Hereinafter, the node to which the first-first gate electrode of the first transistor (T1) is connected may be defined as the first node (N1), and the node to which the second terminal of the first transistor (T1) is connected may be defined as the second node (N2).

[0083] A first transistor (T1) may be connected to a driving voltage line (PL) and a light emitting diode (LED). The first transistor (T1) may be connected between a fifth transistor (T5) and a sixth transistor (T6). The first transistor (T1) may include a first gate electrode, a first terminal, and a second terminal. The second terminal of the first transistor (T1) may be connected to a second node (N2). The first transistor (T1) may include a 1-1 gate electrode connected to the first node (N1). The first transistor (T1) may further include a 1-2 gate electrode connected to its second terminal. The 1-1 gate electrode and the 1-2 gate electrode may be disposed to face each other in different layers. For example, the 1-1 gate electrode and the 1-2 gate electrode of the first transistor (T1) may face each other with a semiconductor layer therebetween. In some embodiments, the first gate electrode of the first transistor (T1) may refer to the first-first gate electrode involved in turning on and off the first transistor (T1).

[0084] The first-first gate electrode of the first transistor (T1) may be connected to the second terminal of the second transistor (T2), the first terminal of the third transistor (T3), and the first capacitor (C1). The first-second gate electrode of the first transistor (T1) may be connected to the first terminal of the sixth transistor (T6), the first capacitor (C1), and the second capacitor (C2). The first terminal of the first transistor (T1) may be connected to the driving voltage line (PL) via the fifth transistor (T5), and the second terminal may be connected to the pixel electrode of the light emitting diode (LED) via the sixth transistor (T6). The first terminal of the first transistor (T1) may be connected to the second terminal of the fifth transistor (T5). The second terminal of the first transistor (T1) may be connected to the first terminal of the sixth transistor (T6), the first capacitor (C1), and the second capacitor (C2). The first transistor (T1) can receive a data signal (DATA) according to the switching operation of the second transistor (T2) and control the amount of driving current flowing to the light-emitting diode (LED).

[0085] The second transistor (T2) may be connected to the data line (DL) and the first gate electrode of the first transistor (T1). The second transistor (T2) may include a second gate electrode connected to the first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second terminal of the second transistor (T2) may be connected to the first gate electrode of the first transistor (T1), a first terminal of a third transistor (T3), and a first capacitor (C1). The second transistor (T2) may be turned on by the first gate signal (GW) transmitted to the first gate line (GWL), electrically connect the data line (DL) and the first node (N1), and transmit the data signal (DATA) transmitted to the data line (DL) to the first node (N1).

[0086] A third transistor (T3) may be connected to a first gate electrode of the first transistor (T1) and a reference voltage line (VRL). The third transistor (T3) may include a third gate electrode connected to a second gate line (GRL), a first terminal connected to a first node (N1), and a second terminal connected to the reference voltage line (VRL). The first terminal of the third transistor (T3) may be connected to the first gate electrode of the first transistor (T1), the second terminal of the second transistor (T2), and the first capacitor (C1). The third transistor (T3) may be turned on by a second gate signal (GR) transmitted to the second gate line (GRL) and may transmit the reference voltage (Vref) transmitted to the reference voltage line (VRL) to the first node (N1).

[0087] The fourth transistor (T4) may be connected to the sixth transistor (T6) and the initialization voltage line (VAL). The fourth transistor (T4) may be connected between a light emitting diode (LED) and the initialization voltage line (VAL). The fourth transistor (T4) may include a fourth gate electrode connected to a fourth gate line (GIL), a first terminal connected to a third node (N3), and a second terminal connected to the initialization voltage line (VAL). The first terminal of the fourth transistor (T4) may be connected to a second terminal of the sixth transistor (T6) and a pixel electrode of the light emitting diode (LED). The fourth transistor (T4) may be turned on by the fourth gate signal (GI) transmitted to the fourth gate line (GIL) and may transmit the initialization voltage (Vaint) transmitted to the initialization voltage line (VAL) to the third node (N3) and initialize the pixel electrode (e.g., anode) of the light emitting diode (LED).

[0088] The fifth transistor (T5) may be connected to the driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a fifth gate electrode connected to the third gate line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to a third gate signal (EM) transmitted to the third gate line (EML).

[0089] The sixth transistor (T6) may be connected to the first transistor (T1) and a light emitting diode (LED). The sixth transistor (T6) may be connected between the second node (N2) and the third node (N3). The sixth transistor (T6) may include a sixth gate electrode connected to the fifth gate line (EMBL), a first terminal connected to the second node (N2), and a second terminal connected to the third node (N3). The first terminal of the sixth transistor (T6) may be connected to the second terminal of the first transistor (T1), the first capacitor (C1), and the second capacitor (C2). The second terminal of the sixth transistor (T6) may be connected to the first terminal of the fourth transistor (T4) and the pixel electrode of the light emitting diode (LED). The sixth transistor (T6) may be turned on or off according to the fifth gate signal (EMB) transmitted to the fifth gate line (EMBL).

[0090] A first capacitor (C1) may be connected between a first gate electrode of a first transistor (T1) and a second terminal of the first transistor (T1). A first electrode of the first capacitor (C1) may be connected to a first node (N1), and a second electrode may be connected to a second node (N2). A first electrode of the first capacitor (C1) may be connected to a first gate electrode of the first transistor (T1), a second terminal of the second transistor (T2), and a first terminal of a third transistor (T3). A second electrode of the first capacitor (C1) may be connected to a second terminal of the first transistor (T1), the first-second gate electrodes, the second electrode of the second capacitor (C2), and a first terminal of a sixth transistor (T6). The first capacitor (C1) may be a storage capacitor and may store a threshold voltage of the first transistor (T1) and a voltage corresponding to a data signal (DATA).

[0091] When the third transistor (T3) and the fifth transistor (T5) are turned on, the first transistor (T1) can be turned on. When the voltage of the second terminal of the first transistor (T1) drops to the difference (Vref-Vth1) between the reference voltage (Vref) and the threshold voltage (Vth1) of the first transistor (T1), the first transistor (T1) is turned off, and a voltage corresponding to the threshold voltage (Vth1) of the first transistor (T1) is stored in the first capacitor (C1), so that the threshold voltage (Vth1) of the first transistor (T1) can be compensated.

[0092] The second capacitor (C2) may be connected between the driving voltage line (PL) and the second node (N2). The first electrode of the second capacitor (C2) may be connected to the driving voltage line (PL). The second electrode of the second capacitor (C2) may be connected to the second terminal and the first-second gate electrode of the first transistor (T1), the second electrode of the first capacitor (C1), and the first terminal of the sixth transistor (T6).

[0093] The capacitance of each of the first capacitor (C1) and the second capacitor (C2) may vary depending on the color of light emitted from the light emitting diode (LED).

[0094] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the sustain voltage line (VSSL), and the pixel electrode of the light emitting diode (LED). The auxiliary capacitor (Ca) stores and maintains a voltage corresponding to the voltage difference between the pixel electrode of the light emitting diode (LED) and the sustain voltage line (VSSL), thereby preventing or substantially preventing the problem of the black luminance increasing when the sixth transistor (T6) is turned off.

[0095] A light emitting diode (LED) may be connected to the first transistor (T1) via a sixth transistor (T6). The light emitting diode (LED) may include a pixel electrode (e.g., an anode) connected to a third node (N3) and a counter electrode (e.g., a cathode) facing the pixel electrode. The counter electrode may receive a common voltage (ELVSS). In one embodiment, the counter electrode (e.g., the cathode) may be electrically connected to a sustain voltage line (VSSL) that extends to a display area and provides the common voltage (ELVSS). A driving current output by the first transistor (T1) flows through the light emitting diode (LED) by the turned-on fifth transistor (T5) and the turned-on sixth transistor (T6), and the light emitting diode (LED) may emit light with a brightness corresponding to the magnitude of the driving current.

[0096] Although FIG. 4 illustrates that the subpixel circuit (PC) includes six transistors, the present invention is not limited thereto. In another embodiment, the subpixel circuit (PC) may include seven transistors. In another embodiment, the number of transistors in the subpixel circuit (PC) may be five or less, or eight or more.

[0097] FIG. 5 is a cross-sectional view showing a portion of a display area of ​​a display device according to one embodiment of the present invention.

[0098] Referring to FIG. 5, the display device (10) includes a light emitting diode (LED) arranged in a display area (DA). The light emitting diode (LED) is arranged on a substrate (100), and a subpixel circuit (PC) may be arranged between the substrate (100) and the light emitting diode (LED). As an example, FIG. 5 illustrates some components of the above-described subpixel circuit (PC), including a first transistor (T1), a first capacitor (C1), and a second capacitor (C2).

[0099] The substrate (100) may include a glass material or a polymer resin. As an example, the substrate (100) may have an alternating laminated structure of a base layer including a polymer resin and a barrier layer including an inorganic insulating material such as silicon oxide or silicon nitride. The polymer resin may include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc.

[0100] A first electrode (C21) of a second capacitor (C2) may be placed on a substrate (100). The first electrode (C21) of the second capacitor (C2) may include a conductive material such as a metal, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned materials.

[0101] The first insulating layer (111) may be disposed on the first electrode (C21) of the second capacitor (C2). The first insulating layer (111) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer structure or a multi-layer structure including the aforementioned inorganic insulating material.

[0102] The second electrode (C22) of the second capacitor (C2) and the second lower electrode (C12b) of the first capacitor (C1) may be disposed on the first insulating layer (111). In one embodiment, the second electrode (C22) of the second capacitor (C2) and the second lower electrode (C12b) of the first capacitor (C1) may be connected to each other and provided as an integral part. The second electrode (C22) of the second capacitor (C2) and the second lower electrode (C12b) of the first capacitor (C1) may include a conductive material such as a metal, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned materials.

[0103] The second insulating layer (112) may be disposed on the second electrode (C22) of the second capacitor (C2) and the second lower electrode (C12b) of the first capacitor (C1). The second insulating layer (112) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned inorganic insulating materials. The second insulating layer (112) may be a kind of buffer layer that prevents or substantially prevents impurities from penetrating into a transistor, for example, the first transistor (T1).

[0104] In this specification, the first electrode (C21) and the second electrode (C22) of the second capacitor (C2) may be referred to as the third electrode and the fourth electrode, respectively.

[0105] The semiconductor layer may be disposed on the second insulating layer (112). For example, FIG. 5 illustrates that the first semiconductor layer (A1) of the first transistor (T1) is disposed on the second insulating layer (112). The first semiconductor layer (A1) may include a channel region and a source region and a drain region disposed on both sides of the channel region. The first semiconductor layer (A1) may include an oxide of at least one of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), or zinc (Zn). For example, the first semiconductor layer (A1) may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, or the like. At least a portion of the first semiconductor layer (A1) may undergo a conductive (or conductive) process by plasma treatment or the like.

[0106] The first gate electrode (G1) may overlap the channel region of the first semiconductor layer (A1) with the third insulating layer (113) therebetween. The second electrode (C22) of the second capacitor (C2) may face the first gate electrode (G1) with the first semiconductor layer (A1) therebetween. The second electrode (C22) of the second capacitor (C2) may be the lower gate electrode of the first transistor (T1), and the first gate electrode (G1) may be the upper gate electrode of the first transistor (T1). The first gate electrode (G1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned materials. The third insulating layer (113) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer structure or a multi-layer structure including the aforementioned inorganic insulating material.

[0107] The first electrode (C11) of the first capacitor (C1) may overlap the second lower electrode (C12b) with the second insulating layer (112) and the third insulating layer (113) therebetween. In Fig. 5, the first electrode (C11) of the first capacitor (C1) is illustrated as being spaced apart from (e.g., separated from) the first gate electrode (G1), but is not limited thereto, and the first electrode (C11) of the first capacitor (C1) may be connected to and integrally formed with the first gate electrode (G1).

[0108] The first electrode (C11) of the first capacitor (C1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned materials.

[0109] The fourth insulating layer (114) may be disposed on the first electrode (C11) and the first gate electrode (G1) of the first capacitor (C1). The fourth insulating layer (114) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned inorganic insulating materials.

[0110] The data line (DL), the first connection pattern (1310), and the second upper electrode (C12t) of the first capacitor (C1) may be disposed on the fourth insulating layer (114). The first connection pattern (1310) may connect the first semiconductor layer (A1) of the first transistor (T1) and the second electrode (C22) of the second capacitor (C2). The second upper electrode (C12t) of the first capacitor (C1) may be at least a part of the first connection pattern (1310). The second upper electrode (C12t) of the first capacitor (C1) may overlap the second lower electrode (C12b) of the first capacitor (C1) with the second insulating layer (112), the third insulating layer (113), and the fourth insulating layer (114) therebetween. The second upper electrode (C12t) of the first capacitor (C1) may be connected to the second lower electrode (C12b) of the first capacitor (C1) through a contact hole penetrating the second insulating layer (112), the third insulating layer (113), and the fourth insulating layer (114). The second upper electrode (C12t) of the first capacitor (C1) may overlap the first electrode (C11) of the first capacitor (C1) with the fourth insulating layer (114) therebetween. The data line (DL), the first connection pattern (1310), and the second upper electrode (C12t) of the first capacitor (C1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned materials.

[0111] The fifth insulating layer (115) is disposed on the data line (DL), the first connection pattern (1310), and the second upper electrode (C12t) of the first capacitor (C1), and may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0112] The upper conductive layer (UCL) may be disposed on the fifth insulating layer (115). The upper conductive pattern disposed on the same layer as the upper conductive layer (UCL) is connected to a light emitting diode (LED), and the upper conductive pattern may be connected to a transistor of a subpixel circuit (PC) (e.g., the sixth transistor (T6, FIG. 4)). In some embodiments, in FIG. 5 viewed from another point of view, another voltage line, for example, a sustain voltage line (VSSL, FIG. 4), may be disposed on the same layer as the upper conductive layer (UCL), for example, the fifth insulating layer (115). The upper conductive layer (UCL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned materials.

[0113] The sixth insulating layer (116) is disposed on the upper conductive layer (UCL) and may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0114] A light emitting diode (LED) may include a pixel electrode (210), a light emitting layer (222), and a counter electrode (230).

[0115] The pixel electrode (210) may be disposed on the sixth insulating layer (116). The pixel electrode (210) may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the pixel electrode (210) may further include a conductive oxide layer on and / or below the aforementioned reflective film. The conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In one embodiment, the pixel electrode (210) may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0116] The bank layer (123) may be disposed on the pixel electrode (210). The bank layer (123) may include an opening (123OP) overlapping the pixel electrode (210), and the bank layer (123) may cover an edge of the pixel electrode (210). The bank layer (123) may include an organic insulator. In some embodiments, the bank layer (123) may include a light-transmitting organic insulator. In other embodiments, the bank layer (123) may include an organic insulator including a light-blocking material. In some embodiments, the bank layer (123) may include a polyimide (PI)-based binder and a pigment in which red, green, and blue are mixed with each other. In other embodiments, the bank layer (123) may include a cardo-based binder resin and a mixture of a lactam black pigment and a blue pigment. In another embodiment, the bank layer (123) may include carbon black. The bank layer (123) may improve the contrast of the display device (10).

[0117] The spacer (125) may be disposed on the bank layer (123). The spacer (125) may include a different material from the bank layer (123). In other words, the bank layer (123) may include a negative photosensitive material, and the spacer (127) may include a positive photosensitive material, and they may each be formed through separate mask processes. In another embodiment, the spacer (125) may include the same material as the bank layer (123) and may be formed together in the same mask process (e.g., a halftone mask process).

[0118] The light-emitting layer (222) may include a high molecular weight organic material or a low molecular weight organic material that emits light of an intended color (e.g., a specific color or a predetermined color). The light-emitting layer (222) may include a material that emits red light, green light, or blue light, depending on the light-emitting diode (LED).

[0119] A functional layer may be included below and / or above the light-emitting layer (222). For example, a first functional layer (221) may be included between the pixel electrode (210) and the light-emitting layer (222), and a second functional layer (223) may be included between the light-emitting layer (222) and a counter electrode (230) to be described later. The first functional layer (221) may include a hole transport layer and / or a hole injection layer. The second functional layer (223) may include an electron transport layer and / or an electron injection layer.

[0120] The counter electrode (230) may be formed of a conductive material having a low work function. For example, the counter electrode (230) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. In another example, the counter electrode (230) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including one or more of the aforementioned materials.

[0121] Unlike the pixel electrodes (210) that are formed individually from each other to correspond to light emitting diodes (LEDs), the counter electrodes (230) may extend to correspond to the pixel electrodes (210). For example, the pixel electrodes (210) of one light emitting diode (LED) and the pixel electrodes (210) of another light emitting diode (LED) may be spaced apart from each other (e.g., separated), but the counter electrodes (230) that overlap the pixel electrodes (210) may extend to cover the pixel electrodes (210) described above.

[0122] The encapsulating layer (300) is disposed on a light-emitting diode (LED) and may include at least one inorganic encapsulating layer and at least one organic encapsulating layer. In one embodiment, FIG. 5 illustrates that the encapsulating layer (300) includes a first inorganic encapsulating layer (310), an organic encapsulating layer (320), and a second inorganic encapsulating layer (330).

[0123] The first inorganic encapsulating layer (310) and the second inorganic encapsulating layer (330) may include at least one inorganic insulating material selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. The first inorganic encapsulating layer (310) and the second inorganic encapsulating layer (330) may be a single layer or multiple layers including one or more of the aforementioned materials. The organic encapsulating layer (320) may include a polymer-based material. Examples of the polymer-based material include acrylic resins, epoxy resins, polyimides, and polyethylene. In one embodiment, the organic encapsulating layer (320) may include acrylate.

[0124] Fig. 6 is a plan view showing the first to third subpixel circuit regions of the first to third subpixels of the display device according to one embodiment of the present invention. Fig. 6 may be a plan structure (e.g., a plan view) of the subpixel circuit (PC) of the display device (10) described with reference to Figs. 4 and 5. Fig. 6 illustrates the first to sixth transistors (T6), the first capacitor (C1), and the second capacitor (C2) of the first subpixel (P1), the second subpixel (P2), and the third subpixel (P3), respectively.

[0125] Referring to FIG. 6, a first subpixel circuit area (PCA1) in which a first subpixel circuit of a first subpixel (P1) is arranged, a second subpixel circuit area (PCA2) in which a second subpixel circuit of a second subpixel (P2) is arranged, and a third subpixel circuit area (PCA3) in which a third subpixel circuit of a third subpixel (P3) is arranged may be arranged adjacent to each other along a first direction (e.g., x direction).

[0126] In one embodiment, the first transistor (T1) and the first capacitor (C1) on the plane can overlap in a third direction (e.g., the z direction).

[0127] In one embodiment, the first channel region (CH1, see FIG. 9) of the first semiconductor layer (A1, see FIG. 9) of the first transistor (T1) of each of the first subpixel (P1) and the second capacitor (C2) on the plane may be non-overlapping. In one embodiment, the first channel region (CH1, see FIG. 9) of the first semiconductor layer (A1, see FIG. 9) of the first transistor (T1) of the third subpixel (P3) on the plane may be overlapping with the second capacitor (C2).

[0128] In one embodiment, on a plane, the second transistor (T2) and the third transistor (T3) may be arranged on one side of the first transistor (T1), and the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may be arranged on the other side (e.g., the opposite side) of the first transistor (T1). For example, on a plane, the second transistor (T2) and the third transistor (T3) may be arranged on an upper side of the first transistor (T1), and the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may be arranged on a lower side of the first transistor (T1).

[0129] A first data line (DL1) electrically connected to the first subpixel circuit of the first subpixel (P1) may be arranged in the first subpixel circuit area (PCA1), a second data line (DL2) electrically connected to the second subpixel circuit of the second subpixel (P2) may be arranged in the second subpixel circuit area (PCA2), and a third data line (DL3) electrically connected to the third subpixel circuit of the third subpixel (P3) may be arranged in the third subpixel circuit area (PCA3).

[0130] On a plane, the side of the driving voltage line (PL) facing the data line (e.g., the first to third data lines (DL1, DL2, DL3)) may be arranged closer to the data line than the side of the first conductive pattern (1050) facing the data line.

[0131] FIGS. 7 to 11 are plan views according to the stacking order of the components of each layer constituting the first to third subpixels of the display device illustrated in FIG. 6. FIG. 12 is a schematic plan view of the driving voltage line (Pl), the first conductive pattern (1050), and data lines (e.g., the first data line (DL1), the second data line (DL2), and the third data line (DL3)) in the display device illustrated in FIG. 6.

[0132] Referring to FIG. 7, a driving voltage line (PL), a reference voltage line (VRL), and a repair line (RL) can be arranged on a substrate (100, see FIG. 5).

[0133] Each of the driving voltage line (PL), the reference voltage line (VRL), and the repair line (RL) may extend in a first direction (e.g., the x direction) so as to pass through a first subpixel circuit area (PCA1), a second subpixel circuit area (PCA2), and a third subpixel circuit area (PCA3). The driving voltage line (PL) may be electrically connected to a power supply circuit (17, see FIG. 3). Based on a power control signal (PCS, see FIG. 3) transmitted from a controller (19, see FIG. 3), the driving voltage line (PL) may receive a driving voltage (ELVDD, see FIG. 3) generated by the power supply circuit (17, see FIG. 3) and transmit the driving voltage (ELVDD, see FIG. 3) to each of the subpixels.

[0134] Referring to FIGS. 7 and 12 together, the driving voltage line (PL) on the plane may include a shielding portion that includes a side facing the data line (e.g., the first data line (DL1), the second data line (DL2), or the third data line (DL3)). The driving voltage line (PL) may include a first shielding portion (SP1) arranged in a first subpixel circuit area (PCA1), a second shielding portion (SP2) arranged in a second subpixel circuit area (PCA2), and a third shielding portion (SP3) arranged in a third subpixel circuit area (PCA3).

[0135] On a plane, the first shielding portion (SP1) may include a first side (SS1a) facing the first data line (DL1) and a second side (SS2a) facing the second data line (DL2). On a plane, the second shielding portion (SP2) may include a first side (SS1b) facing the second data line (DL2) and a second side (SS2b) facing the third data line (DL3). On a plane, the third shielding portion (SP3) may include a first side (SS1c) facing the third data line (DL3) and a second side (SS2c) opposite the first side (SS1c).

[0136] The first shielding portion (SP1) may include a first portion (SP1a) extending in a second direction (e.g., the y direction) perpendicular to the first direction, a second portion (SP1b) extending in the second direction (e.g., the y direction) and spaced apart from the first portion (SP1a) in the first direction (e.g., the x direction), and a third portion (SP1c) connecting the first portion (SP1a) and the second portion (SP1b). In a plane, the first portion (SP1a) of the first shielding portion (SP1) may include a first side surface (SS1a) facing the first data line (DL1). In a plane, the second portion (SP1b) of the first shielding portion (SP1) may include a second side surface (SS1b) facing the second data line (DL2). The first shielding portion (SP1) may have, for example, an omega shape.

[0137] The second shielding portion (SP2) may include a first portion (SP2a) extending in a second direction (e.g., the y direction) intersecting the first direction, a second portion (SP2b) extending in the second direction (e.g., the y direction) and spaced apart from the second portion (SP2b) in the first direction (e.g., the x direction), and a third portion (SP2c) connecting the first portion (SP2a) and the second portion (SP2b). The first portion (SP2a) of the second shielding portion (SP2) may include a first side (SS1b) facing the second data line (DL2). The second portion (SP2b) of the second shielding portion (SP2) may include a second side (SS2b) facing the third data line (DL3). The second shielding portion (SP2) may have, for example, an omega shape.

[0138] In one embodiment, each of the first shielding portion (SP1) and the second shielding portion (SP2) overlaps the first conductive pattern (1050) to form a second capacitor (C2), and has an omega shape that extends to overlap the edge of the first conductive pattern (1050), thereby sufficiently securing the capacitance of the second capacitor (C2).

[0139] In one embodiment, the third shield (SP3) may have a larger area than each of the first shield (SP1) and / or the second shield (SP2). The third shield (SP3) may have, for example, an approximate polygonal shape.

[0140] The driving voltage line (PL) may further include a connecting portion (CP) that connects adjacent shielding portions in a first direction (e.g., x-direction). For example, a first shielding portion (SP1) and a second shielding portion (SP2) may be connected by the connecting portion (CP). For example, a second shielding portion (SP) and a third shielding portion (SP3) may be connected by the connecting portion (CP).

[0141] The driving voltage line (PL) may include a first electrode (C21, see FIG. 5) of a second capacitor (C2, see FIG. 5). For example, the driving voltage line (PL) may include a first electrode (C21a, see FIG. 8) of a second capacitor (C2a, see FIG. 8) of a first subpixel (P1), a first electrode (C21b, see FIG. 8) of a second capacitor (C2b, ​​see FIG. 8) of a second subpixel (P2), and a first electrode (C21c, see FIG. 8) of a second capacitor (C2c, see FIG. 8) of a third subpixel (P3). For example, the first shielding portion (SP1) may include a first electrode (C21a, see FIG. 8) of a second capacitor (C2a, see FIG. 8) of the first subpixel (P1), the second shielding portion (SP2) may include a first electrode (C21b, see FIG. 8) of a second capacitor (C2b, ​​see FIG. 8) of the second subpixel (P2), and the third shielding portion (SP3) may include a first electrode (C21c, see FIG. 8) of a second capacitor (C2c, see FIG. 8). The first electrodes (C21a, C21b, C21c, see FIG. 8) of the second capacitors (C2a, C2b, C2c) of the first to third subpixels (P1, P2, P3) may be connected to each other integrally.

[0142] The repair line (RL) may be a spare line that can be used when a defect occurs in the signal line or voltage line included in the subpixel circuits of the first to third subpixels (P1, P2, P3).

[0143] The driving voltage line (PL), the reference voltage line (VRL), and the repair line (RL) may contain the same material. Each of the driving voltage line (PL), the reference voltage line (VRL), and the repair line (RL) may contain a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned materials.

[0144] Referring to FIGS. 7 and 8, a first insulating layer (111, see FIG. 5) may be disposed on the driving voltage line (PL), the reference voltage line (VRL), and the repair line (RL). A first conductive pattern (1050), a first-first gate line (GWLa), a second initialization voltage line (VAL2), and a third initialization voltage line (VAL3) may be disposed on the first insulating layer (111, see FIG. 5).

[0145] The first conductive pattern (1050) may include an isolated shape. The first conductive pattern (1050) may be arranged to correspond to each of the first subpixel circuit area (PCA1), the second subpixel circuit area (PCA2), and the third subpixel circuit area (PCA3). In other words, the first subpixel (P1), the second subpixel (P2), and the third subpixel (P3) may include a first-first conductive pattern (1050a), a first-second conductive pattern (1050b), and a first-third conductive pattern (1050c), respectively, which overlap at least a portion of the driving voltage line (PL). The first-first conductive pattern (1050a), the first-second conductive pattern (1050b), and the first-third conductive pattern (1050c) may be arranged on the same layer (e.g., the first insulating layer (111, see FIG. 5). At least a portion of the driving voltage line (PL) and at least a portion of the first conductive pattern (1050) may overlap each other to form a second capacitor (C2).

[0146] The first-first conductive pattern (1050a) disposed in the first subpixel circuit area (PCA1) may include a second electrode (C22) of a second capacitor (C2a) overlapping with a first electrode (C21a) of a second capacitor (C2a) of the first subpixel (P1). The first-second conductive pattern (1050b) disposed in the second subpixel circuit area (PCA2) may include a second electrode (C22) of a second capacitor (C2b) overlapping with a first electrode (C21b) of a second capacitor (C2b) of the second subpixel (P2). The 1-3 conductive pattern (1050c) arranged in the 3rd subpixel circuit area (PCA3) may include a second electrode (C22) of a second capacitor (C2c) overlapping with a first electrode (C21c) of a second capacitor (C2c) of the 3rd subpixel (P3).

[0147] The first conductive pattern (1050) may include a second lower electrode (C12b) of the first capacitor (C1). In one embodiment, the first conductive pattern (1050) may include a lower gate electrode (e.g., a first-second gate electrode) of the first transistor (T1, see FIG. 9) overlapping with a first semiconductor layer (A1, see FIG. 9) of the first transistor (T1, see FIG. 9). The second electrode (C22) of the second capacitor (C2) and the second lower electrode (C12b) of the first capacitor (C1) may be provided integrally and connected to the second node (N2) described with reference to FIG. 4.

[0148] For example, the first conductive pattern (1050) includes the second lower electrode (C12b) of the first capacitor (C1), the second electrode (C22) of the second capacitor (C2), and is electrically connected to the sixth semiconductor layer (A6, see FIG. 10) of the sixth transistor (T6, see FIG. 10) and the first semiconductor layer (A1, see FIG. 10) of the first transistor (T1, see FIG. 10) by the first connection pattern (1310, see FIG. 11) described in detail below, and thus may be referred to as a first node electrode corresponding to the first node (N1) described with reference to FIG. 4.

[0149] Referring to FIGS. 8 and 12, the first conductive pattern (1050) disposed in each of the first to third sub-pixel circuit areas (PCA1, PCA2, PCA3) may include side surfaces (SSa, SSb) facing adjacent data lines (DL). For example, the first conductive pattern (1050) may include a first side surface (SSa) and a second side surface (SSb) facing each other.

[0150] For example, the 1-1 conductive pattern (1050a) disposed in the first subpixel circuit area (PCA1) may include a first side (SSa) facing the first data line (DL1) and a second side (SSb) facing the second data line (DL2). For example, the 1-2 conductive pattern (1050b) disposed in the second subpixel circuit area (PCA2) may include a first side (SSa) facing the second data line (DL2) and a second side (SSb) facing the third data line (DL3). For example, the 1-3 conductive pattern (1050c) arranged in the 3rd subpixel circuit area (PCA3) may include a first side (SSa) facing the 3rd data line (DL3), and a second side (SSb) facing the data line adjacent to the 1-3 conductive pattern (1050c) in an area not shown (e.g., arranged on the right side of FIG. 12).

[0151] In one embodiment, each of the first side (SSa) and the second side (SSb) of the 1-1 conductive pattern (1050a) disposed in the first subpixel circuit area (PCA1) may overlap the first shielding portion (SP1). For example, the first side (SSa) of the 1-1 conductive pattern (1050a) may overlap the first portion (SP1a) of the first shielding portion (SP1). For example, the second side (SSb) of the 1-1 conductive pattern (1050a) may overlap the second portion (SP1b) of the first shielding portion (SP1).

[0152] In one embodiment, each of the first side (SSa) and the second side (SSb) of the first-second conductive pattern (1050b) arranged in the second subpixel circuit area (PCA2) may overlap the second shielding portion (SP2). For example, the first side (SSa) of the first-second conductive pattern (1050b) may overlap the first portion (SP2a) of the second shielding portion (SP2). For example, the second side (SSb) of the first-second conductive pattern (1050b) may overlap the second portion (SP2b) of the second shielding portion (SP2).

[0153] In one embodiment, each of the first side (SSa) and the second side (SSb) of the first-third conductive pattern (1050c) arranged in the third subpixel circuit area (PCA3) may overlap with the third shielding portion (SP3).

[0154] The distance (DS1) between the first side (SS1a) of the first portion (SP1a) of the first shielding portion (SP1) and the first data line (DL1) may be smaller than the distance (DS2) between the first-first conductive pattern (1050a) and the first data line (DL1). The distance (DS3) between the second side (SS1b) of the second portion (SP1b) of the first shielding portion (SP1) and the second data line (DL2) may be smaller than the distance (DS4) between the first-first conductive pattern (1050a) and the second data line (DL2).

[0155] Similarly, the distance between the first side (SS1b) of the first part (SP2a) of the second shielding portion (SP2) and the second data line (DL2) may be smaller than the distance between the first-second conductive pattern (1050b) and the second data line (DL2). The distance between the second side (SS2b) of the second part (SP2b) of the second shielding portion (SP2) and the third data line (DL3) may be smaller than the distance between the first-second conductive pattern (1050b) and the third data line (DL3).

[0156] The distance (DS5) between the first side (SS1c) of the third shielding portion (SP3) and the third data line (DL3) may be smaller than the distance (DS6) between the first-third conductive pattern (1050c) and the third data line (DL3).

[0157] In one embodiment of the present invention, by forming a shielding portion (e.g., first to third shielding portions (SP1, SP2, SP3)) of a driving voltage line (PL) on a plane so as to be arranged closer to a data line than a first conductive pattern (1050), which is a first node electrode, coupling between the first node electrode and the data line is reduced, thereby improving the voltage swing of the data line, and transmitting a data signal more stably. In addition, since the shielding portion of the driving voltage line (PL) is arranged under the first conductive pattern (1050), coupling with the data line due to an electric field or magnetic field formed under the first conductive pattern (1050) can be reduced.

[0158] Each of the first gate line (GWLa), the second initialization voltage line (VAL2), and the third initialization voltage line (VAL3) may extend in a first direction (e.g., in the x direction) so as to pass through the first subpixel circuit area (PCA1), the second subpixel circuit area (PCA2), and the third subpixel circuit area (PCA3).

[0159] The first-first gate line (GWLa) may be arranged on one side of the first conductive pattern (1050), and the second initialization voltage line (VAL2) and the third initialization voltage line (VAL3) may each be arranged on the other side (e.g., the opposite side) of the first conductive pattern (1050). For example, on a plane, the first-first gate line (GWLa) may be arranged on an upper side of the first conductive pattern (1050), and the second initialization voltage line (VAL2) and the third initialization voltage line (VAL3) may each be arranged on a lower side of the first conductive pattern (1050). For example, the first conductive pattern (1050) may be located between the first-first gate line (GWLa) and the second initialization voltage line (VAL2).

[0160] The first conductive pattern (1050), the first-first gate line (GWLa), the second initialization voltage line (VAL2), and the third initialization voltage line (VAL3) may include the same material. Each of the first conductive pattern (1050), the first-first gate line (GWLa), the second initialization voltage line (VAL2), and the third initialization voltage line (VAL3) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned materials.

[0161] Referring to FIGS. 8 and 9, a second insulating layer (112, see FIG. 5) may be disposed on the first conductive pattern (1050), the first-first gate line (GWLa), the second initialization voltage line (VAL2), and the third initialization voltage line (VAL3). A semiconductor layer including the first to third semiconductor patterns (1110, 1120, 1130) may be disposed on the second insulating layer (112, see FIG. 5).

[0162] Each of the first semiconductor pattern (1110), the second semiconductor pattern (1120), and the third semiconductor pattern (1130) may include an isolated shape. For example, the first semiconductor pattern (1110), the second semiconductor pattern (1120), and the third semiconductor pattern (1130) may be arranged to be spaced apart from each other. Each of the first semiconductor pattern (1110), the second semiconductor pattern (1120), and the third semiconductor pattern (1130) may be arranged to correspond to each of the first subpixel circuit area (PCA1), the second subpixel circuit area (PCA2), and the third subpixel circuit area (PCA3).

[0163] The first semiconductor pattern (1110) may include a first semiconductor layer (A1) and a fifth semiconductor layer (A5). In other words, the first semiconductor layer (A1) and the fifth semiconductor layer (A5) may be integrally connected. The second semiconductor pattern (1120) may include a second semiconductor layer (A2) and a third semiconductor layer (A3). In other words, the second semiconductor layer (A2) and the third semiconductor layer (A3) may be integrally connected. The third semiconductor pattern (1130) may include a fourth semiconductor layer (A4) and a sixth semiconductor layer (A6). In other words, the fourth semiconductor layer (A4) and the sixth semiconductor layer (A6) may be integrally connected.

[0164] The first semiconductor layer (A1) may include a first channel region (CH1) overlapping with a first gate electrode (G1) of a first transistor (T1) described in detail below with reference to FIG. 10, a first source region (S1) disposed on one side of the first channel region (CH1), and a first drain region (D1) disposed on the other side of the first channel region (CH1).

[0165] The second semiconductor layer (A2) may include a second channel region (CH2) overlapping with a second gate electrode (G2) of a second transistor (T2) described in detail below with reference to FIG. 10, a second source region (S2) disposed on one side of the second channel region (CH2), and a second drain region (D2) disposed on the other side of the second channel region (CH2).

[0166] The third semiconductor layer (A3) may include a third channel region (CH3) overlapping with a third gate electrode (G3) of a third transistor (T3) described in detail below with reference to FIG. 10, a third source region (S3) disposed on one side of the third channel region (CH3), and a third drain region (D3) disposed on the other side of the third channel region (CH3).

[0167] The fourth semiconductor layer (A4) may include a fourth channel region (CH4) overlapping with a fourth gate electrode (G4) of a fourth transistor (T4) described in detail below with reference to FIG. 10, a fourth source region (S4) disposed on one side of the fourth channel region (CH4), and a fourth drain region (D4) disposed on the other side of the fourth channel region (CH4).

[0168] The fifth semiconductor layer (A5) may include a fifth channel region (CH5) overlapping with a fifth gate electrode (G5) of a fifth transistor (T5) described in detail below with reference to FIG. 10, a fifth source region (S5) disposed on one side of the fifth channel region (CH5), and a fifth drain region (D5) disposed on the other side of the fifth channel region (CH5).

[0169] The sixth semiconductor layer (A6) may include a sixth channel region (CH6) overlapping with a sixth gate electrode (G6) of a sixth transistor (T6) described in detail below with reference to FIG. 10, a sixth source region (S6) disposed on one side of the sixth channel region (CH6), and a sixth drain region (D6) disposed on the other side of the sixth channel region (CH6).

[0170] The first to third semiconductor patterns (1110, 1120, 1130) may include the same material. In one embodiment, the first to third semiconductor patterns (1110, 1120, 1130) may include an oxide semiconductor material. For example, each of the first to third semiconductor patterns (1110, 1120, 1130) may include at least one oxide semiconductor material selected from indium (In), gallium (Ga), stannium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and / or zinc (Zn). In another embodiment, the first to third semiconductor patterns (1110, 1120, 1130) may include polysilicon or amorphous silicon.

[0171] Referring to FIGS. 7 and 9, on a plane, the shielding portion of the driving voltage line (PL) arranged in each of the first to third subpixel circuit areas (PCA1, PCA2, PCA3) may be spaced apart so as not to overlap with the first channel area (CH1) of the first semiconductor layer (A1) of the first transistor (T1) or may overlap with the entire first channel area (CH1) of the first semiconductor layer (A1) of the first transistor (T1).

[0172] For example, on a plane, the first channel region (CH1) of the first semiconductor layer (A1) of the first transistor (T1) disposed in the first subpixel circuit area (PCA1) may be spaced apart from the first shielding portion (SP1). For example, on a plane, the first channel region (CH1) of the first semiconductor layer (A1) of the first transistor (T1) disposed in the first subpixel circuit area (PCA1) may be spaced between the first portion (SP1a) and the second portion (SP1b) of the first shielding portion (SP1). For example, on a plane, the first channel region (CH1) of the first semiconductor layer (A1) of the first transistor (T1) disposed in the first subpixel circuit area (PCA1) may be spaced apart from each of the first portion (SP1a), the second portion (SP1b), and the third portion (SP1c) of the first shielding portion (SP1).

[0173] For example, on a plane, the first channel region (CH1) of the first semiconductor layer (A1) of the first transistor (T1) disposed in the second subpixel circuit area (PCA2) may be spaced apart from the second shielding portion (SP2). For example, on a plane, the first channel region (CH1) of the first semiconductor layer (A1) of the first transistor (T1) disposed in the second subpixel circuit area (PCA2) may be spaced between the first portion (SP2a) and the second portion (SP2b) of the second shielding portion (SP2). For example, on a plane, the first channel region (CH1) of the first semiconductor layer (A1) of the first transistor (T1) disposed in the second subpixel circuit area (PCA2) may be spaced apart from each of the first portion (SP2a), the second portion (SP2b), and the third portion (SP2c) of the second shielding portion (SP2).

[0174] For example, on a plane, the entire first channel region (CH1) of the first semiconductor layer (A1) of the first transistor (T1) arranged in the third subpixel circuit region (PCA3) may overlap with the third shielding portion (SP3).

[0175] In the comparative example, when the layer below the first semiconductor layer (A1) includes a stepped portion in the area overlapping with the first channel region (CH1) of the first semiconductor layer (A1), the first semiconductor layer (A1) may not be formed stably and may be electrically unstable. In contrast, in one embodiment of the present invention, since the first shielding portion (SP1) and the second shielding portion (SP2) disposed below the first semiconductor layer (A1) of the first subpixel (P1) and the second subpixel (P2) do not overlap with the first channel region (CH1), a step is not formed in the area where the first channel region (CH1) is disposed, and thus the first semiconductor layer (A1) of the first transistor (T1) may be formed more electrically stably. Similarly, since the third shielding portion (SP3) disposed below the first semiconductor layer (A1) of the third subpixel (P3) overlaps the entire first channel region (CH1), a step is not formed in the region where the first channel region (CH1) is disposed, so the first semiconductor layer (A1) of the first transistor (T1) can be formed more electrically stable.

[0176] Referring to FIGS. 9 and 10, a third insulating layer (113, see FIG. 5) may be disposed on the first to third semiconductor patterns (1110, 1120, 1130). A second conductive pattern (1210), a third conductive pattern (1220), a fourth conductive pattern (1230), a first-second gate line (GWLb), a second gate line (GRL), a third gate line (EML), a fourth gate line (GIL), a fifth gate line (EMBL), and a first initialization voltage line (VAL1) may be disposed on the third insulating layer (113, see FIG. 5).

[0177] Each of the second conductive pattern (1210), the third conductive pattern (1220), and the fourth conductive pattern (1230) may include an isolated shape. For example, the second conductive pattern (1210), the third conductive pattern (1220), and the fourth conductive pattern (1230) may be arranged to be spaced apart from each other. Each of the second conductive pattern (1210), the third conductive pattern (1220), and the fourth conductive pattern (1230) may be arranged to correspond to each of the first subpixel circuit area (PCA1), the second subpixel circuit area (PCA2), and the third subpixel circuit area (PCA3).

[0178] The second challenge pattern (1210) may include a first gate electrode (G1) of the first transistor (T1) overlapping with the first semiconductor layer (A1) of the first transistor (T1).

[0179] The second conductive pattern (1210) may overlap with the first conductive pattern (1050). The second conductive pattern (1210) may include a first electrode (C11) of a first capacitor (C1) connected to the first node (N1) described with reference to FIG. 4. The first electrode (C11) of the first capacitor (C1) may overlap with the second lower electrode (C12b) of the first capacitor (C1). The first capacitor (C1) may include a first electrode (C11), a second lower electrode (C12b), and a second upper electrode (C12t) described in detail below with reference to FIG. 11. For example, the first gate electrode (G1) of the first transistor (T1) and the first electrode (C11) of the first capacitor (C1) may be provided as one piece.

[0180] The third conductive pattern (1220) may overlap at least a portion of the second semiconductor pattern (1120). The third conductive pattern (1220) may include a second gate electrode (G2) of the second transistor (T2) that overlaps the second semiconductor layer (A2) of the second transistor (T2).

[0181] At least a portion of the fourth conductive pattern (1230) may overlap with the reference voltage line (VRL, see FIG. 7). The fourth conductive pattern (1230) may be connected to the reference voltage line (VRL, see FIG. 7) through a contact hole penetrating at least one insulating layer interposed between the fourth conductive pattern (1230) and the reference voltage line (VRL, see FIG. 7). The fourth conductive pattern (1230) may be connected to the fourth connection pattern (1340), which will be described in detail below with reference to FIG. 11. The fourth conductive pattern (1230) may be connected to the second semiconductor pattern (1120, see FIG. 9) through the fourth connection pattern (1340).

[0182] Each of the first and second gate lines (GWLb), the second gate line (GRL), the third gate line (EML), the fourth gate line (GIL), the fifth gate line (EMBL), and the first initialization voltage line (VAL1) may extend in a first direction (e.g., in the x direction) so as to pass through the first subpixel circuit area (PCA1), the second subpixel circuit area (PCA2), and the third subpixel circuit area (PCA3).

[0183] On a plane, each of the first and second gate lines (GWLb) and the second gate line (GRL) may be disposed on one side of the second conductive pattern (1210), and each of the third gate line (EML), the fourth gate line (GIL), the fifth gate line (EMBL), and the first initialization voltage line (VAL1) may be disposed on the other side of the second conductive pattern (1210). For example, on a plane, each of the first and second gate lines (GWLb) and the second gate line (GRL) may be disposed on an upper side of the second conductive pattern (1210), and each of the third gate line (EML), the fourth gate line (GIL), the fifth gate line (EMBL), and the first initialization voltage line (VAL1) may be disposed on a lower side of the second conductive pattern (1210).

[0184] The first-second gate line (GWLb) may be arranged on the first-first gate line (GWLa) to overlap with the first-first gate line (GWLa). The first-first gate line (GWLa) and the first-second gate line (GWLb) may be connected through a contact hole penetrating at least one insulating layer interposed between the first-first gate line (GWLa) and the first-second gate line (GWLb).

[0185] The second gate line (GRL) may overlap at least a portion of the second semiconductor pattern (1120). The second gate line (GRL) may include a third gate electrode (G3) of the third transistor (T3) that overlaps the third semiconductor layer (A3) of the third transistor (T3).

[0186] The third gate line (EML) may overlap at least a portion of the first semiconductor pattern (1110). The third gate line (EML) may include a fifth gate electrode (G5) of the fifth transistor (T5) that overlaps the fifth semiconductor layer (A5) of the fifth transistor (T5).

[0187] The fifth gate line (EMBL) may overlap at least a portion of the third semiconductor pattern (1130). The fifth gate line (EMBL) may include a sixth gate electrode (G6) of the sixth transistor (T6) that overlaps the sixth semiconductor layer (A6) of the sixth transistor (T6).

[0188] The fourth gate line (GIL) may overlap at least a portion of the third semiconductor pattern (1130). The fourth gate line (GIL) may include the sixth gate electrode (G4) of the fourth transistor (T4) overlapping the fourth semiconductor layer (A4) of the fourth transistor (T4).

[0189] The second conductive pattern (1210), the third conductive pattern (1220), the fourth conductive pattern (1230), the first-second gate line, the second gate line (GRL), the third gate line (EML), the fourth gate line (GIL), the fifth gate line (EMBL), and the first initialization voltage line (VAL1) may include the same material. Each of the second conductive pattern (1210), the third conductive pattern (1220), the fourth conductive pattern (1230), the first-second gate line, the second gate line (GRL), the third gate line (EML), the fourth gate line (GIL), the fifth gate line (EMBL), and the first initialization voltage line (VAL1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned materials.

[0190] Referring to FIGS. 10 and 11, a fourth insulating layer (114, see FIG. 5) may be disposed on the second conductive pattern (1210), the third conductive pattern (1220), the fourth conductive pattern (1230), the first and second gate lines (GWLb), the second gate line (GRL), the third gate line (EML), the fourth gate line (GIL), the fifth gate line (EMBL), and the first initialization voltage line (VAL1). The first to third data lines (DL1, DL2, DL3), the first connection pattern (1310), the second connection pattern (1320), the third connection pattern (1330), the fourth connection pattern (1340), the fifth connection pattern (1350), and the sixth connection pattern (1360) may be disposed on the fourth insulating layer (114, see FIG. 5).

[0191] Each of the first connection pattern (1310), the second connection pattern (1320), the third connection pattern (1330), the fourth connection pattern (1340), the fifth connection pattern (1350), and the sixth connection pattern (1360) may be arranged to correspond to each of the first subpixel circuit area (PCA1), the second subpixel circuit area (PCA2), and the third subpixel circuit area (PCA3).

[0192] Each of the first to third data lines (DL1, DL2, DL3) may extend along a second direction (e.g., y direction) intersecting the first direction (e.g., x direction). The first data line (DL1) may be arranged in a first subpixel circuit area (PCA1) and may be electrically connected to a subpixel circuit of the first subpixel (P1). The second data line (DL2) may be arranged in a second subpixel circuit area (PCA2) and may be electrically connected to a subpixel circuit of the second subpixel (P2). The third data line (DL3) may be arranged in a third subpixel circuit area (PCA3) and may be electrically connected to a subpixel circuit of the third subpixel (P3).

[0193] For example, the first data line (DL1) may be electrically connected to a second drain region (D2, see FIG. 9) of a second semiconductor layer (A2) of a second transistor (T2) included in a first subpixel (P1) through a contact hole penetrating at least one insulating layer interposed between the second semiconductor layer (A2) and the first data line (DL1). For example, the second data line (DL2) may be electrically connected to a second drain region (D2, see FIG. 9) of a second semiconductor layer (A2) of a second transistor (T2) included in a second subpixel (P2) through a contact hole penetrating at least one insulating layer interposed between the second semiconductor layer (A2) and the second data line (DL2). For example, the third data line (DL3) can be electrically connected to the second drain region (D2, see FIG. 9) of the second semiconductor layer (A2) of the second transistor (T2) included in the third subpixel (P3) through a contact hole penetrating at least one insulating layer interposed between the second semiconductor layer (A2) and the third data line (DL3).

[0194] The first connection pattern (1310) may be connected to the first semiconductor pattern (1110, see FIG. 9) through a contact hole penetrating at least one insulating layer interposed between the first connection pattern (1310) and the first semiconductor pattern (1110, see FIG. 9). For example, the first connection pattern (1310) may be connected to the first source region (S1, see FIG. 9) of the first semiconductor layer (A1) of the first transistor (T1) through the contact hole.

[0195] The first connection pattern (1310) may be connected to the third semiconductor pattern (1130, see FIG. 9) through a contact hole penetrating at least one insulating layer interposed between the first connection pattern (1310) and the first semiconductor pattern (1130, see FIG. 9). For example, the first connection pattern (1310) may be connected to the sixth drain region (D6, see FIG. 9) of the sixth semiconductor layer (A6) of the sixth transistor (T6) through a contact hole.

[0196] The first connection pattern (1310) may include a second upper electrode (C12t) of the first capacitor (C1). The second upper electrode (C12t) of the first capacitor (C1) may be connected by a contact hole penetrating at least one insulating layer interposed between the second lower electrode (C12b) of the first capacitor (C1) and the second upper electrode (C12t) of the first capacitor (C1) and the second lower electrode (C12b) of the first capacitor (C1). The second upper electrode (C12t) of the first capacitor (C1) may be disposed on the first electrode (C11) of the first capacitor (C1) and may overlap with the first electrode (C11) of the first capacitor (C1).

[0197] The first connection pattern (1310) can connect the first semiconductor layer (A1), the sixth semiconductor layer (A6), the second upper electrode (C12t) of the first capacitor (C1), and the second lower electrode (C12b) of the first capacitor (C1).

[0198] The second connection pattern (1320) can connect the second gate electrode (G2) of the second transistor (T2) and the first-second gate line (GWLb). The second connection pattern (1320) can be connected to the first-second gate line (GWLb) through a contact hole penetrating at least one insulating layer interposed between the second connection pattern (1320) and the first-second gate line (GWLb).

[0199] The third connection pattern (1330) can connect the second semiconductor pattern (1120) and the second conductive pattern (1210). The third connection pattern (1330) can connect the second drain region (D2, see FIG. 9) of the second semiconductor layer (A2) of the second transistor (T2), the third drain region (D3, see FIG. 9) of the third semiconductor layer (A3) of the third transistor (T3), and the first gate electrode (G1) of the first transistor (T1). The third connection pattern (1330) can connect the second drain region (D2, see FIG. 9) of the second semiconductor layer (A2) of the second transistor (T2), the third drain region (D3, see FIG. 9) of the third semiconductor layer (A3) of the third transistor (T3), and the first electrode (C11) of the first capacitor (C1).

[0200] The fourth connection pattern (1340) is connected to the fourth conductive pattern (1230) and the second semiconductor pattern (1120, see FIG. 9) through contact holes, and the fourth conductive pattern (1230) can be connected to the reference voltage line (VRL). For example, the fourth connection pattern (1340) and the fourth conductive pattern (1230) can connect the reference voltage line (VRL) and the third semiconductor layer (A3) of the third transistor (T3).

[0201] The fifth connection pattern (1350) may be a pattern that connects a repair line (RL, see FIG. 7) and a sub-pixel circuit when a defect occurs in a signal line or voltage line included in the sub-pixel circuit. For example, the fifth connection pattern (1350) may be connected to the repair pattern (1060, see FIG. 8) and the third semiconductor pattern (1130), and when a defect occurs in the signal line or voltage line, the repair pattern (1060) may be connected to the repair line (RL, see FIG. 7) by bonding. The repair pattern (1060) may be arranged on the same layer as the first conductive pattern (1050).

[0202] The sixth connection pattern (1360) arranged in the first subpixel circuit area (PCA1) can connect the first initialization voltage line (VAL1) and the fourth source area (S4) of the fourth semiconductor layer (A4) of the fourth transistor (T4) of the first subpixel circuit area (PCA1). The sixth connection pattern (1360) arranged in the second subpixel circuit area (PCA2) can connect the second initialization voltage line (VAL2) and the fourth source area (S4) of the fourth semiconductor layer (A4) of the fourth transistor (T4) of the second subpixel circuit area (PCA2). The sixth connection pattern (1360) arranged in the third subpixel circuit area (PCA3) can connect the third initialization voltage line (VAL3) and the fourth source area (S4) of the fourth semiconductor layer (A4) of the fourth transistor (T4) of the third subpixel circuit area (PCA3).

[0203] The first to third data lines (DL1, DL2, DL3), the first connection pattern (1310), the second connection pattern (1320), the third connection pattern (1330), the fourth connection pattern (1340), the fifth connection pattern (1350), the sixth connection pattern (1360), and the seventh connection pattern (1370) may include the same material. The first to third data lines (DL1, DL2, DL3), the first connection pattern (1310), the second connection pattern (1320), the third connection pattern (1330), the fourth connection pattern (1340), the fifth connection pattern (1350), and the sixth connection pattern (1360) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer structure or a multi-layer structure including one or more of the aforementioned materials.

[0204] Referring to FIGS. 11 and 12, a portion of each of the first data line (DL1), the second data line (DL2), and the third data line (DL3) may overlap with the connection portion (CP) of the driving voltage line (PL). In one embodiment of the present invention, since the first to third shielding portions (SP1, SP2, SP3) reduce the coupling between the first to third data lines (DL1, DL2, DL3) and the first conductive pattern (1050), the area of ​​the driving voltage line (PL) overlapping with the first to third data lines (DL1, DL2, DL3) may not be formed to be large. Accordingly, the area of ​​the area where the connection portion (CP) and the first to third data lines (DL1, DL2, DL3) overlap may be minimized or reduced, thereby minimizing or reducing parasitic capacitance. Accordingly, the RC delay in each subpixel circuit may be reduced.

[0205] In the embodiments of the present invention described with reference to FIGS. 6 to 12, the first shielding portion (SP1) and the second shielding portion (SP2) are illustrated as having an omega shape, and the third shielding portion (SP3) is illustrated as having an approximately polygonal shape. However, the present invention is not limited thereto. For example, the first shielding portion (SP1), the second shielding portion (SP2), and the third shielding portion (SP3) may each have an omega shape. For example, the first shielding portion (SP1) may have an omega shape, and the second shielding portion (SP2) and the third shielding portion (SP3) may have approximately polygonal shapes. Various appropriate changes may be made as needed or desired.

[0206] According to one embodiment of the present invention, a display device having improved picture quality and an electronic device including the display device can be provided. However, the aspects and features of the present invention are not limited thereto.

[0207] The above description is merely illustrative of some embodiments of the present invention and should not be construed as limiting the present invention. Although some embodiments have been described, those skilled in the art will readily understand that various modifications can be made without departing from the technical spirit and scope of the present invention. The description of features or aspects included in each embodiment should be considered to be applicable to similar features or aspects of other embodiments, unless otherwise stated. Accordingly, as will be apparent to those skilled in the art, features, characteristics, and / or components related to a particular embodiment may be used alone or in combination with features, characteristics, and / or components related to other embodiments, unless explicitly stated otherwise. Therefore, the above description is merely illustrative of various exemplary embodiments and is not limited to the specific embodiments disclosed herein, and it should be understood that various modifications to the described embodiments, as well as other exemplary embodiments, are included within the spirit and scope of the present invention defined by the appended claims and their equivalents.

Claims

1. A substrate including a display area including a plurality of pixels and a non-display area disposed outside the display area; A driving voltage line extending in a first direction on the above substrate and transmitting a driving voltage; A conductive pattern disposed on the driving voltage line and overlapping at least a portion of the driving voltage line; A driving transistor including a first semiconductor layer disposed on the conductive pattern, electrically connected to the conductive pattern, and including a channel region, and a first gate electrode disposed on the first semiconductor layer and overlapping the channel region; A first capacitor including a first electrode integrally formed with the first gate electrode and a second lower electrode overlapping the first electrode and included in the conductive pattern; A second capacitor including a third electrode included in the driving voltage line and a fourth electrode overlapping the third electrode and included in the conductive pattern; and Including a data line extending in a second direction perpendicular to the first direction, The above driving voltage line includes a shielding portion including a side facing the data line on a plane, A display device, wherein the distance between the side surface of the shielding portion and the data line on a plane is smaller than the distance between the conductive pattern and the data line.

2. In paragraph 1, A display device, wherein the first capacitor further includes a second upper electrode disposed on the first electrode and electrically connected to the second lower electrode.

3. In paragraph 1, A display device wherein the third electrode is at least a part of the shield.

4. In paragraph 1, The above shielding part, A first portion extending in the second direction and including a side facing the data line; a second portion extending in the second direction and spaced apart from the first portion in the first direction; and A display device comprising a third portion extending in the first direction and connecting the first portion and the second portion.

5. In paragraph 4, A display device, wherein the distance between the side surface facing the data line of the first part of the shielding portion and the data line is smaller than the distance between the conductive pattern and the data line.

6. In paragraph 4, A display device, wherein the shielding portion is spaced apart from the channel region of the first semiconductor layer on a plane.

7. In paragraph 4, A display device in which the channel region of the first semiconductor layer on a plane is disposed between the first part and the second part of the shielding portion and is spaced apart from the third part of the shielding portion.

8. In paragraph 1, A display device in which the shielding portion overlaps the entire channel region of the first semiconductor layer.

9. A substrate including a display area including a first subpixel circuit of an adjacent first subpixel and a second subpixel circuit of a second subpixel, and a peripheral area disposed outside the display area; A driving voltage line that transmits a driving voltage and extends in a first direction on the substrate and passes through a first subpixel circuit region including the first subpixel circuit and a second subpixel circuit region including the second subpixel circuit; A first conductive pattern disposed on the driving voltage line in the first subpixel circuit area and overlapping at least a portion of the driving voltage line; A second conductive pattern disposed on the driving voltage line in the second subpixel circuit area and overlapping at least a portion of the driving voltage line; A first driving transistor including a first semiconductor layer disposed on the first conductive pattern, electrically connected to the first conductive pattern, and including a first channel region, and a first gate electrode disposed on the first semiconductor layer and overlapping the first channel region, and disposed in the first subpixel circuit region; A second driving transistor including a second semiconductor layer disposed on the second conductive pattern, electrically connected to the second conductive pattern, and including a second channel region, and a second gate electrode disposed on the second semiconductor layer and overlapping the second channel region, and disposed in the second subpixel circuit region; A first data line extending in a second direction perpendicular to the first direction and transmitting a data voltage to the first subpixel circuit; and A second data line extending in the second direction and transmitting a data voltage to the second subpixel circuit is included. The driving voltage line is arranged in the first subpixel circuit area and includes a first shielding portion including a first side facing the first data line on a plane and a second side facing the second data line, On a plane, the distance between the first side of the first shielding portion and the first data line is smaller than the distance between the first conductive pattern and the first data line, A display device, wherein the first shielding portion is spaced apart from the first channel region of the first semiconductor layer on a plane.

10. In paragraph 9, A display device, wherein the distance between the second side of the first shielding portion and the second data line is smaller than the distance between the first conductive pattern and the second data line.

11. In paragraph 9, A display device, wherein the driving voltage line further includes a second shielding portion that is arranged in the second subpixel circuit area and includes a third side surface facing the second data line on a plane, and a connecting portion that connects the first shielding portion and the second shielding portion.

12. In paragraph 11, A display device in which the third side of the second shielding portion has a distance between the second data lines smaller than the distance between the second conductive pattern and the second data lines.

13. In paragraph 11, A portion of the above second data line overlaps the above connecting portion, A display device in which the second shielding portion overlaps the entire second channel region of the second semiconductor layer.

14. In paragraph 9, A display device, wherein the first shielding portion includes a first portion extending in the second direction and including a side facing the first data line, a second portion extending in the second direction and spaced apart from the first portion in the first direction and including a side facing the second data line, and a third portion extending in the first direction and connecting the first portion and the second portion.

15. In paragraph 14, A display device in which the first channel region of the first semiconductor layer on a plane is disposed between the first portion and the second portion of the first shielding portion and is spaced apart from the third portion of the first shielding portion.

16. In paragraph 9, Further comprising a first capacitor including a first electrode and a second lower electrode overlapping the first electrode, The first electrode and the first gate electrode are provided integrally with each other, A display device, wherein the second lower electrode is included in the first conductive pattern.

17. In paragraph 16, A display device, wherein the first capacitor further includes a second upper electrode disposed on the first electrode and electrically connected to the second lower electrode.

18. In paragraph 9, Further comprising a second capacitor including a third electrode and a fourth electrode overlapping the third electrode, The third electrode is included in the first shielding portion, A display device, wherein the fourth electrode is included in the first conductive pattern.

19. Display device; and comprising a housing accommodating the display device; The above display device, A substrate comprising a display area including a plurality of pixels and a non-display area disposed outside the display area; A driving voltage line extending in a first direction on the above substrate and transmitting a driving voltage; A conductive pattern disposed on the driving voltage line and overlapping at least a portion of the driving voltage line; A driving transistor including a first semiconductor layer disposed on the conductive pattern, electrically connected to the conductive pattern, and including a channel region, and a first gate electrode disposed on the first semiconductor layer and overlapping the channel region; and Including a data line extending in a second direction perpendicular to the first direction, The above driving voltage line includes a shielding portion including a side facing the data line on a plane, An electronic device, wherein the distance between the side surface of the shield and the data line on a plane is smaller than the distance between the conductive pattern and the data line.

20. In paragraph 19, Including more processors, The display device further includes a controller that receives a control signal from the processor and outputs a power control signal based on the control signal, and a power supply circuit that generates the driving voltage based on the power control signal of the controller. An electronic device in which the above driving voltage line is electrically connected to the power supply circuit and receives the driving voltage.

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