Diode-based radio frequency (RF) matching network with multilevel plasma impedance matching

Abstract

Aspects provided herein generally include apparatus, plasma processing systems and methods for tuning in a radio frequency (RF) plasma processing system for improving substrate processing metrics. Some aspects are directed to an apparatus for processing a substrate in a plasma processing system. The apparatus generally includes: an RF signal generator; a first matching network; a second matching network; a first diode coupled between the RF signal generator and the first matching network; a second diode coupled between the RF signal generator and the second matching network; and a driver having a first output coupled to the first diode and a second output coupled to the second diode.

Description

DIODE-BASED RADIO FREQUENCY (RF) MATCHING NETWORK WITH MULTILEVEL PLASMA IMPEDANCE MATCHINGBACKGROUNDField

[0001] Aspects of the present disclosure generally relate to a system and methods used in semiconductor device manufacturing. More specifically, aspects of the present disclosure relate to a plasma processing system used to process a substrate.Description of the Related Art

[0002] Reliably producing high aspect ratio features is one of the key technology challenges for the next generation of semiconductor devices. One method of forming high aspect ratio features uses a plasma assisted etching process, such as a reactive ion etch (RIE) plasma process, to form high aspect ratio openings in a material layer, such as a dielectric layer, of a substrate. In a typical RIE plasma process, a plasma is formed in a processing chamber and ions from the plasma are accelerated towards a surface of a substrate to form openings in a material layer disposed beneath a mask layer formed on the surface of the substrate.

[0003] A typical RIE plasma processing chamber includes a radio frequency (RF) bias generator, which supplies an RF voltage to a power electrode. In a capacitive coupled gas discharge, the plasma is created by using an RF generator that is coupled to the power electrode that is disposed within an electrostatic chuck (ESC) assembly or within another portion of the processing chamber. Typically, an RF matching network (“RF match”) tunes an RF waveform provided from the RF generator to deliver RF power to an apparent load of 50Q to minimize the reflected power and maximize the power delivery efficiency. If an impedance of the load is not properly matched to an impedance of a source (e.g., the RF generator), a portion of the forward delivered RF waveform can reflect back in an opposite direction along a same transmission line.

[0004] Therefore, there is a need for an apparatus and method for processing a substrate in a plasma processing system that solves the problems described above.SUMMARY

[0005] Aspects provided herein generally include apparatus, plasma processing systems and methods for tuning in a radio frequency (RF) plasma processing system for improving substrate processing metrics.

[0006] Some aspects provide an apparatus for processing a substrate in a plasma processing system. The apparatus generally includes: a radio frequency (RF) signal generator comprising an output; a first matching network comprising an input and an output which is configured to be coupled to a load; a second matching network comprising an input and an output which is configured to be coupled to the load; a first diode coupled between the output of the RF signal generator and the input of the first matching network; a second diode coupled between the output of the RF signal generator and the input of the second matching network; and a driver having a first output coupled to a terminal of the first diode and a second output coupled to a terminal of the second diode.

[0007] Some aspects provide a method for processing a substrate in a plasma processing system. The method generally includes: providing a first bias signal to a first diode coupled between an RF signal generator and a first matching network; providing a second bias signal to a second diode coupled between the RF signal generator and a second matching network; and generating an RF signal via the RF signal generator to be provided to the first matching network or the second matching network through the first diode or the second diode in accordance with the first bias signal and the second bias signal.

[0008] Some aspects provide a plasma processing system. The plasma processing system generally includes: a plasma chamber; an RF signal generator comprising an output; a first matching network comprising an input and an output coupled to the plasma chamber; a second matching network comprising an input and an output coupled to the plasma chamber; a first diode coupled between the output of the RF signal generator and the input of the first matching network; a second diode coupled between the RF signal generator and the second matching network; and a driver having a first output coupled to a terminal of the first diode and a second output coupled to a terminal of the second diode.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary aspects and are therefore not to be considered limiting of its scope, and may admit to other equally effective aspects.

[0010] Figure 1 A is a schematic representation of a plasma processing system, in accordance with certain aspects of the present disclosure.

[0011] Figure 1 B is a schematic detailed cross-sectional view of the plasma processing system, in accordance with certain aspects of the present disclosure.

[0012] Figure 2 shows a voltage waveform that is established on a substrate due to a voltage waveform applied to an electrode of a processing chamber, in accordance with certain aspects of the present disclosure.

[0013] Figures 3-5 illustrate switch control circuitry used to selectively reverse and forward bias PIN diodes for directing signals to different matching networks, in accordance with certain aspects of the present disclosure.

[0014] Figure 6 illustrates switch control circuitry used to selectively reverse and forward bias PIN diodes for directing signals to different matching networks, in accordance with certain aspects of the present disclosure.

[0015] Figure 7 is a process flow diagram illustrating a method for processing a substrate in a plasma processing system, in accordance with certain aspects of the present disclosure.

[0016] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other aspects without further recitation.DETAILED DESCRIPTION

[0017] Aspects of the present disclosure generally relate to a system used in a semiconductor device manufacturing process. More specifically, aspects provided herein generally include apparatus and methods for adjusting a matching impedance using a diode-based switch. For example, switches may be implemented using PIN diodes to selectively provide an RF signal to a chamber through one or multiple matching networks. While some examples provided herein are described with respect to two matching networks, certain aspects of the present disclosure may be implemented with any number of matching networks. If a PIN diode is reverse-biased, the diode provides high impedance for a radio frequency (RF) signal, thereby blocking the RF signal. When forward-biased, the PIN diode allows the RF signal to pass through as the diode acts as a shorted path under the influence of forward bias. In certain aspects, one or more PIN diodes may be configured as a switch that may be controlled via forward and reverse bias signals to adjust a matching impedance for a plasma load.Plasma Processing System Examples

[0018] Figure 1A is a schematic representation of a plasma processing system. The plasma processing system 10 is configured for plasma-assisted etching processes, such as a reactive ion etch (RIE) plasma processing. The plasma processing system 10 can also be used in other plasma-assisted processes, such as plasma-enhanced deposition processes (for example, plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processing, plasma-based ion implant processing, or plasma doping (PLAD) processing. In one configuration, as shown in Figure 1A, the plasma processing system 10 is configured to form a capacitive coupled plasma (CPP). However, in some aspects, a plasma may alternately be generated by an inductively coupled source disposed over a processing region of the plasma processing system 10.

[0019] The plasma processing system 10 includes a processing chamber 100, a substrate support assembly 136, a gas delivery system 182, a high DC voltage supply 173, a radio frequency (RF) generator 171 , and an RF match 172 (e.g. , RF impedancematching network). A chamber lid 123 includes one or more sidewalls and a chamber base that are configured to withstand the pressures and energy applied to them while a plasma 101 is generated within a vacuum environment maintained in a processing volume 129 of the processing chamber 100 during processing.

[0020] The gas delivery system 182, which is coupled to the processing volume 129 of the processing chamber 100 is configured to deliver at least one processing gas from at least one gas processing source 119 to the processing volume 129 of the processing chamber 100. The gas delivery system 182 includes the processing gas source 119 and one or more gas inlets 128 positioned through the chamber lid 123. The gas inlets 128 are configured to deliver one or more processing gasses to the processing volume 129 of the processing chamber 100.

[0021] The processing chamber 100 includes an upper electrode (e.g., the chamber lid 123) and a lower electrode (e.g., the substrate support assembly 136) positioned in the processing volume 129 of the processing chamber 100. The upper and lower electrodes face one another. In one embodiment, the RF generator 171 is electrically coupled to the lower electrode. The RF generator 171 is configured to deliver an RF signal to ignite and maintain the plasma 101 between the upper and lower electrodes. In some alternative configurations, the RF generator 171 can also be electrically coupled to the upper electrode. For example, the RF generator 171 may deliver an RF source power to an RF baseplate within a cathode assembly (e.g., in the substrate support assembly 136) for plasma production, whereas the upper electrode is grounded. A center frequency of the RF source power can be from 13.56 MHz to very high frequency band such as 40 MHz, 60 MHz, 120 MHz or 162 MHz. In some examples, the RF source power can also be delivered through the upper electrode. The RF source power can be operated in a continuous mode or a pulsed mode. A pulsing frequency of the RF power can be from 100 to 10kHz, and duty cycles are ranging from 5% to 95%. The RF generator 171 has a frequency tuning capability and can adjust its RF power frequency within e.g., ±5% or ±10%. In some aspects, the RF generator 171 switches the RF power frequency at a predefined speed (e.g., two nanoseconds, fifty nanoseconds, etc.).

[0022] Referring to Figure 1A and also Figure 1 B, which is a more detailed schematic cross-sectional view of the plasma processing system. The substratesupport assembly 136 may be coupled to a high voltage DC supply 173 that supplies a chucking voltage thereto. The high voltage DC supply 173 may be coupled to a filter assembly 178 that is disposed between the high DC voltage supply 173 and the substrate support assembly 136.

[0023] The filter assembly 178 is configured to electronically isolate the high voltage DC supply 173 during plasma processing. In one configuration, a static DV voltage is between about -5000V and about 5000V, and is delivered using an electrical conductor (such as a coaxial power delivery line). The filter assembly 178 may include multiple filtering components or a single common filter.

[0024] The substrate support assembly 136 is coupled to a pulsed voltage (PV) waveform generator 175 configured to supply a PV to bias the substrate support assembly 136. The PV waveform generator 175 is coupled to the filter assembly 178. The filter assembly 178 is disposed between the PV waveform generator 175 and the substrate support assembly 136. The filter assembly 178 is configured to electronically isolate the PV waveform generator 175 during plasma processing.

[0025] The substrate support assembly 136 is coupled to the RF generator 171 configured to deliver an RF signal to the processing volume 129 of the processing chamber 100. The RF generator 171 is electronically coupled to one of the RF matching circuit M1 and M2 disposed between the RF generator 171 and the processing volume 129 of the processing chamber 100. For example, the RF matching circuit is an electrical circuit used between the RF generator 171 and a plasma reactor (e.g., the processing volume 129 of the processing chamber 100) to optimize power delivery efficiency. One or more RF filters are designed to only allow RF powers in a selected frequency range to pass, and to isolate RF power supplies from each other. In some cases, a bandwidth of an RF filter has to be larger than a frequency tuning range of the RF generator 171 .

[0026] During the plasma processing, the RF generator 171 delivers an RF signal to the substrate support assembly 136 via one of the RF matching circuits M1 and M2. For example, the RF signal is applied to a load (e.g., gas) in the processing volume 129 of the processing chamber 100. If an impedance of the load is not properly matched to an impedance of a source (e.g., the RF generator 171 ), a portionof a waveform can reflect back in an opposite direction. Accordingly, to prevent a substantial portion of the waveform from reflecting back, some implementations find a match impedance (e.g., a matching point) by adjusting one or more components of an RF matching circuit as the source and load impedances change. In some embodiments of the present disclosure, the RF power may be provided to the chamber load through one of multiple matching circuits set to respective impedances, allowing for a more rapid tuning of matching impedance as compared to adjusting an impedance of an RF matching circuit.

[0027] The RF generator 171 and the PV waveform generator 175 are each directly coupled to a system controller 126. The system controller 126 synchronizes the respective generated RF signal and PV waveform.

[0028] Voltage and current sensors can be placed at an input and / or output of the each RF matching circuit to measure impedance and other parameters. These sensors can be synchronized using an external transistor-transistor logic (TTL) synchronization signal from an advanced waveform generator and / or RF generators or using measured voltage and current data to determine timing internally. For example, an output sensor 117 is configured to measure the impedance of the plasma processing chamber 100, and other characteristics such as the voltage, current, harmonics, phase, and / or the like. An input sensor 116 is configured to measure the impedance of the RF generator 171 and other characteristics such as the voltage, current, harmonics, phase, and / or the like. Based on either of the synchronization signals or the characteristics of the plasma processing chamber 100, an RF matching circuit may be able to capture fast impedance changes and optimize impedance matching.

[0029] The PV waveform generator 175 is used to supply a PV waveform and / or a tailored voltage waveform, which is a sum of harmonic frequencies associated with the waveform. The PV waveform generator 175 may output a synchronization TTL signal to each RF matching circuit. The voltage waveform is coupled to a bias electrode (e.g., a bias electrode 104 shown in Figure 1 B) through the filter assembly 178. The high DC voltage supply 173 is applied to chuck a substrate during a process for thermal control of the substrate. In some cases, there can be a third electrode at an edge of the cathode assembly for edge uniformity control.

[0030] Figure 1 B is a schematic detailed cross-sectional view of the plasma processing system 10. As shown in Figure 1 B, the plasma processing system 10 is configured to form a capacitively coupled plasma (CCP). However, in some aspects, the plasma 101 may alternately be generated by an inductively coupled source disposed over the processing region of the plasma processing system 10. In this configuration, a coil may be placed on top of a ceramic lid (e.g., vacuum boundary) of the plasma processing chamber 100.

[0031] The plasma processing system 10 includes the processing chamber 100, the substrate support assembly 136, the gas delivery system 182, a DC power system 183, an RF power system 189, and the system controller 126. The processing chamber 100 includes a chamber body 113 that includes the chamber lid 123, one or more sidewalls 122, and a chamber base 124. The chamber lid 123, the one or more sidewalls 122, and the chamber base 124 collectively define the processing volume 129 of the processing chamber 100. The one or more sidewalls 122 and the chamber base 124 include materials (such as aluminum, aluminum alloys, or stainless steel alloys) that are sized and shaped to form a structural support for elements of the processing chamber 100 and are configured to withstand the pressures and added energy applied to them while the plasma 101 is generated within a vacuum environment maintained in the processing volume 129 of the processing chamber 100 during processing. A substrate 103 is loaded into, and removed from, the processing volume 129 of the processing chamber 100 through an opening (not shown) in one of the sidewalls 122. The opening is sealed with a slit valve (not shown) during plasma processing of the substrate 103.

[0032] The gas delivery system 182, which is coupled to the processing volume 129 of the processing chamber 100, includes the processing gas source 119 and the gas inlet 128 disposed through the chamber lid 123. The gas inlet 128 is configured to deliver one or more processing gases to the processing volume 129 of the processing chamber 100 from the processing gas source 119. In some embodiments, the chamber lid 123 can include a showerhead that is configured to provide gases to the processing volume 129 in which the plasma 101 is formed.

[0033] As noted above, the processing chamber 100 includes the upper electrode (e.g., the chamber lid 123) and the lower electrode (e.g., the substrate supportassembly 136) disposed in the processing volume 129 of the processing chamber 100. The upper electrode and lower electrode are positioned to face each other. As seen in Figure 1 B, the RF generator 171 is electrically coupled to the lower electrode. The RF generator 171 is configured to deliver an RF signal to ignite and maintain the plasma 101 between the upper and lower electrodes. In some alternative configurations, the RF generator 171 can also be electrically coupled to the upper electrode.

[0034] The substrate support assembly 136 includes a substrate support 105, a substrate support base 107, an insulator plate 111 , a ground plate 112, a plurality of lift pins 186, one or more substrate potential sensing assemblies 184 (e.g., including a signal detecting assembly 188), and a bias electrode 104. Each of the lift pins 186 are disposed through a through hole 185 formed in the substrate support assembly 136 and are used to facilitate the transfer of the substrate 103 to and from a substrate receiving surface 105A of the substrate support 105. The substrate support 105 is formed of a dielectric material. The dielectric material can include a bulk sintered ceramic material, a corrosion-resistant metal oxide (for example, aluminum oxide (AI2O3), titanium oxide (TiO), yttrium oxide (Y2O3), a metal nitride material (for example, aluminum nitride (AIN), titanium nitride (TiN)), mixtures thereof, or combinations thereof.

[0035] The substrate support base 107 is formed of a conductive material (for example aluminum, an aluminum alloy, or a stainless steel alloy). The substrate support base 107 is electrically isolated from the chamber base 124 by the insulator plate 111 , and the ground plate 112 interposed between the insulator plate 111 and the chamber base 124. The substrate support base 107 is configured to regulate the temperature of both the substrate support 105, and the substrate 103 disposed on the substrate support 105 during substrate processing. The substrate support base 107 includes one or more cooling channels (not shown) disposed therein that are fluidly coupled to, and in fluid communication with, a coolant source (not shown), such as a refrigerant source or substrate source having a relatively high electrical resistance. The substrate support 105 includes a heater (not shown) to heat the substrate support 105 and the substrate 103 disposed on the substrate support 105.

[0036] The bias electrode 104 is embedded in a dielectric material of the substrate support 105. The bias electrode 104 is formed of one or more electrically conductive parts. The electrically conductive parts include meshes, foils, plates, or combinations thereof. The bias electrode 104 functions as a chucking pole (i.e., electrostatic chucking electrode) that is used to secure (e.g., electrostatically chuck) the substrate 103 to the substrate receiving surface 105A of the substrate support 105. A parallel plate like structure is formed by the bias electrode 104 and a layer of the dielectric material that is disposed between the bias electrode 104 and the substrate receiving surface 105A. The dielectric material can have an effective capacitance CE of between about 5 nF and about 50 nF. A layer of the dielectric material (e.g., aluminum nitride (AIN), aluminum oxide (AI2O3), etc.) has a thickness between about 0.3 mm and about 5 mm, such as between about 0.1 mm and about 3 mm, such as between about 0.1 mm and about 1 mm, or even between about 0.1 mm and 0.5 mm. The bias electrode 104 is electrically coupled to a clamping network, which provides a chucking voltage thereto. The clamping network includes the DC voltage supply 173 (e.g., a high voltage DC supply) that is coupled to a filter 178A of the filter assembly 178 that is disposed between the DC voltage supply 173 and the bias electrode 104. The filter 178A is a low-pass filter that is configured to block RF frequency and PV waveform signals provided by other biasing components found within the processing chamber 100 from reaching the DC voltage supply 173 during the plasma processing. The static DV voltage is between about -5000V and about 5000V, and is delivered using an electrical conductor (such as a coaxial power delivery line 106). The bias electrode 104 may bias the substrate 103 with the respect to the plasma 101 using one or more of the PV biasing schemes.

[0037] The substrate support assembly 136 includes an edge control electrode 115. The edge control electrode 115 is formed of one or more electrically conductive parts. The electrically conductive parts include meshes, foils, plates, or combinations thereof. The edge control electrode 115 is positioned below an edge ring 114 and surrounds the bias electrode 104 and / or is disposed a distance from a center of the bias electrode 104. For the processing chamber 100 that is configured to process circular substrates, the edge control electrode 115 is annular in shape, is made from a conductive material, and is configured to surround at least a portion of the bias electrode 104. As seen in Figure 1 B, the edge control electrode 115 is positionedwithin a region of the substrate support 105, and is biased by use of the PV waveform generator 175. The edge control electrode 115 is biased by use of a PV waveform generator that is different from the PV waveform generator 175 used for the bias electrode 104. The edge control electrode 115 is biased by splitting part of a signal provided from the PV waveform generator 175 to the bias electrode 104.

[0038] The RF power system 189 includes an RF waveform generator 171. As shown in Figure 1 B, two paths labeled “Path 1” and “Path 2” may be used to electrically connect an output of the RF generator 171 to inputs of respective RF matching circuits (e.g., matching networks) labeled “M1” and “M2”. The outputs of the RF matching circuit M1 and M2 may be coupled to an RF filter 174 and the substrate support base 107. As described in more detail herein, Path 1 and Path 2 may be implemented using diode-based switches to selectively delivery power to the chamber through one of the RF matching circuits, allowing for rapid switching of the RF matching impedance. As noted above, during the plasma processing, the DC voltage supply 173 provides a constant chucking voltage, while the RF generator 171 delivers the RF signal to the processing region, and the PV waveform generator 175 establishes the PV waveform at the bias electrode 104. For example, a sufficient amount of the RF power is applied to an RF bias voltage signal (which is also referred to herein as the RF waveform), and the RF waveform is provided to an electrode (e.g., the substrate support base 107) to cause the plasma 101 to be formed in the processing volume 129 of the processing chamber 100. The RF waveform has a frequency range between about 1 MHz and about 200 MHz, such as between 2 MHz and 40 MHz.

[0039] The DC power system 183 includes the DC voltage supply 173, the PV waveform generator 175, and a current source 177. The DC power system 183 includes the filter assembly 178 to electrically isolate one or more of the components contained within the DC power system 183. A power delivery line 160 electrically connects an output of the DC voltage supply 173 to the filter assembly 178. A power delivery line 161 electrically connects the output of the PV waveform generator 175 to the filter assembly 178. A power delivery line 162 connects the output of the current source 177 to the filter assembly 178.

[0040] The current source 177 is selectively coupled to the bias electrode 104 by use of a switch (not shown) disposed in the power delivery line 162, to allow the current source 177 to deliver a desired current to the bias electrode 104 during one or more stages (e.g., ion current stage) of the voltage waveform generated by the PV waveform generator 175.

[0041] The filter assembly 178 includes multiple separate filtering components (i.e., discrete filters 178A-178C) that are each electrically coupled to an output node via a power delivery line 164. The filter assembly 178 may include one common filter electrically coupled to the output node via the power delivery line 164. The power delivery lines 160-164 include electrical conductors that include a combination of coaxial cables, such as a flexible coaxial cable that is connected in series with a rigid coaxial cable, an insulated high-voltage corona-resistant hookup wire, a bare wire, a metal rod, an electrical connector, of any combination of the above.

[0042] The system controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 133, a memory 134, and support circuits 135. The system controller 126 is used to control a process sequence used to process the substrate 103. The CPU is a computer processor configured for use in an industrial setting for controlling the processing chamber and sub-processors related thereto. The memory 134 described herein, which is generally non-volatile memory, can include random access memory, read-inly memory, hard disk drive, or other suitable forms of digital storage, local or remote. The support circuits 135 are coupled to the CPU 133 and include cache, clock circuits, input / output subsystems, power supplied, and the like, and combinations thereof. Software instructions (program) and data can be coded and stored within the memory 134 for instructing a processor within the CPU 133. A software program (or computer instructions) readable by the CPU 133 in the system controller 126 determines which tasks are performable by the components in the plasma processing system 10.

[0043] The program, which is readable by the CPU 133 in the system controller 126 includes code, which, when executed by the CPU 133, performs tasks relating to the plasma processing schemes described herein. The program may include instructions that are used to control the various hardware and electrical components within the plasma processing system 10 to perform the various process tasks andvarious process sequences used to implement the methods described herein. The program includes instructions that are used to perform one or more of the operations described herein.

[0044] Figure 2 illustrates two separate voltage waveforms established at the substrate 103 disposed on the substrate receiving surface 105A of the substrate support assembly 136 of the processing chamber 100 due to the delivery of PV waveforms to the bias electrode 104 of the processing chamber 100 by use of the PV waveform generator 175. A first waveform (e.g., a waveform 225) is an example of a non-compensated PV waveform established at the substrate 103 during the plasma processing. A second waveform (e.g., a waveform 230) is an example of a compensated PV waveform established at the substrate 103 by applying a negative slope waveform to the bias electrode 104 of the processing chamber 100 during an “ion current stage” portion of the PV waveform cycle by use of the current source 177. The compensated PV waveform can alternatively be established by applying a negative voltage ramp during the ion current stage of the PV waveform generated by the PV waveform generator 175. The PV waveform cycle of the waveforms 225, 230 each have a period TP, which is, for example, typically between 2 microsecond (ps) and 10 ps, such as 2.5 ps. The ion current stage of the PV waveform cycle will typically take up between about 50% and about 95% of the period TP, such as from about 80% to about 90% of the period TP.

[0045] The waveforms 225 and 230 include two main stages: an ion current stage and a sheath collapse stage. Both portions (e.g., the ion current stage and the sheath collapse stage) of the waveforms 225 and 230, can be alternately and / or separately established at the substrate 103 during the plasma processing. At a beginning of the ion current stage, a drop in the voltage at the substrate 103 is created, due to the delivery of a negative portion of the PV waveform (e.g., the ion current portion) provided to the bias electrode 104 by the PV waveform generator 175, which creates a high voltage sheath above the substrate 103. The high voltage sheath allows the plasma generated positive ions to be accelerated towards the biased substrate 103 during the ion current stage, and thus, for RIE processes, controls the amount and characteristics of the etching process that occurs on the surface of the substrate 103 during the plasma processing. In some aspects, it is desirable for the ion currentstage to include a region of the PV waveform that achieves the voltage at the substrate 103 that is stable or minimally varying throughout the stage, as illustrated in Figure 2 by the waveform 230. One will note that significant variations in the voltage established at the substrate 103 during the ion current stage, such as shown by the positive slope in the waveform 225, will undesirably cause a variation in the ion energy distribution (IED) and thus cause undesirable characteristics of the etched features to be formed in the substrate 103 during the RIE process.

[0046] Silicon Carbide (SiC)-based Schottky diodes exhibit low junction capacitance (e.g., in the order of tens of picofarads) when reverse-biased to a certain extent. If such a reverse-biased Schottky diode stack with low junction capacitance is placed in the path of an RF signal (e.g., having a frequency of 13.56 MHz), the diode provides high impedance for the RF signal, thereby blocking the RF signal. On the flip side, when forward-biased, the same Schottky diode stack allows the RF signal to pass through as the diode acts as a shorted path under the influence of forward bias. Therefore, the Schottky diode can act as an RF switch (RFS) by virtue of a circuit that can switch between the forward bias and the reverse bias states at the PV waveform frequency. This scheme allows a user to change the overall impedance of a matching network at a higher frequency than conventional implementations by turning on and off the RF switch using a reverse and forward bias. Traditional matching networks may be unable to tune at such high frequencies.Impedance Controlling Circuitry and System

[0047] Certain aspects of the present disclosure are directed towards a PIN diodebased radio frequency (RF) switch. Some aspects provide matching techniques that may be applied for macro-state pulsing of an RF source. The PIN-diode-based RF switch described herein provides increased tuning speed for matching networks corresponding to multi-state macro pulsing.

[0048] A PIN diode may be used to provide increased switching speed capability (e.g., in the range of tens of kHz) compared to traditional matching networks. When PIN diodes are reverse-biased, they exhibit low junction capacitance, thereby providing RF signal isolation, and when forward-biased, they exhibit a low-resistance path for the RF signal. Properly designed bias tee networks can allow adequateisolation between the DC bias network and RF signal generator for proper operation, as described in more detail herein. Multiple PIN diodes can be paralleled to increase the RF power handling capability. Moreover, by integrating a single-pole double-throw (SPDT) or single-pole four-throw (SP4T) PIN diode driver, two to four independent RF signal paths can be established, each corresponding to an independent passive matching network for faster matching to different macro pulse RF power states. While some examples are described with two matching networks to facilitate understanding, certain aspects of the present disclosure may be implemented with any number of matching networks.

[0049] Figures 3-5 illustrate switch control circuitry 300 used to selectively reverse and forward bias PIN diodes for directing signals to a chamber load through different matching networks, in accordance with certain aspects of the present disclosure. As shown, the circuitry 300 may include a first RF signal path (labeled “RF signal path- 1”) and a second RF signal path (labeled “RF signal path-2”). A PIN diode driver 316 may be used to bias the PIN diodes of the first and second RF signal paths. For example, RF signal path-1 may include a PIN diode D1 having a first terminal (e.g., an anode) coupled to an RF generator 302 (e.g., corresponding to the RF generator 171 ) through a direct-current (DC) blocking circuit 304 and a second terminal (e.g., a cathode) coupled to a first matching network (labeled “MN-1”). The switch control circuitry 300 may be part of Path 1 and Path 2 described with respect to Figure 1 B and used to control the routing of an RF signal from an RF generator 302 to a load. The first matching network may be any suitable matching network implemented with impedances for impedance matching. For example, the first matching network may be implemented using one or more capacitive elements and / or one or more inductive elements in any suitable configuration, such as an L-shaped network or a iT-shaped network. In one example, the first matching network is an L-shaped network that comprises at least one variable capacitive element that can be adjusted, set and fixed to a desired shunt capacitance setting in combination with at least one series inductive element to achieve a desired impedance during a first known portion of a plasma processing recipe to maximize the forward RF power delivery to a complex load 312 (i.e. , plasma) and minimize the amount of reflected power provided from the complex load 312.

[0050] The DC blocking circuit 304 blocks DC signals (e.g., used for diode biasing) to flow to the RF generator 302. As used herein, any reference to blocking a signal (e.g., blocking a DC or RF signal) generally refers to blocking at least a portion of the signal. The RF signal path-1 may also include a PIN diode D3 having a first terminal (e.g., an anode) coupled to the cathode of PIN diode D1 , where a second terminal (e.g., a cathode) of PIN diode D3 is coupled to a reference potential node (e.g., electric ground) through a capacitive element 332, as shown. The PIN diode driver 316 may have PIN diode control outputs coupled to the cathodes of PIN diodes D1 and D3 through an RF blocking circuit 314. The PIN diode control outputs may be used to forward-bias (or reverse-bias) the PIN diode D1 and reverse-bias (or forward-bias) the PIN diode D3, to allow the flow (or block) the RF signal from the RF generator to MN- 1 and to an electrode (e.g., chamber lid 123 or substrate support base 107) and a complex load 312 (e.g., plasma 101 ), which is coupled to the output of matching network MN-1 .

[0051] Similarly, RF signal path-2 may include a PIN diode D2 having an anode coupled to the RF generator 302 through the DC blocking circuit 304 and a cathode coupled to a second matching network (labeled “MN-2”). The second matching network may be any suitable matching network implemented with impedances for impedance matching. For example, the matching network may be implemented using one or more capacitive elements and / or one or more inductive elements in any suitable configuration such as an L-shaped network or a iT-shaped network. In one example, as similarly described above, the second matching network can be an L- shaped network that comprises at least one variable capacitive element that can be adjusted, set and fixed to a desired shunt capacitance setting in combination with at least one series inductive element to achieve a desired impedance during a second known portion of a plasma processing recipe to maximize the forward RF power delivery to the complex load 312 (i.e., plasma) and minimize the amount of reflected power provided from the complex load 312.

[0052] The RF signal path-2 may also include a PIN diode D4 having a first terminal (e.g., an anode) coupled to the cathode of PIN diode D2, where a second terminal (e.g., a cathode) of PIN diode D4 is coupled to the reference potential node (e.g., electric ground) through a capacitive element 330, as shown. The PIN diodedriver 316 may have PIN diode control outputs coupled to the cathodes of PIN diodes D2 and D4 through an RF blocking circuit 324. The second PIN diode control outputs may be used to forward-bias (or reverse-bias) the PIN diode D2 and reverse-bias (or forward-bias) the PIN diode D4, to allow the flow (or block) the RF signal from the RF generator to MN-2 and to the electrode (e.g., chamber lid 123 or substrate support base 107) and the complex load 312 (e.g., generated plasma), which is coupled to the output of matching network MN-2.

[0053] The PIN diode driver may bias the PIN diodes based on one or more signals 328 (e.g., one or more transistor-transistor logic (TTL) signals) representing a macropulsing scheme that is provided from a signal source 328 based on commands sent from the system controller 126. For example, the RF power provided to the chamber may be adjusted in accordance with a recipe for substrate processing that is executed by the system controller 126. Based on the signal from the signal source 328, the driver 316 may bias the PIN diodes of the RF signal paths to either direct the supplied RF current from the RF generator 302 to a complex load 312 through the first matching network MN-1 or to the complex load 312 through the second matching network MN- 2. In other words, when the complex load 312 is in a first state (state-1 ) the RF generator 302 is providing a first RF power level (labeled “RF power level-1 ), the RF signal path-1 may be biased to direct current through matching network MN-1 as shown in Figure 4. When the load 312 is in a second state (state-2) and the RF generator 302 is providing a second RF power level (labeled “RF power level-2”), the RF signal path-2 may be biased to direct current through matching network MN-2 as shown in Figure 5. In other words, when the load is in state-1 and RF power level-1 is being provided, the load may have a first impedance that may be matched via matching network MN-1 to reduce reflections, and when the load is in state-2 and RF power level-2 is being provided, the load may have a second impedance that may be matched via matching network MN-2 to reduce reflections.

[0054] Figure 6 illustrates example switch control circuitry 600 used to selectively reverse and forward bias PIN diodes for directing signals to different matching networks, in accordance with certain aspects of the present disclosure. As shown, the driver 316 may be coupled to the cathode of diode D1 to provide a bias signal (labeled “series 1”) through an inductive element L4 in order to bias the diode D1 . Theinductive element L4 may implement RF blocking. That is, the inductive element L4 may form at least part of the RF block circuit 314. Similarly, the driver 316 may be coupled to the cathode of diode D3 to provide a bias signal (e.g., labeled “shunt 1”) through an inductive element L8 for RF blocking. The inductive element L8 may form at least part of the RF block circuit 314. The capacitive element C11 may correspond to the capacitive element 322 of Figure 3. The capacitive elements C7 and C9 may block DC signals to matching network MN-1 and anode of diode D3, respectively.

[0055] Similarly, the driver 316 may be coupled to the cathode of diode D2 to provide a bias signal (labeled “series 2”) through an inductive element L3 in order to bias the diode D2. The inductive element L3 may implement RF blocking. That is, the inductive element L3 may form at least part of the RF block circuit 324. Similarly, the driver 316 may be coupled to the cathode of diode D4 providing a bias signal (labeled “shunt 2”) through an inductive element L5 for RF blocking. The inductive element L5 may form at least part of the RF block circuit 324. The capacitive element C12 may correspond to the capacitive element 330 of Figure 3. The capacitive element C6 may implement DC blocking to prevent DC signals from flowing back to the RF generator. For example, the capacitive element C6 may form part of the DC blocking circuit 304.

[0056] In some aspects, the driver may receive respective TTL signals (labeled “TTL signal 1 ” and “TTL signal 2”) for biasing the RF signal paths. For example, when the TTL signal 1 is logic high and TTL signal 2 is logic low, the series 1 signal may be a high voltage to reverse bias the PIN diode D1 , the shunt 1 signal may be a low voltage to forward bias the PIN diode D3, the series 2 signal may be a low voltage to forward bias the PIN diode D2, the shunt 2 signal may be a high voltage to reverse bias the PIN diode D4. The low voltage may be any suitable voltage to forward bias a PIN diode that may be less than the high voltage. The high voltage may be any suitable voltage to reverse bias the PIN diode that may be more than the low voltage. Thus, the PIN diode D1 may effectively act as an open switch preventing the RF signal flow to the load through matching network MN-1 and the PIN diode D3 may effectively act as a closed switch grounding the cathode of the PIN diode D1 through the AC- coupling capacitive elements C9, C11. The PIN diode D2 may effectively act as aclosed switch allowing the RF signal flow to the load through matching network MN-2 and the PIN diode D4 may effectively act as an open switch.

[0057] When the TTL signal 1 is logic low and TTL signal 2 is logic high, the series 1 signal may be a low voltage to forward bias the PIN diode D1 , the shunt 1 signal may be a high voltage to reverse bias the PIN diode D3, the series 2 signal may be a high voltage to reverse bias the PIN diode D2, the shunt 2 signal may be a low voltage to forward bias the PIN diode D4. Thus, the PIN diode D1 may effectively act as a closed switch allowing the RF signal flow to the load through matching network MN-1 and the PIN diode D3 may effectively act as an open switch. The PIN diode D2 may effectively act as an open switch preventing the RF signal flow to the load through matching network MN-2 and the PIN diode D4 may effectively act as a closed switch grounding the cathode of PIN diode D2 through AC-coupling capacitive elements C10, C12.

[0058] Figure 7 is a process flow diagram illustrating a method 700 for processing a substrate in a plasma processing system, in accordance with certain aspects of the present disclosure. The method 700 can be performed by a plasma processing system, such as the plasma processing system which may include the switch control circuitry 300 or the switch control circuitry 600.

[0059] At operation 710, the plasma processing system may provide a first bias signal (e.g., signal labeled series 1 in Figure 6) to a first diode (e.g., diode D1 of Figures 3-6, which may be a PIN diode) coupled between an RF signal generator (e.g., RF signal generator 302) and a first matching network (e.g., matching network MN-1 ). The first matching network may be set and locked to a first impedance. The setting of the impedance of the first matching network can be based on knowledge of complex load impedance achieved during, for example, the prior performance of the same portion of a plasma process recipe.

[0060] At operation 720, the plasma processing system provides a second bias signal (e.g., signal labeled series 2 in Figure 6) to a second diode (e.g., diode D2 which may be a PIN diode) coupled between the RF signal generator and a second matching network. The second matching network may be set to a second impedance different than the first impedance. The setting of the impedance of the secondmatching network can be based on knowledge of complex load impedance achieved during, for example, the prior performance of the same portion of a plasma process recipe. The first bias signal may be provided to a cathode of the first diode, and the second bias signal may be provided to a cathode of the second diode. In some aspects, providing the first bias signal and the second bias signal may include: forward biasing the first diode and reverse biasing the second diode when operating in a first mode, and reverse biasing the first diode and forward biasing the second diode when operating in a second mode. In some aspects, when operating in the first mode, the RF signal may have a first RF power level, and when operating in the second mode, the RF signal may have a second RF power level different than the first RF power level.

[0061] At operation 730, the plasma processing system generates an RF signal via the RF signal generator to be provided to the first matching network or the second matching network through the first diode or the second diode in accordance with the first bias signal and the second bias signal. The RF signal may be used to initiate and maintain a plasma within the chamber. Operation 730 may be performed before or simultaneously with either or both Operations 710 and 720.

[0062] In some aspects, the plasma processing system provides a third bias signal (e.g., labeled shunt 1 in Figure 6) to a third diode (e.g., diode D3) coupled between a cathode of the first diode and a reference potential node. The plasma processing system may also provide a fourth bias signal (e.g., labeled shunt 2 in Figure 6) to a fourth diode (e.g., diode D4) coupled to a cathode of the second diode and the reference potential node. By biasing the diodes, the flow of RF power to the complex load may be selectively provided through the first matching network or the second matching network that have been set and fixed to a desired impedance setting, allowing for a more rapid tuning of the matching impedance for the provided RF signal as compared to adjusting the impedance settings (e.g., variable inductance or variable capacitance) within the first matching network or the second matching network.

[0063] Providing the first bias signal, the second bias signal, the third bias signal, and the fourth bias signal may include: forward biasing the first diode (e.g., configuring the first diode as a closed switch), reverse biasing the third diode (e.g., configuring the third diode as an open switch), reverse biasing the second diode (e.g., configuringthe second diode as an open switch), and forward biasing the fourth diode (e.g., configuring the fourth diode as a closed switch), when operating in a first mode; and reverse biasing the first diode (e.g., configuring the first diode as an open switch), forward biasing the third diode (e.g., configuring the third diode as a closed switch), forward biasing the second diode (e.g., configuring the second diode as a closed switch), and reverse biasing the fourth diode (e.g., configuring the fourth diode as an open switch), when operating in a second mode.

[0064] In some aspects, the RF signal may be provided to the first matching network or the second matching network through a DC blocking circuit (e.g., DC blocking circuit 304). The first bias signal may be provided to the first diode through a first RF blocking circuit (e.g., RF blocking circuit 314) and the second bias signal may be provided to the second diode through a second RF blocking circuit (e.g., RF blocking circuit 324).

[0065] While the foregoing is directed to aspects of the present disclosure, other and further aspects of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

WHAT IS CLAIMED IS:

1. An apparatus for processing a substrate in a plasma processing system, comprising: a radio frequency (RF) signal generator comprising an output; a first matching network comprising an input and an output which is configured to be coupled to a load; a second matching network comprising an input and an output which is configured to be coupled to the load; a first diode coupled between the output of the RF signal generator and the input of the first matching network; a second diode coupled between the output of the RF signal generator and the input of the second matching network; and a driver having a first output coupled to a terminal of the first diode and a second output coupled to a terminal of the second diode.

2. The apparatus of claim 1 , wherein at least one of the first diode or the second diode comprises a PIN diode.

3. The apparatus of claim 1 , further comprising: a third diode coupled between the terminal of the first diode and a reference potential node, wherein the terminal of the first diode is a cathode; and a fourth diode coupled the terminal of the second diode and the reference potential node, wherein the terminal of the second diode is a cathode.

4. The apparatus of claim 3, further comprising: a first capacitive element coupled between the terminal of the first diode and the reference potential node; and a second capacitive element coupled between the terminals of the second diode and the reference potential node.

5. The apparatus of claim 3, wherein a third output of the driver is coupled to the third diode, and wherein a fourth output of the driver is coupled to the fourth diode.

6. The apparatus of claim 1 , wherein the first output of the driver is coupled to a cathode of the first diode, and wherein the second output of the driver is coupled to a cathode of the second diode.

7. The apparatus of claim 1 , further comprising a direct-current (DC) blocking circuit coupled between the RF signal generator and the first diode.

8. The apparatus of claim 7, wherein the DC blocking circuit comprises a capacitive element.

9. The apparatus of claim 1 , further comprising: a first radio frequency (RF) blocking circuit coupled between the first output of the driver and the first diode; and a second RF blocking circuit coupled between the second output of the driver and the first diode.

10. The apparatus of claim 9, wherein at least one of the first RF blocking circuit or the second RF blocking circuit comprises an inductive element.

11. A method for processing a substrate in a plasma processing system, comprising: providing a first bias signal to a first diode coupled between a radio frequency (RF) signal generator and a first matching network; providing a second bias signal to a second diode coupled between the RF signal generator and a second matching network; and generating an RF signal via the RF signal generator to be provided to the first matching network or the second matching network through the first diode or the second diode in accordance with the first bias signal and the second bias signal.

12. The method of claim 11 , wherein the first bias signal is provided to a cathode of the first diode, and wherein the second bias signal is provided to a cathode of the second diode.

13. The method of claim 11 , wherein providing the first bias signal and the second bias signal comprises: forward biasing the first diode and reverse biasing the second diode when operating in a first mode; and reverse biasing the first diode and forward biasing the second diode when operating in a second mode.

14. The method of claim 13, wherein: when operating in the first mode, the RF signal has a first RF power level; and when operating in the second mode, the RF signal has a second RF power level different than the first RF power level.

15. The method of claim 11 , wherein at least one of the first diode or the second diode comprises a PIN diode.

16. The method of claim 11 , further comprising: providing a third bias signal to a third diode coupled between a cathode of the first diode and a reference potential node; and providing a fourth bias signal to a fourth diode coupled a cathode of the second diode and the reference potential node.

17. The method of claim 16, wherein providing the first bias signal, the second bias signal, the third bias signal, and the fourth bias signal comprises: forward biasing the first diode, reverse biasing the third diode, reverse biasing the second diode, and forward biasing the fourth diode, when operating in a first mode; and reverse biasing the first diode, forward biasing the third diode, forward biasing the second diode, and reverse biasing the fourth diode, when operating in a second mode.

18. The method of claim 11 , wherein the RF signal is provided to the first matching network or the second matching network through a direct-current (DC) blocking circuit.

19. The method of claim 11 , wherein:the first bias signal is provided to the first diode through a first radio frequency (RF) blocking circuit; and the second bias signal is provided to the second diode through a second RF blocking circuit.

20. A plasma processing system, comprising: a plasma chamber; a radio frequency (RF) signal generator comprising an output; a first matching network comprising an input and an output coupled to the plasma chamber; a second matching network comprising an input and an output coupled to the plasma chamber; a first diode coupled between the output of the RF signal generator and the input of the first matching network; a second diode coupled between the output of the RF signal generator and the input of the second matching network; and a driver having a first output coupled to a terminal of the first diode and a second output coupled to a terminal of the second diode.

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