Systems and methods for controlling quantum devices

Abstract

A quantum processor with a plurality of qubits and a plurality of couplers is discussed, in which each qubit communicatively coupled to at least one other qubit by a coupler. A plurality of digital to analog converters (DACs) are communicatively coupled to provide a control signal to a respective qubit of the plurality of qubits. The plurality of DACs are arranged in two or more subsets of DACs. One or more programmable persistent current sources (PPCSs) are communicatively coupled to a respective subset of the plurality of DACs to provide a bias for programming the DACs.

Description

SYSTEMS AND METHODS FOR CONTROLLING QUANTUM DEVICESCROSS-REFERENCE TO RELATED APPLICATION

[0001] This patent application claims priority of U.S. Patent Application No. 63 / 674,944, filed on July 24, 2024, the entire disclosure of which is hereby incorporated by reference herein for all purposes.FIELD

[0002] This disclosure generally relates to quantum computing, and particularly to the design and operation of devices used for programming and operating other quantum devices.BACKGROUNDQuantum Computation

[0003] A quantum computer is a system that makes direct use of at least one quantum-mechanical phenomenon, such as superposition, tunneling, or entanglement, to perform operations on data. The elements of a quantum computer are qubits. Quantum computers can provide speedup for certain classes of computational problems such as computational problems simulating quantum physics.

[0004] Two types of quantum computation include quantum annealing and circuit or gate model quantum computing. Quantum annealing is a computational method that may be used to find a low-energy state of a system, typically preferably the ground state of the system. Similar in concept to classical simulated annealing, the method relies on the underlying principle that natural systems tend towards lower energy states because lower energy states are more stable. Quantum annealing may use quantum effects, such as quantum tunneling, as a source of delocalization to reach an energy minimum more accurately and / or more quickly than classical annealing.

[0005] The quantum circuit model of computation uses quantum logic gates to form quantum circuits for problem solving. A network of quantum logic gates may be formed to describe a particular computation. One type of quantum circuitmodel quantum computation is referred to as surface code, with logical qubits being simultaneously stored and manipulated as topological defects. In surface code there is no fixed Hamiltonian to restrict the subspace. Instead, each term in the Hamiltonian is treated as a stabilizer and by projective measurements of the stabilizers, the protected subspace is enforced and any leakage from the subspace is detected as an error and corrected.Quantum Components

[0006] Quantum components are structures in which quantum mechanical effects are observable. Quantum components may also be referred to as quantum devices. Quantum components include circuits in which current transport is dominated by quantum mechanical effects. Such components include spintronics, where electronic spin is used as a resource, and superconducting circuits. A superconducting circuit is a circuit that includes a superconducting device. A superconducting device is a device that includes superconducting material. A superconducting material is a material that has no electrical resistance below critical levels of current, magnetic field, and temperature. These critical values, such as the critical temperature, are inherent material properties of a given superconducting material. Both spin and superconductivity are quantum mechanical phenomena. Quantum components can be used for measurement instruments, in computing machinery, and the like.Quantum Processor

[0007] A quantum processor may take the form of a superconducting quantum processor. A superconducting quantum processor may include a number of superconducting qubits and associated components that provide a local bias. A superconducting quantum processor may also include coupling devices (also known as couplers) that selectively provide communicative coupling between qubits.

[0008] Superconducting qubits are solid state qubits based on circuits of superconducting materials. Operation of superconducting qubits is based on the underlying principles of magnetic flux quantization, and Josephson tunneling.Superconducting effects can be present in different configurations and can give rise to different types of superconducting qubits including flux, phase, charge, and hybrid qubits. The different configurations can vary in the topology of the loops, the placement of the Josephson junctions, and the physical parameters of elements of the superconducting circuits, such as inductance, capacitance, and Josephson junction critical current.

[0009] The foregoing examples of the related art and limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.BRIEF SUMMARY

[0010] According to an aspect, there is provided a quantum processor comprising: a plurality of programmable devices, a plurality of digital to analog converters (DACs), each DAC of the plurality of DACs communicatively coupled to transmit a control signal to a respective programmable device of the plurality of programmable devices, the plurality of DACs arranged in two or more subsets of DACs, each subset of DACs comprising at least two DACs, and one or more programmable persistent current sources (PPCSs), each PPCS comprising a current storage loop and a compound Josephson junction (CJJ) interrupting the current storage loop at a first connection and a second connection, each PPCS communicatively coupled to a respective subset of DACs of the plurality of DACs to provide a bias current to the two or more DACs of the respective subset of the plurality of DACs.

[0011] According to other aspects, the plurality of programmable devices may comprise a plurality of qubits and a plurality of couplers, and each qubit of the plurality of qubits is communicatively coupled to at least one other qubit of the plurality of qubits by a coupler of the plurality of couplers, the CJJ of each of the one or more PPCSs may comprise an array of CJJs, the array of Josephson junctions may comprise one of 8, 16, and 32 CJJs arranged equal current path distances from the first and the second connections interrupting the current storage loop, each of the one or more PPCSs may comprise a reset resistor, thereset resistor causing a persistent current in the current storage loop to dissipate according to a time decay, the quantum processor may further comprise one or more analog control lines, wherein a number of the one or more analog control lines may be smaller than a number of the one or more PPCSs, and the one or more analog control lines may be multiplexed to provide a respective control signal to each of the one or more PPCS, the one or more analog control lines may provide communication between the quantum processor and a digital processor, and at least one of the one or more PPCSs may be communicatively coupled to an additional PPCS that provides a control signal to the at least one of the one or more PPCSs.

[0012] According to an aspect, there is provided a method of programming a quantum processor, the quantum processor comprising a plurality of qubits, the method comprising: inducing a persistent current in a programmable persistent current source (PPCS), the PPCS comprising a current storage loop and a compound Josephson junction (CJJ) interrupting the current storage loop at a first connection and a second connection, inducing a current in a first digital to analog converter (DAC) based on a combination of the persistent current from the PPCS and a current from a communicatively coupled first control line, inducing a current in a second DAC based on a combination of the persistent current from the PPCS and a current from a communicatively coupled second control line, programming a first qubit of the plurality of qubits by the first DAC, and programming a second qubit of the plurality of qubits by the second DAC.

[0013] According to another aspect, inducing a persistent current in the PPCS may comprise inducing a current in an additional PPCS that is communicatively coupled to the PPCS.

[0014] According to an aspect, there is provided a superconducting integrated circuit comprising: a superconducting current path forming a loop, and a compound Josephson junction (CJJ) structure interrupting the loop at a first connection and a second connection, the CJJ structure comprising at least four CJJs connected to have equal current path distance between each CJJ and the first and second connections.

[0015] According to other aspects, the at least four CJJs may be arranged in parallel, the at least four CJJs may be arranged in a nested structure, the CJJ structure may have internal symmetry, the at least four CJJs may be arranged in a circle around the first and second connections, the CJJ structure may comprise at least eight CJJ loops connected to have equal current path distance between each CJJ loop and the first and second connections, the CJJ structure may comprise sixteen CJJ loops connected to have equal current path distance between each CJJ loop and the first and second connections, the superconducting integrated circuit may further comprise at least one control line communicatively coupled to provide a flux bias to the CJJ structure, the current loop may comprise a high kinetic inductance material, and the current loop and the CJJ structure may comprise a programmable persistent current source (PPCS).

[0016] In other aspects, the features described above may be combined in any reasonable combination as will be recognized by those skilled in the art.BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0017] In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn, are not necessarily intended to convey any information regarding the actual shape of the particular elements, and may have been solely selected for ease of recognition in the drawings.

[0018] Figure 1 is a schematic diagram of a hybrid computing system including a digital computer coupled to a quantum computer, in accordance with the present systems, devices, and methods.

[0019] Figure 2 is a schematic diagram of a portion of an example superconducting quantum processor, in accordance with the present systems, devices, and methods.

[0020] Figure 3 is a schematic diagram of a portion of a superconducting quantum processor having a programmable persistent current source, in accordance with the present systems, devices, and methods.

[0021] Figure 4 is a schematic diagram of a simplified programmable persistent current source, in accordance with the present systems, devices, and methods.

[0022] Figure 5 is a schematic diagram of a Josephson junction structure having ten compound Josephson junctions, in accordance with the present systems, devices, and methods.

[0023] Figure 6 is a schematic diagram of a Josephson junction structure having sixteen compound Josephson junctions, in accordance with the present systems, devices, and methods.

[0024] Figure 7 is a schematic diagram of a portion of a superconducting quantum processor having an alternative implementation of a programmable persistent current source, in accordance with the present systems, devices, and methods.

[0025] Figure 8 is a flow chart of an example method of programming a quantum processor, in accordance with the present systems, devices, and methods.DETAILED DESCRIPTION

[0026] In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed implementations.However, one skilled in the relevant art will recognize that implementations may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with computer systems, server computers, and / or communications networks have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the implementations.

[0027] Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprising” is synonymous with “including,” and is inclusive or open-ended ( / .e., does not exclude additional, unrecited elements or method acts).

[0028] Reference throughout this specification to “one implementation” or “an implementation” means that a particular feature, structure, or characteristic described in connection with the implementation is included in at least one implementation. Thus, the appearances of the phrases “in one implementation” or “in an implementation” in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

[0029] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and / or” unless the context clearly dictates otherwise.

[0030] The headings and Abstract of the Disclosure provided herein are for convenience only and do not interpret the scope or meaning of the implementations.Example Hybrid Computing System

[0031] Figure 1 illustrates a computing system 100 comprising a digital computer 102. The example digital computer 102 includes one or more digital processors 106 that may be used to perform classical digital processing tasks. Digital computer 102 may further include at least one system memory 122, and at least one system bus 120 that couples various system components, including system memory 122 to digital processor(s) 106. System memory 122 may store one or more sets of processor-executable instructions, which may be referred to as modules 124.

[0032] The digital processor(s) 106 may be any logic processing unit or circuitry (for example, integrated circuits), such as one or more central processing units ("CPUs"), graphics processing units ("GPUs"), digital signal processors ("DSPs"), application-specific integrated circuits ("ASICs"), programmable gate arrays ("FPGAs"), programmable logic controllers (“PLCs”), etc., and / or combinations of the same.

[0033] In some implementations, computing system 100 comprises a quantum computer 104, which may include one or more quantum processors 126. Quantum processor 126 may, in some implementations, include at least one superconducting integrated circuit. Digital computer 102 may communicate with quantum computer 104 via, for instance, a controller 118. Certain computations may be performed by quantum computer 104 at the instruction of digital computer 102, as described in greater detail herein.

[0034] Digital computer 102 may include a user input / output subsystem 108. In some implementations, user input / output subsystem 108 includes one or more user input / output components such as a display 110, a mouse 112, and / or a keyboard 114.

[0035] System bus 120 may employ any known bus structures or architectures, including a memory bus with a memory controller, a peripheral bus, and a local bus. System memory 122 may include non-volatile memory, such as read-only memory ("ROM"), static random-access memory (“SRAM”), Flash NAND; and volatile memory such as dynamic random-access memory ("DRAM").

[0036] Digital computer 102 may also include other non-transitory computer- or processor-readable storage media or non-volatile memory 116. Non-volatile memory 116 may take a variety of forms, including: a hard disk drive for reading from and writing to a hard disk (for example, a magnetic disk), an optical disk drive for reading from and writing to removable optical disks, and / or a solid state drive (SSD) for reading from and writing to solid state media (for example NAND- based Flash memory). Non-volatile memory 116 may communicate with digital processor(s) via system bus 120 and may include appropriate interfaces or controllers 118 coupled to system bus 120. Non-volatile memory 116 may serve as long-term storage for processor- or computer-readable instructions, data structures, or other data (sometimes called program modules or modules 124) for digital computer 102.

[0037] Although digital computer 102 has been described as employing hard disks, optical disks and / or solid-state storage media, those skilled in the relevant art will appreciate that other types of nontransitory and non-volatile computer- readable media may be employed. Those skilled in the relevant art will appreciatethat some computer architectures employ nontransitory volatile memory and nontransitory non-volatile memory. For example, data in volatile memory may be cached to non-volatile memory or a solid-state disk that employs integrated circuits to provide non-volatile memory.

[0038] Various processor- or computer-readable and / or executable instructions, data structures, or other data may be stored in system memory 122. For example, system memory 122 may store instructions for communicating with remote clients and scheduling use of resources including resources on the digital computer 102 and quantum computer 104. Also, for example, system memory 122 may store at least one of processor executable instructions or data that, when executed by at least one processor, causes the at least one processor to execute the various algorithms to execute instructions. In some implementations system memory 122 may store processor- or computer-readable calculation instructions and / or data to perform pre-processing, co-processing, and postprocessing to quantum computer 104. System memory 122 may store a set of quantum computer interface instructions to interact with quantum computer 104. For example, the system memory 122 may store processor- or computer- readable instructions, data structures, or other data which, when executed by a processor or computer causes the processor(s) or computer(s) to execute one, more or all of the acts of method 800 as discussed below with respect to Figure 8.

[0039] Quantum computer 104 may include at least one quantum processor such as quantum processor 126. Quantum computer 104 may be provided in an isolated environment, for example, in an isolated environment that shields the internal elements of quantum computer 104 from heat, magnetic field, and other external noise. The isolated environment may include a refrigerator, for instance a dilution refrigerator, operable to cryogenically cool the quantum processor, for example to temperature below approximately 1 K.

[0040] Quantum computer 104 may include programmable elements such as qubits, couplers, and other devices (also referred to herein as controllable devices). Qubits may be read out via a readout system 128. Readout results may be sent to other computer- or processor-readable instructions of digital computer102. Qubits may be controlled via a qubit control system 130. Qubit control system 130 may include on-chip Digital to Analog Converters (DACs) and analog lines that are operable to apply a bias to a target device. As used herein, “off- chip” refers to devices external to the quantum processor, while “on-chip” refers to devices that form part of the quantum processor. It will be understood that “on- chip” includes devices formed on physically distinct chips that are interconnected to form a quantum processor. Couplers that couple qubits may be controlled via a coupler control system 132. Coupler control system 132 may include tuning elements such as on-chip DACs and analog lines. Qubit control system 130 and coupler control system 132 may be used to implement a quantum annealing schedule or a gate model computation on quantum processor 126.Programmable elements may be included in quantum processor 126 in the form of an integrated circuit. Qubits and couplers may be positioned in layers of the integrated circuit that comprise a first material. Other devices, such as those of readout control system 128, may be positioned in other layers of the integrated circuit that comprise a second material. In some examples, quantum computer 104 can be a quantum annealing processor or a circuit model or gate model quantum processor.Example Superconducting Quantum Processor

[0041] Figure 2 is a schematic diagram of a portion of an example superconducting quantum processor 200, according to at least one implementation. The portion of superconducting quantum processor 200 shown in Figure 2 includes two superconducting qubits 201 and 202. Also shown is a tunable coupling (diagonal coupling) via coupler 210 between qubits 201 and 202 ( / .e., providing 2-local interaction). While the portion of quantum processor 200 shown in Figure 2 includes only two qubits 201 , 202 and one coupler 210, those of skill in the art will appreciate that quantum processor 200 may include any number of qubits and any number of couplers coupling information between them.

[0042] Quantum processor 200 includes a plurality of interfaces 221 , 222, 223, 224, and 225 that are used to configure and control the state of quantumprocessor 200. Each of interfaces 221-225 may be realized by a respective inductive coupling structure, as illustrated, as part of a programming subsystem and / or an evolution subsystem. Alternatively, or in addition, interfaces 221-225 may be realized by a galvanic coupling structure. In some implementations, one or more of interfaces 221-225 may form part of or be connected to one or more analog control lines, and / or one or more of interfaces 221-225 may be driven by one or more DACs. Such a programming subsystem and / or evolution subsystem may be separate from quantum processor 200, or may be included locally (7.e. , on-chip with quantum processor 200).

[0043] In the operation of quantum processor 200, interfaces 221 and 224 may each be used to couple a flux signal into a respective compound Josephson junction 231 and 232 of qubits 201 and 202, thereby realizing a tunable tunneling term (the term) in the system Hamiltonian. This coupling provides the off- diagonal axterms of the Hamiltonian and these flux signals are examples of “delocalization signals”. Examples of Hamiltonians (and their terms) used in quantum computing are described in greater detail in, for example, U.S. Patent No. 9,424,526.

[0044] Similarly, interfaces 222 and 223 may each be used to apply a flux signal into a respective qubit loop of qubits 201 and 202, thereby realizing the htterms (dimensionless local fields for the qubits) in the system Hamiltonian. This coupling provides the diagonal azterms in the system Hamiltonian. Furthermore, interface 225 may be used to couple a flux signal into coupler 210, thereby realizing theterm(s) (dimensionless local fields for the couplers) in the system Hamiltonian. This coupling provides the diagonal ozozterms in the system Hamiltonian.

[0045] Throughout this specification and the appended claims, the term “quantum processor” is used to generally describe a collection of physical qubits (e.g., qubits 201 and 202) and qubit couplers (e.g., coupler 210). The physical qubits 201 and 202 and the coupler 210 are referred to as the “controllable devices” of the quantum processor 200 and their corresponding parameters (e.g., the qubit htvalues and the coupler values) are referred to as the “controllable parameters” of the quantum processor. In the context of a quantum processor,the term “programming subsystem” is used to generally describe the interfaces (e.g., “programming interfaces” 222, 223, and 225) used to apply the controllable parameters to the controllable devices of the quantum processor 200 and other associated control circuitry and / or instructions. In some implementations, programming interfaces 222, 223, and 225 may include DACs. DACs may also be considered programmable devices that are used to control controllable devices such as qubits, couplers, and parameter tuning devices.

[0046] As previously described, the programming interfaces of the programming subsystem may communicate with other subsystems which may be separate from the quantum processor or may be included locally on the processor. The programming subsystem may be configured to receive programming instructions in a machine language of the quantum processor and execute the programming instructions to program the programmable and controllable devices in accordance with the programming instructions. Similarly, in the context of a quantum processor, the term “evolution subsystem” generally includes the interfaces (e.g., “evolution interfaces” 221 and 224) used to evolve devices such as the qubits of the quantum processor 200 and other associated control circuitry and / or instructions. For example, the evolution subsystem may include annealing signal lines and their corresponding interfaces (221 , 224) to the qubits (201 , 202).

[0047] Quantum processor 200 also includes readout devices 251 and 252, where readout device 251 is associated with qubit 201 and readout device 252 is associated with qubit 202. In the example implementation shown in Figure 2, each of readout devices 251 and 252 includes a direct current superconducting quantum interference device (DC-SQUID) inductively coupled to the corresponding qubit. In the context of quantum processor 200, the term “readout subsystem” is used to generally describe the readout devices 251 , 252 used to read out the final states of the qubits (e.g., qubits 201 and 202) in the quantum processor to produce a bit string. The readout subsystem may also include other elements, such as routing circuitry (e.g., latching elements, a shift register, or a multiplexer circuit) and / or may be arranged in alternative configurations (e.g., an XY-addressable array, an XYZ-addressable array, etc.), any of which maycomprise DACs. Qubit readout may also be performed using alternative circuits, such as that described in U.S. Patent No. 8,977,576.

[0048] While Figure 2 illustrates only two physical qubits 201 , 202, one coupler 210, and two readout devices 251 , 252, a quantum processor (e.g., processor 200) may employ any number of qubits, couplers, and / or readout devices, including a larger number (e.g., hundreds, thousands or more) of qubits, couplers and / or readout devices. The application of the teachings herein to processors with a different (e.g., larger) number of computational components should be readily apparent to those of ordinary skill in the art.

[0049] Examples of superconducting qubits include superconducting flux qubits, superconducting charge qubits, and the like. In a superconducting flux qubit, the Josephson energy dominates or is equal to the charge energy. In a charge qubit this is reversed. Examples of flux qubits that may be used include radio frequency superconducting quantum interference devices (rf-SQUIDs), which include a superconducting loop interrupted by one Josephson junction, persistent current qubits, which include a superconducting loop interrupted by three Josephson junctions, and the like.Kinetic Inductance

[0050] Current flowing through a metal material in principle stores energy both in the magnetic field of that metal and in the kinetic energy of the charge carriers (e.g., the electrons or Cooper pairs). In non-superconducting metals, the charge carriers collide frequently with the lattice and lose their kinetic energy as Joule heating. This is also referred to as scattering, and quickly releases energy.However, in superconducting materials, scattering is substantially reduced, as the charge carriers are Cooper pairs that are protected against dissipation through scattering. This allows for superconducting materials to store energy in the form of kinetic inductance. Kinetic inductance is at least in part determined by the inertial mass of the charge carriers of a given material and increases as carrier density decreases. As the carrier density decreases, a smaller number of carriers have a proportionally greater velocity in order to produce the same current.Materials that have high kinetic inductance for a given area (as defined below)are referred to as “kinetic inductance materials”, or “high kinetic inductance materials”.

[0051] Kinetic inductance materials are those that have a high normal-state resistivity and / or a small superconducting energy gap, resulting in a larger kinetic inductance per unit of area. In general, total inductance L of a superconducting material is given by L = LK+ LG, where LGis a geometric inductance and LKis a kinetic inductance of the superconducting material. The kinetic inductance of a superconducting film in near-zero temperatures is proportional to an effective penetration deptheff. In particular, for a film with a given thickness t, the kinetic inductance of the film is proportional to a ratio of a length of the film L to a width of the film W, where the length corresponds to a direction in which current flows and the width is orthogonal to the length (note that both width and length are orthogonal to the dimension in which thickness is measured). That is, a kinetic inductance of a superconducting film with a given thickness is: LK~A kinetic inductance fraction of a material is characterized as a =Lk. A materialconsidered to have a high kinetic inductance value would typically have a in the range of: 0.1 < a < 1. Materials with less than 10% of its energy stored as kinetic inductance would be considered traditional magnetic storage inductors with a small correction.Noise

[0052] The operation of quantum processors is often limited by the effects of noise, either due to the external environment, such as heating or electromagnetic radiation, or due to internal noise processes, such as crosstalk between devices and flux trapping. In the present specification, the phrase “noise-susceptible superconducting device” or “superconducting device having high susceptibility to noise” is used to describe a superconducting device for which a noise-free operating environment is highly desirable for performance of a superconducting integrated circuit, for example, a quantum processor. Poor performance of a noise-susceptible device may result in the quantum processor producing an inaccurate or suboptimal solution to a problem, for example, an inaccurate orsuboptimal result of quantum annealing. Note that the phrases “noise- susceptible” and “susceptible to noise” do not necessarily suggest that the device itself is physically more or less sensitive to noise compared to other devices that are not described as noise-susceptible. Instead, “noise-susceptible” is used to refer to the sensitivity of processor performance to noise within a given device. The sensitivity of the processor performance to noise is higher in noise- susceptible devices than in devices that are described as less susceptible to noise or as “devices having low susceptibility to noise”. Sources of noise in a quantum processor may include, but are not limited to, flux noise, charge noise, magnetic fields, and high frequency photons.

[0053] Superconducting quantum processors typically operate in a cryogenic environment, such as a dilution refrigerator, that allows for the processor to be operated in a superconducting state. In order to communicate with the quantum processor, for example, when calibrating, programming, or reading out states from the quantum processor, control lines between at least one computing device located in a room temperature environment and the quantum processor are used. However, these control lines can be a significant source of noise and heating of the quantum processor, and as the number of devices in the quantum processor increases, it becomes infeasible to provide individual device control with dedicated control lines for each device, both due to physical size constraints and the heating and noise introduced. Increasing the scale of a quantum processor, that is, the number of controllable devices within the processor, enables more complex problems to be solved by the quantum processor. In order to scale quantum processors, it is therefore beneficial to explore strategies to reduce the required line count to control each device, such as through line multiplexing and other control schemes. On-chip control structures may provide another way to reduce line count relative to the number of devices in a quantum processor. Herein, “devices on a quantum processor”, or “quantum devices”, refers to distinct structures that perform a defined purpose within the quantum processor. For example, a quantum processor may include a plurality of qubits communicatively coupled by a plurality of couplers, as well as control devicessuch as inductance or capacitance tuners, programming infrastructure, and readout infrastructure.

[0054] In order to perform operations such as calibration, programming, annealing, and readout, a variety of signals are applied to the qubits and couplers. Bias signals can modify the behavior of devices by injecting a current that modifies an amount of magnetic flux within the device. Generally speaking, controlling an on chip device involves changing an amount of flux within the device, such as through application of a flux bias to the CJJ or CCJJ of a coupler or to the body of a qubit. As used herein, “compound-compound Josephson junction” (CCJJ) refers to a Josephson Junction in which one or more of the junctions within a compound Josephson junction is itself a compound Josephson junction. When transmitting a signal to a superconducting device within a cryogenic environment using an inductively coupled control line that originates from a room temperature environment, a current is applied to the control line, and a mutual inductance between the current and the superconducting device results in a flux induced in the superconducting device that is proportional to the current in the line.

[0055] Bias signals may be generated off-chip and transmitted to the superconducting devices, or may be provided by on-chip control devices that are part of the quantum processor. U.S. Patent No. 10,528,886 discusses digital to analog converters (DACs) that act as persistent magnetic memory on-chip and provide a controlled analog current for biasing other devices on a per-device basis. These DACs allow for control signal multiplexing as described in U.S. Patent No. 10,528,886, with control lines that originate from a room temperature environment that transmit bias signals to several devices, and the DAC providing individual control, or flux bias, for coupled devices on chip. In the described example, three control lines are multiplexed to provide signals to the DACs, which in turn provide signals to devices such as qubits and couplers. However, in all of these examples, DACs are provided on a per-device basis, that is, one DAC is coupled to each device to be controlled. As discussed herein, one or more control lines originating from a room temperature environment may beneficially be replaced by additional on-chip devices to allow for a reduction in control linesrelative to the number of devices. A reduction in the number of required control lines relative to the number of devices in the quantum processor may beneficially both enable an increase in the number of devices on the quantum processor that can be supported and may reduce noise experienced by noise-susceptible devices on the quantum processor, resulting in improved solution quality and / or accuracy.Digital to Analog Converters (DACs)

[0056] As discussed above with respect to example quantum processor 200 of Figure 2, quantum processors have a plurality of controllable devices for performing computations with quantum effects. Controllable devices include qubits, couplers (which communicatively couple at least two qubits, and are also referred to as “qubit couplers”), and components thereof. Controllable devices are controlled via signals applied to influence their operation, for example, a bias signal may be applied to a flux qubit to change its flux during computation. These signals may be provided by programmable devices such as DACs.

[0057] Such signals often require conversion and / or storage prior to being applied to controllable devices. For example, a classical computer may generate digital signals for the quantum processor, and those digital signals may be converted to analog signals by one or more digital-to-analog converters (DACs). The converted analog signal may then be applied to the controllable device. As another example, a signal (which may be digital or analog) may be received by the quantum processor at one time before or during a computation and stored via a DAC until the signal is to be applied to a controllable device at a later time. DACs may be used for one or more of these purposes ( / .e., conversion and / or memory) and / or for other purposes including storage, programming, and readout within a quantum processor. Examples of applications of DACs for these and other purposes are described in greater detail in, for example, U.S. Patent Nos. 7,876,248 and 8,098,179. The operation of Josephson junctions (JJs) and / or compound Josephson junctions (CJJs) in DACs is described in greater detail in, for example, U.S. Patent Nos. 7,876,248; 8,098,179; 10,528,886; and 11 ,127,893.

[0058] Superconducting quantum processors often comprise a plurality of DACs for these and other functions. Such DACs include superconducting DACs which store a flux (sometimes referred to as -DACs), which generally comprise a storage inductor (e.g., a superconducting magnetic coil) and a programmable coupling element. -DACs take advantage of the flux rate of change of the circuit (e.g., of the storage inductor) to store energy in their magnetic fields, thereby generating an effective inductance (sometimes referred to as a “magnetic inductance”).

[0059] Although the term DAC is used throughout, it will be understood that the described devices may be used for a variety of purposes which are not necessarily restricted to conversion of digital signals to analog signals, and, in some implementations, do not involve such conversion at all. For example, as described above, superconducting DACs may be used by quantum processors to store a signal for a period of time, and in some examples may thereby operate as a form of on chip memory.Programmable Persistent Current Source

[0060] In non-superconducting devices, an introduced current will dissipate due to resistance unless it is actively maintained by a powered source. However, in superconducting devices the current can persist indefinitely and continue to act as a current source without being actively maintained (beyond maintenance of superconductive state via a sufficiently low temperature). As used herein, persistent current refers to current that can be set to a steady state value and maintained until it is reset. Described herein is an on-chip programmable source of persistent current that can be used to provide control of devices on a quantum processor. A persistent current can be induced in the programmable persistent current source (PPCS), and then this source of persistent current can be used to bias other devices, such as by controlling an amount of flux entering a superconducting loop. This may beneficially provide control schemes that introduce less noise to a quantum processor due to a reduction in a number of control lines communicatively coupled thereto that originate in a room temperature environment as discussed above, or alternatively may allow for anincreased number of superconducting devices to be included on a quantum processor for the same number of control lines.

[0061] In addition, the PPCS may beneficially decouple or at least partially decouple noise between the superconducting devices that are biased by the PPCS and the control lines that originate in the room temperature environment. In particular, the PPCS is programmed by one or more control lines, and then the superconducting devices in communication with the PPCS are programmed by the PPCS. As the PPCS introduces less noise to the coupled device than a control line originating from room temperature, this can decouple the higher noise source from the superconducting device that is programmed by the PPCS. In addition, the signals provided by the PPCS may be more stable than those transmitted through control lines originating at room temperature, as signals transmitted by such control lines can experience signal drift due to variations in line resistance. While DACs, as discussed above, can be used on-chip to bias a single superconducting device, such as a qubit body or a qubit CCJJ, the PPCS is capable of biasing many superconducting devices simultaneously, similar to an external control line, while being an on-chip device that can be itself programmed using a multiplexing or tree programming scheme. This allows the PPCS to bias multiple superconducting devices while also being located on on-chip.Beneficially, the noise of the current flowing in the storage loop of the PPCS may be lower relative to currents driven using external sources that originate from a room temperature environment.

[0062] Figure 3 is a schematic diagram of a portion of a quantum processor 300. Portion of a quantum processor 300 may form part of quantum processor 126 as discussed with respect to Figure 1 , and may be implemented as part of quantum processor 200 of Figure 2. Portion of a quantum processor 300 may be implemented in association with a plurality of qubits and a plurality of couplers, for example as discussed with respect to quantum processor 200 of Figure 2, with each qubit of the plurality of qubits communicatively coupled to at least one other qubit of the plurality of qubits by a coupler of the plurality of couplers.

[0063] As discussed above with respect to Figure 2, interfaces 221 , 222, 223, and 224 may be in communication with digital to analog converters (DACs) forprogramming, calibration, and / or readout. Figure 3 has four DACs 302, 304, 306, and 308 having respective interfaces 302a, 304a, 306a, 308a that are respectively in communication with programmable devices 310, 312, 314, and 316. Programmable devices 310, 312, 314, and 316 may be qubits such as qubits 201 and 202 of Figure 2. Programmable devices 310-316 may also be other programmable devices such as couplers, inductance tuners, and / or other programming or readout devices that, for example, belong to qubit control system 130, coupler control system 132, and / or readout control system 128 of Figure 1 . Each DAC 302-308 is communicatively coupled to provide a control signal to a respective programmable device. DACs 302-308 are arranged in two subsets of DACs, 318 and 320, which in the example of Figure 3 are arranged as two columns. It will be understood that in other implementations each subset of DACs may have more than two DACs, portion of a quantum processor 300 may include more than two subsets of DACs, and the DACs may be arranged differently than illustrated in Figure 3.

[0064] Each subset of DACs 318 and 320 is associated with a respective programmable persistent current source (PPCS) 322 and 324. Each PPCS 322 and 324 has a current storage loop (322a and 324a respectively) and a compound Josephson junction (CJJ) (322b and 324b respectively) interrupting the current storage loop (322a and 324a). Each PPCS 322 and 324 is communicatively coupled to a respective subset of DACs (318, 320), that is, PPCS 322 is communicatively coupled to subset of DACs 318 including DACs 302 and 304, and PPCS 324 is communicatively coupled to subset of DACs 320 including DACs 306 and 308. Each PPCS 322 and 324 is coupled to provide a bias current to each of the DACs in its respective subset of DACs when a persistent current is induced in the respective PPCS.

[0065] In the example implementation of Figure 3, PPCS 322 is in inductive communication with an analog control line 326 and PPCS 324 is in communication with an analog control line 328. In some implementations, these analog control lines (326, 328) provide communication between portion of a quantum processor 300 and a digital processor, such as digital processor 106 of Figure 1. In some implementations the analog control lines (326, 328) may bemultiplexed such that respective control signals are provided to each PPCS (322, 324) from a number of analog control lines that is smaller than the number of PPCSs. In the example implementation of Figure 3, PPCSs 322 and 324 are also communicatively coupled to an additional PPCS 330 having a current storage loop 330a and a CJJ 330b that provides a control signal to PPCSs 322 and 324. It will be understood that in some implementations, additional PPCS 330 may be replaced with analog control lines, and in some implementations, additional PPCS 330 may further be in communication with a further additional PPCS to provide a tree-like control structure.

[0066] Portion of a quantum processor 300 includes one or more superconducting materials and is operated at a temperature below the one or more respective critical temperatures of those superconducting materials such that they exhibit superconductive behavior during operation. One of the intrinsic material properties of superconductors is that there is zero resistance to electrical current flow therethrough. As such, once current is introduced, it will not be dissipated in the current storage loops 322a, 324a, and 330a of PPCSs 322, 324, and 330. While in some implementations it may be beneficial to provide a persistent current source that is maintained until a reset procedure is initiated, in other implementations it may be beneficial to include a reset resistor, allowing for a constant decay of current within the current storage loop (322a, 324a, 330a), as shown, for example, in Figure 4. The addition of a resistor provides a time decay to the circulating current to allow for a built-in reset to zero after a fixed time.

[0067] Portion of a quantum processor 300 may also have additional control lines (only one called out as 332 to reduce clutter) that may be analog control lines such as multiplexed analog control lines for programming one or more of DACs 302-308. In some implementations these control lines may also be provided by additional PPCSs.

[0068] Figure 4 is a schematic diagram of a simplified PPCS 400. PPCS 400 may be PPCS 322, 324, or 330 of Figure 3. PPCS 400 has a current storage loop 402, a CJJ structure 404 interrupting current storage loop 402 at a first connection or node 412 and a second connection or node 414, and a reset resistor 406 in parallel with CJJ structure 404. Reset resistor 406 dissipatespersistent current in current storage loop 402 according to a time decay determined by physical properties of reset resistor 406, such as a resistance value of reset resistor 406. CJJ structure 404 is communicatively coupled to control lines 408 and 410, which may, for example, be additional PPCS devices or analog control lines. In some implementations, PPCSs such as PPCS 322, 324, 330, and 400 may have a CJJ structure formed by an array of Josephson junctions. For example, CJJ structure 404 may be formed from one of 8, 16, and 32 compound Josephson junctions that are arranged equidistantly from the interruptions in the current storage loop (e.g., CJJs of CJJ structure 404 can be arranged equidistantly from first and second connections or nodes 412, 414 in Figure. 4). Such a CJJ structure may be arranged to have internal symmetry (see Figures 5 and 6 for example implementations). In some implementations, current storage loop 402 is partially or entirely formed from a high kinetic inductance superconducting material.

[0069] While the discussion above primarily describes programming DACs, which in turn program other devices, the PPCS may also be used to replace control lines, such as control lines that bias other devices on the quantum processor, including coupler CJJ loops and inductance tuners. In some implementations, the PPCS can reduce the requirement for control lines originating at room temperature to perform operations such as programming, calibration, and / or readout with a quantum processor, or the PPCS may increase the complexity of operations that can be performed using the same number of control lines (e.g., more devices may be programmed). As an example, the PPCS may be used to replace a plurality of DAC control lines, and more specifically, where a DAC would have been controlled with N control lines, those N control lines can be replaced with N PPCSs that are programmed using M lines, where M is less than N. The M lines may, for example, be arranged in a tree or XYZ addressing scheme to allow for multiplexing. Programming is further discussed below with respect to Figure 8.

[0070] Superconducting quantum interference devices (SQUIDs) and CJJ loops have a parameter referred to as beta (ft), where ~ Llc. L is the inductance of the superconducting loop of the SQUID or CJJ loop, and Icis the criticalcurrent of the Josephson junction(s). Beta is proportional to the amount of flux quanta (<t>0) that can stably exist, or persist, within the SQUID loop or CJJ loop. In order to provide an effective multiplexing scheme, it is beneficial to have a large programming range, that is, a wide range between the smallest number of flux quanta that can persist in the loop and a largest number of flux quanta that can persist in the loop. It is beneficial to have both a lower CJJ beta, which sets the minimum value of the programming range, and a high critical current, which sets the maximum value of the programming range. In some implementations, the PPCS as discussed above has a Josephson junction structure with many parallel or nested CJJ loops to allow for the injection of many flux quanta into the storage loop, allowing the device to act as a current source for many other devices.

[0071] Referring to Figure 4, if PPCS 400 had a single CJJ in CJJ structure 404, that is, two JJs in parallel similar to CJJ 231 of Figure 2, and each junction in the CJJ had critical current / c / 2, the CJJ, and therefore the PPCS, would have a total critical current of Ic. The beta of the CJJ loop is proportional to the product of the CJJ critical current ( / c) and the CJJ loop inductance (L) as above. The beta of the CJJ structure (e.g., CJJ structure 404) of the PPCS (e.g., PPCS 400) governs both the PPCS output range and the power dissipated when current is injected into the PPCS. It is beneficial to provide a large output range to allow for more control in programming, however, it is also beneficial to reduce power dissipation, as power dissipation can cause heating and / or noise on the processor.Therefore, it is beneficial to minimize the beta of the CJJ structure by replacing the one CJJ with N CJJs arranged in parallel. If each of the N CJJs has a critical current Ic / N, the total critical current for the N CJJs in parallel is still Ic, as in the previous example with a single CJJ. However, assuming each of the N CJJs has the same inductance as the original CJJ, the beta of each of the N CJJs is reduced by a factor 1 / N, as their individual critical currents are 1 / N smaller. This results in a smaller beta for the overall CJJ structure, which allows for a larger PPCS output range and a smaller power dissipation. This may beneficially be applied in any device for which it is desirable to have a programmable inductance or programmable critical current with a large range and large maximum critical current.

[0072] In the multi-CJJ structures shown, for example, in Figure 4, as well as discussed below in Figures 5 and 6, it can also be beneficial to provide Josephson junction structures having internal symmetry among CJJs, that is, the CJJs of the CJJ structure being laid out in a symmetrical arrangement such that the length of the CJJ body loop reaching each junction is the same for the entire structure. Homogenization of the length of the loop reaching each junction can ensure all of the CJJ loops switch (that is, reach their critical current) together, minimizing the number of transitions in the body storage loop. This may also homogenize the mutual inductance between the CJJ loops and the coupled bias line, which may beneficially reduce mutual inductance mismatches due to gradients that may be induced by fabrication imperfections. In some implementations, the length of the CJJ body loop reaching each junction may vary. Homogenization the beta of the CJJ structure may be achieved by varying the Icof individual CJJs, which leads to homogenization of the multi-CJJ structure.

[0073] The length of the loop as used herein refers to the length of the circuit path provided by traces, lines, or wiring between the start of the CJJ loop and the CJJ. As shown in Figure 4, the start of the CJJ loop is provided by the connection or nodes 412 and 414. It will also be understood that while the circuits shown in Figures 4, 5, and 6 are shown in two dimensions, a fabricated circuit may be formed in three dimensions in a multi-layer stack. Figures 5 and 6 provide examples of parallel and nested arrangements of CJJs. In some implementations damping resistors may be provided across some or all of the Josephson junctions.

[0074] Figure 5 is a schematic diagram of an example implementation of a CJJ structure 500 having an array of Josephson junctions. In the example implementation of Figure 5, CJJ structure 500 has 10 CJJs (only one called out as 502 to avoid clutter) arranged in a circular arrangement, with equal distances of circuit path formed by traces, lines, or wiring from the tapping point or interruption 508 of the current storage loop. Tapping point or interruption 508 has two nodes spaced into and / or out of the drawing page of Figure 5, similar to connection or nodes 412 and 414 of Figure 4. The two nodes of tapping point orinterruption 508 may be first connection or node 412 and second connection or node 414 as shown in Figure 4. As used herein, the connection refers to an intersection in the traces, lines, or wiring, which may be a point or area, that represents the transition between two structures within a circuit, in this case, the transition between the body loop of the device and the CJ J loop. The circular arrangement of CJJ structure 500 provides equal distances of the current path provided by traces, lines, or wiring 510 between each CJJ loop 502 and connection or tapping point or interruption 508. It will be understood that in other implementations different numbers of CJJs may be included, for example, one of 8, 16, and 32 Josephson junctions arranged equidistantly from the interruptions in the current storage loop, that is, with equal current path distance between each CJJ loop and the first and second connections to the storage loop of a PPCS. In CJJ structure 500, each CJJ 502 of the plurality of CJJs is connected to the other CJJs of the plurality of CJJs in parallel. In some implementations, CJJ structure 500 might be CJJ structure 404, with the shape illustrated in Figure 4 shown in dashed lines in Figure 5 as shape 504. CJJ structure 500 also has a control line 506 that is communicatively coupled to each CJJ 502 (control line 506 shown in Figure 5 with a dotted line for visual clarity). It will be understood that control line 506 may be a single control line as shown, or a plurality of control lines as discussed below with respect to control lines 604 of Figure 6.

[0075] Figure 6 is a schematic diagram of an alternative example implementation of a CJJ structure 600 having an array of Josephson junctions. In the example implementation of Figure 6, CJJ structure 600 has 16 CJJs (only one called out as 602 to avoid clutter) arranged in a circular arrangement with equal distance from the tapping point or interruption 608 of the current storage loop, that is, with equal current path distance between each body loop of each CJJ 602 and the first and second tapping point or interruption 608 to the storage loop of a PPCS. Tapping point or interruption 608 has two nodes spaced into the drawing page of Figure 6. The two nodes of tapping point or interruption 608 may be first connection or node 412 and second connection or node 414 as shown in Figure 4. It will be understood that in other implementations different numbers of CJJs may be included. In CJJ structure 600, each CJJ 602 is connected to oneanother and to tapping point or interruption 608 in a nested structure. CJJs 602 of CJJ structure 600 are in communication with control line or lines 604 (with only one interface called out to reduce clutter). Control line 604 may be a single control line similar to line 506 of Figure 5 or a plurality of control lines. One or more control lines may be communicatively coupled to one or more CJJs 602 to apply a bias to each of the CJJs 602 within CJJ structure 600.

[0076] It will be understood that while CJJ structures 500 and 600 are discussed in the context of PPCS 400 above, such CJJ structures may be used with other devices that may benefit from the symmetric arrangement of a plurality of CJJs and / or a small beta parameter. In some examples, qubits having more than two CJJs in parallel may benefit from such a CJJ structure. In some examples these may be flux qubits such as those shown in Figure 2. In other examples these may be qubits having many Josephson junctions arranged serially, which are referred to as fluxonium qubits in gate model quantum computation, as discussed, for example, in International Patent Publication No. WO 2023 / 096670. Generally, a CJJ structure having many CJJs as discussed above allows for a large dynamic range in critical current and inductance, and this may be implemented in any device where a large dynamic range is desired. For example, this may be useful in microwave switches or within a switch matrix used to route signals on-chip. In other implementations, this may be useful where a tunable inductance is desired, such as in a control structure for a qubit such as an inductance tuner, or in couplers for which a large dynamic coupling range is beneficial to the application.

[0077] Figure 7 is a schematic diagram of a portion of a superconducting quantum processor 700. Similar to portion of a superconducting quantum processor 300 of Figure 3, portion of a superconducting quantum processor 700 has two PPCSs 702 and 704. Each PPCS 702 and 704 are communicatively coupled to a plurality of DACs, with PPCS 702 communicatively coupled to DACs 706, 708 and PPCS 704 communicatively coupled to DACs 710, 712, 714, 716. In comparison with DACs 302, 304, 306, and 308 of Figure 3, DACs 706-716 are single stage DACs having a single Josephson junction structure and a single storage loop. DACs 706-716 are communicatively coupled to control lines (onlyone called out as 718). It will be understood that similar principles can be applied to DACs having different numbers of stages, and that the numbers of stages shown in DACs 302-308 and 706-716 are examples. DACs 706-716 are communicatively coupled to controllable devices, such as qubits or couplers, through interfaces 720 (only one called out to reduce clutter). Each PPCS 702 and 704 has a respective current storage loop 702a and 704a and a respective compound Josephson junction (CJJ) 702b and 704b interrupting the current storage loops 702a, 704a. Each PPCS 702, 704 is communicatively coupled to a respective subset of the plurality of DACs 706-716 to provide a bias current to the two or more DACs of the respective subset of the plurality of DACs.

[0078] In a quantum processor such as quantum processor 126 of Figure 1 or quantum processor 200 of Figure 2, programming of on-chip devices can be performed by biasing the Josephson structure of a given device with a first control structure and applying a current into the storage loop of the device with a second control structure. When the applied current is increased past the critical current of the Josephson structure, the current is transferred into the storage loop. Programming generally refers to the application of bias current to devices on a quantum processor, and can include signals required by calibration or a particular problem to be solved on a quantum processor, such as a qubit or coupler bias representing a particular problem.

[0079] Figure 8 is a flow chart of an example method 800 of programming a quantum processor, such as quantum processor 126 that may include elements of circuits 200, 300, 400, 500, 600, and / or 700 of Figures 2, 3, 4, 5, 6, and / or 7, respectively. Method 800 includes acts 802-810, however, a person skilled in the art will understand that the number of acts illustrated is an example, and, in some implementations, certain acts may be omitted, further acts may be added, and / or the order of the acts may be changed. Method 800 may be performed by, for example, a digital computer such as digital computer 102 in communication with a quantum computer such as quantum computer 104.

[0080] At 802, a persistent current is induced in a programmable persistent current source (PPCS) such as PPCS 322 of Figure 3. In the example implementation of Figure 3, a current can be induced by a combination ofadditional PPCS 330 and a control line 326. In other implementations, a current may be induced by a combination of one or more control lines and / or one or more PPCS devices.

[0081] At 804, a current is induced in a first digital to analog converter (DAC), such as DAC 302 of Figure 3, based on a combination of the persistent current from the PPCS ( / .e., the persistent current induced during act 802) and a current from a first control line. In the example implementation of Figure 3, DAC 302 has a plurality of control lines communicatively coupled with each stage of the DAC, with one called out as control line 332. In other implementations, such as the implementation of Figure 7, only one control line (called out as control line 718) may be used in combination with a PPCS. It will be understood that different numbers of control lines may be selected based on the particular programming and multiplexing techniques used.

[0082] At 806, a current is induced in a second DAC, such as DAC 304 of Figure 3, based on a combination of the persistent current from the PPCS and a current from a second control line. Different combinations of control lines may be used, as discussed above with respect to DAC 302.

[0083] At 808, a first qubit, such as qubit 310, is programmed by the first DAC, such as through interface 302a. Programming of qubits by DACs is discussed in more detail in U.S. Patent Nos. 7,876,248 and 8,098,179, and generally involves applying a bias signal to a programming interface of a qubit, where the magnitude of the bias signal is determined by the number of flux quanta that have been programmed into one or more storage loops of the DAC.

[0084] At 810, a second qubit, such as qubit 312, is programmed by the second DAC, such as through interface 304a.

[0085] After 810 the method ends, or the method may be iterated over additional PPCSs and qubits. It will be understood that a plurality of qubits may be programmed simultaneously using a plurality of PPCSs, with an array of DACs and an array of PPCSs.

[0086] Inducing a persistent current in a PPCS, as done, for example, in act 802, may be referred to as “programming” the PPCS. Referring to Figure 4, for example, PPCS 400 has a first control line 408 that biases current storage loop402 and a second control line 410 that biases CJJ structure 404. To induce current in current storage loop 402, the current in first control line 408 must be higher than the critical current of CJJ structure 404. The current in second control line 410 may be used to tune the critical current of CJJ structure 404, thereby reducing the current requirement for inducing a persistent current. When the current in first control line 408 is increased beyond the critical current of CJJ structure 404, the additional current will be transferred into storage loop 402. When the current in control lines 408 and 410 is reduced back to zero, the current loop 402 will be left with the trapped flux, inducing a persistent current in the body. Programming can be performed in both a positive and a negative direction from zero, or in other words, the induced current can circulate in either a clockwise or a counterclockwise direction.

[0087] A PPCS with persistent current may also be reset to remove the persistent current, for example, after programming all of the connected devices or when it is desired to induce a different persistent current. The PPCS will have a nominally zero state in both the positive direction and the negative direction, and the true zero state will be the midpoint between these two states. The state of the PPCS is specified by the persistent current flowing in it, and this nominally zero state will typically be equal in magnitude to the minimum critical current of the PPCS, with a sign that results from the reset procedure.

[0088] Referring to PPCS 400 of Figure 4, reset may also be performed by first and second control lines 408 and 410. In one implementation, reset may be performed by increasing the current in second control line 410 to approximately the same value as the minimum critical current of CJJ structure 404, increasing the current in first control line 408 in the direction of the desired zero state (7_e. , negative or positive) to above the critical current of CJJ structure 404, reducing the current in first control line 408 to zero, and oscillating the current in second control line 410 around the minimum critical current of CJJ structure 404 to arrive at the lowest possible state. This reset can be repeated in the opposite direction to achieve the other nominal zero state. Once the two nominal zero states have been measured, PPCS 400 can be programmed back to a midpoint state to achieve the true zero of PPCS 400.

[0089] The above described method(s), process(es), or technique(s) could be implemented by a series of processor readable instructions stored on one or more nontransitory processor-readable media. Some examples of the above described method(s), process(es), or technique(s) method are performed in part by a specialized device such as an adiabatic quantum computer or a quantum annealer or a system to program or otherwise control operation of an adiabatic quantum computer or a quantum annealer, for instance a computer that includes at least one digital processor. The above described method(s), process(es), or technique(s) may include various acts, though those of skill in the art will appreciate that in alternative examples certain acts may be omitted and / or additional acts may be added. Those of skill in the art will appreciate that the illustrated order of the acts is shown for example purposes only and may change in alternative examples. Some of the example acts or operations of the above described method(s), process(es), or technique(s) are performed iteratively. Some acts of the above described method(s), process(es), or technique(s) can be performed during each iteration, after a plurality of iterations, or at the end of all the iterations.

[0090] The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Although specific implementations of and examples are described herein for illustrative purposes, various equivalent modifications can be made without departing from the spirit and scope of the disclosure, as will be recognized by those skilled in the relevant art. The teachings provided herein of the various implementations can be applied to other methods of quantum computation, not necessarily the example methods for quantum computation generally described above.

[0091] The various implementations described above can be combined to provide further implementations. All of the commonly assigned US patent application publications, US patent applications, foreign patents, and foreign patent applications referred to in this specification and / or listed in the Application Data Sheet are incorporated herein by reference, in their entirety, including but not limited to: U.S. Patent Nos.: 7,876,248; 8,098,179; 8,977,576; 9,424,526;10,528,886; and 11 ,127,893; and International Patent Publication No. WO 2023 / 096670.

[0092] These and other changes can be made to the implementations in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific implementations disclosed in the specification and the claims, but should be construed to include all possible implementations along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims

CLAIMS1. A quantum processor comprising: a plurality of programmable devices; a plurality of digital to analog converters (DACs), each DAC of the plurality of DACs communicatively coupled to transmit a control signal to a respective programmable device of the plurality of programmable devices, the plurality of DACs arranged in two or more subsets of DACs, each subset of DACs comprising at least two DACs; and one or more programmable persistent current sources (PPCSs), each PPCS comprising a current storage loop and a compound Josephson junction (CJJ) interrupting the current storage loop at a first connection and a second connection, each PPCS communicatively coupled to a respective subset of DACs of the plurality of DACs to provide a bias current to the two or more DACs of the respective subset of the plurality of DACs.

2. The quantum processor of claim 1 , wherein the plurality of programmable devices comprises a plurality of qubits and a plurality of couplers, and each qubit of the plurality of qubits is communicatively coupled to at least one other qubit of the plurality of qubits by a coupler of the plurality of couplers.

3. The quantum processor of claim 1 , wherein the CJJ of each of the one or more PPCSs comprises an array of CJJs.

4. The quantum processor of claim 3, wherein the array of Josephson junctions comprises a number of CJJs arranged equal current path distances from the first and the second connections interrupting the current storage loop.

5. The quantum processor of claim 1 , wherein each of the one or more PPCSs comprises a reset resistor, the reset resistor causing a persistent current in the current storage loop to dissipate according to a time decay.

6. The quantum processor of claim 1 , further comprising one or more analog control lines, wherein a number of the one or more analog control lines is smaller than a number of the one or more PPCSs, the one or more analog control lines being multiplexed to provide a respective control signal to each of the one or more PPCS.

7. The quantum processor of claim 6, wherein the one or more analog control lines provide communication between the quantum processor and a digital processor.

8. The quantum processor of claim 1 , wherein at least one of the one or more PPCSs is communicatively coupled to an additional PPCS that provides a control signal to the at least one of the one or more PPCSs.

9. A method of programming a quantum processor, the quantum processor comprising a plurality of qubits, the method comprising: inducing a persistent current in a programmable persistent current source (PPCS), the PPCS comprising a current storage loop and a compound Josephson junction (CJJ) interrupting the current storage loop at a first connection and a second connection; inducing a current in a first digital to analog converter (DAC) based on a combination of the persistent current from the PPCS and a current from a communicatively coupled first control line; inducing a current in a second DAC based on a combination of the persistent current from the PPCS and a current from a communicatively coupled second control line; programming a first qubit of the plurality of qubits by the first DAC; and programming a second qubit of the plurality of qubits by the second DAC.

10. The method of claim 9, wherein inducing a persistent current in the PPCS comprises inducing a current in an additional PPCS that is communicatively coupled to the PPCS.

11. A superconducting integrated circuit comprising: a superconducting current path forming a loop; and a compound Josephson junction (CJJ) structure interrupting the loop at a first connection and a second connection, the CJJ structure comprising at least four CJJs connected to have equal current path distance between each CJJ and the first and second connections.

12. The superconducting integrated circuit of claim 11 , wherein the at least four CJJs are arranged in parallel.

13. The superconducting integrated circuit of claim 11 , wherein the at least four CJJs are arranged in a nested structure.

14. The superconducting integrated circuit of claim 11 , wherein the CJJ structure has internal symmetry.

15. The superconducting integrated circuit of any one of claims 12 through 14, wherein the at least four CJJs are arranged in a circle around the first and second connections.

16. The superconducting integrated circuit of any one of claims 11 through 14, wherein the CJJ structure comprises at least eight CJJ loops connected to have equal current path distance between each CJJ loop and the first and second connections.

17. The superconducting integrated circuit of any one of claims 11 through 14, wherein the CJJ structure comprises sixteen CJJ loops connected to have equal current path distance between each CJJ loop and the first and second connections.

18. The superconducting integrated circuit of claim 11 , further comprising at least one control line communicatively coupled to provide a flux bias to the CJJ structure.

19. The superconducting integrated circuit of claim 11 , wherein the current loop comprises a high kinetic inductance material.

20. The superconducting integrated circuit of claim 11 , wherein the current loop and the CJJ structure comprise a programmable persistent current source (PPCS).

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