Memory device

Abstract

A memory device is disclosed. The memory device comprises a base layer comprising a ferroactive material and a domain wall bound to a surface of the base layer, the domain wall deformable under the application of deforming stimulus to adopt a stable configuration in the base layer, where the stable configuration defines a discernible or measurable electrical property of the memory device.

Description

MEMORY DEVICEPRIORITY DOCUMENT

[0001] The present application claims priority from Australian Provisional Patent Application No. 2024902385 titled “MEMORY DEVICE” and fded on 31 July 2024, the content of which is hereby incorporated by reference in its entirety.INCORPORATION BY REFERENCE

[0002] The following publication is referred to in the present application and its contents are incorporated by reference in their entirety:• “Nonvolatile Ferroelectric Domain Wall Memory”, Pankaj Sharma, Qi Zhang, Daniel Sando, Chi Hou Lei, Yunya Liu, Jiangyu Li, Valanoor Nagarajan, Jan Seidel, Sci. Adv. Vol 3, e 1700512 (2017).TECHNICAL FIELD

[0003] The present disclosure relates to a memory device for storing information. In a particular form, the present disclosure relates to a memory device based on a ferroactive material.BACKGROUND

[0004] An important consideration in improving the performance and size of data processing and computing devices is the ability to store and retrieve information. Data processing architectures typically involve a volatile memory component such as random access memory (RAM) or static RAM (SRAM) and a non-volatile memory component such as read only memory (ROM). There are many different variants of electronic storage arrangements configured to meet these requirements ranging from electromechanical storage devices (eg, hard disks) to semiconductor based devices such as erasable programmable ROM (EEPROM), flash memory, solid state drives (SSD) and non-volatile RAM (NVRAM).

[0005] There have been many improvements in both reducing the size and increasing the capacity of electronic storage devices. It is not uncommon for a hand-held electronic storage device to be capable of storing terabytes of information. Even so, there is still an ongoing need to further reduce the size and increase the capacity of memory storage devices in line with the constant requirement to further miniaturize and increase the data processing capabilities of computing devices.SUMMARY

[0006] In a first aspect, the present disclosure provides a memory device comprising: a base layer comprising a ferroactive material; and a domain wall bound to a surface of the base layer, the domain wall deformable under an application of a deforming stimulus to adopt a stable configuration in the base layer, wherein the stable configuration defines a discernible or measurable electrical property of the memory device.

[0007] In another form, the domain wall separates the base layer into a first ferroactive domain region and a second ferroactive domain region.

[0008] In another form, the measurable electrical property is a conductance / resistance of the memory device.

[0009] In another form, the domain wall is deformable under the application of the deforming stimulus to adopt a plurality of stable configurations each defining an associated measurable electrical property of the memory device.

[0010] In another form, the domain wall extends through an entire thickness of the base layer.

[0011] In another form, the domain wall extends partway through a thickness of the base layer.

[0012] In another form, the domain wall is bound to the surface of the base layer at a surface binding region of the surface of the base layer.

[0013] In another form, there are more than one surface binding regions binding the domain wall to the surface of the base layer.

[0014] In another form, the surface binding region extends along a domain wall-base layer surface boundary.

[0015] In another form, a surface binding region corresponds to a surface morphology of the base layer.

[0016] In another form, the domain wall is initially formed in the base layer through the application of a wall forming stimulus to the base layer above a coercive value.

[0017] In another form, the domain wall may be erased through the application of a wall removing stimulus to the base layer above the coercive value.

[0018] In another form, the domain wall is formed inherently during formation of the base layer.

[0019] In another form, the memory device further comprises a substrate, wherein the base layer is deposited on the substrate.

[0020] In another form, the substrate and base layer are substantially single crystal materials.

[0021] In another form, the base layer is epitaxially formed on the substrate.

[0022] In another form, the base layer and substrate material properties are selected to generate one or more predetermined ferroactive characteristics of the base layer.

[0023] In another form, the base layer and substrate material properties are selected to impart a strain or stress to the base layer in a predetermined orientation.

[0024] In another form, the stable configuration of the domain wall corresponds to an associated charge state of the domain wall.

[0025] In another form, the deforming stimulus comprises an applied electric field.

[0026] In another form, the memory device further comprises first and second electrical contacts and wherein the domain wall is located at least between the first and second electrical contacts.

[0027] In another form, the first and second electrical contacts are operable to apply an electrical field to deform the domain wall to a stable configuration.

[0028] In another form, the memory device further comprises a third electrical contact operable to apply an electrical field to deform the domain wall to the stable configuration.

[0029] In another form, the deforming stimulus comprises a mechanical stress.

[0030] In another form, the deforming stimulus comprises a thermal gradient.

[0031] In another form, the deforming stimulus comprises a magnetic field.

[0032] In another form, the deforming stimulus comprises an optical or electromagnetic field.

[0033] In a second aspect, the present disclosure provides a method of storing information comprising: determining a deforming stimulus in accordance with the information; andapplying the deforming stimulus to a memory device according to the first aspect to store the information in one or more stable configurations of the memory device.

[0034] In a third aspect, the present disclosure provides a method of reading information comprising: measuring an electrical property of a memory device according to the first aspect, wherein the electrical property corresponds to one or more stable configurations of the memory device corresponding to stored information in the memory device.BRIEF DESCRIPTION OF DRAWINGS

[0035] Embodiments of the present disclosure will be discussed with reference to the accompanying drawings wherein:

[0036] FIGs. 1A and IB are figurative sectional and top perspective views of a memory device in accordance with some embodiments;

[0037] FIGs. 2A and 2B are figurative sectional and top perspective views of another memory device in accordance with some embodiments;

[0038] FIG. 3 is a figurative sectional view of a memory device incorporating a substrate in accordance with some embodiments;

[0039] FIGs. 4A and 4B are figurative section and top views of a memory device in accordance with some embodiments;

[0040] FIG. 5 is a figurative perspective view of a memory device in accordance with some embodiments;

[0041] FIGs. 6A and 6B are plots of spectroscopic I-V curves measured at different locations along the domain wall of the memory device shown in FIG. 5;

[0042] FIG. 7 is a topographical image of a memory device in accordance with some embodiments;

[0043] FIG. 8 is a piezoresponse force microscopy (PFM) in plane image of the memory device shown in FIG. 7 showing the ferroelectric domain structure in accordance with some embodiments;

[0044] FIG. 9 shows a series of conductive atomic force microscopy (c-AFM) images of the memory device illustrated in FIG. 7 showing the effect of increasing bias voltage on the current flow along the domain wall and the device in accordance with some embodiments;

[0045] FIG. 10 is a plot depicting histograms of measured electrical current over the circular electrical contact of the memory device illustrated in FIG. 7 as a function of applied bias in accordance with some embodiments;

[0046] FIG. 11 is a plot of the measured cross-sectional current profdes across the circular electrical contact of the memory device illustrated in FIG. 7 for increasing applied bias voltage in accordance with some embodiments;

[0047] FIG. 12 shows a top plot of the measured current of the memory device illustrated in FIG. 7 as a function of time and a bottom plot of a simultaneously applied stepped bias voltage ramp as a function of the same time scale showing the electrically induced stable electronic transitions in the domain wall in accordance with some embodiments;

[0048] FIG. 13 is a plot of the measured current as a function of the applied stepped bias voltage ramp depicted in FIG. 12 showing the hysteretic, quasi -memristive behaviour of the memory device in accordance with some embodiments;

[0049] FIG. 14 shows a top plot of the measured current of the memory device illustrated in FIG. 7 as a function of time and a bottom plot of the simultaneously applied bias voltage pulses as a function of the same time scale in accordance with some embodiments;

[0050] FIG. 15A is a perspective view of a base layer incorporating a modelled domain wall bound to the surface in accordance with theoretical modelling of a memory device of the type illustrated in FIG. 7 in accordance with some embodiments;

[0051] FIG. 15B are a series of sectional images showing modelled changes to the domain wall profile with increasing normalized electric field E* illustrating deformation of the domain wall in accordance with some embodiments;

[0052] FIG. 16 is a plot of the modelled angle the domain wall makes with respect to the vertical direction as a function of increasing electric field in accordance with some embodiments;

[0053] FIGs. 17A and 17B are figurative sectional and top views of a two terminal memory device in accordance with some embodiments;

[0054] FIGs. 18A and 18B are figurative sectional and top views of a two terminal memory device in accordance with some embodiments;

[0055] FIGs. 19A and 19B are figurative sectional and top views of a two terminal memory device in accordance with some embodiments;

[0056] FIGs. 20A and 20B are figurative sectional and top views of a two terminal memory device in accordance with some embodiments;

[0057] FIGs. 21A and 2 IB are figurative sectional and top views of a two terminal memory device in accordance with some embodiments;

[0058] FIGs. 22A and 22B are figurative sectional and top views of a two terminal memory device in accordance with some embodiments;

[0059] FIGs. 23A and 23B are figurative sectional and top views of a three terminal memory device in accordance with some embodiments;

[0060] FIGs. 24A and 24B are figurative sectional and top views of a three terminal memory device in accordance with some embodiments;

[0061] FIGs. 25A and 25B are figurative sectional and top views of a three terminal memory device in accordance with some embodiments;

[0062] FIGs. 26A and 26B are figurative sectional and top views of a three terminal memory device in accordance with some embodiments;

[0063] FIGs. 27A and 27B are figurative sectional and top views of a three terminal memory device in accordance with some embodiments;

[0064] FIGs. 28A and 28B are figurative sectional and top views of a three terminal memory device in accordance with some embodiments;

[0065] FIGs. 29A and 29B are figurative sectional and top views of a three terminal memory device in accordance with some embodiments; and

[0066] FIGs. 30A and 30B are figurative sectional and top views of a three terminal memory device in accordance with some embodiments.

[0067] In the following description, like reference characters designate like or corresponding parts throughout the figures.DESCRIPTION OF EMBODIMENTS

[0068] Referring now to FIGs. 1A and IB, there are shown figurative sectional and top perspective views of a memory device 100 comprising a base layer 110 comprising a ferroactive material and a domain wall 120 bound to a surface 130 of the base layer 110 in accordance with some embodiments.

[0069] Throughout this specification, the term “ferroactive”, in the context of a ferroactive material, is taken to mean that the material is at least ferroelectric or ferroelastic, but in other examples may also have both ferroelectric and ferroelastic characteristics.

[0070] A ferroelectric material exhibits a spontaneous polarization with the presence of two or more stable states and a hysteresis effect between the measured polarization of the ferroelectric material and an applied electric field. This may be contrasted with a ferromagnetic material which exhibits a hysteresis effect between the measured magnetization of the ferromagnetic material and an applied magnetic field.

[0071] A ferroelastic material displays spontaneous strain with the presence of two or more stable crystal orientations and can transition between crystal orientations under the application of an applied external stress to the ferroelastic material. Importantly, a ferroelastic material exhibits a hysteresis effect between the measured strain of the ferroelastic material and an applied external stress.

[0072] As referred to above, a ferroactive material may have both ferroelectric and ferroelastic properties (and even additionally ferromagnetic or antiferromagnetic properties) and these materials are sometimes referred to as multiferroics. Alternatively, as also referred to above, a ferroactive material may include a material that has solely ferroelectric or a ferroelastic material characteristics.

[0073] Domain wall 120 separates the base layer 110 into two different ferroactive domain regions (ie, first and second ferroactive domain regions 150A, 150B). In the example shown in FIGs. 1A and IB, where the domain wall 120 traverses or extends through the entire thickness of base layer 110, the ferroactive domain regions 150A, 150B proximate to the domain wall 120 will also traverse the thickness of base layer 110.

[0074] Throughout this description, the term “domain wall” is taken to mean the atomically sharp topological interface (of the order of a nanometer wide) that divides or separates a base layer material into two different ferroactive domain regions.

[0075] The type of ferroactive domain regions 150A, 150B will depend on the type of ferroactive material. For a ferroelectric material, the different ferroactive domain regions 150A, 150B will be physical regions of the base layer 110 having different polarization orientations. In the case of aferroelastic material, the different ferroactive domain regions 150A, 15 OB will be physical regions of the base layer 110 having different crystal orientations that are separated by domain wall 120.

[0076] The domain wall 120 is deformable under the application of a deforming stimulus to the base layer 110 to adopt a stable configuration (eg, the deformed stable configuration 120A shown in FIG. 1A). In this example, the stable configuration 120A will define a discernible or measurable electrical property of the memory device 100. As would be appreciated, the deforming stimulus will be below a characteristic binding strength of the domain wall 120 to the associated surface 130. It will be understood that the term “stable” may include “meta-stable” in the sense that the stable configuration need only be stable or persistent for a sufficient duration to store information for the particular application.

[0077] In one example, the measurable electrical property of memory device 100 is the conductance / resistance of the memory device 100 which in turn depends on the conductance / resistance of the domain wall 120.

[0078] In one example, the conductance / resistance of the memory device is determinable by measuring a current for a given applied voltage.

[0079] In one example, the domain wall 120 is deformable under the application of the deforming stimulus into the base layer 110 to adopt more than one stable configuration (eg, see additional stable configurations 120B, 120C shown in the inset of FIG. 1A) where each stable configuration defines an associated measurable electrical property of memory device 100.

[0080] In one example, the domain wall 120 is bound to the surface 130 of the base layer 110 at a surface binding region 121 located on surface 130. As shown in the top perspective view of base layer 110 illustrated in FIG. IB which shows a surface patch of base layer 110, surface binding region 121 may be a discrete location on the surface 130 of base layer. In other examples, the surface binding region 121 may be extended over a length of the domain wall-base layer surface boundary. In other examples, there may be two more surface binding regions located along the domain wall at the domain wall-base layer surface boundary.

[0081] In various examples, the surface binding region 121 may arise due to a change in surface morphology at surface 130 such as step change. In other examples, the surface binding region 121 may arise due to one or more of:• naturally present or artificially created elastic or electrical constraints;• localized stress or strain regions;• the presence of bound polarization and screening charges;• direct mechanical modification of the base layer;• electron and / or ion beam based modification, including morphology and surface shaping of the base layer;• charge or ion implantation in the base layer;• crystal defects in the base layer;• electronic and ionic defects in the base layer; or• the presence of impurities in the base layer.

[0082] In one example, the base layer has a natural stripe textured morphology with repeating morphological steps leading to “peaks” and “valleys” characterizing the topography of the base layer. This type of surface morphology may lead to a modulation of the potential profile seen by the domain wall. The valleys correspond to the local energy minima for wall position (through minimization of the domain wall area and / or domain wall’s charge state), and at these surface regions, the domain wall will bind to the surface.

[0083] Moreover, at these regions, the domain wall will remain bound to the surface even in the presence of an external stimulus (eg, an electric field (voltage)) unless the external stimulus magnitude is above a certain threshold value (eg, electrical field threshold value). Below this threshold value, the domain wall will remain bound to the surface of the base layer, however, the deformed wall may still be deformed below the surface into the base layer to adopt various stable configurations by the application of a suitable deforming stimulus (eg, see FIGs. 1A and 2A insets).

[0084] In other examples, modulation of the potential profile leading to specific positions of local energy minima for domain wall position which may act as surface binding regions may arise due to mechanical or electrical factors or a combination of both factors including naturally or artificially created elastic or electrical constraints; localized stress or strain, interplay between bound polarization and screening charges, charge or ion implantation; crystal defects, electronic and ionic defects, and impurities.

[0085] Referring now to FIGs. 2A and 2B, there are shown figurative sectional and top perspective views of a memory device 200 similar to memory device 100 shown in FIGs. 1A and IB in accordance with some embodiments. Memory device 200 also comprises a base layer 110 comprising a ferroactive material and a domain wall 220 bound in this example at surface binding regions 221, 222 to a surface 130 of the base layer 110. In this example, instead of traversing the thickness of base layer 110, domain wall 220 extends part way through the base layer 110 and then returns to the origin surface 130 at a location offset from where the domain wall 220 commences.

[0086] Similar to memory device 100 of FIGs. 1 A and IB, domain wall 220 separates the base layer 110 into two different ferroactive domain regions 150A, 150B, but in this example, first ferroactive domainregion 150A will be fully contained or enclosed by domain wall 220 and separated from second ferroactive domain region 15 OB.

[0087] In accordance with the present disclosure, the domain wall 220 of memory device 200 is deformable under the application of a deforming stimulus into the base layer 110 to adopt a stable configuration (eg, the deformed stable configuration 220A shown in FIGs. 2A and 2B) defining a discernible or measurable electrical property of the memory device 200. In other examples, domain wall 220 is deformable under the application of the deforming stimulus into the base layer 110 to adopt more than one stable configuration (eg, see additional stable configurations 220B, 220C shown in the inset of FIG. 2A)

[0088] As would be appreciated, a given base layer 110 may have multiple domain walls which may extend through the base layer (eg, see FIGs. 1A and IB) or extend partway and return to the originating surface (eg, see FIGs. 2A and 2B) and where an individual domain wall or selection of domain walls may be deformed under the action of a deforming stimulus to adopt a stable state in accordance with the present disclosure.

[0089] In various examples, the ferroactive material may be selected from families of ferroelectrics, perovskite oxide ferroelectrics, organic ferroelectrics, ferroelectric polymers, Wurtzite ferroelectrics, ferroelastics, multiferroics, or 2D van der Waals ferroactive materials.

[0090] Example ferroactive materials include, but are not limited to: BiFcO,. PbZrxTii.xO3, SrBi2Ta20g, LiNbCb, PbTiCfi, BaTiCfi, LiTaO,. HfCE, PbTiCb / SrTiCb superlattices, Mg-doped ZnO, Mg doped LiNbO3, ScxGal-xN, Boron doped AIN, Scandium doped AIN, HfCE (doped with Zr, Si or other dopants), WTe2, SnTe, SnS, SnSe, Cuhfi^Se, polymorphs of I Sc’,. MoTe2, stacking-engineered ferroelectricity in h-BN / graphene, h-BN / hBN bi or multilayers, or transition metal dichalcogenides moire systems or any combination of the foregoing.

[0091] In one example, the ferroactive material is a wide band gap material (ie, bandgap greater than 2 eV) (eg, ferroactive oxide materials). In another example, the ferroactive material has a band gap greater than 2.5 eV. In another example, the ferroactive material may comprise a layered van der Waals ferroactive material having a bandgap in the range of 1.3 eV - 1.8 eV.

[0092] In one example, the base layer has a single crystal structure. In another example, the base layer has a polycrystalline structure where individual grains in the base layer have a crystal structure but where the grains are preferentially oriented or randomly or semi-randomly oriented. In another example, the base layer has a semi-crystalline structure (eg ferroelectric polymers) displaying ferroactive properties.

[0093] In various examples, the thickness of base layer 110 may be selected from the following ranges including, but not limited to: less than 25 nm, 25 nm - 50 nm, 50 nm - 75 nm, 75 nm - 100 nm, 100 nm - 125 nm, 125 nm - 150 nm, 150 nm - 175 nm, 175 nm - 200 nm, or greater than 200 nm.

[0094] In one example, the deforming stimulus comprises an applied electric field. In this example, the applied electric field may couple to the polarisation of the ferroactive base layer and depending on its characteristics (eg, strength and duration) may be configured to deform the domain wall to adopt one or more stable configurations in the base layer.

[0095] In another example, the deforming stimulus comprises an applied mechanical stress. In this example, the applied mechanical stress may induce stress and / or strain gradients in the ferroactive base layer and depending on its characteristics (eg, strength and duration) may be configured to deform the domain wall to adopt one or more stable configurations in the base layer.

[0096] In another example, the deforming stimulus comprises an applied thermal gradient. In this example, the applied thermal gradient may couple to the polarisation of the ferroactive base layer and depending on its characteristics (eg, strength and duration) may be configured to deform the domain wall to adopt one or more stable configurations in the base layer.

[0097] In another example, the deforming stimulus comprises an applied magnetic field. In this example, the applied magnetic field may couple to the ferroactive base layer through magnetoelectric and / or magnetoelastic coupling which depending on its characteristics (eg, strength and duration) may be configured to deform the domain wall to adopt one or more stable configurations in the base layer.

[0098] In another example, the deforming stimulus comprises an applied optical or electromagnetic field. In this example, the applied optical electromagnetic field may couple to the ferroactive base layer due to coupling arising from the polarisation, electric and magnetic fields, which depending on their characteristics (eg, strength and duration) may be configured to deform the domain wall to adopt one or more stable configurations in the base layer.

[0099] In one example, the domain wall is formed in a ferroactive base layer having predetermined ferroactive properties prior to the formation of the domain wall 120. In various examples, the domain wall 120 may be initially formed in the base layer through the application of a wall forming stimulus to the base layer 110 above a coercive value. In various examples, this coercive value is greater than a characteristic binding strength of the domain wall 120 to the associated surface 130 once the domain wall 120 has been formed.

[0100] In one example, the wall forming stimulus comprises an applied electric field applied having a coercive electric field value above which the ferroactive domain direction in the base layer is reversed.

[0101] In another example, the wall forming stimulus comprises an applied mechanical stress applied having a coercive mechanical stress value above which the ferroactive domain direction in the base layer is reversed.

[0102] In another example, the wall forming stimulus comprises an applied thermal gradient having a coercive thermal gradient or temperature value above which the ferroactive domain direction in the base layer is reversed.

[0103] In another example, the wall forming stimulus comprises an applied magnetic field having a coercive magnetic field value above which the ferroactive domain direction in the base layer is reversed.

[0104] In another example, the wall forming stimulus comprises an applied optical or electromagnetic field having a coercive optical or electromagnetic field value above which the ferroactive domain direction in the base layer is reversed.

[0105] In other examples, the wall forming stimulus may be in the form of any combination of stimuli comprised from an applied electric field, mechanical stress, thermal gradient or temperature, magnetic field, optical or electromagnetic field.

[0106] In one example, where the ferroactive base layer is a substantially ferroelectric material the ferroactive property is the bulk spontaneous polarization of the base layer 110 that may be reversed through the application of a wall forming stimulus in the form of an applied electric field (voltage) above a coercive value in the form of a coercive electric field value defined to be the minimum electric field strength required to reverse ferroelectric domains or polarization in order to form the domain wall. The coercive electric field value in various examples will depend on the type of ferroelectric material selected and the time that an electric field is applied.

[0107] In this example, the coercive voltage is a property related to the coercive electric field and is the minimum voltage value required to reverse ferroelectric domains or polarization. The coercive voltage value depends on various aspects including the type of ferroelectric material, the time that any voltage is applied, and also the thickness of the base layer across which the coercive voltage is applied. Generally, the thinner the base layer, the smaller the required coercive voltage.

[0108] In one example, where the ferroactive base layer is a substantially ferroelastic material, the ferroactive property is the bulk spontaneous strain (due to different stable crystal orientations) of the base layer 110 that may be reversed through the application of a wall forming stimulus in the form of an applied mechanical stress above a coercive value in the form of a coercive stress value defined to be the minimum stress needed to reverse ferroelastic domains or strain in order to form the domain wall. The coercive stress field value in various examples will depend on the type of ferroelastic material selected and the time that the stress is applied.

[0109] In other example, where the ferroactive base layer has both ferroelectric and ferroelastic material characteristics, the ferroactive property comprises both the bulk spontaneous polarization and strain of the base layer that may be reversed through the application of an electric field or mechanical stress or a combination of these in order to form the domain wall.

[0110] In ferroactive materials, the value of spontaneous polarization or strain and the coercive value needed to reverse the ferroactive domain depends on the type of ferroactive material selected.

[0111] In various examples, depending on the ferroelectric material selected, the polarization of base layer may be in the following ranges, but not limited to: less than 0. 1 pC / cm2, 0.1 - 1 pC / cm2, 1 - 10 pC / cm2, 10 - 50 pC / cm2, 50 - 100 pC / cm2, 100 - 150 pC / cm2or greater than 150 pC / cm2.

[0112] In various examples, the coercive electric field value for the ferroelectric base layer (depending on the ferroelectric material selected) may be selected from the following ranges including, but not limited to: less than 1 kV / cm, 1 - 10 kV / cm, 10 - 20 kV / cm, 20 - 50 kV / cm, 50 - 100 kV / cm, 100 - 200 kV / cm, 200 - 500 kV / cm or greater than 500 kV / cm. In various examples, depending on the type and thickness of ferroelectric material, the coercive voltage for the ferroelectric base layer 110 may be selected from the following ranges including, but not limited to: less than 0. 1 V, 0.1 - 5 V, 5 - 10 V, 10 - 50 V, 50 - 100 V, 100 - 200 V or greater than 200 V.

[0113] In various examples, the strain percentage of the ferroelastic base layer (depending on the ferroelastic material selected) may be selected from the following ranges including, but not limited to: less than 0.001%, 0.001 - 0.01%, 0.01 - 0.1%, 0.1 - 1%, 1 - 10%, 10 - 20%, or greater than 20%.

[0114] In various examples, depending on the type and thickness of ferroelastic material, the coercive stress field value for the ferroelastic base layer may be selected from the following ranges including, but not limited to: less than 0.05 MPa, 0.05 - 0.1 MPa, 0.1 - 1 MPa, 1 - 10 MPa, 10 - 100 MPa, 100 - 500 MPa or greater than 500 MPa.

[0115] In another example, one or more domain walls are formed inherently during growth or formation of the base layer. In one example, the inherently formed domain walls may have a well-defined period which in various examples may be selected from the following ranges including, but not limited to: less than 10 nm, 10 nm - 50 nm, 50 nm - 100 nm, 100 nm - 500 nm, 500 nm - 1 pm, 1 pm - 10 pm, 10 pm - 50 pm, 50 pm - 100 pm, or greater than 100 pm. In another example, the spacing and / or configuration of the one or more domain walls may be disordered.

[0116] Referring now to FIG. 3, there is shown a figurative sectional view of a memory device 300 in accordance with some embodiments. In this example, memory device 300 comprises the base layer 110 of memory device 100, 200 deposited on a substrate 370.

[0117] In various examples, the material properties of the base layer 110 and substrate 370 are selected to generate the ferroactive properties of the base layer 110.

[0118] In one example, the respective crystal structures of the base layer and the substrate are selected to generate the ferroactive properties with a selected orientation following epitaxial deposition of the base layer on substrate (eg, by imparting a strain or stress to the base layer in a predetermined orientation). This is due to the substrate / base layer combination imposing the required electrical and mechanical boundary conditions (eg, by epitaxial strain) that during growth of the base layer will stabilise a particular crystalline orientation.

[0119] In one example, the ferroactive property is the base layer polarization and its orientation.

[0120] In one example, the substrate material is chosen to provide charge compensation for the base layer polarization.

[0121] In one example, substrate 370 is formed from an insulator material.

[0122] In one example, substrate 370 is formed from a semiconductor material (eg, Nb-dopedSrTiCfi or Si with p or n doping).

[0123] In various examples, substrate 370 may be selected from:• single crystal oxide substrates (eg, SrTiO,. YAIO3, LaAICh. LaGaO,. LaSrAlCfi, LaSrGaCfi, (LaA103)o.3-(SrAlo.5Tao.503)o.7, NdGaCh, DyScCh, GdScCh - all of the foregoing optionally with Nb or Nd doping);• Si (optionally with p or n doping or platinized);• AI2O3, Yttria-stabilized Zirconia, MgO, TiCf. glass substrate, fused silica, ITO or FTO-coated glass substrate;• polydimethylsiloxane (PDMS); or• polyethylene naphthalate, polyethylene terephthalate, polyimide.

[0124] In one example, the base layer is formed on the substrate by pulse layer deposition (PLD).

[0125] In another example, the base layer is formed on the substrate by molecular-beam epitaxy (MBE).

[0126] In another example, the base layer is formed without an epitaxial relationship to the substrate 370.

[0127] In various other examples, the method of forming the base layer may be selected from:• sputtering (eg, magnetron sputtering);• atomic layer deposition;• chemical vapor deposition (CVD), metalorganic CVD (MOCVD); or• solution processing methods (eg, sol gel, hydrothermal, spray pyrolysis) .

[0128] In other examples, a large “thick” crystal may be formed by the following methods from which a thin fdm may be machined using techniques such as ion slicing:• solid state reaction and sintering;• crystal growth from melt (eg, Bridgmann or Czochralski methods); or• chemical vapor phase growth.

[0129] Referring now to FIGs. 4A and 4B, there are shown figurative sectional and top views of a memory device 400 in accordance with some embodiments. Memory device 400 is similar in configuration to memory device 300 comprising a base layer 410 comprising a ferroactive material and a substrate 470. Memory device 400 further comprises an electrical contact arrangement 480 comprising two electrical contacts 481, 482 formed on base layer 410. In this example, domain wall 420 is bound at one or more surface binding regions located on the surface 430 of the base layer 110 and extends into base layer 110 and through to substrate 470. As depicted, domain wall 420 extends the full thickness of base layer 410 but in other examples domain wall 420 may only extend part way through base layer 410.

[0130] As discussed above, domain wall 420 may be present in the initial as-grown state of the base layer 410. Alternatively, the domain wall 420 may be formed or injected by applying a voltage above the coercive voltage between the two electrical contacts 481 and 482 to the base layer 410 that is initially in a single or monodomain state (ie, only one polarization orientation, eg, P ).

[0131] While domain wall 420 is shown as having a generally planar wall type configuration it will be appreciated that this is just a figurative representation and that domain wall 420 will adopt a shape and configuration in accordance with the material properties of the base layer 410 (eg, crystal structure, and orientation) and the application of any applied electrical field causing the domain wall 420 to deform, flex or warp in the base layer 410.

[0132] In this example, an electrical field (below the threshold field that would potentially release the domain wall from being bound at the surface) may be applied to domain wall 420 by applying a voltage between electrical contacts 481, 482 and the electrical property that may be read that depends on the deformed stable configuration of domain wall 420 is the electrical conductance between electrical contacts 481, 482.

[0133] Referring now to FIG. 5, there is shown a figurative perspective view of a memory device 500 in accordance with some embodiments. As can be seen, memory device 500 shares some configuration aspects with memory device 400 shown in FIGs. 4A and 4B.

[0134] Memory device 500 comprises a substrate 570 formed of SrTiCfi (STO) and a base layer 510 formed of a ferroactive material in the form of an initially (110)-oriented single crystalline BiFcCF (BFO) ferroelectric thin film which in this example has been fabricated on STO substrate 570 employing pulsed laser deposition with no conductive buffer layer.

[0135] Memory device 500 further comprises a first electrical contact 581 formed in this example as a lithographically defined fixed metal Pt electrode and a second electrical contact 582 formed by a movable biased conductive tip (used in this example to characterize memory device 500) acting as a second nanoscale electrode.

[0136] In this example, domain wall 520 is present in the as-prepared state of the base layer separating base layer 510 into a first ferroactive domain region 550A having first ferroactive domain variant P and a second ferroactive domain region 550B having second ferroactive domain variant P2-. This domain wall is contacted at the surface with first and second electrical contacts 581 and 582. In this example configuration, the domain wall 520 is characterized as a 71° ferroelectric domain wall formed in the (110)-oriented single crystalline BFO base layer 510. In this example, since base layer 510 is without any conductive bottom electrode or electrical contact, domain wall 520 forms an electrically conductive wall or path that completes the two-terminal electrical circuit between electrical contacts 581, 582.

[0137] The inset of FIG. 5 shows the two ferroactive domain variants (P and P2-) that arise in the BFO (110) base layer 510 and a domain wall 520.

[0138] As noted before, the domain wall may be present in the initial as-prepared state of the base layer or in another example could be injected by applying a voltage above the coercive voltage (eg. 8-9 V in this material for a separation in this example of a few hundreds of nm between the metal contacts 581, 582) between the two electrical contacts 581, 582 at the surface for the base layer 510 that is initially in the monodomain state (ie, having only one polarization orientation, eg, P and accordingly with no domain wall(s) in the base layer).

[0139] Application of a coercive voltage in this example reverses a part of the mono-domain (eg, P ) between the electrical contacts and creates a differently orientated polarization domain (eg, P2-) that is stable even after the removal of the voltage (noting the fundamental property of ferroelectrics, that is, two or more stable polarization domains / states). These different domain states or variants (P and P2-) are separated by the domain wall 420. At this stage, the two ferroactive domain variants (P and P2“) will arise in the BFO (110) base layer 110 following the formation of the domain wall 520 following the application of a coercive bias voltage value of 8-9 V across electrical contacts 581, 582.

[0140] Other aspects of generating or forming a domain wall in a base layer may be found in “Nonvolatile Ferroelectric Domain Wall Memory”, Sharma et al, the disclosure of which is incorporated by reference int its entirety.

[0141] In this example, electrically conductive 71° domain wall 520 is bound to the surface 530 of the BFO (110) base layer 510 and it lies in the morphological valley (between morphological steps, where the valley represents the position of minimum energy for the domain wall). The domain wall is electrically contacted on one end by the first electrical contact 581 and at the other end by the second electrical contact 582.

[0142] In FIG. 5, domain wall 520 lies in the morphological valley (between morphological steps, and the valley represents the position of minimum energy for domain wall 520), and therefore in this case, the domain wall is bound to the surface along a surface binding region comprising more or less the entire length of the domain wall-base layer surface boundary.

[0143] However, in other examples, domain wall 520 may only be bound to the surface at one or a few other specific surface binding regions and not along its entire surface edge (eg, see domain wall 720 in base layer 710 which will be discussed below where domain wall 720 is bound to the surface at surface binding regions 721, 722, 723).

[0144] Furthermore, domain wall 520 in this example may be effectively erased or removed between the electrical contacts 581, 582 by application of a suitably high bias voltage (eg, in this exampleby the application of an opposite polarity coercive voltage of ~ -8 V to -9 V) across the electrical contacts 581, 582.

[0145] More generally, a domain wall may be erased through the application of a wall removing stimulus to the base layer above the coercive value where the wall removing stimulus may be in the form of an applied electric field, mechanical stress, thermal gradient or temperature, magnetic field, optical or electromagnetic field, or any combination of these different stimuli.

[0146] In this case, the application of an opposite polarity coercive voltage results in a corresponding electric field application of sufficiently high magnitude that is oriented in opposite direction to the previously written second ferroactive domain 2 (P2“) resulting in the second ferroactive domain region shrinking (and first ferroelectric domain growing at the expense of the second domain region) resulting in the removal of the domain wall.

[0147] Referring now to FIGs. 6A and 6B, there are shown plots 600, 650 of the spectroscopic I-V curves 611, 661 measured at different locations along the domain wall 520 of memory device 500 shown in FIG. 5

[0148] In this example, I-V curve 611 is measured at location 521 along domain wall 520 and I- V curve 661 is measured at location 522 along domain wall 520 (see inset of FIG. 5).

[0149] In this example, a rectifying wall current behavior due to the nonohmic metal tip-wall contact is observed and as a result the domain wall current arises at positive tip voltages only (negative voltages are omitted for clarity).

[0150] As can be seen from inspection, the conductivity of domain wall 520 is electrically activated and becomes distinctly enhanced during the reverse bias voltage sweep displaying a pronounced hysteresis effect 620 and a quasi-memristive behavior. The position of the domain wall 520 defined by the intersection of the domain wall 520 and the surface 530 of base layer 510 remains unchanged during acquisition of 611, 661 I-V curves and application of a bias voltage to electrical contacts 581, 582 in the range of a few volts.

[0151] Without wishing to be bound by theory, it is thought that the hysteresis effect 620 observed in FIGs. 6A and 6B in the domain wall conductance originates from electrically driven metastable electronic transitions arising from deformation of the domain wall to adopt different stable configurations. In this manner, a single domain wall bound to the surface of the base layer may be selectively manipulated to adopt a stable configuration which defines an associated electrical property ofthe memory device such as the conductance of the domain wall as measured between (in this example) the electrical contacts.

[0152] Referring now to FIG. 7, there is shown a topographical image of a memory device 700 in accordance with some embodiments. In this example, memory device 700 comprises a base layer 710 of ferroactive material comprising a BiFcCf (110) layer. This type of material displays a typical stripe- textured morphology along which the in-plane polarization component of the naturally occurring ferroactive (ferroelastic / ferroelectric) domain variants arises.

[0153] Memory device 700 further comprises a first electrical contact 781 in the form of Pt / Ti metal pad (whose edge shown in FIG. 7) and a second electrical contact 782 in the form of smaller round metal pad where both contacts 781, 782 are fabricated on the surface 730 of base layer 710 using electron-beam nanolithography and metal deposition techniques. In this example, the spacing between electrical contacts 781, 782 is approximately 200 nm. As can be seen by inspection, the planar metal electrical contacts 781, 782 are oriented parallel to the morphological stripes of base layer 710 to enable field application in the plane of the base layer 710 for controlled injection or formation of domain walls by the application of a coercive voltage (eg + 8-9 V) across electrical contacts 781, 782 as previously discussed. In FIG. 7, the domain wall 720 position is shown by a dashed line and the domain wall 720 has a generally bow shaped or triangular profile.

[0154] The domain wall may be removed or erased by the application of a coercive voltage of the opposite polarity (-8 to -9 V) across electrical contacts 781, 782. In this example, the domain wall may be generated or removed by the application of the coercive voltage of the required polarity for a duration ranging from 0.5 s to a few seconds.

[0155] As can be seen, domain wall 720 formed between electrical metal contacts 781, 782 comprises a head-to-head domain wall 720 with the in-plane component of the polarization in the BiFcCF (110) base layer 710 pointing towards each other at the domain wall 720. This is schematically shown at the bottom of FIG. 7 for BiFcCF (110) where in the polarization vectors are pointing towards each other at the domain wall 720.

[0156] In this example, domain wall 720 is bound to surface 730 at three surface binding regions 721, 722, 723 where at these three locations a portion or domain wall segment of domain wall 720 straightens and effectively falls into the morphological valley (between morphological steps) of the base layer 710 representing a position of minimum energy for the domain wall 720 and functioning to bind the domain wall 720 to the surface 730.

[0157] Referring now to FIG. 8, there is shown the PFM in plane image of the memory device 700 shown in FIG. 7 showing the ferroelectric domain structure in accordance with some embodiments. As can be seen by inspection, domain wall 720 in this example separates base layer 710 into two different ferroactive domain regions 750A, 750B which in this example comprise two different ferroactive (ferroelastic / ferroelectric) domain regions.

[0158] Referring now to FIG. 9, there is shown a series of conductive atomic force microscopy (c-AFM) images 900 of the memory device 700 depicted in FIG. 7 showing the effect of increasing bias voltage on the current flow along the domain wall 720 and the device itself in accordance with some embodiments.

[0159] Moving from left to right of c-AFM images 900, the applied bias voltage is increased from 1.0 V to 4.5 V (which is well below the writing / erasure coercive voltage of ± 8-9 V) and showing that memory device 700 first exhibits conduction at an applied bias voltage of approximately 2 V and then increasing current flow along domain wall 720 as the bias voltage increases to 4.5 V. PFM measurements were simultaneously conducted to track the spatial location of domain wall 720 (shown in dashed line).

[0160] Referring now to FIG. 10, there is shown a plot 1000 depicting histograms 1011, 1012, 1013, 1014, 1015, 1016, 1017 of measured electrical current over the circular electrical contact 782 of the memory device 700 illustrated in FIG. 7 as a function of applied bias voltage in accordance with some embodiments;

[0161] Histograms 1011, 1012, 1013, 1014, 1015, 1016, 1017 of the recorded current distribution over the small circular electrode (as seen in FIG. 9) at the applied bias voltages of 1.0 V, 2.0 V, 2.5 V, 3.0 V, 3.5 V, 4.0 V and 4.5 V respectively. The inset of FIG. 10 shows a plot of average current as a function of bias voltage.

[0162] As can be seen by inspection, the distributions of measured electrical current shown in FIG. 10 in the memory device becomes increasingly broad. At low voltages the current distribution is quite narrow and sharp (eg, see histograms 1011-1013 at bias voltages of 1.0 V - 2.5 V) but becomes wider at higher voltages (eg, see histograms 1016, 1017 at bias voltages of 4.0 V and 4.5 V respectively). Furthermore, the recorded domain wall position at the surface of the base layer shows no observable change upon increasing the bias from +1 V up to +4.5 V over the structure of memory device 700 (see FIG. 9).

[0163] Not wishing to be bound by theory, it would appear that the increasingly broad current distribution that occurs with the increasing applied bias voltage (ie, the quasi-memristive behavior of thedomain wall) does not originate not from any movement of the location of the domain wall as defined by the intersection of the top edge of the domain wall with the surface of the base layer (ie, the domain wallbase layer surface boundary) which stays static, but rather from electrically induced metastable electronic transitions within the domain wall bulk (ie, the wall’s internal structure) arising from deformation of the domain wall into associated stable configurations in the base layer.

[0164] Referring now to FIG. 11, there is shown a plot 1100 of the measured cross-sectional current profiles 1111, 1112, 1113, 1114, 1115, 1116, 1117 across electrical contact 782 of memory device 700 illustrated in FIG. 7 for increasing applied bias voltage.

[0165] In this example, the cross-sectional profdes are measured over dashed line 992 extending over electrical contact 782 as shown in FIG. 9.

[0166] Cross-sectional profdes 1111, 1112, 1113, 1114, 1115, 1116, 1117 correspond to bias voltages of 1.0 V, 2.0 V, 2.5 V, 3.0 V, 3.5 V, 4.0 V and 4.5 V respectively.

[0167] FIG 11 illustrates that the measured current in the device increases in a non-linear fashion with applied bias voltage and agrees with the observed data shown in the inset of FIG. 10, and I-V curves shown in FIGs. 6A and 6B acquired using a tip as the second movable metal contact along the domain wall.

[0168] Referring now to FIG. 12, there is shown atop plot 1200 of the measured electrical current 1220 of memory device 700 illustrated in FIG. 7 as a function of time and a bottom plot 1250 of the simultaneously applied stepped bias voltage ramp 1270 as a function of the same time scale showing the electrically induced stable electronic transitions in the domain wall in accordance with some embodiments.

[0169] Bottom plot 1250 shows the applied bias voltage ramp up 1270 in half volt steps up to 4.5 V and then subsequent ramp down in half volt steps back to 0.0 V over approximately 2000 seconds (ie, a few minutes). Top plot 1200 shows the simultaneously measured electrical current 1220 between the electrical contacts.

[0170] As can be seen by the dashed lines linking plots 1200 and 1250, depending on the history of applied bias voltage 1270, the measured electrical current 1220 is different as indicated by the vertical step (eg, 1225) linking the measured current before the maximum bias voltage of 4.5 V has been applied (ie, on the ramp up) to the measured current after maximum bias voltage of 4.5 V has been applied (ie, on the ramp down).

[0171] Furthermore, the plateaus in the measured electrical current 1220 are close to horizontal at a set applied bias voltage which implies that the current relaxation after the writing of a deformed domain wall “memristive” state on a timescale of minutes is negligible.

[0172] Referring now to FIG. 13, there is shown a plot 1300 of the measured current 1320 as a function of the applied stepped bias voltage ramp depicted in FIG. 12 showing the hysteretic, quasi - memristive behavior of memory device 700 in accordance with some embodiments. The inset shows plot 1300 on a semi-log (y axis is logarithmic) scale.

[0173] As can be seen from inspection of FIGs. 12 and 13, the different domain wall deformed configurations in this example define an associated discernible or measurable electrical property of the memory device which in this case is a unique conduction state of the domain wall and hence the memory device.

[0174] Referring now to FIG. 14, there is shown atop plot 1400 of the measured current 1420 of the memory device 700 illustrated in FIG. 7 as a function of time and a bottom plot 1450 of the simultaneously applied bias voltage pulses 1470 as a function of the same time scale in accordance with some embodiments.

[0175] FIG. 14 shows the multiple conductance states of memory device 700 following the application of consecutive voltage pulses 1470 of amplitude 3 V and 4.5 V (duration in the range of 25-50 seconds) where the electrical voltage is set to zero in between these voltage pulses. As can be seen by inspection, depending on the history and sequence of pulses 1470, several closely spaced unique device conductance states (eg, 1421 vs 1422) are achieved and are seen to be stable over several minutes.

[0176] For instance, the device conductance at 3 V is enhanced after application of a 4.5 V pulse but, however, returns to the initial state after the bias stays zero for about 10 seconds. In a few instances, distinct sharp jumps (eg, 1420) in device conductance after some time has elapsed during a fixed applied bias voltage are seen and point to the electronic nature of the electrically induced wall transitions. It is assumed that the contribution of polarization switching transients is negligible - given that the domain wall position stays constant and the conductance states measured over several minutes are stable.

[0177] As has been observed (eg, see FIG. 9), the surface trace of the domain wall remains unperturbed at applied voltages below the threshold (ie, where the domain wall may be unbound from the surface as a result of applying the threshold voltage / electric field) or the critical (ie, where the domain wall may be removed or erased as a result of applying the critical voltage / electric field) value indicating that the domain wall is bound to the surface of the base layer but where these voltages are neverthelesssufficient to drive the domain wall to deform in the base layer and adopt a stable configuration that defines an electrical property of the memory device such as conduction.

[0178] Not wishing to be bound by theory, but it is theorized that the deformation of the domain wall as it extends throughout the thickness of the base layer results in a change to the domain wall’s charge state. In order to further understand the domain wall changes on binding to the surface of the base layer and subsequent electrical biasing between electrodes, phase-field modelling has been conducted of the memory device configuration shown in FIG. 7.

[0179] Referring now to FIG. 15 A, there is shown a perspective view 1500 of a base layer 1510 incorporating a modelled domain wall 1520 bound to the surface 1530 in accordance with theoretical modelling of a memory device of the type illustrated in FIG. 7 in accordance with some embodiments.

[0180] As can be seen by inspection, phase field modelling results reproduces the bow-shaped domain in theoretical BFO (110) base layer 1510 on the application of a coplanar switching field between the metal electrodes or electrical contacts on the base layer surface 1530.

[0181] In this example, the domain wall 1520 is bound at the surface along the entire curved portion indicated by the arrow in FIG. 15A showing the “wall pinned at the surface” by assuming a fixed distribution of surface charge between the metal electrodes that results in the bow-shaped domain between the metal electrodes (no electric potential is imposed on the two electrodes in this initial step).

[0182] Referring now to FIG. 15B, there are shown a series of sectional images showing modelled changes to the domain wall profile with increasing normalized electric field E* illustrating deformation of the domain wall in accordance with some embodiments.

[0183] As can be seen, the application of an electric field with an orientation similar to that shown in FIG. 7 (in a direction opposite to those produced by fixed surface charges that bind the domain wall 1520 at the surface 1530) reveals the changes to domain wall geometry / conformation and charge state into the depth of the base layer 1510 (ie, in the base layer 1510). A distinct deformation bending of the domain wall 1520 in the base layer 1510 results and this deformation increases with the applied electrical field (ie, moving down FIG. 15B). Under the strong surface binding (due to assumed fixed charges at the surface), the absolute lateral displacement of the domain wall 1520 at the surface 1530 of base layer 1510 however is minimal in agreement with the measured properties of memory device 700 (as an example).

[0184] Referring now to FIG. 16, there is shown a plot 1600 of the modelled angle 1610 that the domain wall makes with respect to the vertical direction (as defined by the thickness of the base layer)close to the surface as a function of increasing electric field in accordance with some embodiments. As can be seen, generally the deformation will increase with the increasing value of the applied electric field as the domain wall flexes or deforms into different stable configurations that in this example define a different resistance / conductance state for the domain wall and accordingly the memory device.

[0185] The warping of the wall leading to a change in its vertical angle is approximately 9° close to the surface under the electric field range considered (ie, below any threshold electrical field / voltage that would unbind the domain wall), and this can certainly drive significant changes in the conductivity across nearly an order of magnitude (eg, as seen in the results shown in FIGs. 12 and 13).

[0186] The phase field modelling, therefore, explains observed behavior of memory devices in accordance with the present disclosure. In the absence of binding the domain wall to the surface of the base layer, the modelling results reveal, as expected, no wall deformation but rather a considerable lateral displacement of the domain wall as the favored polarization domain that is aligned with the applied electric field grows at the expense of the neighboring opposite domain resulting in the entire plane of the domain wall being displaced.

[0187] Referring now to FIGs. 17A and 17B, there are shown figurative sectional and top views of a two terminal memory device 1700 in accordance with some embodiments. In this example, memory device 1700 comprises a substrate 1770 formed of an insulating material and a base layer formed of a ferroactive material. Base layer 1 extends upwardly from the substrate 1770 and is configured to form a base layer island 1710 extending between and filling an intra-contact region between the first and second electrical contacts 1781, 1782 and whose upper surface 1730 is substantially coplanar with the upper surface of electrical contacts 1781, 1782 which are in turn formed on substrate 1770.

[0188] In various examples, the base layer island 1710 may be formed by either self-assembly or patterning fabrication techniques. In various examples, the self-assembly fabrication techniques may involve physical vapor deposition or chemical or solution-based processing methods as noted previously where the synthesis conditions are configured in accordance with the substrate and base layer materials and their respective orientations.

[0189] In various examples, the patterning techniques may involve forming the base layer island from a continuous base layer film on the substrate and then removing material using process such as reactive ion etching, focused ion beam milling, or photolithography / electron-beam lithography. In another example, patterning may be achieved by applying a hard mask on the substrate surface during film growth of the base layer resulting in the base layer island being formed on the substrate at any exposed regions of the mask.

[0190] While in this example, the external dimensions or profile of base layer island 1710 are defined to some extent by the external dimensions or profile of electrical contacts 1781, 1782, it would be appreciated that the base layer island 1710 may adopt many different configurations as long as the ferroactive material comprising the base layer at least extends between electrical contacts 1781, 1782. In one example, the two terminal base layer island configuration or architecture of memory device 1700 may be adopted when polarization of the ferroactive base layer is in the plane of the base layer or at least comprising a polarization component in this plane.

[0191] Referring now to FIGs. 18A and 18B, there are shown figurative sectional and top views of a two terminal memory device 1800 in accordance with some embodiments. In this example, memory device 1800 comprises a substrate 1870 formed of an insulating material and a base layer formed of a ferroactive material and spaced apart first and second electrical contact 1881, 1882 forming an intracontact region between contacts 1881, 1882. In this example, base layer extends upwardly to fill intracontact region and form a base layer pillar 1810 extending between electrical contacts 1881, 1882 and whose upper surface 1830 is substantially coplanar with the upper surface of electrical contacts 1881, 1882.

[0192] In various examples, the base layer pillar 1810 may be formed by either self-assembly or patterning fabrication techniques such as previously described.

[0193] While in this example, the external dimensions or profile of base layer pillar 1810 are defined to some extent by the external dimensions or profile of electrical contacts 1881, 1882, it would be appreciated that the base layer pillar 1810 may adopt many different configurations as long as the ferroactive material comprising the base layer at least extends between electrical contacts 1781, 1782.

[0194] In one example, the two terminal base layer pillar configuration or architecture of memory device 1800 may be adopted when polarization of the ferroactive base layer is in the plane of the base layer or at least comprising a polarization component in this plane.

[0195] Referring now to FIGs. 19A and 19B, there are shown figurative sectional and top views of a two terminal memory device 1900 in accordance with some embodiments. In this example, memory device 1900 comprises a substrate 1970 formed of an insulating material and an electrical contact layer 1982 formed from a conductive material and located on top of the substrate 1970 and effectively forming a first terminal of the memory device 1900. Located on top of electrical contact layer 1982 is a base layer 1910 formed from a ferroactive material and positioned on base layer 1910 is electrical contact 2181 effectively forming the second terminal of memory device 1900.

[0196] In one example, the vertical two terminal configuration or architecture of memory device 1900 may be adopted when polarization of the ferroactive base layer is normal to the plane of the base layer or at least comprising a polarization component normal to this plane.

[0197] As would be appreciated, in this vertical configuration the applied field electric will be out of plane and would couple to out-of-plane / vertical polarization or a polarization component along an out of plane direction across the domain wall. In one example, before forming the top electrical contact 1981, unless there are natural features on the surface to form surface binding regions to bind the domain wall in accordance with the present disclosure then these may need to be artificially created using techniques such as reactive ion etching, focused ion beam milling or other related methods.

[0198] Referring now to FIGs. 20A and 20B, there are shown figurative sectional and top views of a two terminal memory device 2000 in accordance with some embodiments. In this example, and similar to memory device 1900, memory device 2000 comprises a substrate 2070 formed of an insulating material and an electrical contact layer 2082 formed from a conductive material and located on top of the substrate 2070 and effectively forming a first terminal of the memory device 2000.

[0199] By contrast to memory device 1900 and analogous to memory device 1700, the base layer formed on electrical contact layer 2082 is configured as a base layer island 2010 that in turn supports electrical contact 2081 which effectively forms the second terminal of memory device 2000. In this example, the outer profile of base layer island 2010 substantially matches the outer profile or form of electrical contact 2081 but as would be appreciated the base layer island 2010 may be larger or have a different shape to electrical contact 2081.

[0200] Similar to memory device 1900, in one example the vertical two terminal base layer island configuration or architecture of memory device 2000 may be adopted when polarization of the ferroactive base layer is normal to the plane of the base layer or at least comprising a polarization component normal to this plane as the applied field electric will be out of plane and would couple to out- of-plane / vertical polarization or a polarization component along an out-of plane direction across the domain wall. Additionally, and similar to memory device 1900, surface binding regions may need to be artificially created using techniques such as reactive ion etching, focused ion beam milling or other related methods.

[0201] Referring now to FIGs. 21A and 2 IB, there are shown figurative sectional and top views of a two terminal memory device 2100 in accordance with some embodiments. In this example, memory device 2100 comprises a substrate 2170 formed of an insulating material and an electrical contact layer 2182 formed from a conductive material and located on top of the substrate 2170 and effectively forming a first terminal of the memory device 2100. Located on top electrical contact layer 1982 is a base layerformed from a ferroactive material and positioned on base layer 1910 is electrical contact 1981 effectively forming the second terminal of memory device 1900.

[0202] In this example, a central portion of base layer extends upwardly to form a base layer pillar 2110 (eg, see also FIG. 18 A) extending between electrical contact layer 2182 and electrical contact 2181 and whose outer profde or form substantially matches the outer profde or form of electrical contact 2181 but as would be appreciated the base layer pillar 2110 may be larger or have a different shape to electrical contact 2181.

[0203] Similar to memory devices 1900, 2000, in one example the vertical two terminal base layer pillar configuration or architecture of memory device 2000 may be adopted when polarization of the ferroactive base layer is normal to the plane of the base layer or at least comprising a polarization component normal to this plane as the applied field electric will be out of plane and would couple to out- of-plane / vertical polarization or a polarization component along an out-of plane direction across the domain wall. Additionally, and similar to memory devices 1900, 2000, surface binding regions may need to be artificially created using techniques such as reactive ion etching, focused ion beam milling or other related methods.

[0204] Referring now to FIGs. 22A and 22B, there are shown figurative sectional and top views of a two terminal memory device 2200 in accordance with some embodiments. In this example, memory device 2200 comprises a substrate 2270 formed of an insulating material. Memory device 2200 is similar to memory device 2000 except that electrical contact layer 2282 is confined to have the same outer profile or form as base layer island 2210 and electrical contact 2281 forming in combination a sandwich configuration extending upwardly from substrate 2270.

[0205] Similar to memory devices 1900, 2000, 2100, in one example the vertical two terminal sandwich configuration or architecture of memory device 2200 may be adopted when polarization of the ferroactive base layer is normal to the plane of the base layer or at least comprising a polarization component normal to this plane as the applied field electric will be out of plane and would couple to out- of-plane / vertical polarization or a polarization component along an out of plane direction across the domain wall. Additionally, and similar to memory devices 1900, 2000, 2100, surface binding regions may need to be artificially created using techniques such as reactive ion etching, focused ion beam milling or other related methods.

[0206] Referring now to FIGs. 23A and 23B, there are shown figurative sectional and top views of a three terminal memory device 2300 in accordance with some embodiments. In this example, memory device 2300 comprises a substrate 2370 formed of an insulating material and a base layer 2310 formed of a ferroactive material.

[0207] Formed on base layer 2310 are source (S) 2381, drain (D) 2382 and gate (G) 2383 electrical contacts.

[0208] In one example, a domain wall (or multiple domain walls) may be injected and extend between or bridge source and drain electrical contacts 2381, 2382 following application of a coercive voltage across contacts 2381, 2382 such as previously described. In accordance with the present disclosure, the injected or generated domain wall will be stable and bound at the surface at one or more surface binding regions and the formed domain wall will form a conductive channel between the source and drain electrical contacts 2381 2382.

[0209] Once injected, the third terminal or electrical contact 2383 may be used to apply a gating electric field to deform the domain wall generated between source and drain contacts 2381, 2382 in the base layer into different stable configurations (eg, see FIGs. 1A and 2A). Each of these stable deformed wall configurations will define an associated electrical property of the device, eg, the resistance / conductance of the channel connecting source and drain electrical contacts 2381, 2382. In this manner, memory device 2300 would function as a multistate non-volatile memory device.

[0210] In one example, the upper surface of the base layer 2310 is configured to be substantially co-planar with S, D and G contacts 2381, 2382 and 2383 (eg, see memory device 1800 in FIGs. 18A and 18B).

[0211] In another example, portions of base layer 2310 extends upwardly to form respective base layer pillars (eg, see also FIG 21A) extending between substrate 2370 and S, D and G contacts 2381, 2382, 2383 and whose outer profile or form substantially matches the outer profile or form of these contacts but as would be appreciated individual base layer pillars may be larger or have a different shape to the respective contact 2381, 2382, 2383.

[0212] Referring now to FIGs. 24A and 24B, there are shown figurative sectional and top views of a three terminal memory device 2400 in accordance with some embodiments. In this example, memory device 2400 comprises a substrate 2470 formed of an insulating material and a gate layer 2483 formed from a conductive material and located on top of the substrate 2470 and effectively forming a G contact for the memory device 2400. Formed on top of gate layer 2483 is a base layer 2410 formed from a ferroactive material and on base layer 2410 are source (S) contact 2481 and drain (D) contact 2482.

[0213] In one example, the base layer 2410 formed on electrical G layer 2483 is configured as individual base layer islands that in turn support S contact 2481 and D contact 2482 respectively (eg, see memory device 2000 in FIGs. 20A and 20B). In this example, the outer profiles of the base layer islandssubstantially match the outer profile or form of the S and D contacts 2481, 2482 but as would be appreciated the base layer island may be larger or have a different shape to these contacts as required.

[0214] In another example, portion of base layer 2410 extends upwardly to form base layer pillars (eg, see also FIG 21 A) extending between G layer 2483 and respective S and D contact 2481, 2482 and whose outer profile or form substantially matches the outer profile or form of these contacts but as would be appreciated the base layer pillar may be larger or have a different shape to the respective contacts 2481, 2482.

[0215] Similar to memory device 2300, following forming of a domain wall (or multiple domain walls) extending between source and drain electrical contacts 2481, 2482 following the application of a relevant coercive voltage the electrical gate contact 2383 may be used to apply a gating electric field to deform the domain wall generated between electrical contacts 2481, 2482 in the base layer into different stable configurations. Each of these stable deformed wall configurations will then define an associated electrical property of the device, eg, the resistance / conductance of the channel connecting source and drain electrical contacts 2481, 2482. In this manner, memory device 2400 would function as a multistate non-volatile memory device.

[0216] Referring now to FIGs. 25A and 25B, there are shown figurative sectional and top views of a three terminal memory device 2500 in accordance with some embodiments. Memory device 2500, similar to memory device 2400, comprises a substrate 2570 formed of an insulating material and a gate layer 2583 formed from a conductive material and located on top of the substrate 2570 and effectively forming a G contact for the memory device 2500. Instead of being formed on top of gate layer 2583 as in memory device 2400, there is an intermediate or buffer layer 2595 formed of a dielectric material and the base layer 2510 is then formed on top of this buffer layer 2595. Source (S) contact 2581 and drain (D) contact 2582 are then located on base layer 2510.

[0217] In various examples, buffer layer 2595 may be formed from single oxide substrates as referred to previously or other appropriately doped semiconducting materials. In various examples, the buffer layer 2595 may be epitaxially formed on gate layer 2583 and base layer 2510 then epitaxially formed on buffer layer 2595 using deposition techniques such as PLD or MBE.

[0218] Similar to memory devices 2300, 2400, following forming of a domain wall (or multiple domain walls) extending between source and drain electrical contacts 2581, 2582 following the application of a relevant coercive voltage the electrical gate layer 2583 may be used to apply a gating electric field to deform the domain wall generated between electrical contacts 2581, 2582 in the base layer into different stable configurations. In this example, buffer layer 2595 functions to increase the electric field available to deform the domain wall.

[0219] Each of these stable deformed wall configurations will then define an associated electrical property of the device, eg, the resistance / conductance of the channel connecting source and drain electrical contacts 2581, 2582. In this manner, memory device 2500 would function as a multistate non-volatile memory device.

[0220] Referring now to FIGs. 26A and 26B, there are shown figurative sectional and top views of a three terminal memory device 2600 in accordance with some embodiments. In this example, memory device 2600 comprises a substrate 2670 formed of an insulating material and a base layer 2610 formed of a ferroactive material. Formed on base layer 2610 are source (S) 2681, drain (D) 2682 and gate (G) 2683 electrical contacts.

[0221] In one example, a domain wall (or multiple domain walls) may be injected and extend between or bridge source and drain electrical contacts 2681, 2682 following application of a coercive voltage across contacts 2681, 2682 such as previously described. In accordance with the present disclosure, the injected or generated domain wall will be stable and bound at the surface at one or more surface binding regions and the formed domain wall will form a conductive channel between the source and drain electrical contacts 2681 2682.

[0222] Memory device 2600, while similar to FIGs. 23A and 23B, features a gate contact 2683 straddling the entire gap between and in close proximity to the source and drain contacts 2681, 2682. In such a device, a wall (or multiple walls) may be injected between the source and drain contacts by applying a wall forming stimulus (eg, a coercive electric field or voltage), and the third terminal gate contact 2683 would be used to gate and deform the walls. The injected or generated domain wall(s) will be stable and bound at the surface at one or more surface binding regions and the formed domain wall will form a conductive channel between the source and drain electrical contacts .

[0223] The configuration of memory device 2600 may be adopted to induce wall deformation over most of the source-drain gap G at a lower wall deforming stimulus and increase the contrast or difference between measurable electrical properties of the device (ie, higher resistance / conductivity contrast between multiple stable states). The resulting configuration will depend on a range of factors, including the nature and orientation of the ferroactive base layer 2610, which, among other things, displays an in-plane polarization or at least an in-plane component of the polarization.

[0224] Referring now to FIGs. 27A and 27B, there are shown figurative sectional and top views of a three terminal memory device 2700 in accordance with some embodiments. In this example, memory device 2700 comprises a substrate 2770 formed of an insulating material and a base layer 2710 formed of a ferroactive material. Formed on base layer 2710 are source (S) 2781, drain (D) 2782 and gate (G) 2783 electrical contacts.

[0225] In one example, a domain wall (or multiple domain walls) may be injected and extend between or bridge source and drain electrical contacts 2781, 2782 following application of a coercive voltage across contacts 2781, 2782 such as previously described. In accordance with the present disclosure, the injected or generated domain wall will be stable and bound at the surface at one or more surface binding regions and the formed domain wall will form a conductive channel between the source and drain electrical contacts 2781,2782.

[0226] Memory device 2700, while similar to the two terminal device 1800 shown in FIGs. 18A and 18B, features three electrical contacts 2781, 2782, 2783 with different positions relative to the base layer pillar 2710A, which can be formed either through self-assembly or the patterning techniques noted before. In such a device, a wall forming stimulus (eg, a coercive electric field or voltage), is applied between the source-drain terminals 2781, 2782 at the same potential and the gate terminal 2783. This will lead to the creation of a ferroactive domain and a pair of domain walls, with a first domain wall between the gate 2783 and source 2781 electrical contacts, and a second domain wall between the gate 2783 and drain 2782 electrical contacts.

[0227] On increasing wall forming stimulus further, these ferroactive domains are expected to coalesce and form a domain wall between the base pillar 2710A and underlying substrate 2770 and as a result connecting the source 2781 and drain 2782 terminal at one of its ends. Once the source 2781 and drain 2782 terminals are connected through the wall, the gate 2783 contact can be used to apply the deforming stimulus to enable the domain wall to adopt different stable configurations. The injected or generated domain wall will be stable and bound at the interface between the base layer pillar 2710A and the underlying base layer 2710, at one or more binding regions, and the formed domain wall will form a conductive channel between the source and drain electrical contacts 2781, 2782.

[0228] The configuration of memory device 2700 may be adopted to enable wall deformation over some or the entire base layer pillar 2710A, leading to multiple stable states and large device currents (e.g. compared to memory device 2300 shown in FIGs. 23A and 23B and memory device 2600 shown in FIGs. 26A and 26B) for fast device operation. The resulting configuration will depend on a range of factors, including the nature and orientation of the ferroactive base layer 2710, which, among other things, displays an in-plane polarization or at least an in-plane component of the polarization.

[0229] Referring now to FIGs. 28A and 28B, there are shown figurative sectional and top views of a three terminal memory device 2800 in accordance with some embodiments. In this example, memory device 2800 comprises a substrate 2870 formed of an insulating material and a base layer 2810 formed of a ferroactive material. Formed on base layer 2810 are source (S) 2881, drain (D) 2882 and gate (G) 2883 electrical contacts.

[0230] In one example, a domain wall (or multiple domain walls) may be injected and extend between or bridge source and drain electrical contacts 2881, 2882 following application of a coercive voltage across contacts 2881, 2882 such as previously described. In accordance with the present disclosure, the injected or generated domain wall will be stable and bound at the surface at one or more surface binding regions and the formed domain wall will form a conductive channel between the source and drain electrical contacts 2881 2882.

[0231] Memory device 2800, while similar to the memory device 2700 shown in FIGs. 27A and 27B, encapsulates or bounds the base layer pillar 2810A at its sides, between source 2881 and drain 2882 contacts. In this example, gate 2883 contact is positioned directly over the base layer pillar 2810A. Base layer pillar 2810A can be formed either through self-assembly or the patterning techniques noted before. In such a device, a domain wall (or multiple walls) may be injected between the source 2881 and drain 2882 contacts by applying a wall-forming stimulus (eg, a coercive electric field or voltage), and the third electrical contact 2983 may be used to gate and deform the domain walls.

[0232] The injected or generated domain wall(s) will be stable and bound at the interface between the base layer pillar 2810A and the underlying base layer 2810, at one or more binding regions, and the formed domain wall will form a conductive channel between the source 2881 and drain 2882 electrical contacts. In various examples, the configuration of memory device 2800 may be adopted to enable: i) the gate 2883 contact to exert a greater degree of control over wall deformation; ii) larger device currents (eg, compared to the memory devices of FIGs. 23A and 23B, FIGs. 26A and 26B and FIGs. 27A and 27B) for fast device operation; and iii) less gate leakage current (compared to FIGs. 27A and 27B).This configuration may be used and will depend on a range of factors, including the nature and orientation of the ferroactive base layer 2810, which, among other things, displays an in -plane polarization or at least an in-plane component of the polarization.

[0233] Referring now to FIGs. 29A and 29B, there are shown figurative sectional and top views of a three terminal memory device 2900 in accordance with some embodiments. In this example, memory device 2900 comprises a substrate 2970 formed of an insulating material and a base layer 2910 formed of a ferroactive material. Formed on base layer 2910 are source (S) 2981, drain (D) 2982 and gate (G) 2983 electrical contacts.

[0234] In one example, a domain wall (or multiple domain walls) may be injected and extend between or bridge source and drain electrical contacts 2981, 2982 following application of a coercive voltage across contacts 2981, 2982 such as previously described. In accordance with the present disclosure, the injected or generated domain wall will be stable and bound at the surface at one or moresurface binding regions and the formed domain wall will form a conductive channel between the source and drain electrical contacts 2981 2982.

[0235] The configuration of memory device 2900 is similar to memory device 2800 shown in FIGs. 28A and 28B, albeit with smaller electrical contacts 2981, 2982, 2983 in comparison to the dimensions of the base layer pillar 2910. The configuration of memory device 2900 may be adopted, apart from the features already noted with respect to memory device 2800 shown in FIGs. 28A and 28B, to enable a much higher planar 3 -terminal device density, avoiding edge -related or fringing effects, leading to more uniform device operation and characteristics.

[0236] Referring now to FIGs. 30A and 30B, there are shown figurative sectional and top views of a three terminal memory device 3000 in accordance with some embodiments. In this example, memory device 3000 comprises a substrate 3070 formed of an insulating material and a base layer 3010 formed of a ferroactive material. Formed on base layer 3010 are source (S) 3081, drain (D) 3082 and gate (G) 3083 electrical contacts.

[0237] In one example, a domain wall (or multiple domain walls) may be injected and extend between or bridge source and drain electrical contacts 3081, 3082 following application of a coercive voltage across contacts 3081, 3082 such as previously described. In accordance with the present disclosure, the injected or generated domain wall will be stable and bound at the surface at one or more surface binding regions and the formed domain wall will form a conductive channel between the source and drain electrical contacts 3081 3082.

[0238] Memory device 3000 is similar in configuration to memory device 2800 shown in FIGs. 28A and 28B and memory device 2900 shown in FIGs. 29A and 29B but instead comprises a base layer island 3010 in a three-terminal device configuration. Base layer island 3010 may be formed either through self-assembly or the patterning techniques noted before. In such a device, a wall (or multiple walls) may be injected between the source 3081 and drain 3082 electrical contacts by applying a wallforming stimulus (eg, a coercive electric field or voltage), and the third gate 3083 electrical contact would be used to gate and deform the one or more domain walls.

[0239] The injected or generated domain wall will be stable and bound at one or more surface binding regions, and the formed domain wall will form a conductive channel between the source 3081 and drain 3082 electrical contacts. The device configuration of memory device 3000 may in various examples be adopted to enable: i) the gate contact to exert a greater degree of control over wall deformation; ii) larger device currents; iii) less gate leakage current; andiv) a much higher planar 3 -terminal device density.This configuration may be used and will depend on a range of factors, including the nature and orientation of the ferroactive base layer, which, among other things, displays an in-plane polarization or at least an in-plane component of the polarization.

[0240] Considerations that may go into determining whether a given memory device configuration or architecture should be adopted include, but are not limited to one or more of the following:• the selection and orientation of the particular ferroactive material;• the type and number of ferroactive domain wall;• the expected Neel or Ising like polarization evolution at and across the domain wall;• the requirement to achieve intricate or non-trivial polarization textures and domain walls (eg, center convergent or divergent domains or crossed domain walls);• the choice and orientation of substrate materials;• device requirements (eg, two or three terminal);• integration and compatibility considerations a memory device architecture and compatibility with Si-based CMOS platforms; or• requirement to minimize interference (leakage current sneak paths) between neighboring memory devices in a large M x N array.

[0241] As is apparent, memory devices in accordance with the present disclosure provide an alternative nanoscale electronic storage mechanism based on the manipulation of a domain wall in a ferroactive materials where an electric property of the memory device may be “written” or stored by application of a suitable application of a deforming stimulus (eg, voltage / electric field) to the memory device in accordance with the information to be stored and then the information subsequently “read” by measuring an electrical property of the memory device such as its conductance to form a non-volatile memory device.

[0242] In some examples of a memory device in accordance with the present disclosure, the domain wall, when subjected to an applied voltage can be deformed into multiple stable states. Each such state defines a unique resistance state, thus facilitating multi-state data storage within a single device. As a result, the data storage densities of such memory devices may be significantly enhanced compared to those achievable with traditional binary bits.

[0243] In some examples of a memory device in accordance with the present disclosure, low- voltage read operations to determine the electronic state of the domain wall and the overall device status are enabled as a result ensuring energy-efficient data retrieval processes.

[0244] In some examples of a memory device in accordance with the present disclosure, the active element of the device is a domain wall that is only a few nanometers wide. As such, the size of the device / metal contacts may be as small as the active element itself as a result enabling ultrahigh data storage densities.

[0245] In some examples of a memory device in accordance with the present disclosure, the need for repetitive domain wall injection or erasure protocols for domain wall -based data encoding is eliminated resulting in much simpler, energy-efficient wall device architectures.

[0246] As would be appreciated, examples of memory devices in accordance with the present disclosure enable further miniaturization including the provision of stable domain structures with reduced creep and minimal needed wall warping for memristor functionality.

[0247] In addition, examples of memory devices in accordance with the present disclosure present a low power vertically integrated alternative to current semiconductor devices for providing memory functionality which in one example be applied to applications such as neuromorphic computing reproducing brain-inspired architectures for data processing.

[0248] The reference to any prior art in this specification is not, and should not be taken as, an acknowledgement or any form of suggestion that such prior art forms part of the common general knowledge.

[0249] It will be understood that the terms “comprise” and “include” and any of their derivatives (e.g. comprises, comprising, includes, including) as used in this specification, and the claims that follow, is to be taken to be inclusive of features to which the term refers, and is not meant to exclude the presence of any additional features unless otherwise stated or implied.

[0250] In some cases, a single embodiment may, for succinctness and / or to assist in understanding the scope of the disclosure, combine multiple features. It is to be understood that in such a case, these multiple features may be provided separately (in separate embodiments), or in any other suitable combination. Alternatively, where separate features are described in separate embodiments, these separate features may be combined into a single embodiment unless otherwise stated or implied. This also applies to the claims which can be recombined in any combination. That is a claim may be amended to include a feature defined in any other claim. Further a phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.

[0251] It will be appreciated by those skilled in the art that the disclosure is not restricted in its use to the particular application or applications described. Neither is the present disclosure restricted in its preferred embodiment with regard to the particular elements and / or features described or depicted herein. It will be appreciated that the disclosure is not limited to the embodiment or embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the scope as set forth and defined by the following claims.

Claims

CLAIMS1. A memory device comprising: a base layer comprising a ferroactive material; and a domain wall bound to a surface of the base layer, the domain wall deformable under an application of a deforming stimulus to adopt a stable configuration in the base layer, wherein the stable configuration defines a discernible or measurable electrical property of the memory device.

2. The memory device of claim 1, wherein the domain wall separates the base layer into a first ferroactive domain region and a second ferroactive domain region.

3. The memory device of claims 1 or 2, wherein the measurable electrical property is a conductance / resistance of the memory device.

4. The memory device of any one of claims 1 to 3, wherein the domain wall is deformable under the application of the deforming stimulus to adopt a plurality of stable configurations each defining an associated measurable electrical property of the memory device.

5. The memory device of any one of claims 1 to 4, wherein the domain wall extends through an entire thickness of the base layer.

6. The memory device of any one of claims 1 to 4, wherein the domain wall extends partway through a thickness of the base layer.

7. The memory device of any one of the preceding claims, wherein the domain wall is bound to the surface of the base layer at a surface binding region of the surface of the base layer.

8. The memory device of claim 7, wherein there are more than one surface binding regions binding the domain wall to the surface of the base layer.

9. The memory device of claim 7, wherein the surface binding region extends along a domain wall- base layer surface boundary.

10. The memory device of any one of claims 7 to 9, wherein a surface binding region corresponds to a surface morphology of the base layer.

11. The memory device of any one of the preceding claims, wherein the domain wall is initially formed in the base layer through the application of a wall forming stimulus to the base layer above a coercive value.

12. The memory device of claim 11, wherein the domain wall may be erased through the application of a wall removing stimulus to the base layer above the coercive value.

13. The memory device of any one of claims 1 to 10, wherein the domain wall is formed inherently during formation of the base layer.

14. The memory device of any one of the preceding claims, further comprising a substrate, wherein the base layer is deposited on the substrate.

15. The memory device of claim 14, wherein the substrate and base layer are substantially single crystal materials.

16. The memory device of claim 15, wherein the base layer is epitaxially formed on the substrate.

17. The memory device of claim 16, wherein the base layer and substrate material properties are selected to generate one or more predetermined ferroactive characteristics of the base layer.

18. The memory device of claim 17, wherein the base layer and substrate material properties are selected to impart a strain or stress to the base layer in a predetermined orientation.

19. The memory device of any one of claims 1 to 18, wherein the stable configuration of the domain wall corresponds to an associated charge state of the domain wall.

20. The memory device of any one of claims 1 to 19, wherein the deforming stimulus comprises an applied electric field.

21. The memory device of claim 20, further comprising first and second electrical contacts and wherein the domain wall is located at least between the first and second electrical contacts.

22. The memory device of claim 21, wherein the first and second electrical contacts are operable to apply an electrical field to deform the domain wall to a stable configuration.

23. The memory device of claim 21 or 22, further comprising a third electrical contact operable to apply an electrical field to deform the domain wall to the stable configuration.

24. The memory device of any one of claims 1 to 19, wherein the deforming stimulus comprises a mechanical stress.

25. The memory device of any one of claims 1 to 19, wherein the deforming stimulus comprises a thermal gradient.

26. The memory device of any one of claims 1 to 19, wherein the deforming stimulus comprises a magnetic field.

27. The memory device of any one of claims 1 to 19, wherein the deforming stimulus comprises an optical or electromagnetic field.

28. A method of storing information comprising: determining a deforming stimulus in accordance with the information; and applying the deforming stimulus to a memory device according to any one of claims 1 to 27 to store the information in one or more stable configurations of the memory device.

29. A method of reading information comprising: measuring an electrical property of a memory device according to any one of claims 1 to 27, wherein the electrical property corresponds to one or more stable configurations of the memory device corresponding to stored information in the memory device.

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