Pixel circuit and drive method therefor, display substrate, and display apparatus

Abstract

Provided in the present disclosure is a pixel circuit, used for driving N light-emitting elements connected in series to emit light; a first electrode of the ith light-emitting element is coupled to a second electrode of the (i-1)th light-emitting element, N being an integer greater than 1, and i being an integer greater than 1 and less than or equal to N. The pixel circuit comprises: a first control circuit (10) and N-1 second control circuits (20-1, 20-2). The first control circuit (10) is coupled to a first electrode of a first light-emitting element (D1) amongst the N light-emitting elements, and is configured to provide a drive signal to the N light-emitting elements. The (i-1)th second control circuit is coupled to the first electrode of the ith light-emitting element, and is configured to adjust a drive signal provided to the ith light-emitting element.

Description

Pixel circuit, driving method thereof, display substrate and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a pixel circuit, a driving method thereof, a display substrate and a display device. BACKGROUND

[0002] Micro light emitting elements (LED) are a new generation of display technology, such as micro light emitting diode (Micro LED) and mini light emitting diode (Mini LED), which have the advantages of small size and high brightness. Micro LED display has gradually become a hot spot in the field of display panels, and is mainly applied in the fields of augmented reality (AR), virtual reality (VR), television (TV) and outdoor display.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] The present embodiment provides a pixel circuit, a driving method thereof, a display substrate and a display device.

[0006] In one aspect, the present embodiment provides a pixel circuit for driving N light emitting elements connected in series to emit light, a first electrode of an i-th light emitting element in the N light emitting elements is coupled with a second electrode of an (i-1)-th light emitting element, N is an integer greater than 1, and i is an integer greater than 1 and less than or equal to N. The pixel circuit comprises a first control circuit and N-1 second control circuits. The first control circuit is coupled with a first electrode of a first light emitting element in the N light emitting elements and configured to provide a driving signal to the N light emitting elements. An (i-1)-th second control circuit in the N-1 second control circuits is coupled with a first electrode of an i-th light emitting element in the N light emitting elements and configured to adjust the driving signal provided to the i-th light emitting element. The first control circuit comprises a first data writing sub-circuit, a first driving transistor and a first capacitor. The first data writing sub-circuit is configured to write a first data signal provided by a first first data terminal to a first node under the control of a first scan line. A gate of the first driving transistor is coupled with the first node, a first pole of the first driving transistor is coupled with a first first power supply input terminal, and a second pole of the first driving transistor is coupled with a first electrode of the first light emitting element. A first electrode of the first capacitor is coupled with the first node, and a second electrode of the first capacitor is coupled with a storage voltage line.

[0007] In some example embodiments, the first data write-in sub-circuit comprises: a first switch transistor, a gate of the first switch transistor is coupled with the first scan line, a first pole of the first switch transistor is coupled with the first data terminal, and a second pole of the first switch transistor is coupled with the first node. Alternatively, the first data write-in sub-circuit comprises: a first N-type transistor and a first P-type transistor; the first scan line comprises a first first scan line and a first second scan line. A gate of the first N-type transistor is coupled with the first first scan line, and a gate of the first P-type transistor is coupled with the first second scan line; a first pole of the first N-type transistor and a first pole of the first P-type transistor are coupled with the first data terminal, and a second pole of the first N-type transistor and a second pole of the first P-type transistor are coupled with the first node.

[0008] In some example embodiments, the i-1th second control circuit is coupled with the i th first data terminal, the i-1th second data terminal, the i th first power input terminal and the i-1th second power input terminal, and is configured to increase the driving signal provided to the i th light emitting element by using the first power signal provided by the i th first power input terminal under the control of the i th first data terminal, or to decrease the driving signal provided to the i th light emitting element by using the second power signal provided by the i-1th second power input terminal under the control of the i-1th second data terminal.

[0009] In some example embodiments, the i-1th second control circuit comprises: a charging circuit and a discharging circuit. The charging circuit of the i-1th second control circuit is coupled with the i th first data terminal and the i th first power input terminal, and is configured to increase the driving signal provided to the i th light emitting element by using the first power signal provided by the i th first power input terminal under the control of the i th first data terminal when the gray scale of the i th light emitting element is higher than the gray scale of the i-1th light emitting element. The discharging circuit of the i-1th second control circuit is coupled with the i-1th second data terminal and the i-1th second power input terminal, and is configured to decrease the driving signal provided to the i th light emitting element by using the second power signal provided by the i-1th second power input terminal under the control of the i-1th second data terminal when the gray scale of the i th light emitting element is lower than the gray scale of the i-1th light emitting element.

[0010] In some example embodiments, the charging circuit of the i-1th second control circuit comprises a second data writing sub-circuit, a second storage sub-circuit and a second driving sub-circuit; the second data writing sub-circuit, the second storage sub-circuit and the second driving sub-circuit are coupled with the same node. The second data writing sub-circuit is further coupled with the i th first data terminal and the i th scanning line, and is configured to write the second data signal provided by the i th first data terminal into the second storage sub-circuit under the control of the i th scanning line when the gray scale of the i th light emitting element is higher than the gray scale of the i-1th light emitting element. The second storage sub-circuit is further coupled with a storage voltage line, and is configured to store the written second data signal. The second driving sub-circuit is further coupled with the i th first power input terminal and the first electrode of the i th light emitting element, and is configured to provide a driving signal to the first electrode of the i th light emitting element under the control of the second data signal.

[0011] In some example embodiments, the second data writing sub-circuit comprises a second switch transistor, or comprises a second N-type transistor and a second P-type transistor. The second storage sub-circuit comprises a second capacitor, and the second driving sub-circuit comprises a second driving transistor. The gate of the second switch transistor is coupled with the i th scanning line, the first pole of the second switch transistor is coupled with the i th first data terminal, and the second pole of the second switch transistor is coupled with the first electrode of the second capacitor and the gate of the second driving transistor. The second electrode of the second capacitor is coupled with the storage voltage line. The first pole of the second driving transistor is coupled with the i th first power input terminal, and the second pole of the second driving transistor is coupled with the first electrode of the i th light emitting element. The gate of the second N-type transistor is coupled with the i th first scanning line, the gate of the second P-type transistor is coupled with the i th second scanning line, the first pole of the second N-type transistor and the first pole of the second P-type transistor are both coupled with the i th first data terminal, and the second pole of the second N-type transistor and the second pole of the second P-type transistor are coupled with the first electrode of the second capacitor and the gate of the second driving transistor.

[0012] In some example embodiments, the discharge circuit of the i-1th second control circuit comprises a third data writing sub-circuit, a third storage sub-circuit and a third driving sub-circuit; the third data writing sub-circuit, the third storage sub-circuit and the third driving sub-circuit are coupled with the same node. The third data writing sub-circuit is further coupled with the i-1th second data terminal and the i-th scan line, and is configured to write a third data signal provided by the i-1th second data terminal to the third storage sub-circuit under the control of the i-th scan line when the gray scale of the i-th light emitting element is lower than the gray scale of the i-1th light emitting element. The third storage sub-circuit is further coupled with a storage voltage line, and is configured to store the written third data signal. The third driving sub-circuit is further coupled with the i-1th second power input terminal and the first electrode of the i-th light emitting element, and is configured to provide a driving signal to the i-1th second power input terminal under the control of the third data signal.

[0013] In some example embodiments, the third data writing sub-circuit comprises a third switch transistor, or comprises a third N-type transistor and a third P-type transistor. The third storage sub-circuit comprises a third capacitor; and the third driving sub-circuit comprises a third driving transistor. The gate of the third switch transistor is coupled with the i-th scan line, the first pole of the third switch transistor is coupled with the i-1th second data terminal, and the second pole of the third switch transistor is coupled with the first electrode of the third capacitor and the gate of the third driving transistor. The second electrode of the third capacitor is coupled with the storage voltage line. The first pole of the third driving transistor is coupled with the i-1th second voltage input terminal, and the second pole of the third driving transistor is coupled with the first electrode of the i-th light emitting element. The gate of the third N-type transistor is coupled with the i-th first scan line, the gate of the third P-type transistor is coupled with the i-th second scan line, the first poles of the third N-type transistor and the third P-type transistor are both coupled with the i-1th second data terminal, and the second poles of the third N-type transistor and the third P-type transistor are both coupled with the first electrode of the third capacitor and the gate of the third driving transistor.

[0014] In some example embodiments, the first control circuit is coupled with a first power input, and each second control circuit is coupled with a first power input. The first power input coupled with the first control circuit and the N-1 first power inputs coupled with the N-1 second control circuits are configured to receive the same first power signal; or, the first power input coupled with the first control circuit and the N-1 first power inputs coupled with the N-1 second control circuits are configured to receive different first power signals, wherein the first power signal received by the i-th first power input is less than the first power signal received by the (i-1)-th first power input.

[0015] In some example embodiments, each second control circuit is coupled with a second power input. The N-1 second power inputs coupled with the N-1 second control circuits are configured to receive the same second power signal; or, the N-1 second power inputs coupled with the N-1 second control circuits are configured to receive different second power signals, wherein the second power signal received by the i-th second power input is less than the second power signal received by the (i-1)-th second power input.

[0016] In some example embodiments, the first control circuit is coupled with a first data terminal, and each second control circuit is coupled with a first data terminal and a second data terminal. The first data terminal coupled with the first control circuit and the N-1 first data terminals coupled with the N-1 second control circuits are configured to be coupled with the same first data line. The N-1 second data terminals coupled with the N-1 second control circuits are configured to be coupled with the same second data line.

[0017] In some example embodiments, the pixel circuit further comprises a light emitting control circuit coupled with a light emitting control line, the first drive transistor of the first control circuit, and the first power input. The light emitting control circuit is configured to turn on the first electrode of the first drive transistor and the first power input under the control of the light emitting control line.

[0018] In some example embodiments, the light emitting control circuit comprises a light emitting control transistor. A gate electrode of the light emitting control transistor is coupled with the light emitting control line, a first electrode of the light emitting control transistor is coupled with the first power input, and a second electrode of the light emitting control transistor is coupled with the first electrode of the first drive transistor.

[0019] In some example embodiments, the pixel circuit further comprises a first reset circuit coupled with the reset control line, the first driving transistor of the first control circuit, and a reset voltage line, and configured to turn on the first electrode of the first driving transistor and the reset voltage line under the control of the reset control line.

[0020] In some example embodiments, the first reset circuit comprises a first reset transistor, a gate of the first reset transistor coupled with the reset control line, a first electrode of the first reset transistor coupled with the reset voltage line, and a second electrode of the first reset transistor coupled with the first electrode of the first driving transistor.

[0021] In some example embodiments, the pixel circuit further comprises a second reset circuit coupled with the light-emitting control line, the first electrode of the first light-emitting element, and a reset voltage line, and configured to turn on the first electrode of the first light-emitting element and the reset voltage line under the control of the light-emitting control line.

[0022] In some example embodiments, the second reset circuit comprises a second reset transistor, a gate of the second reset transistor coupled with the light-emitting control line, a first electrode of the second reset transistor coupled with the reset voltage line, and a second electrode of the second reset transistor coupled with the first electrode of the first light-emitting element.

[0023] In some example embodiments, the pixel circuit comprises silicon-based transistors.

[0024] In another aspect, the present embodiment provides a driving method of a pixel circuit, applied to the pixel circuit as described above, and the driving method comprises: a first control circuit providing a driving signal to N light-emitting elements connected in series; and an i-1th second control circuit adjusting the driving signal provided to an i th light-emitting element among the N light-emitting elements.

[0025] In some example embodiments, the i-1th second control circuit adjusting the driving signal provided to the i th light-emitting element among the N light-emitting elements comprises: when a gray scale of the i th light-emitting element is higher than a gray scale of an i-1th light-emitting element, the i-1th second control circuit increases the driving signal provided to the i th light-emitting element; and when the gray scale of the i th light-emitting element is lower than the gray scale of the i-1th light-emitting element, the i-1th second control circuit decreases the driving signal provided to the i th light-emitting element.

[0026] In another aspect, the embodiment provides a display substrate, comprising a substrate, a plurality of pixel circuits arranged on the substrate, and a plurality of light emitting elements; the pixel circuit is the pixel circuit as described above, and the pixel circuit is configured to drive N light emitting elements connected in series, N being an integer greater than 1.

[0027] In some example embodiments, the substrate is a silicon substrate, and the plurality of light emitting elements are micro light emitting elements.

[0028] In another aspect, the embodiment provides a display device, comprising the display substrate as described above.

[0029] Other aspects can become apparent from a review of the drawings and detailed description.

[0030] SUMMARY

[0031] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0032] Fig. 1 is a structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0033] Fig. 2 is an equivalent circuit diagram of a first control circuit according to at least one embodiment of the present disclosure;

[0034] Fig. 3 is a structural schematic diagram of a second control circuit according to at least one embodiment of the present disclosure;

[0035] Fig. 4 is a structural schematic diagram of a charging circuit and a discharging circuit of the second control circuit according to at least one embodiment of the present disclosure;

[0036] Fig. 5 is an equivalent circuit diagram of the second control circuit according to at least one embodiment of the present disclosure;

[0037] Fig. 6 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0038] Fig. 7 is a working timing diagram of the pixel circuit shown in Fig. 6;

[0039] Figs. 8A and 8B are working state schematic diagrams of a pixel circuit according to at least one embodiment of the present disclosure;

[0040] Fig. 9 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0041] Fig. 10 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0042] Fig. 11 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0043] FIG. 12 is another equivalent circuit diagram of the pixel circuit according to an embodiment of the present disclosure;

[0044] FIG. 13 is another structural schematic diagram of the pixel circuit according to an embodiment of the present disclosure;

[0045] FIG. 14 is another equivalent circuit diagram of the pixel circuit according to an embodiment of the present disclosure;

[0046] FIG. 15 is a timing chart of the pixel circuit shown in FIG. 14;

[0047] FIG. 16 is another structural schematic diagram of the pixel circuit according to an embodiment of the present disclosure;

[0048] FIG. 17 is another equivalent circuit diagram of the pixel circuit according to an embodiment of the present disclosure;

[0049] FIG. 18 is a timing chart of the pixel circuit shown in FIG. 17;

[0050] FIG. 19 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0051] DETAILED DESCRIPTION

[0052] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. The embodiments can be implemented in various forms. It is readily apparent to those skilled in the art that the embodiments and features thereof can be changed or replaced without departing from the gist of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the following embodiments. The embodiments and features in the present disclosure can be combined with each other as long as they are not inconsistent with each other.

[0053] In the drawings, the size, the thickness or the region of one or more constituent elements, or layers, shown in the drawings, is sometimes exaggerated for the sake of explanation. Therefore, one embodiment of the present disclosure should not be interpreted as being limited to the shape or the size illustrated in the drawings. The drawings are schematically shown for the sake of explanation, and one embodiment of the present disclosure is not limited to the shape or the value illustrated in the drawings.

[0054] The ordinal numbers "first", "second", "third", and the like in the present specification are used to avoid confusion among constituent elements, and are not used to limit the number thereof in the specification. "A plurality of" in the present disclosure means two or more.

[0055] In this specification, terms of "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or locational relationship are used to describe the positional relationship of the components with reference to the drawings for the convenience of the description of this specification and the simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is changed as appropriate according to the direction of the components described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0056] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected", "coupled" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate, or connected between two elements. The person of ordinary skill in the art can understand the meaning of the above terms in the present disclosure according to the situation. Among them, "coupled" can include "electrically connected", "electrically connected" can include the case where the components are connected together through elements having certain electrical effects. The "element having certain electrical effects" is not particularly limited as long as it can transmit electrical signals between the connected components. Examples of "elements having certain electrical effects" include not only electrodes and wires, but also switching elements such as transistors, resistors, inductors, capacitors, other elements with multiple functions, and the like.

[0057] In this specification, a transistor refers to an element including at least a gate (gate electrode), a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to a region where current flows mainly.

[0058] In this specification, the first electrode can be a drain, and the second electrode can be a source, or the first electrode can be a source, and the second electrode can be a drain. In addition, the gate can also be referred to as a control electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source" and "drain" are sometimes exchanged with each other. Therefore, in this specification, "source" and "drain" can be exchanged with each other.

[0059] In this specification, "about", "approximately", and the like mean that the limit is not strictly defined, and the range within the process and measurement error is allowed. In the present disclosure, "the same" includes the case where the numerical value differs by 10% or less, such as the case where the numerical value differs by 5% or less.

[0060] Micro-LED has great application prospects in the display field due to its high brightness, long service life, small size and many other advantages. However, Micro-LED has the problem of excessive pixel current, resulting in large power consumption. For example, compared with the pixel current of an organic light-emitting diode (OLED) using a silicon substrate, which is in the order of nanampere (nA), the pixel current of a Micro-LED using a silicon substrate is in the order of magnitude of several orders of magnitude. For example, in an augmented reality (AR) application, the pixel current of a Micro-LED using a silicon substrate is about in the order of microampere (uA); in a car lamp application, the pixel current of a Micro-LED using a silicon substrate is as high as in the order of milliampere (mA), which is 10 6 times the pixel current of an OLED using a silicon substrate. Such a large current poses a huge challenge to the IR drop of the display substrate, module heat dissipation and power consumption.

[0061] The embodiment provides a pixel circuit and a driving method thereof, a display substrate and a display device, which are beneficial to reducing power consumption.

[0062] FIG. 1 is a structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of the embodiment is used to drive N light-emitting elements connected in series to emit light. A first electrode of an i-th light-emitting element in the N light-emitting elements is coupled with a second electrode of an (i-1)-th light-emitting element. A second electrode of an N-th light-emitting element is coupled with a third power supply line. A third power supply signal transmitted by the third power supply line can be less than 0V. Wherein, N is an integer greater than 1, and i is an integer greater than 1 and less than or equal to N. Wherein, the first electrode of the light-emitting element can be an anode, and the second electrode of the light-emitting element can be a cathode.

[0063] In FIG. 1, three light-emitting elements (for example, including light-emitting elements D1, D2 and D3) are taken as an example for illustration. A second electrode of a first light-emitting element D1 is coupled with a first electrode of a second light-emitting element D2, and a second electrode of the second light-emitting element D2 is coupled with a first electrode of a third light-emitting element D3.

[0064] In some examples, the light-emitting element can be a micro light-emitting element, for example, a Micro-LED or a Mini-LED. Micro-LED technology, i.e., LED miniaturization and matrix technology, refers to the integration of a high-density micro-sized LED array on a chip. Each LED can be addressed and driven individually to light up, and the pixel point distance between two adjacent LEDs can be reduced from millimeters to microns, improving the display effect. Micro-LED has the advantages of self-luminous display, full solid state, long service life, high brightness, low power consumption, small size, ultra-high resolution, and can be applied to extreme environments such as high temperature or radiation.

[0065] In some examples, the pixel circuit can include one first control circuit 10 and N-1 second control circuits. Two second control circuits 20-1 and 20-2 are taken as an example in FIG. 1. The first control circuit 10 is coupled with the first electrode of the first light emitting element D1 and configured to provide a driving signal to the N light emitting elements connected in series. The i-1th second control circuit is coupled with the first electrode of the i-th light emitting element and configured to adjust the driving signal provided to the i-th light emitting element. As shown in FIG. 1, the first second control circuit 20-1 is coupled with the first electrode of the second light emitting element D2, and the second second control circuit 20-2 is coupled with the first electrode of the third light emitting element D3. The first second control circuit 20-1 can be configured to adjust the driving signal provided to the second light emitting element D2, and the second second control circuit 20-2 can be configured to adjust the driving signal provided to the third light emitting element D3. For example, the driving signal can include a driving current. By controlling the size of the driving current input to the light emitting elements through the pixel circuit, the luminous intensity (gray scale) of the light emitting elements can be controlled to achieve display of different gray scales. For example, in low gray scale display, a smaller driving current is provided to reduce the luminous intensity (gray scale) of the light emitting elements; in high gray scale display, a larger driving current is provided to increase the luminous intensity (gray scale) of the light emitting elements. The present example can meet the display gray scale corresponding to each light emitting element connected in series by adjusting the driving current of the light emitting elements connected in series.

[0066] The pixel circuit of the present embodiment drives the N light emitting elements connected in series to emit light. The first control circuit provides a driving signal to the N light emitting elements, and the driving signal provided to the second light emitting element to the N-th light emitting element is adjusted by the corresponding second control circuit, so that the display gray scale corresponding to each light emitting element connected in series can be met. Compared with the scheme in which multiple light emitting elements are independently provided and independently driven by the corresponding pixel circuit, the present embodiment is advantageous in reducing power consumption.

[0067] In some examples, as shown in FIG. 1, the first control circuit 10 can include a first data writing sub-circuit 111, a first storage sub-circuit 112, and a first driving sub-circuit 113. The first data writing sub-circuit 111 is coupled with the first data terminal DA1, the first scan line DL1, and the first node N1, and is configured to write a first data signal provided by the first data terminal DA1 to the first node N1 under the control of the first scan line DL1. The first storage sub-circuit 112 is coupled with the first node N1 and the storage voltage line VD, and is configured to store the first data signal written to the first node N1. The first driving sub-circuit 113 is coupled with the first node N1, the first power input terminal V11, and the first electrode of the first light emitting element D1, and is configured to provide a driving signal to the first electrode of the first light emitting element D1 under the control of the first node N1.

[0068] In some examples, the first power input terminal V11 is configured to transmit a first power signal, and the first power signal transmitted by the first power input terminal V11 can be greater than the voltage signal transmitted by the storage voltage line VD. For example, the voltage signal transmitted by the storage voltage line VD can be 0V.

[0069] FIG. 2 is an equivalent circuit diagram of the first control circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIGS. 1 and 2, the first data writing sub-circuit 111 can include a first switch transistor T11, the first storage sub-circuit 112 can include a first capacitor C11, and the first driving sub-circuit 113 can include a first driving transistor T12.

[0070] In some examples, as shown in FIG. 2, the gate of the first switch transistor T11 is coupled with the first scan line GL1, the first pole of the first switch transistor T11 is coupled with the first data terminal DA1, and the second pole of the first switch transistor T11 is coupled with the first node N1. The first electrode of the first capacitor C11 is coupled with the first node N1, and the second electrode of the first capacitor C11 is coupled with the storage voltage line VD. The gate of the first driving transistor T12 is coupled with the first node N1, the first pole of the first driving transistor T12 is coupled with the first power input terminal V11, and the second pole of the first driving transistor T12 is coupled with the first electrode of the first light emitting element D1.

[0071] The example structures of the first data writing sub-circuit, the first storage sub-circuit, and the first driving sub-circuit are shown in FIG. 2, and it is easy for those skilled in the art to understand that the implementation of the above sub-circuits is not limited thereto, as long as the corresponding functions can be achieved.

[0072] FIG. 3 is a schematic diagram of a structure of a second control circuit according to at least one embodiment of the present disclosure. FIG. 3 illustrates an example in which three light emitting elements (e.g., including light emitting elements D1, D2, and D3) are connected in series and two second control circuits (e.g., including a first second control circuit 20-1 and a second second control circuit 20-2). As shown in FIG. 3, the first second control circuit 20-1 can be coupled to a second first data terminal DA2, a first second data terminal DB1, a second first power input terminal V12, and a first second power input terminal V21, and configured to increase a driving signal provided to the second light emitting element D2 using a first power signal provided by the second first power input terminal V12 under control of the second first data terminal DA2, or decrease the driving signal provided to the second light emitting element D2 using a second power signal provided by the first second power input terminal V21 under control of the first second data terminal DB1. The second second control circuit 20-2 can be coupled to a third first data terminal DA3, a second second data terminal DB2, a third first power input terminal V13, and a second second power input terminal V22, and configured to increase a driving signal provided to the third light emitting element D3 using a first power signal provided by the third first power input terminal V13 under control of the third first data terminal DA3, or decrease the driving signal provided to the third light emitting element D3 using a second power signal provided by the second second power input terminal V22 under control of the second second data terminal DB2. The data signal provided to the first second control circuit 20-1 by the second first data terminal DA2 and the first second data terminal DB1 can be determined according to the gray scale of the second light emitting element D2 and the first light emitting element D1, and the data signal provided to the second second control circuit 20-2 by the third first data terminal DA3 and the second second data terminal DB2 can be determined according to the gray scale of the second light emitting element D2 and the third light emitting element D3.

[0073] In some examples, as shown in FIG. 3, each second control circuit can include a charging circuit and a discharging circuit. For example, the first second control circuit 20-1 can include a charging circuit 21-1 and a discharging circuit 22-1, and the second second control circuit 20-2 can include a charging circuit 21-2 and a discharging circuit 22-2.

[0074] In some examples, as shown in FIG. 3, the charging circuit 21-1 of the first second control circuit 20-1 can be coupled with the second first data terminal DA2 and the second first power input terminal V12, and configured to increase the driving signal provided to the second light emitting element D2 using the first power signal provided by the second first power input terminal V12 under the control of the second first data terminal DA2 when the gray scale of the second light emitting element D2 is higher than that of the first light emitting element D1. The discharging circuit 22-1 of the first second control circuit 20-1 can be coupled with the first second data terminal DB1 and the first second power input terminal V21, and configured to decrease the driving signal provided to the second light emitting element D2 using the second power signal provided by the first second power input terminal V21 under the control of the first second data terminal DB1 when the gray scale of the second light emitting element D2 is lower than that of the first light emitting element D1.

[0075] In some examples, as shown in FIG. 3, the charging circuit 21-2 of the second second control circuit 20-2 can be coupled with the third first data terminal DA3 and the third first power input terminal V13, and configured to increase the driving signal provided to the third light emitting element D3 using the first power signal provided by the third first power input terminal V13 under the control of the third first data terminal DA3 when the gray scale of the third light emitting element D3 is higher than that of the second light emitting element D2. The discharging circuit 22-2 of the second second control circuit 20-2 can be coupled with the second second data terminal DB2 and the second second power input terminal V22, and configured to decrease the driving signal provided to the third light emitting element D3 using the second power signal provided by the second second power input terminal V22 under the control of the second second data terminal DB2 when the gray scale of the third light emitting element D3 is lower than that of the second light emitting element D2.

[0076] In some examples, the first power signal provided by each first power input terminal can be greater than the second power signal provided by each second power input terminal. For example, the first power signal can be greater than the second power signal, and the second power signal can be greater than or equal to 0V.

[0077] In some examples, the first control circuit is coupled with the first first data terminal, and each second control circuit is coupled with one first data terminal and one second data terminal. The first first data terminal coupled with the first control circuit and the N-1 first data terminals coupled with the N-1 second control circuits can be configured to be coupled with the same first data line; and the N-1 second data terminals coupled with the N-1 second control circuits can be configured to be coupled with the same second data line. The connection mode of the present example is advantageous in reducing the number of wires. In other examples, a plurality of first data terminals can be connected with separate data lines respectively, and a plurality of second data terminals can be connected with separate data lines respectively.

[0078] In some examples, when the gray scale of the second light emitting element D2 is higher than the gray scale of the first light emitting element D1, the charging circuit 21-1 of the first second control circuit 20-1 works, the discharging circuit 22-1 does not work, and the driving signal provided to the second light emitting element D2 can be increased; when the gray scale of the second light emitting element D2 is lower than the gray scale of the first light emitting element D1, the charging circuit 21-1 of the first second control circuit 20-1 does not work, the discharging circuit 22-1 works, and the driving signal provided to the second light emitting element D2 can be reduced. When the gray scale of the third light emitting element D3 is higher than the gray scale of the second light emitting element D2, the charging circuit 21-2 of the second second control circuit 20-2 works, the discharging circuit 22-2 does not work, and the driving signal provided to the third light emitting element D3 can be increased; when the gray scale of the third light emitting element D3 is lower than the gray scale of the second light emitting element D2, the charging circuit 21-2 of the second second control circuit 20-2 does not work, the discharging circuit 22-2 works, and the driving signal provided to the third light emitting element D3 can be reduced.

[0079] FIG. 4 is a structural schematic diagram of the charging circuit and the discharging circuit of the second control circuit according to at least one embodiment of the present disclosure. In FIG. 4, the structure of the charging circuit 21-1 and the discharging circuit 22-1 of the first second control circuit 20-1 is taken as an example for illustration. In the present example, the plurality of first data terminals are configured to be coupled with the first data line DH, and the plurality of second data terminals are configured to be coupled with the second data line DL.

[0080] In some examples, as shown in FIG. 4, the charging circuit 21-1 of the first second control circuit can include a second data writing sub-circuit 211, a second storage sub-circuit 212 and a second driving sub-circuit 213. The second data writing sub-circuit 211, the second storage sub-circuit 212 and the second driving sub-circuit 213 are all coupled with the second node N2. The second data writing sub-circuit 211 is further coupled with the first data line DH and the second scan line GL2, and is configured to write the second data signal provided by the first data line DH to the second node N2 under the control of the second scan line GL2 when the gray scale of the second light emitting element D2 is higher than the gray scale of the first light emitting element D1. The second storage sub-circuit 212 is further coupled with the storage voltage line VD, and is configured to store the written second data signal. The second driving sub-circuit 213 is further coupled with the second first power input terminal V12 and the first electrode of the second light emitting element D2, and is configured to provide a driving signal to the first electrode of the second light emitting element D2 under the control of the second data signal. Since the first light emitting element D1 and the second light emitting element D2 are connected in series, when the gray scale of the second light emitting element D2 is higher than the gray scale of the first light emitting element D1, the driving signal provided to the second light emitting element D2 can be obtained by superimposing the driving signal generated by the first control circuit and the charging circuit 21-1 of the first second control circuit, and compared with the driving signal provided to the first light emitting element D1, the driving signal provided to the second light emitting element D2 can be increased.

[0081] In some examples, as shown in FIG. 4, the discharging circuit 22-1 of the first second control circuit can include a third data writing sub-circuit 221, a third storage sub-circuit 222, and a third driving sub-circuit 223. The third data writing sub-circuit 221, the third storage sub-circuit 222, and the third driving sub-circuit 223 are coupled with the third node N3. The third data writing sub-circuit 221 is further coupled with the second data line DL and the second scan line GL2, and is configured to write a third data signal provided by the second data line DL to the third node N3 under the control of the second scan line GL2 when the gray scale of the second light emitting element D2 is lower than the gray scale of the first light emitting element D1. The third storage sub-circuit 222 is further coupled with the storage voltage line VD, and is configured to store the written third data signal. The third driving sub-circuit 223 is further coupled with the first second power input terminal V21 and the first electrode of the second light emitting element D2, and is configured to provide a driving signal to the first second power input terminal V21 under the control of the third data signal. Since the first light emitting element D1 and the second light emitting element D2 are connected in series, when the gray scale of the second light emitting element D2 is lower than the gray scale of the first light emitting element D1, the driving signal provided to the second light emitting element D2 can be obtained by superimposing the driving signal generated by the first control circuit and the driving signal derived by the discharging circuit 22-1 of the first second control circuit, which can reduce the driving signal provided to the second light emitting element D2 compared with the driving signal provided to the first light emitting element D1.

[0082] In some examples, the second data signal provided by the first data line DH to the charging circuit of the i-1th second control circuit can be determined according to the gray scale data of the connected i th light emitting element and the i-1th light emitting element; and the third data signal provided by the second data line DL to the discharging circuit of the i-1th second control circuit can be determined according to the gray scale data of the connected i th light emitting element and the i-1th light emitting element. The second data signals provided by the first data line DH to different second control circuits can be different or partially the same, and the third data signals provided by the second data line DL to different second control circuits can be different or partially the same. The embodiments are not limited in this regard.

[0083] FIG. 5 is an equivalent circuit diagram of the second control circuit according to at least one embodiment of the present disclosure. In FIG. 5, the equivalent circuit of the first second control circuit is taken as an example for illustration.

[0084] In some examples, as shown in FIG. 5, the second data write-in sub-circuit of the charging circuit 21-1 of the first second control circuit can include a second switch transistor T21, the second storage sub-circuit can include a second capacitor C21, and the second driving sub-circuit can include a second driving transistor T22. The third data write-in sub-circuit of the discharging circuit 22-1 of the first second control circuit can include a third switch transistor T23, the third storage sub-circuit can include a third capacitor C22, and the third driving sub-circuit can include a third driving transistor T24.

[0085] In some examples, the gate of the second switch transistor T21 is coupled with the second scan line GL2, the first pole of the second switch transistor T21 is coupled with the first data line DH, and the second pole of the second switch transistor T21 is coupled with the second node N2. The first electrode of the second capacitor C21 is coupled with the second node N2, and the second electrode is coupled with the storage voltage line VD. The gate of the second driving transistor T22 is coupled with the second node N2, the first pole of the second driving transistor T22 is coupled with the second first power input terminal V12, and the second pole of the second driving transistor T22 is coupled with the first electrode of the second light emitting element D2. The second node N2 is the connection point of the second pole of the second switch transistor T21, the first electrode of the second capacitor C21, and the gate of the second driving transistor T22.

[0086] In some examples, the gate of the third switch transistor T23 is coupled with the second scan line GL2, the first pole of the third switch transistor T23 is coupled with the second data line DL, and the second pole of the third switch transistor T23 is coupled with the third node N3. The first electrode of the third capacitor C22 is coupled with the third node N3, and the second electrode is coupled with the storage voltage line VD. The gate of the third driving transistor T24 is coupled with the third node N3, the first pole of the third driving transistor T24 is coupled with the first second voltage input terminal V21, and the second pole of the third driving transistor T24 is coupled with the first electrode of the second light emitting element D2. The third node N3 is the connection point of the second pole of the third switch transistor T23, the first electrode of the third capacitor C22, and the gate of the third driving transistor T24.

[0087] The exemplary structures of the second data write-in sub-circuit, the second storage sub-circuit, the second driving sub-circuit, the third data write-in sub-circuit, the third storage sub-circuit, and the third driving sub-circuit are shown in FIG. 5, and it is easy for those skilled in the art to understand that the implementation of the above-mentioned sub-circuits is not limited thereto, as long as the corresponding functions can be achieved.

[0088] FIG. 6 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In FIG. 6, a pixel circuit driving three light emitting elements (e.g., including light emitting elements D1, D2, and D3) in series is taken as an example for illustration.

[0089] In some examples, as shown in FIG. 6, the pixel circuit can include a first control circuit 10, a first second control circuit of a charging circuit 21-1 and a discharging circuit 22-1, a second second control circuit of a charging circuit 21-2 and a discharging circuit 22-2. The first control circuit 10 can include a first switch transistor T11, a first capacitor C11, and a first drive transistor T12. The first second control circuit of the charging circuit 21-1 can include a second switch transistor T21, a second capacitor C21, and a second drive transistor T22. The first second control circuit of the discharging circuit 22-1 can include a third switch transistor T23, a third capacitor C22, and a third drive transistor T24. The second second control circuit of the charging circuit 21-2 can include a second switch transistor T31, a second capacitor C31, and a second drive transistor T32. The second second control circuit of the discharging circuit 22-2 can include a third switch transistor T33, a third capacitor C32, and a third drive transistor T34. A first electrode of the first light emitting element D1 is coupled to the first control circuit 10, a second electrode of the first light emitting element D1 is coupled to a first electrode of the second light emitting element D2, the first electrode of the second light emitting element D2 is further coupled to the first second control circuit of the charging circuit 21-1 and the discharging circuit 22-1, a second electrode of the second light emitting element D2 is coupled to a first electrode of the third light emitting element D3, the first electrode of the third light emitting element D3 is further coupled to the second second control circuit of the charging circuit 21-2 and the discharging circuit 22-2. A second electrode of the third light emitting element D3 is coupled to a third power supply line VSS.

[0090] In some examples, a gate of the first switch transistor T11 is coupled to a first scan line GL1, a first electrode of the first switch transistor T11 is coupled to a first data line DH, and a second electrode of the first switch transistor T11 is coupled to a first electrode of the first capacitor C11 and a gate of the first drive transistor T12. A second electrode of the first capacitor C11 is coupled to a storage voltage line VD. A first electrode of the first drive transistor T12 is coupled to a first first power supply input terminal, and a second electrode of the first drive transistor T12 is coupled to the first electrode of the first light emitting element D1.

[0091] In some examples, the gate of the second switch transistor T21 is coupled with the second scan line GL2, the first pole of the second switch transistor T21 is coupled with the first data line DH, and the second pole of the second switch transistor T21 is coupled with the first pole of the second capacitor C21 and the gate of the second drive transistor T22. The second pole of the second capacitor C21 is coupled with the storage voltage line VD. The first pole of the second drive transistor T22 is coupled with the second first power input terminal, and the second pole of the second drive transistor T22 is coupled with the first pole of the second light emitting element D2. The gate of the third switch transistor T23 is coupled with the second scan line GL2, the first pole of the third switch transistor T23 is coupled with the second data line DL, and the second pole of the third switch transistor T23 is coupled with the first pole of the third capacitor C22 and the gate of the third drive transistor T24. The second pole of the third capacitor C22 is coupled with the storage voltage line VD. The first pole of the third drive transistor T24 is coupled with the second second power input terminal, and the second pole of the third drive transistor T24 is coupled with the first pole of the second light emitting element D2.

[0092] In some examples, the gate of the second switch transistor T31 is coupled with the third scan line GL3, the first pole of the second switch transistor T31 is coupled with the first data line DH, and the second pole of the second switch transistor T31 is coupled with the first pole of the second capacitor C21 and the gate of the second drive transistor T32. The second pole of the second capacitor C31 is coupled with the storage voltage line VD. The first pole of the second drive transistor T32 is coupled with the third first power input terminal, and the second pole of the second drive transistor T32 is coupled with the first pole of the third light emitting element D3. The gate of the third switch transistor T33 is coupled with the third scan line GL3, the first pole of the third switch transistor T33 is coupled with the second data line DL, and the second pole of the third switch transistor T33 is coupled with the first pole of the third capacitor C32 and the gate of the third drive transistor T34. The second pole of the third capacitor C32 is coupled with the storage voltage line VD. The first pole of the third drive transistor T34 is coupled with the second second power input terminal, and the second pole of the third drive transistor T34 is coupled with the first pole of the third light emitting element D2.

[0093] In some examples, the first drive transistor T12, the second drive transistor T22 and T32, and the third drive transistor T23 and T33 can be N-type transistors. Compared with P-type transistors, N-type transistors have smaller leakage current. By setting the drive transistors of the present example as N-type transistors, it can be ensured that the brightness is low enough at low gray scale.

[0094] In some examples, the first switch transistor T11, the second switch transistor T21 and T31, and the third switch transistor T23 and T33 can be N-type transistors or P-type transistors. The present example is not limited in this regard.

[0095] In some examples, the first, second and third first power input terminals can be coupled with the same first power line VH and configured to receive the same first power signal. In other words, the first poles of the first driving transistor T12, the second driving transistors T22 and T32 are coupled with the first power line VH. The connection manner of the present example can be conducive to reducing the number of wirings.

[0096] In some examples, the first and second second power input terminals can be coupled with the same second power line VL and configured to receive the same second power signal. In other words, the first poles of the third driving transistors T24 and T34 are coupled with the second power line VL. The connection manner of the present example can be conducive to reducing the number of wirings.

[0097] In some examples, the first power signal provided by the first power line VH can be greater than the second power signal provided by the second power line VL, and the second power signal provided by the second power line VL can be greater than or equal to the voltage signal transmitted by the storage voltage line VD. The voltage signal transmitted by the storage voltage line VD can be greater than the third power signal provided by the third power line VSS. For example, the voltage signal transmitted by the storage voltage line VD can be 0V.

[0098] FIG. 7 is a working timing diagram of the pixel circuit shown in FIG. 6. FIGS. 8A and 8B are working state diagrams of the pixel circuit according to at least one embodiment of the present disclosure. The present example takes the first driving transistor T12, the second driving transistors 22 and T32, the third driving transistors T23 and T33, the first switching transistor T11, the second switching transistors T21 and T31, and the third switching transistors T23 and T33 as N-type transistors for example. FIG. 8A illustrates the working state of the charging circuit of the first second control circuit; FIG. 8B illustrates the working state of the discharging circuit of the first second control circuit; wherein the black arrows in FIGS. 8A and 8B indicate the transmission path of the driving signal.

[0099] In some examples, as shown in FIGS. 6 and 7, in the first data writing stage S11, the first scan line GL1 provides a high-level signal, the first switching transistor T11 of the first control circuit 10 is turned on, the first data signal provided by the first data line DH is written to the first node N1, the first capacitor C11 stores the first data signal, so that the first data signal controls the working state of the first driving transistor T12, and generates a driving signal provided to the three light emitting elements connected in series. Wherein, the first data signal can be determined by integrating the gray scales of the three light emitting elements D1, D2 and D3.

[0100] In some examples, in the second data writing stage S12, the second scan line GL2 provides a high level signal, the second switch transistor T21 and the third switch transistor T23 are turned on; the second capacitor C21 stores the data signal provided by the first data line DH, and the third capacitor C22 stores the data signal provided by the second data line DL; the working state of the second driving transistor T22 is controlled by the data signal provided by the first data line DH, and the working state of the third driving transistor T24 is controlled by the data signal provided by the second data line DL.

[0101] In some examples, as shown in FIG. 8A, when the gray scale of the second light emitting element D2 is higher than that of the first light emitting element D1, the charging circuit 21-1 of the first second control circuit works, and the discharging circuit 22-1 does not work. In this case, the first data line DH transmits the corresponding second data signal in the second data writing stage S12, so that the second driving transistor T22 generates the driving signal provided to the second light emitting element D2. For example, the second data signal can be determined by integrating the gray scale of the second light emitting element D2 and the gray scale of the first light emitting element D1. The second data line DL transmits the fourth data signal (for example, a low level signal such as 0V) in the second data writing stage S12, so as to control the third driving transistor T24 to be turned off. When the charging circuit 21-1 works and the discharging circuit 22-1 does not work, the driving signal provided to the second light emitting element D2 is obtained by superimposing the driving signal generated by the charging circuit of the first control circuit and the first second control circuit. Compared with the driving signal provided to the first light emitting element D1, the driving signal provided to the second light emitting element D2 can be increased.

[0102] In some examples, as shown in FIG. 8B, when the gray scale of the second light emitting element D2 is lower than that of the first light emitting element D1, the charging circuit 21-1 of the first second control circuit does not work, and the discharging circuit 22-1 works. In this case, the first data line DH transmits the fourth data signal (for example, a low level signal such as 0V) in the second data writing stage S12, so as to control the second driving transistor T22 to be turned off. The second data line DL transmits the corresponding third data signal in the second data writing stage S12, so that the third driving transistor T24 leads out the driving signal to the second power line VL. For example, the third data signal can be determined by integrating the gray scale of the second light emitting element D2 and the gray scale of the first light emitting element D1. When the charging circuit 21-1 does not work and the discharging circuit 22-1 works, the driving signal provided to the second light emitting element D2 is obtained by superimposing the driving signal generated by the first control circuit and the driving signal led out by the discharging circuit of the first second control circuit. Compared with the driving signal provided to the first light emitting element D1, the driving signal provided to the second light emitting element D2 can be reduced.

[0103] In some examples, in a third data writing stage S13, the third scan line GL3 provides a high level signal, and the first data line DH and the second data line DL write data signals to the second second control circuit. When the gray scale of the third light emitting element D3 is higher than the gray scale of the second light emitting element D2, the charging circuit 21-2 of the second second control circuit works, and the discharging circuit 22-2 does not work. When the gray scale of the third light emitting element D3 is lower than the gray scale of the second light emitting element D2, the charging circuit 21-2 of the second second control circuit does not work, and the discharging circuit 22-2 works. The working processes of the charging circuit and the discharging circuit can refer to the descriptions of FIGS. 8A and 8B, and thus will not be described here again.

[0104] The pixel circuit provided in the present example drives a plurality of (for example, three) light emitting elements connected in series, and respectively adjusts the driving signals of the plurality of light emitting elements, which can be beneficial to reduce power consumption.

[0105] FIG. 9 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In FIG. 9, two light emitting elements (for example, including the light emitting elements D1 and D2) connected in series are taken as an example for illustration.

[0106] In some examples, as shown in FIG. 9, the first pole of the first driving transistor T12 of the first control circuit 10 is connected to a first first power input end, and the first pole of the second driving transistor T22 of the charging circuit 21-1 of the first second control circuit is connected to a second first power input end, which are connected to different first power lines and configured to receive different first power signals. The first pole of the first driving transistor T12 is coupled to a first first power line VH1, and the first pole of the second driving transistor T22 is coupled to a second first power line VH2.

[0107] In some examples, the first power signal transmitted by the first first power line VH1 is different from the first power signal transmitted by the second first power line VH2. The first power signal transmitted by the first first power line VH1 can be greater than the first power signal transmitted by the second first power line VH2. Both the first power signal transmitted by the first first power line VH1 and the first power signal transmitted by the second first power line VH2 are greater than the second power signal transmitted by the second power line VL.

[0108] In the present example, by providing the second driving transistor T22 with a smaller first power signal and the first driving transistor T12 with a larger first power signal, the voltage difference of the second driving transistor T22 can be reduced, the multi-gray scale display can be met, and the power consumption can be further reduced. The descriptions of the remaining structures of the present embodiment can refer to the descriptions of the foregoing embodiments, and thus will not be described here again.

[0109] FIG. 10 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. FIG. 10 illustrates an example in which three light emitting elements (e.g., including light emitting elements D1, D2, and D3) are connected in series.

[0110] In some examples, as shown in FIG. 10, a first second power input terminal to which a first electrode of a third driving transistor T24 of a discharging circuit 22-1 of a first second control circuit is connected, a second second power input terminal to which a first electrode of a third driving transistor T34 of a discharging circuit 22-2 of a second second control circuit is connected are connected to different second power lines configured to receive different second power signals. In some examples, the first electrode of the third driving transistor T24 is coupled to a first second power line VL1, and the first electrode of the third driving transistor T34 is coupled to a second second power line VL2.

[0111] In some examples, the second power signal transmitted by the first second power line VL1 is different from the second power signal transmitted by the second second power line VL2. In some examples, the second power signal transmitted by the first second power line VL1 can be greater than the second power signal transmitted by the second second power line VL2. The first power signal transmitted by the first power line VH can be greater than the second power signal transmitted by the first second power line VL1, and greater than the second power signal transmitted by the second second power line VL2.

[0112] In some examples, by providing different second power signals to different second control circuits, the voltage difference of the third driving transistor can be reduced, multi-gray scale conditions can be met, and power consumption can be further reduced. The remaining structures of the present embodiment can be described with reference to the foregoing embodiments, and thus will not be described again.

[0113] FIG. 11 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. FIG. 11 illustrates an example in which three light emitting elements (e.g., including light emitting elements D1, D2, and D3) are connected in series.

[0114] In some examples, as shown in FIG. 11, a first first power input terminal to which a first electrode of a first driving transistor T12 of a first control circuit 10 is connected, a second first power input terminal to which a first electrode of a second driving transistor T22 of a charging circuit 21-1 of a first second control circuit is connected, and a third first power input terminal to which a first electrode of a second driving transistor T32 of a charging circuit 21-2 of a second second control circuit is connected are connected to different first power lines configured to receive different first power signals. In some examples, the first electrode of the first driving transistor T12 is coupled to a first first power line VH1, the first electrode of the second driving transistor T22 is coupled to a second first power line VH2, and the first electrode of the second driving transistor T32 is coupled to a third first power line VH3. In some examples, the first power signal transmitted by the first first power line VH1 is different from the first power signal transmitted by the second first power line VH2, and the first power signal transmitted by the second first power line VH2 is different from the first power signal transmitted by the third first power line VH3. In some examples, the first power signal transmitted by the first first power line VH1 can be greater than the first power signal transmitted by the second first power line VH2, and the first power signal transmitted by the second first power line VH2 can be greater than the first power signal transmitted by the third first power line VH3.

[0115] In some examples, the first power signal transmitted by the first first power line VH1 can be greater than the first power signal transmitted by the second first power line VH2, and the first power signal transmitted by the second first power line VH2 can be greater than the first power signal transmitted by the third first power line VH3.

[0116] In some examples, as shown in FIG. 11, the first second power input end to which the first electrode of the third driving transistor T24 of the discharging circuit 22-1 of the first second control circuit is connected and the second second power input end to which the first electrode of the third driving transistor T34 of the discharging circuit 22-2 of the second second control circuit is connected are connected to different second power lines and are configured to receive different second power signals. Among them, the first electrode of the third driving transistor T24 is coupled to the first second power line VL1, and the first electrode of the third driving transistor T34 is coupled to the second second power line VL2.

[0117] In some examples, the second power signal transmitted by the first second power line VL1 can be greater than the second power signal transmitted by the second second power line VL2. The first power signal transmitted by any first power line is greater than the second power signal transmitted by any second power line.

[0118] In some examples, when N light emitting elements are connected in series, the pixel circuit includes a first control circuit and N-1 second control circuits, the first control circuit is coupled to a first power line, the charging circuit of each second control circuit is coupled to a first power line, and the discharging circuit of each second control circuit is coupled to a second power line. The first power signal transmitted by the first power line connected to the first control circuit is greater than the first power signal transmitted by the first power line connected to any second control circuit, the first power signal received by the first second control circuit to the N-1 second control circuit can gradually decrease, and the second power signal received by the first second control circuit to the N-1 second control circuit can gradually decrease.

[0119] The present example provides different first power signals and second power signals to different second control circuits, which is beneficial to reduce the voltage difference of the second driving transistor and the voltage difference of the third driving transistor, can meet the multi-gray scale case, and further reduce power consumption. The remaining structure of the present embodiment can be referred to the description of the foregoing embodiments, and will not be described here.

[0120] FIG. 12 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In FIG. 12, three light emitting elements (for example, including light emitting elements D1, D2 and D3) connected in series are taken as an example for illustration.

[0121] In some examples, as shown in FIG. 12, the first control circuit 10 can include a first switch, a first capacitor C11, and a first drive transistor T12. The first switch can include a first N-type transistor T11N and a first P-type transistor T11P. A gate of the first N-type transistor T11N is coupled to a first first scan line GL1N, and a gate of the first P-type transistor T11P is coupled to a first second scan line GL1P. A first electrode of the first N-type transistor T11N and a first electrode of the first P-type transistor T11P are coupled to a first data line DH, and a second electrode of the first N-type transistor T11N and a second electrode of the first P-type transistor T11P are coupled to a first electrode of the first capacitor C11 and a gate of the first drive transistor T12. A second electrode of the first capacitor C11 is coupled to a storage voltage line VD. A first electrode of the first drive transistor T12 is coupled to a first first power input, and a second electrode of the first drive transistor T12 is coupled to a first electrode of a first light emitting element D1. The first first scan line GL1N and the first second scan line GL1P can be configured to provide opposite control signals. For example, the first first scan line GL1N provides a high level signal, and the first second scan line GL1P provides a low level signal.

[0122] In some examples, the charging circuit 21-1 of the first second control circuit can include a second switch, a second capacitor C21, and a second drive transistor T22. The second switch can include a second N-type transistor T21N and a second P-type transistor T21P. A gate of the second N-type transistor T21N is coupled to a second first scan line GL2N, and a gate of the second P-type transistor T21P is coupled to a second second scan line GL2P. A first electrode of the second N-type transistor T21N and a first electrode of the second P-type transistor T21P are coupled to the first data line DH, and a second electrode of the second N-type transistor T21N and a second electrode of the second P-type transistor T21P are coupled to a first electrode of the second capacitor C21 and a gate of the second drive transistor T22. A second electrode of the second capacitor G21 is coupled to the storage voltage line VD. A first electrode of the second drive transistor T22 is coupled to a second first power input, and a second electrode of the second drive transistor T22 is coupled to a first electrode of a second light emitting element D2. The second first scan line GL2N and the second second scan line GL2P can be configured to provide opposite control signals. For example, the second first scan line GL2N provides a high level signal, and the second second scan line GL2P provides a low level signal.

[0123] In some examples, the discharging circuit 22-1 of the first second control circuit can include a third switch, a third capacitor C22 and a third driving transistor T24. The third switch can include a third N-type transistor T23N and a third P-type transistor T23P. The gate of the third N-type transistor T23N is coupled with the second first scan line GL2N, the gate of the third P-type transistor T23P is coupled with the second second scan line GL2P, the first pole of the third N-type transistor T23N and the first pole of the third P-type transistor T23P are coupled with the second data line DL, and the second poles of the third N-type transistor T23N and the third P-type transistor T23P are coupled with the first pole of the third capacitor C22 and the gate of the third driving transistor T24. The second pole of the third capacitor C22 is coupled with the storage voltage line VD. The first pole of the third driving transistor T24 is coupled with the first second voltage input end, and the second pole of the third driving transistor T24 is coupled with the first pole of the second light emitting element D2.

[0124] In some examples, the charging circuit 21-2 of the second second control circuit can include a second switch, a second capacitor C31 and a second driving transistor T32. The second switch can include a second N-type transistor T31N and a second P-type transistor T31P. The gate of the second N-type transistor T31N is coupled with the third first scan line GL3N, the gate of the second P-type transistor T31P is coupled with the third second scan line GL3P, the first poles of the second N-type transistor T31N and the second P-type transistor T31P are coupled with the first data line DH, and the second poles of the second N-type transistor T31N and the second P-type transistor T31P are coupled with the first pole of the second capacitor C31 and the gate of the second driving transistor T32. The second pole of the second capacitor G31 is coupled with the storage voltage line VD. The first pole of the second driving transistor T32 is coupled with the second first power input end, and the second pole of the second driving transistor T32 is coupled with the first pole of the third light emitting element D3. The third first scan line GL3N and the third second scan line GL3P can be configured to provide opposite control signals. For example, when the third first scan line GL3N provides a high level signal, the third second scan line GL3P provides a low level signal.

[0125] In some examples, the discharge circuit 22-2 of the second second control circuit can include a third switch, a third capacitor C32 and a third drive transistor T34. The third switch can include a third N-type transistor T33N and a third P-type transistor T33P. The gate of the third N-type transistor T33N is coupled with the third first scan line GL3N, the gate of the third P-type transistor T33P is coupled with the third second scan line GL3P, the first poles of the third N-type transistor T33N and the third P-type transistor T33P are coupled with the second data line DL, and the second poles of the third N-type transistor T33N and the third P-type transistor T33P are coupled with the first pole of the third capacitor C32 and the gate of the third drive transistor T34. The second pole of the third capacitor C32 is coupled with the storage voltage line VD. The first pole of the third drive transistor T34 is coupled with the second second voltage input end, and the second pole of the third drive transistor T34 is coupled with the first pole of the third light emitting element D3.

[0126] In some examples, the first first power input end, the second first power input end and the third first power input end are all coupled with the first power line VH, and the first second power input end and the second second power input end are all coupled with the second power line VL. In other words, the first drive transistor T12, the second drive transistor T22 and T32 are all coupled with the first power line VH, and the third drive transistor T24 and T34 are all coupled with the second power line VL.

[0127] The first switch, the second switch and the third switch in the present example are all complementary metal-oxide-semiconductor (CMOS) switches. By using CMOS switches, lossless signal transmission can be achieved, and power consumption can be reduced. The remaining structures of the present embodiment can be described with reference to the foregoing embodiments, and thus will not be described here.

[0128] FIG. 13 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 13, the pixel circuit of the present example can include a first control circuit 10, a plurality of second control circuits (for example, including second control circuits 20-1 and 20-2), a light emitting control circuit 30 and a first reset circuit 31. The light emitting control circuit 30 can be coupled with the light emitting control line EM, the first drive sub-circuit of the first control circuit 10 and the first first power input end V11, and configured to turn on the first drive sub-circuit and the first first power input end V11 under the control of the light emitting control line EM. The first reset circuit 31 is coupled with the reset control line RST, the first drive sub-circuit of the first control circuit 10 and the reset voltage line VR, and configured to turn on the first drive sub-circuit and the reset voltage line VR under the control of the reset control line RST.

[0129] FIG. 14 is another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 14, the light emitting control circuit 30 can include a light emitting control transistor M1, a gate of the light emitting control transistor M1 coupled to the light emitting control line EM, a first electrode of the light emitting control transistor M1 coupled to the first first power input terminal, and a second electrode of the light emitting control transistor M1 coupled to the first electrode of the first driving transistor T12 of the first driving sub-circuit. The first first power input terminal can be coupled to the first first power line VH1. The first reset circuit 31 can include a first reset transistor M2. A gate of the first reset transistor M2 is coupled to the reset control line RST, a first electrode of the first reset transistor M2 is coupled to the reset voltage line VR, and a second electrode of the first reset transistor M2 is coupled to the first electrode of the first driving transistor T12 of the first driving sub-circuit. The remaining structure of the pixel circuit according to the present embodiment can be referred to the description of the previous embodiments, and thus will not be described here.

[0130] FIG. 15 is a working timing diagram of the pixel circuit shown in FIG. 14. In the present example, the light emitting control transistor M1 is a P-type transistor, and the remaining transistors are N-type transistors. In the present example, the first power signal provided by the first first power line VH1 is greater than the first power signal provided by the second first power line VH2, the first power signal provided by the second first power line VH2 is greater than the first power signal provided by the third first power line VH3, the first power signal provided by the third first power line VH3 is greater than the second power signal provided by the first second power line VL1, the second power signal provided by the first second power line VL1 is greater than the second power signal provided by the second second power line VL2, the second power signal provided by the second second power line VL2 is greater than the second power signal provided by the third second power line VL3, and the second power signal provided by the third second power line VL3 is greater than the third power signal provided by the third power line VSS.

[0131] In some examples, as shown in FIG. 14 and FIG. 15, in the reset stage S2, the reset control line RST provides a high-level signal, the reset transistor M2 is turned on, and the reset voltage line VR provides a reset voltage signal to the first electrode of the first driving transistor T12. In this stage, the light emitting control line EM provides a high-level signal, and the light emitting control transistor M1 is turned off.

[0132] In the data writing stage S1, corresponding data signals are sequentially written under the control of the first scan line GL1, the second scan line GL2, and the third scan line GL3. The working process of the data writing stage S1 can be referred to the working timing diagram shown in FIG. 7, and thus will not be described here.

[0133] In the light emitting stage S3, the light emitting control line EM provides a low level signal, the light emitting control transistor M1 is turned on, the first power supply line VH1 provides the first power supply signal to the first electrode of the first driving transistor T12, and the first driving transistor T12 generates the driving signal. In this stage, the reset control line RST provides a low level signal, and the reset transistor M2 is turned off.

[0134] The present example can optimize the performance of the pixel circuit by providing the light emitting control circuit and the first reset circuit.

[0135] FIG. 16 is another structural schematic diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 16, the pixel circuit of the present example can include the first control circuit 10, a plurality of second control circuits (for example, including the second control circuits 20-1 and 20-2), the light emitting control circuit 30, and the second reset circuit 32. The light emitting control circuit 30 can be coupled with the light emitting control line EM, the first driving sub-circuit of the first control circuit 10, and the first first power input terminal V11, and be configured to turn on the first driving sub-circuit and the first first power input terminal V11 under the control of the light emitting control line EM. The second reset circuit 32 is coupled with the light emitting control line EM, the first electrode of the first light emitting element D1, and the reset voltage line VR, and be configured to turn on the first electrode of the first light emitting element D1 and the reset voltage line VR under the control of the reset control line RST.

[0136] FIG. 17 is another equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 17, the light emitting control circuit 30 can include the light emitting control transistor M1, the gate of the light emitting control transistor M1 is coupled with the light emitting control line EM, the first electrode of the light emitting control transistor M1 is coupled with the first first power input terminal, and the second electrode of the light emitting control transistor M1 is coupled with the first electrode of the first driving transistor T12 of the first driving sub-circuit. The first first power input terminal can be coupled with the first power supply line VH1. The second reset circuit 32 can include the second reset transistor M3. The gate of the second reset transistor M3 is coupled with the light emitting control line EM, the first electrode of the second reset transistor M3 is coupled with the reset voltage line VR, and the second electrode of the second reset transistor M3 is coupled with the first electrode of the first light emitting element D1. The remaining structure of the pixel circuit of the present embodiment can be referred to the description of the previous embodiments, and thus will not be described here.

[0137] FIG. 18 is a working timing diagram of the pixel circuit shown in FIG. 17. The present example takes the light emitting control transistor M1 as a P-type transistor, and the remaining transistors as N-type transistors as an example for description.

[0138] In some examples, as shown in FIGS. 17 and 18, in the reset stage S2, the light-emitting control line EM provides a high-level signal, the light-emitting control transistor M1 is turned off, the second reset transistor M3 is turned on, and the reset voltage line VR provides a reset voltage signal to the first electrode of the first light-emitting element D1.

[0139] In the data writing stage S1, data signals are sequentially written under the control of the first scan line GL1, the second scan line GL2 and the third scan line GL3. The working process of the data writing stage S1 can be described with reference to the working timing shown in FIG. 7, which will not be described here.

[0140] In the light-emitting stage S3, the light-emitting control line EM provides a low-level signal, the second reset transistor M3 is turned off, the light-emitting control transistor M1 is turned on, the first power supply line VH1 provides a first power supply signal to the first electrode of the first driving transistor T12, and the first driving transistor T12 generates a driving signal.

[0141] The present example can optimize the performance of the pixel circuit by providing the light-emitting control circuit and the second reset circuit, and the light-emitting control circuit and the second reset circuit can be controlled by the light-emitting control line, thereby saving signal sources.

[0142] In some examples, the pixel circuit provided by the present example includes silicon-based transistors. The silicon-based transistors can be thin film transistors provided on a silicon substrate. Compared with glass-based thin film transistors, the silicon-based transistors have the following advantages: the size of the silicon-based transistors is tens of nanometers to hundreds of nanometers, and the size of the glass-based thin film transistors is several micrometers to tens of micrometers. The silicon-based transistors have a small volume, which is conducive to reducing the area occupied by the pixel circuit, thereby improving the pixel density and achieving higher resolution (PPI) display. The silicon-based transistors have a faster conduction time of tens of picoseconds, and the glass-based thin film transistors have a conduction time of tens to hundreds of nanoseconds. The silicon-based transistors have higher stability than the transistors prepared on the glass substrate. The pixel circuit composed of the silicon-based transistors does not need to compensate the threshold voltage, which is conducive to simplifying the pixel circuit and reducing the area occupied by the pixel circuit, thereby improving the pixel density.

[0143] The pixel circuit provided by the present embodiment has a simple structure and good stability, is used to drive micro-LEDs using a silicon substrate, can save the occupied area, meet the requirements of silicon-based integrated technology, and effectively reduce power consumption.

[0144] The present embodiment further provides a driving method of a pixel circuit, which is applied to the pixel circuit as described above. The driving method includes: a first control circuit providing a driving signal to N light-emitting elements connected in series; and an i-1th second control circuit adjusting the driving signal provided to an i th light-emitting element in the N light-emitting elements.

[0145] In some example embodiments, the i-1th second control circuit adjusting the driving signal provided to the i-th light emitting element of the N light emitting elements can include: when the gray scale of the i-th light emitting element is higher than the gray scale of the i-1th light emitting element, the i-1th second control circuit increasing the driving signal provided to the i-th light emitting element; and when the gray scale of the i-th light emitting element is lower than the gray scale of the i-1th light emitting element, the i-1th second control circuit decreasing the driving signal provided to the i-th light emitting element.

[0146] The driving method of the present embodiment provides the driving signal to the N light emitting elements by the first control circuit, and the driving signal provided to the second light emitting element to the Nth light emitting element is adjusted by the corresponding second control circuit, which can meet the corresponding display gray scale of each light emitting element. Compared with the scheme of independently setting and driving the plurality of light emitting elements by the corresponding pixel circuit, the present embodiment is advantageous to reduce power consumption.

[0147] The related description of the present embodiment can refer to the description of the foregoing embodiments, and thus will not be described here.

[0148] The present embodiment also provides a display substrate, which includes: a substrate, a plurality of pixel circuits and a plurality of light emitting elements disposed on the substrate. The pixel circuit is the pixel circuit described in the foregoing embodiments, and the pixel circuit is configured to drive the N light emitting elements connected in series, and N is an integer greater than 1.

[0149] In some examples, the substrate can be a silicon substrate, and the plurality of light emitting elements can be micro light emitting elements. Compared with the micro LED display substrate using a glass substrate, the micro LED display substrate using a silicon substrate can greatly reduce the area of the pixel circuit, thereby greatly improving the PPI.

[0150] FIG. 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 19, the present embodiment provides a display device 91, which includes a display substrate 910. The display substrate 910 is the display substrate provided in the foregoing embodiments. The display substrate 910 can be a Micro-LED display substrate or a Mini-LED display substrate. The display device 91 can be: a vehicle window glass, a shopping mall cabinet, an augmented reality (AR) device, a virtual reality (VR) device, or any product or component having a transparent display function. However, the present embodiment is not limited thereto.

[0151] In the description of the specification, the description using the terms "one embodiment", "some embodiments", "an example", "some examples" or the like means that the particular feature, structure, material or characteristic following the term is included in at least one embodiment or example of the application. The illustrative appearances of the above terms in various places in the specification are not necessarily referred to the same embodiment or example. Also, the particular features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples. Furthermore, in non-contradictory relation to each other, those skilled in the art can combine and combine the features described in the specification of different embodiments or examples and the features of different embodiments or examples.

[0152] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary, and are not to be interpreted as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A pixel circuit for driving N light emitting elements connected in series to emit light, a first electrode of an i th light emitting element of the N light emitting elements being coupled with a second electrode of an (i-1) th light emitting element, N being an integer greater than 1, i being an integer greater than 1 and less than or equal to N; the pixel circuit comprising: a first control circuit and N-1 second control circuits; the first control circuit being coupled with a first electrode of a first light emitting element of the N light emitting elements and configured to provide a driving signal to the N light emitting elements; the first control circuit comprising: a first data writing sub-circuit, a first driving transistor and a first capacitor; the first data writing sub-circuit being configured to write a first data signal provided by a first data terminal to a first node under control of a first scan line; a gate of the first driving transistor being coupled with the first node, a first electrode of the first driving transistor being coupled with a first power input terminal, and a second electrode of the first driving transistor being coupled with the first electrode of the first light emitting element; a first electrode of the first capacitor being coupled with the first node, and a second electrode of the first capacitor being coupled with a storage voltage line; an (i-1) th second control circuit of the N-1 second control circuits being coupled with a first electrode of an i th light emitting element of the N light emitting elements and configured to adjust the driving signal provided to the i th light emitting element.

2. The pixel circuit of claim 1, wherein, the first data writing sub-circuit comprising: a first switch transistor, a gate of the first switch transistor being coupled with the first scan line, a first electrode of the first switch transistor being coupled with the first data terminal, and a second electrode of the first switch transistor being coupled with the first node; or; the first data writing sub-circuit comprising: a first N-type transistor and a first P-type transistor; the first scan line comprising a first first scan line and a first second scan line; a gate of the first N-type transistor being coupled with the first first scan line, and a gate of the first P-type transistor being coupled with the first second scan line; a first electrode of the first N-type transistor and a first electrode of the first P-type transistor being coupled with the first data terminal, and a second electrode of the first N-type transistor and a second electrode of the first P-type transistor being coupled with the first node.

3. The pixel circuit of claim 1, wherein, the (i-1) th second control circuit being coupled with an i th first data terminal, an (i-1) th second data terminal, an i th first power input terminal and an (i-1) th second power input terminal and configured to increase the driving signal provided to the i th light emitting element by using a first power signal provided by the i th first power input terminal under control of the i th first data terminal, or to decrease the driving signal provided to the i th light emitting element by using a second power signal provided by the (i-1) th second power input terminal under control of the (i-1) th second data terminal.

4. The pixel circuit of claim 3, wherein, the (i-1) th second control circuit comprising: a charging circuit and a discharging circuit. The charging circuit of the i-1th second control circuit is coupled with the i th first data terminal and the i th first power input terminal, and is configured to increase the driving signal provided to the i th light emitting element by using the first power signal provided by the i th first power input terminal under the control of the i th first data terminal when the gray scale of the i th light emitting element is higher than that of the i-1th light emitting element; The discharging circuit of the i-1th second control circuit is coupled with the i-1th second data terminal and the i-1th second power input terminal, and is configured to decrease the driving signal provided to the i th light emitting element by using the second power signal provided by the i-1th second power input terminal under the control of the i-1th second data terminal when the gray scale of the i th light emitting element is lower than that of the i-1th light emitting element.

5. The pixel circuit of claim 4, wherein, The charging circuit of the i-1th second control circuit comprises a second data writing sub-circuit, a second storage sub-circuit and a second driving sub-circuit; the second data writing sub-circuit, the second storage sub-circuit and the second driving sub-circuit are coupled with the same node; The second data writing sub-circuit is further coupled with the i th first data terminal and the i th scanning line, and is configured to write the second data signal provided by the i th first data terminal into the second storage sub-circuit under the control of the i th scanning line when the gray scale of the i th light emitting element is higher than that of the i-1th light emitting element; The second storage sub-circuit is further coupled with a storage voltage line, and is configured to store the written second data signal; The second driving sub-circuit is further coupled with the i th first power input terminal and the first electrode of the i th light emitting element, and is configured to provide the driving signal to the first electrode of the i th light emitting element under the control of the second data signal.

6. The pixel circuit of claim 5, wherein, The second data writing sub-circuit comprises a second switching transistor, or comprises a second N-type transistor and a second P-type transistor; the second storage sub-circuit comprises a second capacitor, and the second driving sub-circuit comprises a second driving transistor; The gate of the second switching transistor is coupled with the i th scanning line, the first pole of the second switching transistor is coupled with the i th first data terminal, and the second pole of the second switching transistor is coupled with the first electrode of the second capacitor and the gate of the second driving transistor; The second electrode of the second capacitor is coupled with the storage voltage line; The first pole of the second driving transistor is coupled with the i th first power input terminal, and the second pole of the second driving transistor is coupled with the first electrode of the i th light emitting element; The gate of the second N-type transistor is coupled with the i th first scanning line, the gate of the second P-type transistor is coupled with the i th second scanning line, the first pole of the second N-type transistor and the first pole of the second P-type transistor are both coupled with the i th first data terminal, and the second pole of the second N-type transistor and the second pole of the second P-type transistor are coupled with the first electrode of the second capacitor and the gate of the second driving transistor.

7. The pixel circuit of claim 4, wherein, The discharge circuit of the i-1th second control circuit comprises a third data writing sub-circuit, a third storage sub-circuit and a third driving sub-circuit; the third data writing sub-circuit, the third storage sub-circuit and the third driving sub-circuit are coupled with the same node; The third data writing sub-circuit is further coupled with the i-1th second data terminal and the i-th scan line, and is configured to write the third data signal provided by the i-1th second data terminal into the third storage sub-circuit under the control of the i-th scan line when the gray scale of the i-th light emitting element is lower than that of the i-1th light emitting element; The third storage sub-circuit is further coupled with a storage voltage line and is configured to store the written third data signal; The third driving sub-circuit is further coupled with the i-1th second power input terminal and the first electrode of the i-th light emitting element, and is configured to provide a driving signal to the i-1th second power input terminal under the control of the third data signal.

8. The pixel circuit of claim 7, wherein, The third data writing sub-circuit comprises a third switch transistor or a third N-type transistor and a third P-type transistor; the third storage sub-circuit comprises a third capacitor; and the third driving sub-circuit comprises a third driving transistor; The gate of the third switch transistor is coupled with the i-th scan line, the first pole of the third switch transistor is coupled with the i-1th second data terminal, and the second pole of the third switch transistor is coupled with the first electrode of the third capacitor and the gate of the third driving transistor; The second electrode of the third capacitor is coupled with the storage voltage line; The first pole of the third driving transistor is coupled with the i-1th second voltage input terminal, and the second pole of the third driving transistor is coupled with the first electrode of the i-th light emitting element; The gate of the third N-type transistor is coupled with the i-th first scan line, the gate of the third P-type transistor is coupled with the i-th second scan line, the first poles of the third N-type transistor and the third P-type transistor are both coupled with the i-1th second data terminal, and the second poles of the third N-type transistor and the third P-type transistor are both coupled with the first electrode of the third capacitor and the gate of the third driving transistor.

9. The pixel circuit of claim 3, wherein, The first control circuit is coupled with a first power input terminal, and each second control circuit is coupled with a first power input terminal; The first power input terminal coupled with the first control circuit and the N-1 first power input terminals coupled with the N-1 second control circuits are configured to receive the same first power signal; Alternatively, the first power input terminal coupled with the first control circuit and the N-1 first power input terminals coupled with the N-1 second control circuits are configured to receive different first power signals, wherein the first power signal received by the i-th first power input terminal is smaller than the first power signal received by the i-1th first power input terminal.

10. The pixel circuit of claim 3, wherein, Each second control circuit is coupled with a second power input terminal; The N-1 second power input ends coupled with the N-1 second control circuits are configured to receive the same second power signal. Alternatively, the N-1 second power input ends coupled with the N-1 second control circuits are configured to receive different second power signals, wherein the second power signal received by the i-th second power input end is smaller than the second power signal received by the (i-1)-th second power input end.

11. The pixel circuit of claim 3, wherein, The first control circuit is coupled with a first data terminal, and each second control circuit is coupled with a first data terminal and a second data terminal. The first data terminal coupled with the first control circuit and the N-1 first data terminals coupled with the N-1 second control circuits are configured to be coupled with the same first data line. The N-1 second data terminals coupled with the N-1 second control circuits are configured to be coupled with the same second data line.

12. The pixel circuit of any one of claims 1-11, further comprising: The light-emitting control circuit is coupled with a light-emitting control line, a first driving transistor of the first control circuit, and a first power input end, and is configured to turn on a first electrode of the first driving transistor and the first power input end under control of the light-emitting control line.

13. The pixel circuit of claim 12, wherein, The light-emitting control circuit includes a light-emitting control transistor, a gate electrode of the light-emitting control transistor is coupled with the light-emitting control line, a first electrode of the light-emitting control transistor is coupled with the first power input end, and a second electrode of the light-emitting control transistor is coupled with the first electrode of the first driving transistor.

14. The pixel circuit of claim 12, further comprising: The first reset circuit is coupled with a reset control line, a first driving transistor of the first control circuit, and a reset voltage line, and is configured to turn on the first electrode of the first driving transistor and the reset voltage line under control of the reset control line.

15. The pixel circuit of claim 14, wherein, The first reset circuit includes a first reset transistor, a gate electrode of the first reset transistor is coupled with the reset control line, a first electrode of the first reset transistor is coupled with the reset voltage line, and a second electrode of the first reset transistor is coupled with the first electrode of the first driving transistor.

16. The pixel circuit of claim 12, further comprising: The second reset circuit is coupled with the light-emitting control line, a first electrode of the first light-emitting element, and a reset voltage line, and is configured to turn on the first electrode of the first light-emitting element and the reset voltage line under control of the light-emitting control line.

17. The pixel circuit of claim 16, wherein, The second reset circuit includes a second reset transistor, a gate electrode of the second reset transistor is coupled with the light-emitting control line, a first electrode of the second reset transistor is coupled with the reset voltage line, and a second electrode of the second reset transistor is coupled with the first electrode of the first light-emitting element.

18. The pixel circuit of claim 1, wherein, The transistors included in the pixel circuit are all silicon-based transistors.

19. A driving method of a pixel circuit, applied to the pixel circuit of any one of claims 1 to 18, the driving method comprising: the first control circuit provides a driving signal to the N light-emitting elements connected in series; the (i-1)-th second control circuit adjusts the driving signal provided to the i-th light-emitting element among the N light-emitting elements.

20. The driving method according to claim 19, wherein The i-1th second control circuit adjusts a driving signal provided to an i-th light emitting element of the N light emitting elements, including: When a gray scale of the i-th light emitting element is higher than a gray scale of the i-1th light emitting element, the i-1th second control circuit increases the driving signal provided to the i-th light emitting element; When the gray scale of the i-th light emitting element is lower than the gray scale of the i-1th light emitting element, the i-1th second control circuit decreases the driving signal provided to the i-th light emitting element. 21.A display substrate, comprising a substrate, a plurality of pixel circuits and a plurality of light emitting elements disposed on the substrate; the pixel circuit is the pixel circuit according to any one of claims 1 to 18, and the pixel circuit is configured to drive N light emitting elements connected in series, N being an integer greater than 1.

22. The display substrate of claim 21, wherein, The substrate is a silicon substrate, and the plurality of light emitting elements are micro light emitting elements. 23.A display device, comprising the display substrate according to any one of claims 21 to 22.

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