Package structure and electronic device

Abstract

The present application provides a package structure and an electronic device. The package structure comprises: a carrier structure; at least two conductive structures, a part of each conductive structure being located inside the carrier structure, and the remaining part of each conductive structure being located outside the carrier structure; and at least two electroplating lines, wherein any one of the electroplating lines is disposed on a surface of or inside the carrier structure, a first electroplating line among the at least two electroplating lines is connected to a first conductive structure among the at least two conductive structures, and a second electroplating line among the at least two electroplating lines is connected to a second conductive structure among the at least two conductive structures. The first electroplating line and the second electroplating line are stacked in a thickness direction of the carrier structure, and a projection of the first electroplating line on the carrier structure overlaps with a projection of the second electroplating line on the carrier structure. The present application can reduce the surface area of the package structure while reducing far-end crosstalk.

Description

Package structure and electronic device TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, and in particular to a package structure and an electronic device. BACKGROUND

[0002] In an electronic device including a high-speed parallel interface, far-end crosstalk between ports becomes a key bottleneck restricting the electronic device. The electronic device usually includes a package structure and a circuit board, and the package structure is connected to the circuit board through a plurality of solder balls arranged at the bottom. In order to avoid far-end crosstalk between adjacent solder balls, a ground solder ball is usually added between adjacent solder balls, but this will result in a large surface area of the package structure, thereby increasing the cost of the package structure. SUMMARY

[0003] In order to solve the above technical problems, the present application provides a package structure and an electronic device, which can reduce the surface area of the package structure while reducing far-end crosstalk.

[0004] In a first aspect of the present application, a package structure is provided, comprising a carrier structure, at least two conductive structures, and at least two plated lines. The at least two conductive structures include a first conductive structure and a second conductive structure, and a part of each conductive structure is located inside the carrier structure, and the remaining part of each conductive structure is located outside the carrier structure. For example, the conductive structure can include a conductive hole and a soldering part, and the conductive hole can be a through silicon via or a plated hole, and the soldering part can include a solder ball and / or a solder pad. Any plated line is arranged on the surface or inside the carrier structure, and the at least two plated lines include a first plated line and a second plated line. The first plated line is connected to the first conductive structure, and the second plated line is connected to the second conductive structure. The first plated line and the second plated line are stacked along the thickness direction of the carrier structure, and the projection of the first plated line on the carrier structure and the projection of the second plated line on the carrier structure overlap.

[0005] In the present application, the overlapping part of the first plated line and the second plated line can form a mutual capacitance structure. Since the first plated line is connected to the first conductive structure and the second plated line is connected to the second conductive structure, the mutual capacitance value between the first conductive structure and the second conductive structure can be increased. According to the calculation formula of the capacitive coupling coefficient between two transmission lines, the capacitive coupling coefficient is positively correlated with the mutual capacitance value, and the capacitive coupling coefficient is much smaller than the inductive coupling coefficient of the package structure, which will result in a large far-end crosstalk. When the mutual capacitance value between the first conductive structure and the second conductive structure increases, the capacitive coupling coefficient between the first conductive structure and the second conductive structure increases, so that the capacitive coupling coefficient is as close as possible to the inductive coupling coefficient between the first conductive structure and the second conductive structure, thereby reducing the far-end crosstalk between the first conductive structure and the second conductive structure.

[0006] In addition, the technical solution can reduce far-end crosstalk between the first conductive structure and the second conductive structure, so that a ground solder ball does not need to be added between the first conductive structure and the second conductive structure. Compared with a solution of reducing far-end crosstalk by adding a ground solder ball, the surface area of the bearing structure is smaller, that is, the surface area of the package structure can be reduced by the application, thereby reducing the surface area and cost of the package structure. Therefore, the application can reduce the surface area of the package structure while reducing the far-end crosstalk.

[0007] In addition, based on the process consideration of electroplating filling, generally, an electroplating line is originally arranged on the package structure. The first electroplating line and the second electroplating line are arranged in a stacked manner in the application for the purpose of reducing far-end crosstalk. Therefore, the process route of the existing package structure does not need to be changed, and the cost of the package structure is not increased.

[0008] In a possible embodiment of the application, a projection of an end portion of the first electroplating line on the bearing structure away from the conductive structure coincides with a projection of an end portion of the second electroplating line on the bearing structure away from the conductive structure.

[0009] In another possible embodiment of the application, a projection of a first end portion of the first electroplating line on the bearing structure away from the conductive structure does not overlap with a projection of a second end portion of the second electroplating line on the bearing structure away from the conductive structure. In the process of manufacturing the package structure, the multilayer large-size substrate can be sequentially stacked to form a large-size bearing structure, and then the chip is bonded to the large-size bearing structure, and cutting is performed to form the package structure. In the process of cutting, copper ions on the electroplating line may migrate, thereby causing short circuit between adjacent electroplating lines, and further causing short circuit of the package structure in use. In the present solution, the projection of the first end portion of the first electroplating line on the bearing structure away from the conductive structure does not overlap with the projection of the second end portion of the first electroplating line on the bearing structure away from the conductive structure. Therefore, the distance between the first end portion of the first electroplating line away from the conductive structure and the first end portion of the second electroplating line away from the conductive structure is greater than the distance between the first end portion and the second end portion in the stacking direction, and greater than the distance between the projection of the first end portion on the bearing structure and the projection of the second end portion on the bearing structure. Therefore, the distance between the first end portion and the second end portion can be increased, thereby reducing the migration of copper ions on the first electroplating line to the second electroplating line, and further avoiding short circuit.

[0010] In a specific implementation, the electroplating line includes a connection segment, a body segment and an extension segment connected in sequence, the extension segment is located at an end of the connection segment away from the conductive structure, and the length of the body segment is greater than the lengths of the connection segment and the extension segment. The projection of the body segment of the first electroplating line on the carrier structure coincides with the projection of the body segment of the second electroplating line on the carrier structure. In this way, the body segment of the first electroplating line and the body segment of the second electroplating line can form a mutual containment structure, thereby being able to increase the capacitive coupling coefficient between the first conductive structure and the second conductive structure, and further reduce the far-end crosstalk. Moreover, the projection of the extension segment of the first electroplating line on the carrier structure does not overlap with the projection of the extension segment of the second electroplating line on the carrier structure. In this way, the distance between the first end of the extension segment of the first electroplating line away from the first end of the conductive structure and the second end of the extension segment of the second electroplating line away from the second end of the conductive structure is large, thereby being able to avoid the situation that copper ions of the first electroplating line migrate to the second electroplating line in the process of cutting, and further avoid short circuit.

[0011] In a possible implementation, the extension segment extends along a straight line in the extension direction of the extension segment. In this case, the extension direction of the extension segment of the first electroplating line is different from the extension direction of the extension segment of the second electroplating line.

[0012] In an example, the extension segment of the first electroplating line and the extension segment of the second electroplating line are located on the same side of the body segment, but the extension direction of the extension segment of the first electroplating line is different from the extension direction of the extension segment of the second electroplating line. For example, the first electroplating line has a first included angle between the extension segment and the body segment, the second electroplating line has a second included angle between the extension segment and the body segment, and the first included angle and the second included angle are different. Since the electroplating line is used for electroplating filling from the end of the electroplating line away from the conductive structure, in order to facilitate the electroplating liquid to fill more smoothly in the packaging structure, the first included angle and the second included angle can both be obtuse angles. For example, the first included angle is 135°, and the second included angle is greater than or less than 135°; or, the second included angle is 135°, and the first included angle is greater than or less than 135°.

[0013] In another example, in order to further increase the distance between the first end of the extension segment of the first electroplating line away from the first conductive structure and the second end of the extension segment of the second electroplating line away from the second conductive structure, the extension segment of the first electroplating line and the extension segment of the second electroplating line are respectively located on opposite sides of the body segment. For example, the extension segment of the first electroplating line is located on a first side of the body segment, the extension segment of the second electroplating line is located on a second side of the body segment, and the first side and the second side are different sides. In this way, the distance between the first end of the extension segment of the first electroplating line away from the first conductive structure and the second end of the extension segment of the second electroplating line away from the second conductive structure can be further increased, thereby better avoiding short circuit.

[0014] In another possible implementation, the extension section includes a first sub-extension section close to the body section and a second sub-extension section away from the body section, the second sub-extension section is different from the first sub-extension section in the extension direction, and the included angle between the second sub-extension section and the first sub-extension section is obtuse, and the included angle between the first sub-extension section and the body section is also obtuse. In an example, the extension section of the first electroplating line and the extension section of the second electroplating line can be located on the same side of the body section. In another example, the extension section of the first electroplating line and the extension section of the second electroplating line can be located on different sides of the body section, thereby further increasing the distance between the extension section of the first electroplating line away from the first end of the first conductive structure and the extension section of the second electroplating line away from the second end of the second conductive structure.

[0015] In some embodiments of the present application, the connection section of the first electroplating line is located on the first side of the body section, and the connection section of the second electroplating line is located on the second side of the body section, the first side and the second side are different sides. That is, the first electroplating line and the second electroplating line are respectively located on opposite sides of the body section. Specifically, the included angle between the connection section of the first electroplating line and the body section is obtuse, and the included angle between the connection section of the second electroplating line and the body section is also obtuse, and the first electroplating line and the second electroplating line extend towards each other at the connection section until the projections on the carrier structure coincide. Thus, the overall length of the first electroplating line and the second electroplating line is relatively close, and the electroplating filling time of each electroplating line is more close during the electroplating filling process, thereby improving the electroplating efficiency.

[0016] Since the number of conductive structures of the packaging structure is usually greater than 2, each conductive structure corresponds to at least one electroplating line, and the structure for reducing the far-end crosstalk between three conductive structures is described here. For example, the at least two conductive structures further include a third conductive structure, and the at least two electroplating lines further include a third electroplating line connected to the third conductive structure. The second conductive structure is located between the first conductive structure and the third conductive structure. Therefore, the distance between the first conductive structure and the third conductive structure is large, and the far-end crosstalk between the two is small. The first conductive structure and the second conductive structure can be adjacent conductive structures, and the second conductive structure and the third conductive structure can be adjacent conductive structures, so the far-end crosstalk between the first conductive structure and the second conductive structure and the far-end crosstalk between the second conductive structure and the third conductive structure are relatively large.

[0017] In one possible implementation, the first and third plated lines are arranged in the same layer and are spaced apart. Since the first and second plated lines are arranged in a stacked manner, the third plated line is also arranged in a stacked manner with the second plated line. Moreover, the projection of the body segment of the first plated line and the projection of the body segment of the third plated line on the bearing structure are both within the projection of the body segment of the second plated line on the bearing structure. When the projection of the body segment of the first plated line on the bearing structure is within the projection of the body segment of the second plated line on the bearing structure, a mutual capacitance structure can be formed between the first and second plated lines, thereby increasing the capacitive coupling coefficient between the first and second conductive structures and reducing the far-end crosstalk between the first and second conductive structures. When the projection of the body segment of the third plated line on the bearing structure is within the projection of the body segment of the second plated line on the bearing structure, a mutual capacitance structure can be formed between the third and second plated lines, thereby increasing the capacitive coupling coefficient between the third and second conductive structures and reducing the far-end crosstalk between the third and second conductive structures.

[0018] In another possible implementation, the first, second and third plated lines are arranged in different layers respectively, and the projections of the first, second and third plated lines on the bearing structure all overlap. In this way, a mutual capacitance structure can be formed between the first and second plated lines, thereby reducing the far-end crosstalk between the first and second conductive structures; and a mutual capacitance structure can also be formed between the second and third plated lines, thereby reducing the far-end crosstalk between the second and third conductive structures.

[0019] Moreover, the projections of the first, second and third end portions of the first, second and third plated lines on the bearing structure do not overlap. That is, the projection of the first end portion of the first plated line, the projection of the second end portion of the second plated line, and the projection of the third end portion of the third plated line on the bearing structure do not overlap, thereby increasing the distance between the first end portion of the first plated line and the second end portion of the second plated line, and increasing the distance between the second end portion of the second plated line and the third end portion of the third plated line, so as to avoid short circuit.

[0020] In another possible implementation, the at least two electroplated lines further include a fourth electroplated line, the third electroplated line is connected to the second conductive structure, and the fourth electroplated line is connected to the third conductive structure. The fourth electroplated line is stacked along the thickness direction with the third electroplated line, and the fourth electroplated line is in the same layer as the second electroplated line and is spaced apart from the second electroplated line, and the third electroplated line is in the same layer as the first electroplated line and is spaced apart from the first electroplated line. In this way, a mutual capacitance structure can be formed between the first electroplated line and the second electroplated line, and a mutual capacitance structure can be formed between the third electroplated line and the fourth electroplated line, thereby reducing far-end crosstalk between the first conductive structure and the second conductive structure and reducing far-end crosstalk between the second conductive structure and the third conductive structure, respectively.

[0021] In some embodiments of the present application, the carrier structure includes at least two layers of substrates stacked along the thickness direction and a dielectric layer between adjacent two layers of substrates, and the first electroplated line and the second electroplated line are stacked between the top surface of the top layer of substrates and the bottom surface of the bottom layer of substrates. For example, the first electroplated line can be arranged on the surface of the substrate or inside the dielectric layer. Specifically, the first electroplated line can be arranged on the top surface or the bottom surface of the top layer of substrates or on the top surface or the bottom surface of the bottom layer of substrates. The second electroplated line can be arranged on the surface of the substrate or inside the dielectric layer. Specifically, the second electroplated line can be arranged on the top surface or the bottom surface of the top layer of substrates or on the top surface or the bottom surface of the bottom layer of substrates, as long as the first electroplated line and the second electroplated line are stacked. In this way, the arrangement of the first electroplated line and the second electroplated line is more convenient.

[0022] In some embodiments of the present application, the conductive structure includes a conductive hole inside the carrier structure and a solder outside the carrier structure, and the solder of the first conductive structure and the solder of the second conductive structure are adjacent or spaced apart. That is, in the present application, the electroplated lines of the two conductive structures are arranged in a stacked structure to form a mutual capacitance structure to reduce far-end crosstalk. The electroplated line has the advantage of flexible wiring, so the present application can not only arrange the structure for reducing far-end crosstalk for adjacent solders, but also arrange the structure for reducing far-end crosstalk for spaced-apart solders, that is, the arrangement of the structure for reducing far-end crosstalk in the present application is more flexible.

[0023] The second aspect of the present application also provides an electronic device including a circuit board and the packaging structure of any of the above embodiments, and the packaging structure is arranged on the circuit board. The electronic device can realize all the effects of the packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments of the present application will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0025] Figure 1 is a schematic diagram of a scheme to reduce far-end crosstalk in related technologies;

[0026] Figure 2 shows the equivalent circuit diagram of the two transmission lines;

[0027] Figure 3 is a schematic diagram showing the adjustment of the self-capacitance and mutual capacity of the two transmission lines;

[0028] Figure 4 is a schematic diagram of the encapsulation structure in the first embodiment of this application;

[0029] Figure 5 is a three-dimensional structural diagram of part of the structure in Figure 4;

[0030] Figure 6 is a top view of Figure 4;

[0031] Figure 7 is a schematic diagram of the cross-section at point AA in Figure 4;

[0032] Figure 8 is a schematic diagram of the cross-section at point BB in Figure 4;

[0033] Figure 9 is a three-dimensional schematic diagram showing the positional relationship between the conductive structure, microstrip line, and electroplating line of the packaging structure shown in Figure 4.

[0034] Figure 10 is a structural schematic diagram of the positional relationship shown in Figure 9 from a first perspective;

[0035] Figure 11 is a structural schematic diagram of the positional relationship shown in Figure 9 from a second perspective;

[0036] Figure 12 is a schematic diagram of the positional relationship between the conductive structure, microstrip line and electroplating line of the encapsulation structure in the second embodiment of this application from a second perspective.

[0037] Figure 13 is a three-dimensional schematic diagram of the positional relationship between the conductive structure, microstrip line and electroplating line of the packaging structure in the third embodiment of this application;

[0038] Figure 14 shows the crosstalk curves of this embodiment and related technologies in the frequency domain;

[0039] Figure 15 shows the crosstalk curves in the time domain for this embodiment and related technologies;

[0040] Figure 16 shows the eye diagram of the relevant technology;

[0041] Figure 17 is an eye diagram of this embodiment;

[0042] Figure 18 is a three-dimensional schematic diagram of the positional relationship between the conductive structure, microstrip line and electroplating line of the packaging structure in the fourth embodiment of this application;

[0043] Figure 19 is a schematic diagram of the positional relationship between the conductive structure, microstrip line and electroplating line of the packaging structure in the fifth embodiment of this application from a second perspective.

[0044] Fig. 20 is a structural schematic diagram of the positional relationship shown in Fig. 19 in a first perspective view;

[0045] Fig. 21 is a structural schematic diagram of the positional relationship of the conductive structure, the microstrip line and the plated wire of the packaging structure in the sixth embodiment of the present application in a second perspective view;

[0046] Fig. 22 is a structural schematic diagram of the positional relationship of the conductive structure, the microstrip line and the plated wire of the packaging structure in the sixth embodiment of the present application in a second perspective view;

[0047] Fig. 23 is a structural schematic diagram of the positional relationship of the conductive structure, the microstrip line and the plated wire of the packaging structure in the sixth embodiment of the present application in a second perspective view.

[0048] Fig. 23 is a structural schematic diagram of the positional relationship of the conductive structure, the microstrip line and the plated wire of the packaging structure in the sixth embodiment of the present application in a second perspective view. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0050] The term "and / or", merely used to describe associated objects, means that there can be three relationships, for example, A and / or B, can mean: A alone, A and B exist at the same time, B alone, the three cases, where A, B can be singular or plural. The character " / " generally represents the "or" relationship between the associated objects before and after. "At least one" means one or more, "multiple" means two or more. "At least one" or the like means any combination of these items, including single or multiple items. For example, at least one of a, b or c, can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0051] The terms "first" and "second" and the like in the description and claims of the present application are used to distinguish different objects, not to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, not to describe the specific order of the target objects.

[0052] The terms "connection", "connected", and the like are used to express the intercommunication or interaction between different components, which can include direct connection or indirect connection through other components. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, including a series of steps or units. The method, system, product or device does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", and the like are only used for the orientation of the components in the drawings, and these directional terms are relative concepts, which are used for relative description and clarification, which can change accordingly according to the orientation of the components placed in the drawings.

[0053] In the embodiments of the present application, the words "exemplary" or "for example" are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" and the like is intended to present the relevant concept in a specific manner.

[0054] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more. For example, multiple processing units mean two or more processing units; multiple systems mean two or more systems.

[0055] High-speed parallel interfaces, such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), high bandwidth memory (HBM), etc., often have far-end crosstalk (FEXT) between signal ports, which becomes a key bottleneck restricting the performance of devices, especially based on packaging structures such as wire bonding (WB).

[0056] To find other solutions to reduce FEXT, an equivalent circuit of two lossless coupled transmission lines can be established as shown in FIG. 2. As shown in FIG. 2, a1 is one of the transmission lines, a2 is the other transmission line, and a3 is the ground line. S L represents the self-inductance per unit length of a single transmission line, M C represents the mutual inductance per unit length of two transmission lines, M C represents the mutual capacitance per unit length between two transmission lines, g C represents the capacitance per unit length of a single transmission line to ground. Here, the interference of transmission line a1 on transmission line a2 is analyzed, i.e., transmission line a1 is the attacking line, and transmission line a2 is the victim line. Then, the FEXT on transmission line a2 can be calculated as follows:

[0057] In the formula, k represents a constant.

[0058] If the packaging structure includes structures such as blind holes (BH), buried holes (BH), plating through holes (PTH), solder balls, connectors, WB, etc., the following expression exists:

[0059] wherein, is a capacitive coupling coefficient, is an inductive coupling coefficient, that is, if the packaging structure comprises the above structure, it indicates that the capacitive coupling coefficient is less than the inductive coupling coefficient, and the capacitive coupling coefficient is much smaller than the inductive coupling coefficient.

[0060] When the capacitive coupling coefficient is equal to the inductive coupling coefficient, the far-end crosstalk between the two transmission lines is almost 0, that is, the closer the capacitive coupling coefficient is to the inductive coupling coefficient, the smaller the far-end crosstalk between the two transmission lines. Therefore, in order to reduce the far-end crosstalk, the capacitive coupling coefficient can be increased or the inductive coupling coefficient can be reduced. Specifically, as shown in FIG. 3, the mutual capacitance C M or the ground capacitance C g of the transmission line a1 and the ground capacitance C g of the transmission line a2 are increased to increase the capacitive coupling coefficient. The self-inductance L S or the mutual inductance L M is increased to reduce the inductive coupling coefficient.

[0061] Based on this, in the embodiments of the present application, a packaging structure is proposed, which can increase the mutual capacitance value, thereby increasing the capacitive coupling coefficient, making the capacitive coupling coefficient as close as possible to the inductive coupling coefficient, thereby reducing the far-end crosstalk; at the same time, it can also reduce the surface area of the packaging structure, thereby reducing the cost of the packaging structure.

[0062] The embodiment can be applied to a DDR SDRAM, a LPDDR SDRAM, an HBM, an interconnection between chips, a parallel interconnection scenario of a single-ended signal, a serial interconnection scenario of a single-ended signal, a parallel interconnection scenario of a differential signal, or a serial interconnection scenario of a differential signal. Specifically, the packaging structure of the embodiment can be a memory, specifically a DDR or a LPDDR, etc. The packaging structure can be applied to an electronic device, which can include a circuit board, specifically a printed circuit board (PCB), in addition to the packaging structure. The packaging structure is arranged on the circuit board and is electrically connected to the circuit board. Here, the electronic device can be, for example, a server, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc., which are not limited by the embodiment of the present application. Illustratively, the consumer electronic product can be a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet, etc.), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, etc. The home electronic product can be a smart door lock, a television, a smart sound box, a refrigerator, a sweeping robot, etc. The vehicle-mounted electronic product can be a vehicle-mounted navigator, a vehicle-mounted display, etc. The financial terminal product can be an automated teller machine (ATM), a self-service electronic device, etc. The communication electronic product can be a server, a memory, a radar, a base station, etc.

[0063] For ease of description, three directions can be defined, which are a first direction (X direction), a second direction (Y direction), and a third direction (Z direction), where the X direction can refer to a length direction of the packaging structure, the Y direction can refer to a width direction of the packaging structure, and the Z direction can refer to a thickness direction of the packaging structure. The X direction, the Y direction, and the Z direction are perpendicular to each other.

[0064] As shown in FIG. 4, the packaging structure 1 can include a bearing structure 10, at least two conductive structures 20, and at least two plating lines 30.

[0065] As shown in FIG. 4, in the embodiment, the carrying structure 10 can include at least two layers of substrates 11 and a dielectric layer 12. The at least two layers of substrates 11 are stacked along the Z direction, and the dielectric layer 12 is located between the adjacent two layers of substrates 11. In other embodiments, the carrying structure 10 can also be a circuit board, which can include a plurality of layers of PCBs stacked in sequence, or the carrying structure 10 can also be a chip or other structure or a carrier plate made of insulating material, etc.

[0066] The number of layers of the dielectric layer 12 is related to the number of layers of the substrate 11. For example, in the embodiment, as shown in FIG. 4, when the number of layers of the substrate 11 is two, the number of layers of the dielectric layer 12 is one. In other embodiments, when the number of layers of the substrate 11 is three, the number of layers of the dielectric layer 12 is two, and each layer of the dielectric layer 12 is located between each adjacent two layers of the substrate 11.

[0067] Referring to FIG. 4, part of each conductive structure 20 is located inside the carrying structure 10, and the rest of each conductive structure 20 is located outside the carrying structure 10. Specifically, the conductive structure 20 can include a conductive hole 21 and a solder 22. The conductive hole 21 is located inside the carrying structure 10, and the solder 22 is located outside the carrying structure 10. The conductive hole 21 can be a buried hole, a blind hole or a PTH. The PTH can penetrate from the top surface to the bottom surface of the carrying structure 10, and the buried hole or the blind hole has a size along the Z direction smaller than the size of the carrying structure 10 along the Z direction.

[0068] As shown in FIG. 5, the solder 22 can specifically include a solder ball 223 and a solder pad 224. The solder ball 223 is electrically connected to the conductive hole 21 through the solder pad 224. For example, as shown in FIG. 5, the solder pad 224 is in contact with the conductive hole 21, thereby realizing electrical connection.

[0069] Referring to FIGS. 4 and 6, the packaging structure 1 in the embodiment can further include a chip 40, a chip pad 41, a WB 50, a substrate pad 111 and a microstrip line 60. As shown in FIG. 5, one end of the WB 50 is connected to the chip pad 41, the other end of the WB 50 is connected to the substrate pad 111, and the substrate pad 111 is electrically connected to the microstrip line 60. The microstrip line 60 can be a copper line provided on the surface of the substrate 11, and the microstrip line 60 can be in contact with and electrically connected to the conductive hole 21. Therefore, the chip 40 shown in FIG. 4 can be electrically connected to the solder 22 shown in FIG. 4 through the chip pad 41, the WB 50, the substrate pad 111, the microstrip line 60 and the conductive hole 21, and then electrically connected to the circuit board in the electronic device through the solder 22. It can be understood that in FIG. 4, the solder 22 can be a signal solder ball for signal transmission.

[0070] In the embodiment, the chip 40 can be an unpackaged chip 40, i.e., a bare chip, or a packaged functional module. For example, the chip 40 can be a system on chip (SOC), a test or dummy chip, a central processing unit (CPU), a graphics processing unit (GPU), a memory, an input / output (I / O) chip, an integrated passive device (IPD), etc. The chip 40 can also be integrated with other packaged functional modules, such as a high bandwidth memory (HBM), a die on silicon interposer (DOI), a fan out RDL interposer (FOI), etc. In actual applications, a plurality of chips 40 can be provided according to requirements. The plurality of chips 40 can include at least one of the chips 40 listed above.

[0071] Referring to FIG. 4, any of the electroplated lines 30 is arranged on the surface or inside of the carrier structure 10. For example, any of the electroplated lines 30 can be arranged on the surface of the substrate 11 or inside the dielectric layer 12, and each of the electroplated lines 30 extends to the edge of the carrier structure 10. The electroplated lines 30 and the conductive holes 21 can be generally formed by electroplating filling. For example, during the process of forming the packaging structure 1, a plurality of through holes and electroplated holes are formed on the carrier structure 10, each of the through holes is in communication with one or more electroplated holes, and each of the electroplated holes extends to the edge of the carrier structure 10. After the bonding of the chip 40 is completed, electroplating liquid can be filled into each of the electroplated holes, and the electroplating liquid flows from the electroplated hole to the through hole, thereby forming the electroplated lines 30 and the conductive holes 21. Moreover, any of the conductive holes 21 is connected with one or more electroplated lines 30.

[0072] As shown in FIG. 4, the number of the conductive structures 20 in the packaging structure 1 is greater than two. Hereinafter, the scheme for reducing far-end crosstalk is described by taking two conductive structures 20 as an example.

[0073] As shown in FIGS. 7 and 8, for the convenience of description, the at least two conductive structures 20 include a first conductive structure 201 and a second conductive structure 202. The first conductive structure 201 and the second conductive structure 202 are arranged along the Y direction.

[0074] Referring to FIG. 9, the at least two plated wires 30 include a first plated wire 31 and a second plated wire 32. The first plated wire 31 is connected to the first conductive structure 201, and the second plated wire 32 is connected to the second conductive structure 202. Specifically, the first plated wire 31 can be connected to the conductive hole 21 or the soldering part 22 of the first conductive structure 201, and the second plated wire 32 can be connected to the conductive hole 21 or the soldering part 22 of the second conductive structure 202.

[0075] As shown in FIG. 8, the first plated wire 31 and the second plated wire 32 are stacked along the Z direction. In specific implementation, the first plated wire 31 and the second plated wire 32 are stacked between the top surface of the top substrate 11 and the bottom surface of the bottom substrate 11. For example, the first plated wire 31 can be arranged on the surface of the substrate 11 or inside the dielectric layer 12. Specifically, the first plated wire 31 can be arranged on the top surface or the bottom surface of the top substrate 11, or arranged on the top surface or the bottom surface of the bottom substrate 11. The second plated wire 32 can be arranged on the surface of the substrate 11 or inside the dielectric layer 12. Specifically, the second plated wire 32 can be arranged on the top surface or the bottom surface of the top substrate 11, or arranged on the top surface or the bottom surface of the bottom substrate 11, as long as the first plated wire 31 and the second plated wire 32 are stacked. In this way, the arrangement of the first plated wire 31 and the second plated wire 32 is more convenient.

[0076] Referring to FIG. 8, the projection of the first plated wire 31 on the carrier structure 10 overlaps with the projection of the second plated wire 32 on the carrier structure 10. That is, the partial projection of the first plated wire 31 on the carrier structure 10 coincides with the partial projection of the second plated wire 32 on the carrier structure 10. In this way, the overlapping part of the first plated wire 31 and the second plated wire 32 can form a mutual capacity structure. Since the first plated wire 31 is connected to the first conductive structure 201, and the second plated wire 32 is connected to the second conductive structure 202, the mutual capacity value between the first conductive structure 201 and the second conductive structure 202 can be increased. According to the calculation formula of the capacitive coupling coefficient between two transmission lines, the capacitive coupling coefficient is positively correlated with the mutual capacity value, and the capacitive coupling coefficient is much smaller than the inductive coupling coefficient of the packaging structure 1, which will result in a larger far-end crosstalk. It can be understood that the inductive coupling usually exists between the WB50 and the WB50, and exists between the microstrip line 60 and the microstrip line 60. When the mutual capacity value between the first conductive structure 201 and the second conductive structure 202 increases, the capacitive coupling coefficient between the first conductive structure 201 and the second conductive structure 202 increases, so that the capacitive coupling coefficient is as close as possible to the inductive coupling coefficient between the first conductive structure 201 and the second conductive structure 202, thereby reducing the far-end crosstalk between the first conductive structure 201 and the second conductive structure 202.

[0077] The technical solution can be applied to the current high-density signal ground ratio scene. For example, in the related art shown in FIG. 1, the ratio of the signal solder ball 221 to the ground solder ball 222 is high. Since the technical solution can reduce the far-end crosstalk between the first conductive structure 201 and the second conductive structure 202 shown in FIG. 8, it is not necessary to add a ground solder ball between the first conductive structure 201 and the second conductive structure 202. Compared with the solution of reducing far-end crosstalk by adding a ground solder ball, the surface area of the bearing structure 10 of the embodiment is smaller, that is, the embodiment can reduce the surface area of the bearing structure 10, thereby reducing the surface area and cost of the packaging structure 1. Therefore, the embodiment can reduce the surface area of the packaging structure 1 while reducing the far-end crosstalk.

[0078] In addition, based on the process consideration of electroplating filling, generally, an electroplating line is originally arranged on the packaging structure 1. The embodiment specially designs the positional relationship of the first electroplating line 31 and the second electroplating line 32, for example, the first electroplating line 31 and the second electroplating line 32 are arranged in layers, for the purpose of reducing the far-end crosstalk. Therefore, it is not necessary to change the process route of the existing packaging structure 1, and the cost of the packaging structure 1 will not be increased.

[0079] Furthermore, in some related art, a mutual capacity structure is added on the pad and other structures to increase the mutual capacity value, so as to increase the capacitive coupling coefficient. However, this solution will cause impedance discontinuity or structural mutation on the signal link, thereby affecting the signal transmission.

[0080] The continuity of impedance is mainly related to whether the size of the conductive hole 21 and the solder part 22 is mutated. Since the mutual capacity structure is not added on the conductive hole 21 or the solder part 22 in the embodiment to increase the mutual capacity structure, the conductive structure 20 can maintain the continuity of the impedance, thereby ensuring that the insertion loss of the packaging structure 1 is not deteriorated. Furthermore, the conductive hole 21 and the solder part 22 do not have structural mutation caused by the added extension structure, and therefore, there is no structural mutation on the signal link, thereby not affecting the signal transmission.

[0081] As shown in FIG. 8, in the embodiment, the solder part 22 of the first conductive structure 201 and the solder part 22 of the second conductive structure 202 are adjacent solder parts 22. In other embodiments, the solder part 22 of the first conductive structure 201 and the solder part 22 of the second conductive structure 202 are spaced apart solder parts 22. The electroplating line 30 has the advantage of flexible wiring, and therefore, the embodiment can not only arrange the structure for reducing the far-end crosstalk on the adjacent solder parts 22, but also arrange the structure for reducing the far-end crosstalk on the spaced apart solder parts 22, that is, the structure for reducing the far-end crosstalk of the embodiment is more flexible.

[0082] In the embodiment, as shown in FIG. 7, the projection of the first end portion 311 of the first electroplated line 31 on the carrier structure 10 away from the conductive structure 20 does not overlap with the projection of the second end portion 321 of the second electroplated line 32 on the carrier structure 10 away from the conductive structure 20. In the process of manufacturing the packaging structure 1, the multi-layer large-size substrate 11 can be sequentially stacked to form the large-size carrier structure 10, and then the chip 40 is bonded to the large-size carrier structure 10, and cutting is performed to form the packaging structure 1. In the process of cutting, copper ions on the electroplated line 30 can migrate, thereby causing short circuit between adjacent electroplated lines 30, and further causing short circuit of the packaging structure 1 in the process of use. In the present solution, the projection of the first end portion 311 of the first electroplated line 31 on the carrier structure 10 away from the conductive structure 20 does not overlap with the projection of the second end portion 321 of the second electroplated line 32 on the carrier structure 10 away from the conductive structure 20, so that the distance d between the first end portion 311 of the first electroplated line 31 and the second end portion 321 of the second electroplated line 32 shown in FIG. 9 is greater than the distance d1 between the first end portion 311 and the second end portion 321 along the Z direction shown in FIG. 10, and greater than the distance d2 between the projection of the first end portion 311 on the carrier structure 10 and the projection of the second end portion 321 on the carrier structure 10 shown in FIG. 11, so that the distance between the first end portion 311 and the second end portion 321 can be increased, thereby reducing the migration of copper ions on the first electroplated line 31 to the second electroplated line 32, and further avoiding short circuit.

[0083] It can be understood that in other embodiments, if the distance between the first conductive structure 201 and the second conductive structure 202 is large, the projection of the end portion of the first electroplated line 31 on the carrier structure 10 away from the conductive structure 20 overlaps with the projection of the end portion of the second electroplated line 32 on the carrier structure 10 away from the conductive structure 20.

[0084] Referring to FIG. 9, the electroplated line 30 includes a connection segment 301, a body segment 302 and an extension segment 303 connected in sequence. The connection segment 301 is connected with the conductive structure 20. The extension segment 303 is located at one end of the connection segment 301 away from the conductive structure 20. The length of the body segment 302 is greater than the length of the connection segment 301 and the length of the extension segment 303. That is, the length of the body segment 302 is greater than the length of the connection segment 301, and the length of the body segment 302 is also greater than the length of the extension segment 303.

[0085] Referring to FIG. 11, the projection of the body segment 302 of the first electroplated line 31 on the carrier structure 10 shown in FIG. 8 overlaps with the projection of the body segment 302 of the second electroplated line 32 on the carrier structure 10 shown in FIG. 8. Thus, the body segment 302 of the first electroplated line 31 and the body segment 302 of the second electroplated line 32 can form a mutual capacitive structure, thereby increasing the capacitive coupling coefficient between the first conductive structure 201 and the second conductive structure 202, and further reducing far-end crosstalk.

[0086] Furthermore, as shown in FIG. 11, the projection of the extension segment 303 of the first electroplated line 31 on the carrier structure 10 shown in FIG. 8 does not overlap with the projection of the extension segment 303 of the second electroplated line 32 on the carrier structure 10 shown in FIG. 8. Thus, the extension segment 303 of the first electroplated line 31 is away from the first end portion 311 of the first conductive structure 201, and the distance between the extension segment 303 of the second electroplated line 32 and the second end portion 321 of the second conductive structure 202 is large, so that the copper ions of the first electroplated line 31 can be prevented from migrating to the second electroplated line 32 during the cutting process, and thus short circuit can be avoided.

[0087] In one possible implementation, the extension segment 303 extends along a straight line in the extension direction of the extension segment 303, as shown in FIG. 11. In this case, the extension direction of the extension segment 303 of the first electroplated line 31 is different from the extension direction of the extension segment 303 of the second electroplated line 32.

[0088] In one example, the extension segment 303 of the first electroplated line 31 and the extension segment 303 of the second electroplated line 32 are located on the same side of the body segment 302, but the extension direction of the extension segment 303 of the first electroplated line 31 is different from the extension direction of the extension segment 303 of the second electroplated line 32. For example, the first electroplated line 31 has a first included angle with the body segment 302, the second electroplated line 32 has a second included angle with the body segment 302, and the first included angle is different from the second included angle. Since the electroplated line 30 is used for electroplated filling from the end portion of the electroplated line 30 away from the conductive structure 20, in order to facilitate the electroplating solution to fill more smoothly in the packaging structure 1, the first included angle and the second included angle can both be obtuse angles. For example, the first included angle is 135°, and the second included angle is greater than or less than 135°; or, the second included angle is 135°, and the first included angle is greater than or less than 135°.

[0089] In another example, to further increase the distance d between the extension 303 of the first plated wire 31 away from the first end 311 of the conductive structure 20 and the extension 303 of the second plated wire 32 away from the second end 321 of the conductive structure 20, the extension 303 of the first plated wire 31 and the extension 303 of the second plated wire 32 are respectively located on opposite sides of the body segment 302. For example, as shown in FIG. 9, the extension 303 of the first plated wire 31 is located on a first side of the body segment 302 and the extension 303 of the second plated wire 32 is located on a second side of the body segment 302, the first side and the second side being different sides. In this way, the distance between the first end 311 of the extension 303 of the first plated wire 31 and the second end 321 of the extension 303 of the second plated wire 32 can be further increased, thereby better avoiding short circuit. In this case, the first angle and the second angle can both be obtuse angles and the same, for example, both 135°.

[0090] In another possible embodiment, as shown in FIG. 12, the extension 303 includes a first sub-extension 3031 close to the body segment 302 and a second sub-extension 3032 away from the body segment 302, the second sub-extension 3032 being different from the first sub-extension 3031 in the direction of extension, and the angle between the second sub-extension 3032 and the first sub-extension 3031 is an obtuse angle, and the angle between the first sub-extension 3031 and the body segment 302 is also an obtuse angle. In another example, as shown in FIG. 12, the extension 303 of the first plated wire 31 and the extension 303 of the second plated wire 32 can be located on different sides of the body segment 302, thereby further increasing the distance between the first end 311 of the extension 303 of the first plated wire 31 and the second end 321 of the extension 303 of the second plated wire 32. In one example, the extension 303 of the first plated wire 31 and the extension 303 of the second plated wire 32 can be located on the same side of the body segment 302.

[0091] As shown in FIG. 11, the connecting segment 301 of the first electroplating line 31 is located at a first side of the body segment 302, and the connecting segment 301 of the second electroplating line 32 is located at a second side of the body segment 302, the first side and the second side are different sides. That is, the first electroplating line 31 and the second electroplating line 32 are located at opposite sides of the body segment 302 respectively. Specifically, the included angle between the connecting segment 301 of the first electroplating line 31 and the body segment 302 is an obtuse angle, and the included angle between the connecting segment 301 of the second electroplating line 32 and the body segment 302 is also an obtuse angle, and the first electroplating line 31 and the second electroplating line 32 extend towards each other at the connecting segment 301 until the projections on the carrier structure 10 coincide. Thus, the overall length of the first electroplating line 31 and the second electroplating line 32 is relatively close, and the electroplating filling time of each electroplating line 30 is closer during the electroplating filling process, thereby improving the electroplating efficiency.

[0092] Since the number of the conductive structures 20 of the packaging structure 1 is usually greater than 2, each conductive structure 20 corresponds to at least one electroplating line 30, the above scheme mainly describes the scheme for reducing the far-end crosstalk between two conductive structures 20, and the structure for reducing the far-end crosstalk between three conductive structures 20 will be described below.

[0093] For example, as shown in FIG. 13, the at least two conductive structures 20 further include a third conductive structure 203, and the at least two electroplating lines 30 further include a third electroplating line 33, the third electroplating line 33 is connected to the third conductive structure 203. The second conductive structure 202 is located between the first conductive structure 201 and the third conductive structure 203. Therefore, the distance between the first conductive structure 201 and the third conductive structure 203 is large, and the far-end crosstalk therebetween is small. The first conductive structure 201 and the second conductive structure 202 can be adjacent conductive structures 20, and the second conductive structure 202 and the third conductive structure 203 can be adjacent conductive structures 20, therefore, the far-end crosstalk between the first conductive structure 201 and the second conductive structure 202, and the far-end crosstalk between the second conductive structure 202 and the third conductive structure 203 are relatively large.

[0094] In a possible implementation, as shown in FIG. 13, the first electroplating line 31 and the third electroplating line 33 are arranged in the same layer and are spaced apart. Since the first electroplating line 31 and the second electroplating line 32 are arranged in a stacked manner, the third electroplating line 33 and the second electroplating line 32 are also arranged in a stacked manner. Moreover, the projection of the body segment 302 of the first electroplating line 31 and the body segment 302 of the third electroplating line 33 on the carrier structure 10 shown in FIG. 8 are both located within the projection range of the body segment 302 of the second electroplating line 32 on the carrier structure 10 shown in FIG. 8.

[0095] That is, the projection of the body segment 302 of the first plated wire 31 on the carrier structure 10 shown in Fig. 8 is located within the projection range of the body segment 302 of the second plated wire 32 on the carrier structure 10 shown in Fig. 8, and a mutual-capacitance structure can be formed between the first plated wire 31 and the second plated wire 32, thereby improving the capacitive coupling coefficient between the first conductive structure 201 and the second conductive structure 202, and reducing the far-end crosstalk between the first conductive structure 201 and the second conductive structure 202.

[0096] Furthermore, when the projection of the body segment 302 of the third plated wire 33 on the carrier structure 10 shown in Fig. 8 is located within the projection range of the body segment 302 of the second plated wire 32 on the carrier structure 10 shown in Fig. 8, a mutual-capacitance structure can be formed between the third plated wire 33 and the second plated wire 32, thereby improving the capacitive coupling coefficient between the third conductive structure 203 and the second conductive structure 202, and reducing the far-end crosstalk between the third conductive structure 203 and the second conductive structure 202.

[0097] Further, to avoid short circuit, as shown in Fig. 13, the projection of the first end portion 311 of the first plated wire 31 away from the conductive structure 20, the second end portion 321 of the second plated wire 32 away from the conductive structure 20, and the third end portion 331 of the third plated wire 33 away from the conductive structure 20 on the carrier structure 10 do not overlap. For example, the extension segment 303 of the first plated wire 31 and the extension segment 303 of the third plated wire 33 are respectively located on opposite sides of the body segment 302, and the extension segment 303 of the second plated wire 32 and the body segment 302 have the same extension direction.

[0098] Taking the package structure 1 shown in Fig. 13 as an example of LPDDR, the far-end crosstalk performance of the LPDDR is analyzed. The thickness of the carrier structure 10 is 0.3 mm, and the rate of the LPDDR is 3.2 Gbps. As shown in Fig. 13, the first conductive structure 201 and the corresponding microstrip line 60a and the second conductive structure 202 and the corresponding microstrip line 60b represent an attack network, and the dashed arrow represents the signal direction of the attack network. The third conductive structure 203 and the corresponding microstrip line 60c represent a victim network, and the solid arrow represents the signal direction of the victim network. The performance analysis results are shown in Figs. 14-17.

[0099] Fig. 14 is a crosstalk curve in the frequency domain of the present embodiment and the related art. As shown in Fig. 14, the horizontal coordinate represents the frequency of the signal, and the vertical coordinate represents the crosstalk. As can be seen from Fig. 14, the crosstalk of the present embodiment at 4.8 GHz is -40.6607 dB, and the crosstalk of the related art at 4.8 GHz is -24.7916 dB. Therefore, compared with the related art, the present embodiment has a crosstalk gain of -24.7916-(-40.6607) = 15.8691 dB.

[0100] FIG. 15 is a crosstalk curve in time domain of the present embodiment and the related art. As shown in FIG. 15, the horizontal axis represents time, and the vertical axis represents voltage. As can be seen from FIG. 15, the crosstalk of the present embodiment is 30 mV, and the crosstalk of the related art is 48 mV. Therefore, compared with the related art, the crosstalk of the present embodiment is smaller, that is, the present embodiment can reduce the crosstalk in time domain, and the specific crosstalk gain is 37.5%.

[0101] FIG. 16 is an eye diagram of the related art, and FIG. 17 is an eye diagram of the present embodiment. As can be seen from FIG. 16, the eye width of the related art is 112 ps, and the eye height is 227 mV. As can be seen from FIG. 17, the eye width of the present embodiment is 139 ps, and the eye height is 239 mV. It can be seen that, compared with the related art, the eye width of the present embodiment is increased from 112 ps to 139 ps, and the gain is 24%. The eye height of the present embodiment is increased from 227 mV to 239 mV, and the gain is 5.2%.

[0102] In another possible implementation, as shown in FIG. 18, the first electroplated line 31, the second electroplated line 32 and the third electroplated line 33 are respectively located in different layers, and the projections of the first electroplated line 31, the second electroplated line 32 and the third electroplated line 33 on the bearing structure 10 shown in FIG. 8 all overlap. Thus, a mutual capacitance structure can be formed between the first electroplated line 31 and the second electroplated line 32, so as to reduce the far-end crosstalk between the first conductive structure 201 and the second conductive structure 202. A mutual capacitance structure can also be formed between the second electroplated line 32 and the third electroplated line 33, so as to also reduce the far-end crosstalk between the second conductive structure 202 and the third conductive structure 203.

[0103] Moreover, the projections of the end portions of the first electroplated line 31, the second electroplated line 32 and the third electroplated line 33 away from the conductive structure 20 on the bearing structure 10 all do not overlap. That is, the projection of the first end portion 311 of the first electroplated line 31 away from the conductive structure 20, the projection of the second end portion 321 of the second electroplated line 32 away from the conductive structure 20, and the projection of the third end portion 331 of the third electroplated line 33 away from the conductive structure 20 all do not overlap on the bearing structure 10, thereby increasing the distance between the first end portion 311 of the first electroplated line 31 and the second end portion 321 of the second electroplated line 32, and increasing the distance between the second end portion 321 of the second electroplated line 32 and the third end portion 331 of the third electroplated line 33, so as to avoid short circuit.

[0104] In still another possible implementation, as shown in Fig. 19, the at least two plated lines 30 further include a fourth plated line 34, the third plated line 33 is connected to the second conductive structure 202, and the fourth plated line 34 is connected to the third conductive structure 203. As shown in Fig. 20, the fourth plated line 34 is stacked along the Z direction with the third plated line 33, and the fourth plated line 34 is in the same layer with the second plated line 32 and is spaced apart from the second plated line 32, and the third plated line 33 is in the same layer with the first plated line 31 and is spaced apart from the first plated line 31. In this way, a mutual-capacitance structure can be formed between the first plated line 31 and the second plated line 32, thereby reducing the far-end crosstalk between the first conductive structure 201 and the second conductive structure 202, respectively. Moreover, the third plated line 33 and the fourth plated line 34 can form a mutual-capacitance structure, thereby reducing the far-end crosstalk between the second conductive structure 202 and the third conductive structure 203.

[0105] In addition, the projection shape of the body segment 302 of each plated line 30 on the carrier structure 10 shown in Fig. 8 can be other regular or irregular shapes besides the rectangular shape shown in the above embodiments. For example, as shown in Fig. 21, the projection shape of the body segment 302 of the plated line 30 is a combined shape of a rectangle and an ellipse. As shown in Fig. 22, the projection shape of the body segment 302 of the plated line 30 is a combined shape formed by connecting two half-circle rings. As shown in Fig. 23, the projection shape of the body segment 302 of the plated line 30 is a comb shape.

[0106] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the specific embodiments described above, which are merely illustrative rather than restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims, which are all within the scope of the present application.

Claims

1. A package structure, characterized by, The application relates to a bearing structure, which comprises: a bearing structure; at least two conductive structures, parts of the conductive structures being located inside the bearing structure, and the rest of the conductive structures being located outside the bearing structure; at least two electroplated lines, any of the electroplated lines being arranged on the surface or inside of the bearing structure, a first electroplated line of the at least two electroplated lines being connected to a first conductive structure of the at least two conductive structures, a second electroplated line of the at least two electroplated lines being connected to a second conductive structure of the at least two conductive structures, the first electroplated line and the second electroplated line being stacked along the thickness direction of the bearing structure, and the projection of the first electroplated line on the bearing structure and the projection of the second electroplated line on the bearing structure being overlapped.

2. The package structure of claim 1, wherein, The projection of the end of the first electroplated line away from the conductive structure on the bearing structure is not overlapped with the projection of the end of the second electroplated line away from the conductive structure on the bearing structure.

3. The package structure of claim 1 or 2, wherein, The electroplated line comprises a connecting section, a body section and an extension section connected in sequence, the extension section being located at one end of the connecting section away from the conductive structure, and the length of the body section being greater than the length of the connecting section and the length of the extension section. The projection of the body section of the first electroplated line on the bearing structure is coincided with the projection of the body section of the second electroplated line on the bearing structure, and the projection of the extension section of the first electroplated line on the bearing structure is not overlapped with the projection of the extension section of the second electroplated line on the bearing structure.

4. The package structure of claim 3, wherein, The extension section of the first electroplated line is located at a first side of the body section, and the extension section of the second electroplated line is located at a second side of the body section, the first side and the second side being different sides.

5. The package structure of claim 3 or 4, wherein, The extension section extends along a straight line, and the extension direction of the extension section of the first electroplated line is different from the extension direction of the extension section of the second electroplated line.

6. The package structure of claim 4, wherein, The extension section comprises a first sub-extension section close to the body section and a second sub-extension section away from the body section, and the included angle between the second sub-extension section and the first sub-extension section is an obtuse angle.

7. The package structure of any of claims 3-6, wherein, The connecting section of the first electroplated line is located at a first side of the body section, and the connecting section of the second electroplated line is located at a second side of the body section, the first side and the second side being different sides.

8. The package structure of any one of claims 3-7, wherein, The at least two conductive structures further comprise a third conductive structure, the second conductive structure being located between the first conductive structure and the third conductive structure, and the at least two electroplated lines further comprise a third electroplated line connected to the third conductive structure. The first electroplated line and the third electroplated line are arranged in the same layer and are spaced apart, and the projection of the body section of the first electroplated line on the bearing structure and the projection of the body section of the third electroplated line on the bearing structure are both located in the projection range of the body section of the second electroplated line on the bearing structure.

9. The package structure of any one of claims 1-7, wherein, The at least two conductive structures further comprise a third conductive structure, the second conductive structure being located between the first conductive structure and the third conductive structure, and the at least two electroplated lines further comprise a third electroplated line connected to the third conductive structure. The first, second and third electroplated lines are located in different layers respectively, and projections of the first, second and third electroplated lines on the carrier structure all have overlaps.

10. The package structure of claim 9, wherein, Projections of the first, second and third electroplated lines on the carrier structure all have no overlaps.

11. The package structure of any one of claims 1-7, wherein, The at least two conductive structures further include a third conductive structure, the second conductive structure is located between the first and third conductive structures, the at least two electroplated lines further include a third and fourth electroplated lines, the third electroplated line is connected to the second conductive structure, and the fourth electroplated line is connected to the third conductive structure. The fourth electroplated line is stacked with the third electroplated line along the thickness direction, and the fourth electroplated line is in the same layer with the second electroplated line and is spaced apart, and the third electroplated line is in the same layer with the first electroplated line and is spaced apart.

12. The package structure of any one of claims 1-11, wherein, The carrier structure includes at least two layers of substrates stacked along the thickness direction and a dielectric layer between adjacent two layers of substrates, the first electroplated line is arranged on the surface of the substrate or inside the dielectric layer, and the second electroplated line is arranged on the surface of the substrate or inside the dielectric layer.

13. The package structure of any one of claims 1-12, wherein, The conductive structure includes a conductive hole and a solder, the conductive hole is located inside the carrier structure, the solder is located outside the carrier structure, and the solder of the first conductive structure and the solder of the second conductive structure are adjacent or spaced apart.

14. An electronic device, comprising: The package structure includes a circuit board and the package structure according to any one of claims 1-13, and the package structure is arranged on the circuit board.

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