Optoelectronic integrated semiconductor package structure and manufacturing method therefor

Abstract

Disclosed in the present invention are an optoelectronic integrated semiconductor package structure and a manufacturing method therefor. The optoelectronic integrated semiconductor package structure comprises a first redistribution layer, metal pillars are located on the first redistribution layer, and one ends of the metal pillars are electrically connected to the first redistribution layer. An optical waveguide layer is located on the first redistribution layer and arranged around the metal pillars. An intermediate layer is located on the first redistribution layer and arranged in a middle region defined by the metal pillars. A package layer is located on the first redistribution layer and applied to the space between the metal pillars, the optical waveguide layer, and the intermediate layer. A second redistribution layer is located on the package layer, and the second redistribution layer is electrically connected to the other ends of the metal pillars and has through grooves exposing waveguide facets. An electronic chip and an optical chip are both bonded onto the second redistribution layer, and a photosensitive region of the optical chip is arranged corresponding to the through grooves. The present invention can achieve stacked interconnection and staggered distribution of electrical signal wires and optical signal wires, reduce the package area, increase the wire density, and reduce the signal transmission distance.

Description

Optoelectronic integrated semiconductor package structure and preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to an optoelectronic integrated semiconductor package structure and a preparation method thereof. BACKGROUND

[0002] With the continuous development of big data, artificial intelligence, remote medical treatment, Internet of Things, e-commerce and 5G communication, global data traffic is growing explosively, and circuits with lower cost, higher reliability, faster speed and higher density are the goal of integrated circuit packaging.

[0003] In order to meet the demand of Internet traffic, the bandwidth of data center nodes needs to reach 10 Tb / s, and in order to slow down the trend of increasing energy consumption of data centers, it is necessary to reduce the power consumption of systems and devices. Silicon optical chips organically combine mature microelectronics and optoelectronic technology, which can not only reduce chip size, cost and power consumption, but also improve reliability, and is expected to become a "beyond Moore" high-speed information engine. Therefore, it is necessary to introduce silicon optical technology, since the purpose of introducing silicon optical technology is to increase input / output (I / O) bandwidth and reduce energy consumption to the greatest extent, how to package the optical integrated circuit (PIC) and the electrical integrated circuit (EIC) is crucial, which will directly affect the I / O bandwidth and energy consumption.

[0004] Most of the existing optoelectronic integrated semiconductor package structures directly bond the optical integrated chip and the electrical integrated chip on the substrate, and are electrically connected with the substrate by wire-bonds or Flip-Chip. Since the silicon optical process node is relatively backward compared with the electrical chip process, the most advanced process of single-chip integration is 45nm and 32nm process, which is far from the 10nm and below process of electrical chips. This kind of packaging cannot integrate electrical chips and optical chips together. Therefore, a higher density integrated packaging method must be developed. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the present application aims to provide an optoelectronic integrated semiconductor package structure and a preparation method thereof, which can solve the problem of high-density integrated packaging of optical chips and electrical chips in the prior art.

[0006] In order to achieve the above-mentioned purpose and other related purposes, the present application provides an optoelectronic integrated semiconductor package structure, which comprises at least one package body, and the package body comprises:

[0007] a first re-distribution layer;

[0008] a metal column on the first re-wiring layer, and one end of the metal column is electrically connected with the first re-wiring layer;

[0009] an optical waveguide layer on the first re-wiring layer, and the optical waveguide layer is arranged at the periphery of the metal column, and the optical waveguide layer comprises a waveguide light port and a waveguide transmission port;

[0010] an intermediate layer on the first re-wiring layer, and the intermediate layer is arranged in a middle region enclosed by the metal column;

[0011] an encapsulation layer on the first re-wiring layer, and the encapsulation layer fills a region between the metal column, the optical waveguide layer and the intermediate layer, a surface of the encapsulation layer exposes the other end of the metal column and the waveguide light port, and a side surface of the encapsulation layer exposes the waveguide transmission port;

[0012] a second re-wiring layer on the encapsulation layer, the second re-wiring layer is electrically connected with the other end of the metal column, and the second re-wiring layer has a through slot exposing the waveguide light port;

[0013] an electrical chip and an optical chip, the electrical chip and the optical chip are both bonded on the second re-wiring layer, and both are electrically connected with the second re-wiring layer, and a photosensitive region of the optical chip is arranged corresponding to the through slot.

[0014] Optionally, the encapsulation further comprises:

[0015] an optical lens arranged on the encapsulation layer and in the through slot.

[0016] Optionally, the encapsulation further comprises:

[0017] a metal bump arranged on a side of the first re-wiring layer away from the intermediate layer, and the metal bump is electrically connected with the first re-wiring layer.

[0018] Optionally, the optical chip and the electrical chip are connected to the first re-wiring layer through the second re-wiring layer and the intermediate layer, and interconnection is formed through the first re-wiring layer.

[0019] Optionally, the optoelectronic integrated semiconductor encapsulation structure comprises:

[0020] a plurality of encapsulations, adjacent encapsulations are interconnected through connectors, and the connectors correspond to the waveguide transmission ports of the adjacent encapsulations.

[0021] Optionally, a light shielding layer is further arranged on a side wall of the optical lens.

[0022] According to an aspect of the present application, a method for preparing an optoelectronic integrated semiconductor encapsulation structure is also provided, and the method comprises:

[0023] providing a first support substrate, and forming a second re-wiring layer on the first support substrate;

[0024] Forming a metal column and an optical waveguide layer on the periphery of the second re-wiring layer, one end of the metal column is electrically connected with the first re-wiring layer, and the optical waveguide layer comprises a waveguide light port and a waveguide transmission port;

[0025] Forming an intermediate layer on the middle of the second re-wiring layer;

[0026] Forming an encapsulation layer on the second re-wiring layer, the encapsulation layer covers the metal column, the optical waveguide layer and the intermediate layer, and the surface of the encapsulation layer exposes the other end of the metal column and the waveguide light port;

[0027] Forming a first re-wiring layer on the encapsulation layer, the first re-wiring layer is electrically connected with the other end of the metal column;

[0028] Forming a metal bump on the first re-wiring layer, the metal bump is electrically connected with the first re-wiring layer;

[0029] Providing a second support substrate, and bonding the second support substrate on the surface of the first re-wiring layer;

[0030] Removing the first support substrate to expose the second re-wiring layer;

[0031] Forming a through slot on the second re-wiring layer, the through slot corresponds to the optical waveguide layer, and the second support substrate is removed;

[0032] Bonding an electrical chip and an optical chip on the second re-wiring layer, the electrical chip and the optical chip are both electrically connected with the second re-wiring layer to form a package, the side surface of the package exposes the waveguide transmission port, and the photosensitive area of the optical chip is arranged corresponding to the through slot.

[0033] Optionally, after the step of forming the through slot on the second re-wiring layer, the method further comprises:

[0034] Arranging an optical lens in the through slot.

[0035] Optionally, the optoelectronic integrated semiconductor package structure comprises a plurality of packages, and the preparation method further comprises:

[0036] Interconnecting adjacent packages through a connector, and the connector is arranged corresponding to the waveguide transmission port of the adjacent packages.

[0037] Optionally, the method for forming the optical waveguide layer comprises a 3D printing method, and the formed optical waveguide layer comprises an organic polymer optical waveguide wire, a silicon-based optical waveguide wire, a lithium niobate optical waveguide wire or a lithium borate optical waveguide wire.

[0038] Compared with the prior art, the optoelectronic integrated semiconductor package structure and the preparation method thereof have at least the following advantages Beneficial effects:

[0039] The photoelectric integrated semiconductor packaging structure of the present application comprises a first re-wiring layer, a metal column, an optical waveguide layer, an intermediate layer, a packaging layer, a second re-wiring layer, an electrical chip and an optical chip. The metal column is located on the first re-wiring layer, and one end of the metal column is electrically connected with the first re-wiring layer. The optical waveguide layer is located on the first re-wiring layer and is arranged at the periphery of the metal column, and the optical waveguide layer comprises a waveguide light port and a waveguide transmission port. The intermediate layer is located on the first re-wiring layer and is arranged in the middle region enclosed by the metal column. The packaging layer is located on the first re-wiring layer and fills the region between the metal column, the optical waveguide layer and the intermediate layer, and the surface of the packaging layer exposes the other end of the metal column and the waveguide light port, and the side surface of the packaging layer exposes the waveguide transmission port. The second re-wiring layer is located on the packaging layer, the second re-wiring layer is electrically connected with the other end of the metal column, and the second re-wiring layer has a through slot exposing the waveguide light port. The electrical chip and the optical chip are both bonded on the second re-wiring layer and are electrically connected with the second re-wiring layer, and the photosensitive region of the optical chip is arranged correspondingly to the through slot. In the present application, the intermediate layer, the metal column and the optical waveguide layer are arranged in the same layer, and the re-wiring layers are arranged on the upper and lower sides of the layer, so that the stacking interconnection and staggered wiring of the electrical signal wiring and the optical signal wiring are realized, thereby reducing the packaging area, increasing the wiring density and reducing the signal transmission distance. Moreover, the optical waveguide in the present application is led out from the side surface of the packaging body, which can increase the modular combination capability, realize system packaging and meet the demand of high-density integrated packaging.

[0040] The preparation method of the photoelectric integrated semiconductor packaging structure of the present application prepares the above-mentioned photoelectric integrated semiconductor packaging structure, which also has the above-mentioned technical effects. BRIEF DESCRIPTION OF DRAWINGS

[0041] Fig. 1 is a structural schematic diagram of the photoelectric integrated semiconductor packaging structure in the embodiment of the present application;

[0042] Fig. 2 is a structural schematic diagram of providing a first support substrate and forming a second re-wiring layer on the first support substrate;

[0043] Fig. 3 is a structural schematic diagram of forming a metal column on the surface of the second re-wiring layer in Fig. 2;

[0044] Fig. 4 is a structural schematic diagram of forming an optical waveguide layer on the surface of the second re-wiring layer in Fig. 3;

[0045] Fig. 5 is a structural schematic diagram of forming an intermediate layer on the surface of the second re-wiring layer in Fig. 4 and forming a first re-wiring layer on the surface of the intermediate layer;

[0046] Fig. 6 is a structural schematic diagram of forming a bottom filling layer on the surface of the first re-wiring layer in Fig. 5 and forming a second support substrate on the bottom filling layer;

[0047] Figure 7 is a schematic diagram of the structure after removing the first support substrate in Figure 6 and forming a through slot on the second support substrate exposed after removing the first support substrate;

[0048] Figure 8 is a schematic diagram of the structure after attaching an optical lens to the through slot in Figure 7;

[0049] Figure 9 is a schematic diagram of the structure cut along the center of the M-shaped optical waveguide layer;

[0050] Figure 10 is a schematic diagram of the structure cut along the center of the M-shaped optical waveguide layer and forming a transverse waveguide transmission port;

[0051] Figure 11 is a schematic diagram of the structure of a single package formed after bonding an optical chip and an electrical chip to the second re-wiring layer in Figure 10;

[0052] Figure 12 is a schematic diagram of the system package structure formed after connecting multiple packages in Figure 11 through a connector to form a modular combination.

[0053] List of reference numerals: 100 first support substrate 101 first separation layer 110 second support substrate 111 second separation layer 200 second re-wiring layer 201 through slot 202 optical lens 203 light shielding layer 300 metal column 400 optical waveguide layer 401 waveguide light port 402 waveguide transmission port 500 packaging layer 600 intermediate layer 700 first re-wiring layer 800 metal bump 900 bottom filling layer 1000 optical chip 1001 photosensitive region 1010 electrical chip 1100 connector A package DETAILED DESCRIPTION

[0054] Following detailed description of the application by specific embodiments, those skilled in the art can easily understand other advantages and effects of the application from the disclosure of the specification. The application can also be implemented or applied by other different embodiments, and various modifications or changes can be made to the details in the specification based on different views and applications without departing from the spirit of the application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0055] It should be understood that the diagrams provided in the embodiments of the application only illustrate the basic concepts of the application in a schematic manner, and although only the components related to the application are shown in the diagrams, the diagrams are not drawn according to the number, shape and size of the components in actual implementation, and the shape, number and proportion of each component in actual implementation can be changed at will, and the layout form of the components can also be more complex. The structure, proportion, size, etc. shown in the drawings of the specification are only used to cooperate with the content disclosed in the specification for those skilled in the art to understand and read, and are not used to limit the defined conditions that can be implemented by the application, so they do not have technical substantive significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects that can be produced by the application and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the application.

[0056] As shown in FIG. 1, the embodiment provides an optoelectronic integrated semiconductor packaging structure and a preparation method. By arranging the interposer, metal column and optical waveguide layer in the same layer, and arranging the redistribution layer on both sides of the layer to realize the stacked interconnection and staggered wiring of electrical signal wiring and optical signal wiring, the packaging area is reduced, the wiring density is increased, and the signal transmission distance is reduced. Moreover, the optical waveguide in the embodiment is guided out from the side of the package, which can increase the modular combination capability, realize system packaging, and meet the needs of high-density integrated packaging.

[0057] The optoelectronic integrated semiconductor packaging structure and the preparation method thereof will be described in detail below with reference to FIGS. 1-12.

[0058] Embodiment 1

[0059] The embodiment provides an optoelectronic integrated semiconductor packaging structure. Referring to FIG. 1, the optoelectronic integrated semiconductor packaging structure includes at least one package A, and the package A includes a first redistribution layer 700, a metal column 300, an interposer 600, an optical waveguide layer 400, a packaging layer 500, a second redistribution layer 200, an electrical chip 1010 and an optical chip 1000.

[0060] The first rewiring layer 700 can be a damascene rewiring layer, an organic rewiring layer, or a stacked combination of the two, i.e., the dielectric layer can be made of silicon oxide, silicon nitride, or polyimide, etc., and the metal wiring can be made of copper, aluminum, etc. In this embodiment, the first rewiring layer 700 is an organic rewiring layer, and the dielectric layer therein can be made of polyimide, etc., to avoid the influence of high temperature on the previously formed optical waveguide layer during the preparation of the first rewiring layer 700. Of course, the material, number of layers, and preparation method of the first rewiring layer 700 can also be selected according to actual needs, which are not limited in this embodiment. Optionally, metal bumps 800 are also provided on the first rewiring layer 700 in a spaced manner, and the metal bumps 800 are electrically connected to the first rewiring layer 700, for subsequent bonding of the entire package A to other structures.

[0061] The metal column 300 is formed on the first rewiring layer 700, and one end of the metal column 300 is electrically connected to the first rewiring layer 700. The method for forming the metal column 300 can be bonding, electroplating, etc. The material of the metal column 300 can include copper, aluminum, etc., and the material, distribution, and preparation method of the metal column 300 are not limited.

[0062] The optical waveguide layer 400 is formed on the first rewiring layer 700 and is arranged at the periphery of the metal column 300. The optical waveguide layer 400 includes a waveguide light port 401 and a waveguide transmission port 402. The optical waveguide layer 400 is a 3D optical waveguide formed by optical wire bonding. By analogy with the idea of metal wire bonding, optical wire bonding is used to realize the interconnection between different photonic chips, chips, and optical fibers, and the "wire" that plays a connecting role is no longer metal, but an optical waveguide. By controlling the focal point of a high-energy pulse (High-NA fs laser beam), multi-photon polymerization occurs at a specific position of the photoresist, forming a 3D (three-dimensional) optical waveguide. The method for forming the optical waveguide layer 400 can be 3D printing, but is not limited thereto. The optical waveguide layer 400 can include an organic polymer optical waveguide wiring, a silicon-based optical waveguide wiring, a lithium niobate optical waveguide wiring, or a lithium borate optical waveguide wiring, such as a polymethyl methacrylate, polystyrene, polycarbonate epoxy resin, fluorine-containing polyimide, etc. Other materials or preparation methods can also be used, which are not limited in this embodiment.

[0063] The interposer 600 is formed on the first re-distribution layer 700 and is arranged in the middle region of the first re-distribution layer 700 enclosed by the metal posts 300. The interposer 600 includes an insulating layer and a via formed in the insulating layer, and the via is filled with a conductive post. The conductive post in the interposer 600 is electrically connected to the first re-distribution layer 700. The interposer 600 can be a pre-made interposer 600 arranged on the first re-distribution layer 700, or can be directly formed on the first re-distribution layer 700.

[0064] The encapsulation layer 500 is arranged on the first re-distribution layer 700 and fills the region between the metal posts 300, the optical waveguide layer 400 and the interposer 600. The surface of the encapsulation layer 500 exposes the other end of the metal posts 300 and the waveguide light port 401, and the side surface of the encapsulation layer 500 exposes the waveguide transmission port 402. The method of forming the encapsulation layer 500 can include molding, vacuum lamination molding and spin coating molding, etc. The material of the encapsulation layer 500 can be a commonly used epoxy resin, or can be other encapsulation materials. The encapsulation layer 500 can protect the metal posts 300, the interposer 600 and the optical waveguide layer 400, and provide fixation and support. After the encapsulation layer 500 is formed, if the surface of the encapsulation layer 500 is not flat or covers the surface of the metal posts 300, the interposer 600 and the optical waveguide layer 400, a grinding process can be used to thin or planarize the encapsulation layer 500, and expose the conductive connection points on the metal posts 300, the interposer 600 and the optical waveguide layer 400. Alternatively, a chemical mechanical grinding method (CMP) can be used to grind and thin the encapsulation layer 500.

[0065] The second re-wiring layer 200 is formed on the packaging layer 500. The second re-wiring layer 200 is electrically connected with the other end of the metal column 300, and the through slot 201 exposing the waveguide light port 401 is formed on the second re-wiring layer 200. The second re-wiring layer 200 can be a Damascus re-wiring layer, an organic re-wiring layer, or a stacked combination of the two, that is, the material of the dielectric layer can include silicon oxide, silicon nitride, or polyimide, etc., and the material of the metal wiring can include copper, aluminum, etc. The material, number of layers, layout, preparation method, etc. of the second re-wiring layer 200 can also be selected as needed. After the second re-wiring layer 200 is formed, the through slot 201 can be formed on the second re-wiring layer 200 corresponding to the waveguide light port 401 of the optical waveguide layer 400. The forming method of the through slot 201 can include mechanical drilling, laser drilling, chemical etching, etc. Optionally, in order to better transmit the optical signal, an optical lens 202 is also arranged in the through slot 201. The optical lens 202 can collect the light transmitted by the waveguide light port 401 of the optical waveguide layer 400, avoid the divergence of the light, and cannot be effectively transmitted to the light sensing area 1001 of the optical chip 1000. Further, the both sides of the optical lens 202 are also provided with a light shielding layer 203, which can shield or reflect the light emitted to the lens sidewall to avoid light loss. The light shielding layer 203 can be a reflective material or other non-transparent material, and the material of the light shielding layer 203 is not limited in the embodiment.

[0066] The electrical chip 1010 and the optical chip 1000 are bonded on the second re-wiring layer 200 and are electrically connected with the second re-wiring layer 200. The optical chip 1000 has a light sensing area 1001, and the light sensing area 1001 of the optical chip 1000 is arranged corresponding to the through slot 201 to receive the optical signal transmitted by the optical waveguide layer 400. Optionally, the electrical chip 1010 and the optical chip 1000 are electrically connected with the second re-wiring layer 200 in a flip-chip manner. In the embodiment, the optical chip 1000 is connected with the metal column 300 through the second re-wiring layer 200, and is connected to the first re-wiring layer 700 through the metal column 300. At the same time, the optical chip 1000 is also electrically connected with the first re-wiring layer 700 through the second re-wiring layer 200 and the interlayer 600. The electrical chip 1010 is connected with the optical chip 1000 through the second re-wiring layer 200 and the interlayer 600, and is also electrically connected with the first re-wiring layer 700. The electrical chip 1010 and the optical chip 1000 can form interconnection through the first re-wiring layer 700.

[0067] Referring to FIGS. 1 and 12, when the number of the package A is plural, the plural package A can be connected by the connector 1100. Specifically, each package A can be bonded to the same substrate (not shown in the figure), and the plural package A is connected by the connector 1100 between the adjacent package A, and the connector 1100 can also be bonded on the substrate to fix it. The connector 1100 is arranged corresponding to the waveguide transmission port 402 in the adjacent package A, to realize the light transmission of the adjacent package A through the waveguide transmission port 402 of the optical waveguide layer 400.

[0068] Embodiment 2

[0069] The embodiment also provides a preparation method of the optoelectronic integrated semiconductor package structure. Referring to FIGS. 2-12, the preparation method comprises:

[0070] Referring to FIG. 2, a step S1 is performed to provide a first support substrate 100, and a second re-wiring layer 200 is formed on the first support substrate 100.

[0071] Specifically, the first support substrate 100 can include, for example, a glass substrate, a metal substrate, a semiconductor substrate, etc., to provide support for the subsequent process through the first support substrate 100. In addition, in order to facilitate the subsequent removal of the first support substrate 100, a first separation layer 101 is also formed on the surface of the first support substrate 100 in the embodiment, and the first separation layer 101 includes but is not limited to a tape and a polymer layer, for example, the first separation layer 101 can be selected as a light-heat conversion layer, and the first separation layer 101 can be heated by, for example, a laser in the subsequent process, until it loses adhesion after failure, and then the first support substrate 100 is removed. Alternatively, the first support substrate 100 can include a wafer-level substrate with a size of 4 inches, 6 inches, 8 inches or 12 inches, etc., or other sizes of substrates.

[0072] The first re-wiring layer 700 can be a Damascus re-wiring layer, an organic re-wiring layer, or a stacked combination of the two, i.e., the material of the dielectric layer can include silicon oxide, silicon nitride, or polyimide, etc., and the material of the metal wiring can include copper, aluminum, etc.

[0073] Referring to FIGS. 3 and 4, a step S2 is performed to form a metal column 300 and an optical waveguide layer 400 on the periphery of the second re-wiring layer 200, one end of the metal column 300 is electrically connected with the first re-wiring layer 700, and the optical waveguide layer 400 includes a waveguide light port 401 and a waveguide transmission port 402.

[0074] Specifically, a plurality of spaced metal pillars 300 can be formed on the periphery of the second re-routed layer 200 by direct bonding or direct plating, each of the metal pillars 300 being electrically connected to the second re-routed layer 200. A waveguide layer 400 is formed on the periphery of the metal pillars 300 of the second re-routed layer 200. The waveguide layer 400 can be formed by 3D printing. In this embodiment, the waveguide layer 400 is formed in an M shape.

[0075] Referring to FIG. 5, step S3 is performed to form an intermediate layer 600 on the second re-routed layer 200.

[0076] Specifically, the intermediate layer 600 can be formed by direct bonding. The intermediate layer 600 includes an insulating layer and a conductive pillar (not shown) formed in the insulating layer (not shown), the conductive pillar penetrating the insulating layer, two end faces of the conductive pillar being exposed to two surfaces of the insulating layer, respectively.

[0077] Referring to FIG. 5, step S4 is performed to form an encapsulation layer 500 on the second re-routed layer 200, the encapsulation layer 500 encapsulating the metal pillars 300, the waveguide layer 400 and the intermediate layer 600, a surface of the encapsulation layer 500 exposing the other end of the metal pillars 300 and the waveguide light port 401.

[0078] Specifically, the encapsulation layer 500 is formed on the second re-routed layer 200, the encapsulation layer 500 filling between the metal pillars 300, the waveguide layer 400 and the intermediate layer 600 and encapsulating the metal pillars 300, the waveguide layer 400 and the intermediate layer 600. A surface of the encapsulation layer 500 exposes the other end of the metal pillars 300 and the waveguide light port 401 of the waveguide layer 400.

[0079] Referring to FIG. 5, step S5 is performed to form a first re-routed layer 700 on the encapsulation layer 500, the first re-routed layer 700 being electrically connected to the other end of the metal pillars 300.

[0080] Specifically, the first re-routed layer 700 is formed on the encapsulation layer 500, the first re-routed layer 700 being electrically connected to the other end of the metal pillars 300. In this embodiment, the first re-routed layer 700 is an organic re-routed layer, and a dielectric layer in the first re-routed layer 700 can be made of polyimide or the like, so as to avoid the influence of high temperature on the waveguide layer during the preparation of the first re-routed layer 700.

[0081] Referring to FIG. 5, step S6 is performed to form a metal bump 800 on the first re-routed layer 700, the metal bump 800 being electrically connected to the first re-routed layer 700. The metal bump 800 can be formed by solder reflow.

[0082] Referring to FIG. 6, a second support substrate 110 is provided, and the second support substrate 110 is bonded to the surface of the first re-wiring layer 700.

[0083] Specifically, in order to remove the first support substrate 100, the second support substrate 110 can be bonded to the surface of the first re-wiring layer 700. Since the surface of the first re-wiring layer 700 has the metal bumps 800, a bottom filling layer 900 can be first formed between the metal bumps 800 and the surface of the metal bumps 800, so that the formed interface is a flat interface, and the second support substrate 110 is formed on the flat interface. Optionally, a second separation layer 111 is further formed between the surface of the second support substrate 110 in contact with the packaging structure, and the second separation layer 111 is a photo-thermal conversion layer, which can be irradiated by a light source to be failed later, and then the peeling of the second support substrate 110 is facilitated.

[0084] Referring to FIG. 7, the first support substrate 100 is removed, and the second re-wiring layer 200 is exposed.

[0085] After the second support substrate 110 is formed, the first support substrate 100 is irradiated by a laser, so that the first separation layer 101 is failed by the laser irradiation, and the first support substrate 100 is peeled off, and the second re-wiring layer 200 adhered to the first support substrate 100 is exposed.

[0086] Continuing to refer to FIG. 7, a step S9 is performed, and a through slot 201 is formed on the second re-wiring layer 200, and the through slot 201 corresponds to the waveguide light port 401 on the optical waveguide layer 400.

[0087] Specifically, the through slot 201 is formed on the second re-wiring layer 200, so that the through slot 201 corresponds to the position of the waveguide light port 401 of the optical waveguide layer 400. In this embodiment, the laser drilling method can be used to form the through slot 201 on the second re-wiring layer 200 corresponding to the position of the waveguide light port 401.

[0088] In this embodiment, referring to FIG. 8, after the through slot 201 is formed, a step of attaching an optical lens 202 in the through slot 201 is further included. An optical shielding layer 203 is arranged on the sidewall of each optical lens 202, which is used to block the light emitted from the sidewall of the optical lens, so as to avoid light loss. After the optical lens 202 is attached, a step of removing the second support substrate 110 is further included. Specifically, the second support substrate 110 is irradiated by a laser, so that the second separation layer 111 is failed and loses adhesion, and the second support substrate 110 is peeled off.

[0089] Before the bonding of the electrical chip 1010 and the optical chip 1000, a step of cutting the packaging structure is further included. Referring to FIGS. 9 and 10, the cutting is along the center of the M-shaped optical waveguide layer 400, so that the optical waveguide layer 400 includes the vertically upward waveguide light port 401 and the horizontally waveguide transmission port 402, and the side of the entire packaging body A is formed with the waveguide transmission port 402, which can realize the horizontal light transmission between adjacent packaging bodies A.

[0090] Referring to FIG. 11, a step S7 is performed to bond the electrical chip 1010 and the optical chip 1000 on the second re-wiring layer 200, and the electrical chip 1010 and the optical chip 1000 are electrically connected with the second re-wiring layer 200, and the photosensitive area 1001 of the optical chip 1000 is arranged corresponding to the through groove 201.

[0091] Specifically, the electrical chip 1010 and the optical chip 1000 are bonded on the second re-wiring layer 200. The optical chip 1000 has the photosensitive area 1001, and the photosensitive area 1001 of the optical chip 1000 is arranged corresponding to the through groove 201 to receive the optical signal transmitted by the optical waveguide layer 400. In the embodiment, the electrical chip 1010 and the optical chip 1000 are electrically connected with the second re-wiring layer 200 in a flip-chip manner.

[0092] When the optoelectronic integrated semiconductor packaging structure includes a plurality of packaging bodies A, the plurality of packaging bodies A can be modularly combined. Referring to FIG. 12, when the plurality of packaging bodies A are modularly combined, a substrate (not shown) can be provided, and the plurality of packaging bodies A are bonded on the substrate, and the substrate is electrically connected with the metal bumps 800 of the packaging bodies A. The waveguide transmission ports 402 in adjacent packaging bodies A are arranged corresponding to each other to realize the light transmission between the adjacent packaging bodies A through the waveguide transmission ports 402. In the embodiment, the waveguide transmission ports 402 of the adjacent packaging bodies A realize the light transmission through the connector 1100, and at this time, the connector 1100 can be bonded on the substrate, and the connector 1100 is arranged between the waveguide transmission ports 402 of the adjacent packaging bodies A. In this way, the plurality of packaging bodies A are interconnected to form a modular combination, and system packaging is realized to meet the demand of high-density integrated packaging.

[0093] In summary, the optoelectronic integrated semiconductor packaging structure can integrate a plurality of optical chips and electrical chips on the packaging body, and the electrical signal lines and the optical signal lines are laid and stacked and interconnected, the electrical signal and the optical signal are integrated in the same interlayer, and the packaging area is reduced, the wiring density is increased, and the signal transmission distance is reduced. The optical chip and the electrical chip are connected through the interlayer, and the waveguide transmission ports are arranged on the side of each packaging body, the waveguide transmission ports on the sides of the plurality of packaging bodies are connected corresponding to each other to realize the modular combination, a larger module is formed, and the high-density integrated packaging is facilitated.

[0094] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. An optoelectronic integrated semiconductor package structure, comprising: The package includes at least one package body, the package body including: a first re-distribution layer; a metal post on the first re-distribution layer, and one end of the metal post being electrically connected to the first re-distribution layer; an optical waveguide layer on the first re-distribution layer, and being disposed at the periphery of the metal post, the optical waveguide layer including a waveguide light port and a waveguide transmission port; an intermediate layer on the first re-distribution layer, and being disposed at an intermediate region enclosed by the metal post; a packaging layer on the first re-distribution layer, filling a region between the metal post, the optical waveguide layer and the intermediate layer, a surface of the packaging layer exposing the other end of the metal post and the waveguide light port, and a side surface of the packaging layer exposing the waveguide transmission port; a second re-distribution layer on the packaging layer, the second re-distribution layer being electrically connected to the other end of the metal post, and having a through slot exposing the waveguide light port; an electrical chip and an optical chip, the electrical chip and the optical chip being bonded on the second re-distribution layer, and being electrically connected to the second re-distribution layer, and a light sensing region of the optical chip being disposed corresponding to the through slot.

2. The optoelectronic integrated semiconductor package structure of claim 1, wherein, The package further includes: an optical lens disposed on the packaging layer and in the through slot.

3. The optoelectronic integrated semiconductor package structure of claim 1, wherein, The package further includes: a metal bump disposed on a side of the first re-distribution layer away from the intermediate layer, and being electrically connected to the first re-distribution layer.

4. The optoelectronic integrated semiconductor package structure of claim 1, wherein, The optical chip and the electrical chip are connected to the first re-distribution layer through the second re-distribution layer and the intermediate layer, and are interconnected through the first re-distribution layer.

5. The optoelectronic integrated semiconductor package structure of claim 1, wherein, The optoelectronic integrated semiconductor package structure includes: a plurality of package bodies, adjacent package bodies being interconnected through connectors corresponding to waveguide transmission ports of adjacent package bodies.

6. The optoelectronic integrated semiconductor package structure of claim 2, wherein, A light shielding layer is further disposed on a side wall of the optical lens.

7. A method of fabricating an optoelectronic integrated semiconductor package structure, comprising: The preparation method includes: providing a first support substrate, and forming a second re-distribution layer on the first support substrate; forming a metal post and an optical waveguide layer at the periphery of the second re-distribution layer, one end of the metal post being electrically connected to the first re-distribution layer, and the optical waveguide layer including a waveguide light port and a waveguide transmission port; forming an intermediate layer at the middle of the second re-distribution layer; forming a packaging layer on the second re-distribution layer, the packaging layer covering the metal post, the optical waveguide layer and the intermediate layer, a surface of the packaging layer exposing the other end of the metal post and the waveguide light port; forming a first re-distribution layer on the packaging layer, the first re-distribution layer being electrically connected to the other end of the metal post; forming a metal bump on the first re-distribution layer, the metal bump being electrically connected to the first re-distribution layer; providing a second support substrate, and bonding the second support substrate to the surface of the first re-distribution layer; removing the first support substrate to expose the second re-distribution layer; forming a through slot on the second re-distribution layer, the through slot corresponding to the optical waveguide layer, and removing the second support substrate; Bonding an electrical chip and an optical chip on the second rewiring layer, the electrical chip and the optical chip are electrically connected with the second rewiring layer to form a package, a side of the package exposes the waveguide transmission port, and a light sensing area of the optical chip is arranged correspondingly to the through groove.

8. The method of claim 7, wherein the method further comprises: After the step of forming the through groove on the second rewiring layer, the method further comprises: Arranging an optical lens in the through groove.

9. The method of claim 7, wherein the method further comprises: The optoelectronic integrated semiconductor package structure comprises a plurality of the packages, and the preparation method further comprises: Interconnecting adjacent packages through a connector, and the connector is arranged correspondingly to the waveguide transmission port of the adjacent packages.

10. The method of claim 7, wherein the method further comprises: The method for forming the optical waveguide layer comprises a 3D printing method, and the formed optical waveguide layer comprises an organic polymer optical waveguide wire, a silicon-based optical waveguide wire, a lithium niobate optical waveguide wire or a lithium borate optical waveguide wire.

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