Method for applying a reflective layer to a front side of a substrate wafer and for passivating exposed surfaces of the substrate wafer

Abstract

The invention relates to a method for applying a reflective layer (110) to a front side (12) of a substrate wafer (10) and for passivating exposed surfaces (44) of the substrate wafer (10). In the method, at least the following method steps are carried out: According to a), trenches (36) are introduced on the front side (12) of the substrate wafer (10) and an ALD coating (46) is applied at least to the side walls (40) thereof. Then, according to b), the trenches (36) introduced according to a) are temporarily filled with a filling layer (50, 52). According to c), a coating comprising a reflective layer (110) and an electrically conductive protective layer (62) is applied to the front side (12) of the substrate wafer (10) and, according to d), a protective wafer (66) is temporarily applied to the front side (12) already coated according to c) and all exposed surfaces (44) are passivated with an ALD coating (46, 82).

Description

[0001] Description

[0002] title

[0003] Method for applying a reflective layer to a front side of a substrate wafer and for passivating exposed surfaces of the substrate wafer

[0004] Technical field

[0005] The invention relates to a method for applying a reflective layer to a front face of a substrate wafer and for passivating exposed surfaces of the substrate wafer. Furthermore, the invention relates to the use of the method for applying a reflective layer to a top face of a MEMS device and for applying an ALD coating to externally exposed surfaces of the MEMS device, in particular a micromirror.

[0006] State of the art

[0007] Specific applications of microelectromechanical systems (MEMS), particularly MEMS wafers, can incorporate movable micromirrors on their front surface and metal contacts on the back of the wafer after fabrication. The movable micromirrors serve to selectively deflect extreme ultraviolet (EUV) light. For this purpose, a reflective layer is applied to their surface. This layer typically comprises a Bragg stack. This stack, in turn, consists of numerous stacked layers of two materials with different refractive indices. The materials and their layer thicknesses are tailored to the wavelength. This stack is electrically conductive for EUV light and must be protected from etching by the EUV-generated plasma by a similarly electrically conductive layer. The micromirrors and the reflective layer can become electrically charged in the EUV plasma and must therefore be electrically grounded.Without electrical grounding, the elements become electrically charged, leading to malfunctions in the actuator or tilt sensor function. The silicon material used to manufacture the micromirrors is also chemically insensitive in plasma environments and must be protected from etching, i.e., passivated, for example, by applying a metal oxide layer. To prevent electrical short circuits, the metal oxide layers suitable for chemical protection must be electrically insulating, as they also need to be applied to drive electrodes. Such a protective layer can be applied essentially isotropically using atomic layer deposition (ALD).

[0008] If the reflective layer is applied before the micromirrors are exposed, it must subsequently be structured to allow for the exposure process. Polishing or wet-chemical cleaning of the exposed micromirror surfaces is no longer possible after exposure. In this case, the ALD layer would have to be applied after exposure, as the sides of the mirror elements, which are only exposed during the exposure process, also need to be passivated. In EUV plasma, this electrically non-conductive layer would become charged above the reflective surface and interfere with the actuator or tilt sensor function.

[0009] If the reflective layer is applied after the micromirrors have been exposed and before the ALD coating, the electrically conductive reflective layer (or its protective layer) can short-circuit exposed electrical conductors or electrodes located beneath the mirror surface. Since the side surfaces also need protection, the ALD layer can only be applied after the micromirrors have been exposed.

[0010] If the ALD layer is applied after the cutout and before the reflective layer, short circuits caused by the reflective layer can be avoided, but in this case, the reflective layer is electrically isolated and not grounded. Complete and dense passivation of all surfaces of the MEMS device is required. The passivation over the reflective surface must be electrically conductive, while all other surfaces must be electrically insulating. Currently, there is no manufacturing process that allows the reflective layer, including the passivation layer, to be applied only to the top surface of the micromirrors, and the ALD protective layer for the silicon (hereinafter referred to as ALD) to be applied to all other externally exposed surfaces, but not to the reflective surface.

[0011] DE 10 2009 033 511 A1 relates to a micromirror arrangement comprising at least one micromirror with a reflective surface formed on a mirror substrate and an antireflective coating formed on the mirror substrate outside the reflective surface. The antireflective coating, which may have a structure, comprises at least one absorbing layer made of a preferably non-metallic material that absorbs at a wavelength in the UV range. DE 10 2009 033 511 A1 further relates to a method for producing an antireflective coating. The antireflective coating can, in particular, serve to compensate for the layer tension of a reflective coating on which the reflective surface is formed.

[0012] DE 20 122 618 U1 relates to a micromirror connected to a substrate via a post, a hinge, and metal sections, and to an array of micromirrors arranged in a right-angled configuration with the ability to rotate around a switching axis between on and off states corresponding to pixels in a viewed image. Light is directed from a source to the reflectors non-perpendicularly to at least two sides of a reflector, while reflected light is received by collector optics. Various layer structures of the micromirrors are also described.

[0013] DE 10 2015 213 714 A1 relates to a micromechanical component, wherein the micromechanical component is adaptable to a wide variety of applications, for example, its use as a micromirror is proposed, with a layered structure consisting of at least one substrate, a first conductive layer, a piezoelectrically active layer, and a second conductive layer, wherein the first and the second conductive layers form electrodes for the piezoelectrically active layer. The substrate material is simultaneously a mechanical functional layer as a support for the piezoelectrically active layer and is designed such that it deforms together with the piezoelectrically active layer.

[0014] Disclosure of the invention: According to the invention, a method for applying a reflective layer to a front face of a substrate wafer and for passivating exposed surfaces of the substrate wafer is proposed, comprising the following process steps: a) creating trenches on the front face of the substrate wafer and applying an ALD coating at least to its side walls, b) temporarily filling the trenches created according to process step a) with a filling layer, c) applying a coating comprising a reflective layer and an electrically conductive protective layer to the front face of the substrate wafer, and d) temporarily applying a protective wafer to the front face already coated according to process step c) and passivating all exposed surfaces by means of an ALD coating.

[0015] The method proposed according to the invention advantageously makes it possible to apply a reflective layer, for example in the form of a multilayer Bragg stack, only to one top surface of a MEMS device, such as a micromirror, and to apply a protective layer in the form of an ALD protective layer to all other externally exposed surfaces, but not to the reflective surface.

[0016] In an advantageous further development of the solution proposed according to the invention, the trenches are introduced within separation areas between mirror elements or within separation areas between mirror elements and edge areas of the substrate wafer according to process step a).

[0017] In the method proposed according to the invention, it is further advantageously provided that structures buried in the silicon material of the substrate wafer, separated from each other by silicon oxide, as well as channels lined with silicon oxide, are carried out.

[0018] The method proposed according to the invention is advantageously designed such that at least one access opening for supplying etching or coating media is formed on the substrate wafer. Such access openings are preferably located on the front side of the silicon-based substrate wafer. The method proposed according to the invention is advantageously characterized in that, according to process step a), the grooves are created by an etching medium, wherein the side walls of the grooves are formed at an undercut angle or a bevel angle of more than 90°.

[0019] In an advantageous further development of the method proposed according to the invention, the ALD coating is deposited as aluminium oxide, as titanium oxide or as tantalum oxide according to process step a).

[0020] The method proposed according to the invention further has the advantage that, after carrying out process step a), the ALD coating on the front of the substrate wafer can be removed from parts of the trench bottoms of the trenches by means of a directed dry etching process, with the ALD coating remaining on the side walls of the trenches.

[0021] The method proposed according to the invention is further characterized in that, according to process step b), the trenches and the front side of the substrate wafer each have an amorphous layer of silicon material onto which an epitaxially grown polysilicon can be applied or filled as a filling layer.

[0022] In a further development of the method proposed according to the invention, it is provided that the epitaxially grown polysilicon layer is removed by means of leveling through CMP polishing on an original surface on the front side of the substrate wafer, while the ALD coating of the side walls remains exposed on the substrate surface, thereby giving the substrate surface a high optical quality that facilitates the application of a reflective layer. This allows the reflective layer, preferably designed as a Bragg multilayer stack, to be applied in a particularly advantageous manner.

[0023] In the method proposed according to the invention, it is further provided that, according to process step c), the reflective layer is designed as a multilayer Bragg stack. The multilayer Bragg stack can be structured as a multilayer structure of at least two materials having different refractive indices. Furthermore, in the method proposed according to the invention, it is advantageously provided that, according to process step c), the electrically conductive protective layer is deposited onto the reflective layer.

[0024] Furthermore, the method proposed according to the invention is characterized in that, according to process step d), the protective wafer, containing a buried shadow mask, is detachably fixed to the front side of the substrate wafer by means of temporary bond connections. The use of the protective wafer effectively protects a previously structured or high-quality reflective surface in the form of a Bragg stack against etching.

[0025] In the method proposed according to the invention, it is further provided that after opening an exposed silicon closure on a front side of the protective wafer, the reflective layer or the electrically conductive layer above the area of ​​the trenches is etched by means of an IB E-etching process, followed by etching out the silicon material from channels by means of isotropic SFβ or XeF2 etching to a silicon oxide coating, thereby obtaining isolated mirror elements.

[0026] Furthermore, the method proposed according to the invention advantageously provides that silicon oxide exposed by HF gas phase etching is removed from channels and from all surfaces.

[0027] Advantageously, in the method proposed according to the invention, it is provided that, according to process step d), all exposed surfaces and channels are passivated by means of an ALD coating, wherein the front of the substrate wafer is shielded by the applied protective wafer.

[0028] The method proposed according to the invention further provides that, according to process step d), an ALD coating is removed from the front of the protective wafer and / or from a back side of the substrate wafer by means of the IBE etching process. Furthermore, the method proposed according to the invention provides that a cover part serving as a sealing layer of the protective wafer is removed by means of trench etching or SF6 / XeF2 etching.

[0029] Furthermore, the method proposed according to the invention is characterized in that the openings of the shadow mask buried in the protective wafer allow the removal of the electrically conductive protective layer above the reflective layer, which is preferably designed as a multi-layered Bragg stack, or above the filled trenches.

[0030] In the method proposed according to the invention, it is further provided that the polysilicon is etched out of the filled trenches through the openings of the shadow mask by an anisotropic etching process, wherein the etching is limited by reaching an ALD coating part.

[0031] In the method proposed according to the invention, it is further advantageously provided that the ALD layer in the area of ​​trench bottoms is etched out through the openings of the shadow masks by an anisotropic etching process. To minimize the etching of the ALD layer in the access channel, its cross-section can be minimized or a lateral offset in the form of a baffle can be formed in the vertical part of the channel.

[0032] In the method proposed according to the invention, the protective wafer is detached from the front of the substrate wafer after the temporary bond is broken. This makes it possible to reuse it.

[0033] The method proposed according to the invention further provides that at least one further trench, reduced in width, is inserted into an existing trench filled with a backfill layer. The reduction of the trench widths can be carried out in several passes, so that their geometry can be adapted to a wide variety of requirements.

[0034] Furthermore, the invention relates to the use of the method for applying a reflective surface to a top surface of a MEMS device and for applying an ALD coating to externally exposed surfaces of a MEMS device, preferably a micromirror of a micromirror array.

[0035] Advantages of the invention

[0036] The solution proposed according to the invention provides a method for the three-stage passivation of exposed surfaces of a MEMS array. In a first stage, trenches with flank angles of more than 90° are introduced on a front surface, corresponding to an undercut, the walls of which are coated with an ALD protective or passivation layer and subsequently temporarily filled with polysilicon.

[0037] In the second stage, a front-side coating is applied, consisting of a reflective layer and a protective layer. In a third stage, the remaining surfaces are passivated. During this process, the already coated front side is protected by a temporarily applied protective cap. After processing is complete, the polysilicon is removed from the trenches using a shadow mask via trench etching. The shadow mask is integrated into the protective wafer or embedded within it and can be exposed in a corresponding process step. The protective wafer is then removed.

[0038] By means of such a filling, the wafer surface can be sealed for the micromirrors, and its surface roughness can be reduced, for example through polishing processes, to such an extent that very high optical quality is achieved. Furthermore, the filling advantageously enables the application of the reflective layer across essentially the entire surface, resulting in the aforementioned high optical quality. The filling, together with the shadow mask protection wafer, protects the front of the wafer from etching or coating processes. The filling also allows for ALD coating of all externally exposed component elements, while simultaneously protecting the front of the micromirrors from ALD coating.

[0039] After the polysilicon infill is removed at the end of the process, the micromirrors are exposed, meaning they are essentially movable in all directions, leaving only the ALD-coated trench walls. Together with the previously applied ALD coating, these layers protect the micromirrors on all sides—except for the reflective surface on the wafer front, which has a Bragg stack with an electrically conductive protective layer.

[0040] All MEMS elements of the component are protected on all sides from etching in an EUV plasma environment by a passivation layer comprising an ALD coating and a protective layer on the reflective surface. By temporarily filling the trenches and using a protective wafer with an integrated, "buried" shadow mask, complete passivation of all surfaces can be achieved. The passivation of the front surface is an electrically conductive protective layer, while an electrically insulating layer can be applied to all other surfaces.

[0041] Brief description of the drawings

[0042] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

[0043] They show:

[0044] Figure 1 shows a silicon substrate wafer with buried areas or structures separated by SiÜ2,

[0045] Figure 2 shows grooves or depressions introduced on the front side of the substrate wafer in the separation area.

[0046] Figure 3 shows an ALD coating of the front side of the substrate wafer,

[0047] Figure 4 shows a partial removal of the ALD layer on the front of the

[0048] Substrate wafers,

[0049] Figure 5 shows the trenches being filled with an amorphous silicon starter layer and polysilicon; Figure 6 shows the removal of the previously applied silicon layer by means of CMP polishing.

[0050] Figure 7 shows a deposition of a reflective layer as a multilayer Bragg stack.

[0051] Figure 8 shows an optional structuring of the previously separated multilayer Bragg stack,

[0052] Figure 9 shows a full-surface deposition of an electrically conductive protective layer for the Bragg stack,

[0053] Figure 10 shows the provision of a protective wafer which has a buried shadow mask integrated into it.

[0054] Figure 11 shows the adjustment and bonding of the protective wafer to the front of the substrate wafer.

[0055] Figure 12 shows a first etching process on the front of the protective wafer using isotropic SFβ or XeF2 or anisotropic trench etching,

[0056] Figure 13 shows a subsequent RF gas phase etching step according to Figure 12 for the removal of exposed silicon oxide from channels and all surfaces,

[0057] Figure 14 shows the application of an ALD protective layer to all exposed surfaces for passivation.

[0058] Figure 15 shows the removal of the ALD layer from the front of the protective wafer and optionally also from the back of the wafer.

[0059] Figure 16 shows the opening of the protective wafer at its front by removing the top part.

[0060] Figure 17 shows the opening of the protective layer of the Bragg stack in the area above previously filled trenches; Figure 18 shows the etching of polysilicon from previously filled trenches using anisotropic trench etching.

[0061] Figure 19 shows the etching out of remaining ALD layers from the trench floors.

[0062] Figure 20 shows the removal of the protective wafer including the shadow mask from the front of the substrate wafer by debonding temporary bond connections and

[0063] Figures 21.1 - 22.3 show optional additional process steps to improve all-around closed passivation, especially at the contact point between the electrically conductive protective layer on the front of the substrate wafer and the electrically insulating ALD protective layer on the trench flanks.

[0064] Embodiments of the invention

[0065] In the following description of embodiments of the invention, identical or similar elements are designated by the same reference numerals, and repeated descriptions of these elements are omitted in individual cases. The figures represent the subject matter of the invention only schematically.

[0066] Figure 1 shows a substrate wafer with embedded structures that are separated from the silicon material 20 of the substrate wafer 10 by layers of silicon oxide 22.

[0067] As can be seen from the illustration in Figure 1, the substrate wafer 10 is made of a silicon material 20 and has embedded structures that are separated from each other, for example, by thin layers of silicon oxide 22. A front side of the substrate wafer 10, as shown in Figure 1, is identified by reference numeral 12, and its back side by reference numeral 14. The substrate wafer 10 in Figure 1 comprises edge regions 16, between which a mirror element 18, shown here by way of example, is arranged. The mirror element 18, indicated in Figure 1, can be separated from the edge regions 16 along separation regions 24 extending substantially vertically through the substrate wafer 10 by etching processes and other process steps.In the present context, the separation area 24 does not involve a complete separation of the mirror element 18 and its edge regions 16; otherwise, the mirror elements 18 would fall out of the wafer assembly. The separation occurs only in the mirror, spring, and actuator planes, and not in a base plane. The mirror plane is freed laterally and vertically to allow movement (tilting); however, a connection to the spring plane remains, through which it also remains connected to the base plane. At least one access opening 26 is located on the front face 12 of the substrate wafer 10, as shown in Figure 1. This access opening 26 is present in the substrate but is only etched free in a later step over the attached protective wafer 66. Etching media, such as SFe or XeF2, can be introduced through this opening into the interior of the substrate wafer 10 for processing.

[0068] Reference numeral 28 designates a mirror plane in the substrate wafer 10, in which the mirror element 18 is essentially located. This mirror element, as will be explained later, is isolated within the substrate wafer 10. Reference numeral 30 designates a spring plane, i.e., the plane in which a subsequently isolated mirror element 18 (see position 78 in the following description) is movable. Reference numeral 32 identifies an actuator plane (in BZL: etching plane) located above a base plane 34 in the silicon material 20 of the substrate wafer 10. In the representation according to Figure 1, the substrate wafer 10 comprises a single mirror element 18, which is surrounded by the respective edge regions 16. However, a plurality of mirror elements 18 can also be formed in the silicon material 20 of the substrate wafer 10, each framed by edges.The representation in Figure 1 further shows that channels formed in the substrate wafer 10 can be encased in silicon oxide 22. The layer sequence shown in Figure 1 is merely one example of many possible embodiments, as a multitude of other layer configurations are possible.

[0069] Figure 2 shows that on the front face 12 of the substrate wafer 10, above the parting lines 24 shown in Figure 1, depressions in the form of trenches 36 are created. These depressions are produced by trench etching. In trench etching, the etching parameters are selected such that a negative sidewall angle 42, also referred to as the undercut angle, of more than 90° is generated. This results in trenches 36, as shown in Figure 2, which have a trench bottom 38 that runs essentially horizontally and sidewalls 40 that run at the aforementioned negative sidewall angle 42 of more than 90°.

[0070] Subsequently, as shown in Figure 3, an ALD coating 46, for example formed from aluminum oxide, titanium oxide, or tantalum oxide, is conformally applied to exposed surfaces 44 using an atomic layer coating. The ALD coating 46 is applied to all exposed surfaces. The structures still embedded in this coating, in particular the mirror element 78 which will be exposed later, are separated from each other by thin layers of silicon oxide 22.

[0071] Subsequently, as shown in Figure 4, the previously applied ALD coating 46 on the front 12 and back 14 of the substrate wafer 10 and on a partial area 48 of the trench bottoms 38 of the trenches 36 is removed by means of a directed dry etching process, for example by means of ion beam etching. On the side walls 40 of the trenches, the ALD coating 46 is protected from etching due to the anisotropic etching effect, so that the ALD coating 46 remains on the side walls 40. The trench bottoms 38, as shown in Figure 2, are only exposed within a partial area 48, as can be seen from Figure 4.

[0072] Figure 5 shows that both on the front side 12 of the substrate wafer 10, i.e., on the exposed surface 44, and in the trenches 36, an epitaxially grown polysilicon 52 is applied to an amorphous silicon starter layer present there. A filling layer 50 is formed in particular by the epitaxially grown polysilicon 52. The thickness of the growing filling layer 50 is sufficient to obtain a smooth surface after leveling, as can be seen, for example, in the illustration according to Figure 6.

[0073] Figure 6 shows that the epitaxially grown polysilicon 52 applied according to Figure 5 is removed by a removal process, for example, chemical mechanical polishing (CMP polishing). The removal of the previously applied epitaxially grown polysilicon 52, as shown in Figure 6, proceeds down to an original surface 54 on the front side 12 of the substrate wafer 10. Its back side 14 remains covered by a silicon oxide layer 22. After removal, as shown in Figure 6, the ALD coatings 46, applied to the side walls 40 of the grooves 36, are exposed on the front side 12 of the substrate wafer 10. The surface, i.e., the front side 12 of the substrate wafer 10, acquires a very high optical quality during CMP polishing, which is particularly suitable for the subsequent application of a reflective layer.The reflective layer 110 to be applied after the treatment according to Figure 6 is in particular a multi-layered Bragg coating 58.

[0074] Figure 7 shows that a reflective layer in the form of a multilayer Bragg layer stack 58 is deposited onto the original surface 54, which has been previously prepared to a high surface quality, as shown in Figure 6. This is done over the entire surface. Optionally, a shadow mask can be used for structured deposition of the multilayer Bragg coating 58. Figure 7 illustrates the application of a multilayer reflective layer in the form of a Bragg coating 58 to the previously treated original surface 54.

[0075] Figure 8 shows an optional process step in which, for example, but not necessarily, the reflective layer 110 applied to the original surface 54 in Figure 7 can be structured in the form of the Bragg coating 58. In particular, those areas of the multilayer Bragg coating 58 that are located above the filled trenches 36, as well as the access openings 26 (see illustration in Figure 1), are exposed.

[0076] As can be seen in Figure 9, an electrically conductive protective layer 62 is now deposited over the entire surface of the reflective layer in the form of the multilayer Bragg coating 58. In the case of an optionally structured Bragg stack 60, as shown, for example, in Figure 8, this electrically conductive protective layer 62 also protects the side faces 64 of the multilayer Bragg coating 58, which were previously exposed during structuring. If passivation of the side faces 64 of the Bragg coating 58 is not required, structuring, as shown, for example, in Figures 7 and 8, can be omitted entirely. As can be seen in Figure 10, a protective wafer 66 is then used, i.e., after the application of the electrically conductive protective layer 62 to the multilayer Bragg coating 58, whether structured or provided with structured areas 60.Figure 10 shows that the protective wafer 66, formed by a base part 68 and a top part 70, comprises a buried shadow mask 88. The buried shadow mask 88 is preferably formed in the base part 68 of the protective wafer 66, as shown schematically in Figure 10. The electrically conductive protective layer 62 is still located above the structured or unstructured multilayer Bragg coating 58. The trenches 36 on the front face 12 of the substrate wafer 10 are still filled with the infill layer 50 in the form of epitaxially grown polysilicon 52.

[0077] The illustration in Figure 11 shows that the protective wafer 66 provided in Figure 10, formed by the bottom part 68 and the lid part 70, is adjusted on the front side 12 of the substrate wafer 10 and is then attached to the substrate wafer 10 in a position adjusted relative to the front side 12, for example by means of releasable temporary bond connections 72.

[0078] Figure 11 further shows that an exposed silicon seal 74 is located in the cover part 70 of the protective wafer 66, as depicted in Figure 11. This seal is still closed in Figure 11 and, as can be seen in Figure 12, can be opened, for example, by isotropic SFβ or XeF2 etching or by anisotropic trench etching. The open state of the exposed silicon seal 74 in the cover part 70 of the protective wafer 66 is shown in Figure 12. An etching step or release step 76 is then performed through the now open exposed silicon seal 74 by introducing SFβ etching gas or the like. Subsequently, the Bragg coating 58 is etched using IBE with the previously applied electrically conductive protective layer 62, or with only the electrically conductive protective layer 62 in the area of ​​the trenches 36.Subsequently, silicon material 20 is etched out of a channel system or the access channels up to the silicon oxide 22 coating within the substrate wafer 10 by means of isotropic SFβ or XeF2 etching. As indicated in Figure 12, this process step leads, due to the channels 80 now being free of silicon material 20, to the aforementioned isolated mirror element 78, as shown in Figure 12. The isolated mirror element 78 is connected to its adjacent areas only via the still partially filled trenches 36 and via the spring element.

[0079] As can be seen in Figure 13, RF vapor phase etching 81 is now performed through the exposed silicon seal 74, which remains open, thereby removing the exposed silicon oxide 22 from the channels 80 and from all accessible surfaces. This is illustrated in Figure 13. The protective wafer 66, applied via temporary bond connections 72, remains in an adjusted position on the front face 12 of the substrate wafer 10 and on the areas of the electrically conductive protective layer 62.

[0080] As shown in Figure 14, after the RF vapor phase etching 81 according to Figure 13, an ALD coating 82 is applied to all exposed surfaces 44 of the substrate wafer 10 and the protective wafer 66 by means of an atomic layer coating. This ALD coating 82 of all exposed surfaces 44 serves as a protective or passivation layer. This protective or passivation layer, formed by the ALD coating 82 according to Figure 14, prevents the etching of the silicon material 20 and the silicon oxide 22 by the EUV plasma. The areas located below the protective wafer 66 with the buried shadow mask 88 are protected by the ALD coating 82 before the coating process, as they are inaccessible.

[0081] A comparison between Figures 14 and 15 shows that, in further development of the method proposed according to the invention as shown in Figure 15, the ALD coating 82 is now removed from a front surface 84 of the protective wafer 66 and / or from the back surface 14 of the substrate wafer 10 by means of IBE etching. After this removal step, further processes can optionally be carried out on the back surface 14 of the substrate wafer 10. These include, for example, the fabrication of an electrical wiring layer with conductor tracks and the application of solderable contact surfaces. Alternatively, it is possible to remove a base layer and bond a wafer with integrated electrical wiring and solderable contact surfaces on the front and / or back surface.Figure 15 shows that after the ALD coating 82 of all accessible surfaces, the silicon-free channels 80 are provided with an ALD coating 82, as is the underside of the now exposed mirror element 78.

[0082] Figure 16 shows that the cover part 70, which represents a sealing layer 86, is removed from the front 84 of the cover part 70. The shadow mask 88, including its openings 90, is exposed after the cover part 70 is removed. The cover part 70 can be opened, for example, by trench etching or SF6 / XeF2 etching.

[0083] Figure 17 shows that, starting from the open state of the protective wafer 66 as depicted in Figure 16, the opening of the electrically conductive protective layer 62 above the filled trenches 36 now occurs through the openings 90 in the shadow mask 88, as shown in Figure 16. The filled trenches 36 remain filled with a filler layer 50 of epitaxially grown polysilicon 52.

[0084] Figure 18 shows that the epitaxially grown polysilicon 52, which forms the infill layer 50 of the trenches 36, is etched out through the openings 90 of the shadow mask 88. This etching is carried out, for example, by anisotropic trench etching. This etching process ends as soon as the ALD coating 82 shown in Figure 18 is reached above the trench bottoms 38. The trenches 36 and the openings 90 of the shadow mask 88 located above them are then clear. Figure 18 shows that, with the exposure 92 of the trenches 36, they are now separated from the silicon-free channel system 80 only by the ALD coating 82.

[0085] Figure 19 shows that the ALD coating 82 is now removed from the previously filled trenches 36 by means of anisotropic etching 93. To minimize the etching of the ALD coating 82 in the access channel 80, its cross-section can be reduced 94, or a lateral offset 96 in the form of a baffle can be provided in the vertical parts of the access channel 80. During the anisotropic etching of the ALD coating 82 in the trenches 36, this area within the access channel 80 is also etched. The illustration in Figure 19 shows that the removal 93 of the ALD coating 82 from the trench bottoms 38 allows passage to the bottom of the essentially vertical silicon-free channels 80.

[0086] As shown in Figure 20, after the removal of the ALD coating 82 from the trench bottoms 38 of the previously backfilled trenches 36, the protective wafer 66 is detached by means of a vertical upward detachment 98 by breaking the temporary bond connections 72. The protective wafer 66, together with the shadow mask 88 integrated therein, is removed. The temporary bond connections 72 can be broken using a laser debonding process.

[0087] The illustrations in Figures 21.1 to 21.3 and 22.1 to 22.3 show optional additional process steps that can be carried out within the separation zones 24, as shown in Figure 1, at the depressions formed as trenches 36. These additional steps can significantly increase the reliability of a completely closed passivation, particularly at a contact point between the electrically conductive protective layer 62 on the front surface 12 and the electrically insulating ALD protective layer 46, which is applied to the side walls 40 of the trenches 36, as previously described with reference to Figures 3, 4, and 5. The process sequence shown in Figures 21.1 to 21.3 demonstrates that, starting from the trenches 36 filled with the epitaxially grown polysilicon 52 backfill layer 50, the previously applied ALD coating 46 is present. According to Figure 21.2 The trench width is formed in a reduced width, followed by a renewed application of an ALD coating 82, so that overall the aforementioned reduced trench width 102 is achieved.

[0088] Figures 22.1 to 22.3 show that the trench 36, formed with the reduced trench width 102 according to Figure 22.2, is again filled with the backfill layer 50 of epitaxially grown polysilicon 52. As described above, this polysilicon is removed from the silicon material 20 of the substrate wafer 10 down to the original surface 54, so that the aforementioned completely filled, reduced trench is formed. The trench with a reduced width 102 can, for example, be fitted into an already formed trench 36 filled with epitaxially grown polysilicon. This process sequence, shown here as an option, can be repeated cyclically several times with progressively smaller trench widths.

[0089] The manufacturing process described above is not limited to mirror elements 18 that become isolated mirror elements 78, and in particular not to MEMS devices. It can also be used for other products within the framework of MEMS structures with similar requirements. In particular, the method proposed according to the invention can be carried out with the protective wafer 66, which advantageously has said buried shadow mask 88. The combination with the protective wafer 66 provides optimal access to the recesses 36 formed within the parting lines 24 of the substrate wafer 10 and allows their machining, as is shown in particular in Figures 11 to 19.

[0090] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, within the scope specified by the claims, a multitude of modifications are possible that fall within the bounds of what is considered skilled in the art.

Claims

Claims 1. Method for applying a reflective layer (110) to a front face (12) of a substrate wafer (10) and for passivating exposed surfaces (44) of the substrate wafer (10) comprising at least the following process steps: a) creating trenches (36) on the front face (12) of the substrate wafer (10) and applying an ALD coating (46) at least to its side walls (40), b) temporarily filling the trenches (36) created according to a) with a filling layer (50, 52), c) applying a coating comprising a reflective layer (110) and an electrically conductive protective layer (62) to the front face (12) of the substrate wafer (10), and d) temporarily applying a protective wafer (66) to the front face (12) of the substrate wafer (10) already coated according to c) and passivating all exposed surfaces (44) with an ALD Coating (46, 82).

2. Method according to claim 1, characterized in that according to method step a) the trenches (36) are introduced within separation areas (48) between mirror elements (18) or within separation areas (48) between mirror elements (18) and edge areas (16) of the substrate wafer (10).

3. Method according to claims 1 and 2, characterized in that structures (18, 78) buried in the silicon material (20) of the substrate wafer (10) and separated from each other by silicon oxide (22) and channels lined with silicon oxide (22) are carried out.

4. Method according to claims 1 to 3, characterized in that at least one access opening (26) for etching and coating media is formed on the substrate wafer (10).

5. Method according to claims 1 to 4, characterized in that according to method step a) the trenches (36) are introduced by an etching process, wherein side walls (40) of the trenches (36) are formed at an etching angle (42) of more than 90°.

6. Method according to claims 1 to 5, characterized in that according to process step a) the ALD coating (46) is deposited as aluminium oxide, titanium oxide or tantalum oxide.

7. Method according to claims 1 to 6, characterized in that after carrying out method step a) the ALD coating (46) on the front side (12) of the substrate wafer (10) is removed on partial areas (48) of trench bottoms (38) of the trenches (36) by means of a directed dry etching process and the ALD coating (46) remains on the side walls (40) of the trenches (36).

8. Method according to claims 1 to 7, characterized in that according to process step b) an epitaxially grown polysilicon (52) is filled as a filling layer (50) onto an amorphous layer of silicon material (20) of the trenches (36) and / or the front side (12) of the substrate wafer (10).

9. Method according to claims 1 to 8, characterized in that the epitaxially grown layer of polysilicon (52) is removed by means of leveling by CMP polishing to an original surface (54) on the front (12) of the substrate wafer (10), the ALD coating (46) of the side walls (40) remains exposed to a substrate surface (56), wherein the substrate surface (56) is given a high optical quality required for the application of the reflective layer (58).

10. Method according to claims 1 to 9, characterized in that according to method step c) the Bragg coating (58) is carried out as a multi-layer Bragg stack.

11. Method according to claims 1 to 10, characterized in that, according to method step c), the electrically conductive protective layer (62) is deposited onto the Bragg coating (58).

12. Method according to claims 1 to 11, characterized in that according to method step d) the protective wafer (66) containing a buried shadow mask (88) is detachably fixed to the front side (12) of the substrate wafer (10) by means of temporary bond connections (72).

13. Method according to claims 1 to 12, characterized in that after opening an exposed silicon closure (74) on a front side (84) of the protective wafer (66), an IB E-etching of the Bragg coating (58) and / or the electrically conductive protective layer (62) above the area of ​​the trenches (36) is carried out, followed by an etching out of the silicon material (20) by means of isotropic SF6 or XeF2 etching from channels (80) to a silicon oxide coating (22), whereby isolated mirror elements (78) are obtained.

14. Method according to claims 1 to 13, characterized in that silicon oxide (22) exposed by means of HF gas phase etching (81) is removed from channels (80) and from all surfaces.

15. Method according to claims 1 to 14, characterized in that according to method step d) all exposed surfaces (44) and channels (80) are passivated by means of an ALD coating (82), wherein the front side (12) of the substrate wafer (10) is shielded by the applied protective wafer (66).

16. Method according to claims 1 to 15, characterized in that, after process step d), an ALD coating (82) is removed from the front (84) of the protective wafer (66) and / or from the back (14) of the substrate wafer (10) by IBE etching.

17. Method according to claims 1 to 16, characterized in that a cover part (70) serving as a closure layer (86) of the protective wafer (66) is removed by trench etching or SFβ / or XeF2 etching.

18. Method according to claims 1 to 17, characterized in that the electrically conductive protective layer (62) or above the Bragg coating (58) above the filled trenches (36) is removed through openings (90) of the shadow mask (88) in the protective wafer (66).

19. Method according to claim 18, characterized in that the polysilicon is etched (93) out of the filled trenches (36) through the openings (90) of the shadow mask (88) by an anisotropic etching process, wherein the etching (93) is limited by reaching the ALD coating (82).

20. Method according to claim 18, characterized in that the ALD layer (82) is etched out (93) through the openings (90) of the shadow mask (88) on trench bottoms (38).

21. Method according to claims 1 to 20, characterized in that the protective wafer (66) is lifted off the front side (12) of the substrate wafer (10) after releasing the temporary bond connections (72).

22. Method according to claims 1 to 21, characterized in that at least one trench (102) with a reduced trench width is introduced into a trench (104) that has already been created and filled with a backfill layer (50, 52).

23. Use of the method according to claims 1 to 22 for applying a substrate surface of the highest quality (56) to a top surface of a MEMS device and for applying an ALD coating (46, 82) to externally exposed surfaces (44) of a MEMS device, in particular a micromirror.

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