Machine-learning assisted extrapolation of wafer-scale metrology using alignment read-outs

Abstract

A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for training a machine learning model to predict images on a wafer to provide data for determining an edge placement error (EPE) of the wafer. The operations include: measuring a plurality of markings on the wafer; obtaining images of the wafer near each of the plurality of markings; obtaining an image of another portion of the wafer; and training a machine learning model using the plurality of markings and the image of the another portion of the wafer to predict the images near each of the plurality of markings, wherein the predicted images near each of the plurality of markings provide data for determining the EPE of the wafer.

Description

MACHINE-LEARNING ASSISTED EXTRAPOLATION OF WAFER-SCALE METROLOGY USING ALIGNMENT READ-OUTSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of EP application 24191913.3 which was filed on 30 July 2024 and which is incorporated herein in its entirety by reference.TECHNICAL FIELD

[0002] The embodiments provided herein relate to using asymmetric markings on a wafer and one or more images of the wafer to predict images of the wafer to provide data for determining edge placement error, and more particularly to training a machine learning model to predict images for nonimaged locations on the wafer to provide data for determining edge placement error.BACKGROUND

[0003] In manufacturing processes of integrated circuits (ICs), unfinished or finished circuit components are inspected to ensure that they are manufactured according to design and are free of defects. Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes, such as a scanning electron microscope (SEM) can be employed. As the physical sizes of IC components continue to shrink, accuracy and yield in defect detection become more important. Various metrology tools are developed and used to check whether the ICs are correctly manufactured.

[0004] When performing metrology on an IC after manufacturing, one feature that may be examined includes edge placement error (EPE), which is a misalignment between different layers of the IC. For example, EPE occurs when features of a bottom layer do not line up with corresponding features of a top layer formed on top of the bottom layer. For example, and as will be discussed below, the different layers may be examined using charged-particle beam inspection images of the IC. Existing methods to detect misalignment include edge detection methods, wherein the distance between the detected edges is used to extract an overlay value. The EPE values may be calculated based the overlay values and then may be averaged. But the averaging may ignore differences in local EPE distribution that originates from various process steps or imaging fingerprints. The resulting averaged value may over-estimate or under-estimate the actual EPE values in different areas of the wafer.

[0005] It may be helpful to better determine the EPE in different areas of the wafer by taking more images of the wafer, but taking the images is a time-consuming process.SUMMARY

[0006] Some embodiments provide a non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for training a machine learning model to predict images on a wafer toprovide data for determining an edge placement error (EPE) of a wafer. The operations include: measuring a plurality of markings on the wafer; obtaining images of the wafer near each of the plurality of markings; obtaining an image of another portion of the wafer; and training a machine learning model using the plurality of markings and the image of the another portion of the wafer to predict the images near each of the plurality of markings, wherein the predicted images near each of the plurality of markings provide data for determining the EPE of the wafer.

[0007] Some embodiments provide a non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for training a machine learning model to predict key performance indicators (KPIs) on a wafer to provide data for determining an edge placement error (EPE) of a wafer. The operations include: measuring a plurality of markings on the wafer; obtaining images of the wafer near each of the plurality of markings; obtaining an image of another portion of the wafer; and training a machine learning model using the plurality of markings and the image of the another portion of the wafer to predict the KPIs near each of the plurality of markings, wherein the predicted KPIs near each of the plurality of markings provide data for determining the EPE of the wafer.

[0008] Some embodiments provide an apparatus for training a machine learning model to predict images on a wafer to provide data for determining an edge placement error (EPE) of a wafer. The apparatus includes a memory storing a set of instructions and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations. The operations include: receiving measurement data from an alignment sensor for a plurality of asymmetric markings on the wafer, wherein each of the plurality of asymmetric markings is located near an outer edge of the wafer; obtaining images of the wafer near each of the plurality of asymmetric markings; obtaining an image of another portion of the wafer, wherein the another portion of the wafer does not include any of the plurality of markings; and training a machine learning model using the plurality of asymmetric markings and the image of the another portion of the wafer to predict the images near each of the plurality of asymmetric markings, wherein the predicted images near each of the plurality of asymmetric markings provide data for determining the EPE of the wafer.

[0009] Other advantages of the embodiments of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present invention.BRIEF DESCRIPTION OF FIGURES

[0010] The above and other aspects of the present disclosure will become more apparent from the description of exemplary embodiments, taken in conjunction with the accompanying drawings.

[0011] Fig. 1 is a schematic diagram illustrating an example charged-particle beam inspection (CPBI) system, consistent with some embodiments of the present disclosure.

[0012] Fig. 2 is a schematic diagram illustrating an example charged-particle beam tool, consistent with some embodiments of the present disclosure that may be a part of the example charged-particle beam inspection system of Fig. 1.

[0013] Fig. 3 is a schematic diagram illustrating an example multi-beam tool, consistent with embodiments of the present disclosure that can be a part of the example charged-particle beam inspection system of Fig. 1.

[0014] Fig. 4 is a block diagram of an exemplary server, consistent with some embodiments of the present disclosure.

[0015] Fig. 5 is a schematic diagram illustrating an example neural network, consistent with some embodiments of the present disclosure.

[0016] Fig. 6 is a diagram of two example asymmetric markings on a wafer, consistent with some embodiments of the present disclosure.

[0017] Fig. 7A is a top view of a training wafer showing marking measurement locations and image locations, consistent with embodiments of the present disclosure.

[0018] Fig. 7B is a top view of a test wafer showing marking measurement locations and an image location, consistent with embodiments of the present disclosure.

[0019] Fig. 8 is a flowchart of an example method for training a machine learning model to predict images of a wafer, consistent with embodiments of the present disclosure.

[0020] Fig. 9 is a flowchart of an example method for using a trained machine learning model to predict an image of a new location on a wafer, consistent with embodiments of the present disclosure.

[0021] Fig. 10 is a flowchart of an example method for using a trained machine learning model to predict an image of a new wafer, consistent with embodiments of the present disclosure.DETAILED DESCRIPTION

[0022] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the disclosed embodiments as recited in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, the disclosure is not so limited. Other types of charged-particle beams (e.g., including protons, ions, muons, or any other particle carrying electric charges) may be similarly applied. Furthermore, other imaging systems may be used, such as optical imaging, photon detection, x-ray detection, ion detection, etc.

[0023] Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings, the same or like reference numbers refer to the same or likecomponents or entities, and only the differences with respect to the individual embodiments are described. As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a component may include A or B, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or A and B. As a second example, if it is stated that a component may include A, B, or C, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0024] Electronic devices are constructed of circuits formed on a piece of semiconductor material called a substrate. The semiconductor material may include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium, or the like. Many circuits may be formed together on the same piece of silicon and are called integrated circuits or ICs. The size of these circuits has decreased dramatically so that many more of them can be fit on the substrate. For example, an IC chip in a smartphone can be as small as a thumbnail and yet may include over 2 billion transistors, the size of each transistor being less than l / 1000th the size of a human hair.

[0025] Making these ICs with extremely small structures or components is a complex, timeconsuming, and expensive process, often involving hundreds of individual steps. Errors in even one step have the potential to result in defects in the finished IC, rendering it useless. Thus, one goal of the manufacturing process is to avoid such defects to maximize the number of functional ICs made in the process; that is, to improve the overall yield of the process.

[0026] One component of improving yield is monitoring the chip-making process to ensure that it is producing a sufficient number of functional integrated circuits. One way to monitor the process is to inspect the chip circuit structures at various stages of their formation. Inspection can be carried out using a scanning charged-particle microscope (SCPM). For example, an SCPM may be a scanning electron microscope (SEM). An SCPM can be used to image these extremely small structures, in effect, taking a “picture” of the structures of the wafer. The image can be used to determine if the structure was formed properly in the proper location. If the structure is defective, then the process can be adjusted, so the defect is less likely to recur.

[0027] The working principle of an SCPM (e.g., an SEM) is similar to a camera. A camera takes a picture by receiving and recording intensity of light reflected or emitted from people or objects. An SCPM takes a “picture” by receiving and recording energies or quantities of charged particles (e.g., electrons) reflected or emitted from the structures of the wafer. Typically, the structures are made on a substrate (e.g., a silicon substrate) that is placed on a platform, referred to as a stage, for imaging. Before taking such a “picture,” a charged-particle beam may be projected onto the structures, and when the charged particles are reflected or emitted (“exiting”) from the structures (e.g., from the wafer surface, from the structures underneath the wafer surface, or both), a detector of the SCPM may receive and record the energies or quantities of those charged particles to generate an inspection image. To take such a “picture,” the charged-particle beam may scan through the wafer (e.g., in a line-by-line or zig-zag manner), and the detector may receive exiting charged particles coming from a region under charged particle-beam projection (referred to as a “beam spot”). The detector may receive and record exiting charged particles from each beam spot one at a time and join the information recorded for all the beam spots to generate the inspection image. Some SCPMs use a single charged-particle beam (referred to as a “single-beam SCPM,” such as a single-beam SEM) to take a single “picture” to generate the inspection image, while some SCPMs use multiple charged- particle beams (referred to as a “multi-beam SCPM,” such as a multi-beam SEM) to take multiple “sub-pictures” of the wafer in parallel and stitch them together to generate the inspection image. By using multiple charged-particle beams, the SCPM may provide more charged-particle beams onto the structures for obtaining these multiple “sub-pictures,” resulting in more charged particles exiting from the structures. Accordingly, the detector may receive more exiting charged particles simultaneously and generate inspection images of the structures of the wafer with higher efficiency and faster speed.

[0028] As the physical sizes of IC components continue to shrink, accuracy and yield in defect detection become more important. Metrology tools can be used to determine whether the ICs are correctly manufactured by identifying a number of defects on each wafer, including at different levels of detail, such as a pattern level, an image (field of view) level, a die level, a care area level, or a wafer level.

[0029] Embodiments of the present disclosure can provide a method for training a machine learning model to predict images at multiple locations on a wafer which may provide data to assist in determining an edge placement error (EPE). EPE is typically measured by combining SEM data from dual layer structures (e.g., a top layer and a bottom layer) and their relevant overlay measurements. But this approach ignores local EPE distribution that results from various process steps or imaging fingerprints, such that the EPE may be over-estimated or under-estimated. It would be beneficial to take more SEM measurements on a wafer, but this can be a time-consuming process. This process may be made faster by training a machine learning model. A plurality of markings on a wafer can be read by an alignment sensor, and measurement data on those markings may be obtained from the alignment sensor. These markings are different from alignment marks on the wafer because they are not used to align different layers of a wafer. For example, these markings may be asymmetric markings (contrasted with alignment markings, which are symmetric markings). In a multi-layer wafer, the bottom layer includes the asymmetric markings and predictions (either images or key performance indicators) may be made for the bottom layer because the markings are present on the bottom layer.

[0030] Images (for example, SEM images) of the wafer near each of the plurality of markings are obtained. An image (for example, an SEM image) of a portion of the wafer, such as a middle portion of the wafer, is obtained. An image of another portion of the wafer may also be used. A machine learning model (for example, a CNN) is trained using the plurality of markings and the image of theportion of the wafer to predict the images near each of the plurality of markings. The predicted images near each of the plurality of markings may provide data for determining the EPE of the wafer.

[0031] Fig. 1 illustrates an exemplary charged-particle beam inspection (CPBI) system 100 consistent with some embodiments of the present disclosure. CPBI system 100 may be used for imaging. For example, CPBI system 100 may use an electron beam for imaging. As shown in Fig. 1, CPBI system 100 includes a main chamber 101, a load / lock chamber 102, a beam tool 104, and an equipment front end module (EFEM) 106. Beam tool 104 is located within main chamber 101. EFEM 106 includes a first loading port 106a and a second loading port 106b. EFEM 106 may include additional loading port(s). First loading port 106a and second loading port 106b receive wafer front opening unified pods (FOUPs) that contain wafers (e.g., semiconductor wafers or wafers made of other material(s)) or samples to be inspected (the terms “wafers” and “samples” may be used interchangeably). A “lot” is a plurality of wafers that may be loaded for processing as a batch.

[0032] One or more robotic arms (not shown) in EFEM 106 may transport the wafers to load / lock chamber 102. Load / lock chamber 102 is connected to a load / lock vacuum pump system (not shown) which removes gas molecules in load / lock chamber 102 to reach a first pressure below the atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) may transport the wafer from load / lock chamber 102 to main chamber 101. Main chamber 101 is connected to a main chamber vacuum pump system (not shown) which removes gas molecules in main chamber 101 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer is subject to inspection by beam tool 104. Beam tool 104 may be a single-beam system or a multi-beam system.

[0033] A controller 109 is electronically connected to beam tool 104. Controller 109 may be a computer that may execute various controls of CPBI system 100. While controller 109 is shown in Fig. 1 as being outside of the structure that includes main chamber 101, load / lock chamber 102, and EFEM 106, it is appreciated that controller 109 may be a part of the structure.

[0034] In some embodiments, controller 109 may include one or more processors (not shown). A processor may be a generic or specific electronic device capable of manipulating or processing information. For example, the processor may include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PL A), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field- Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), or any type of circuit capable of data processing. The processor may also be a virtual processor that includes one or more processors distributed across multiple machines or devices coupled via a network.

[0035] In some embodiments, controller 109 may further include one or more memories (not shown). A memory may be a generic or specific electronic device capable of storing codes and data accessible by the processor (e.g., via a bus). For example, the memory may include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or any type of storage device. The codes may include an operating system (OS) and one or more application programs (or “apps”) for specific tasks. The memory may also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.

[0036] Fig. 2 illustrates an example imaging system 200 consistent with some embodiments of the present disclosure. Beam tool 104 of Fig. 2 may be configured for use in CPBI system 100. Beam tool 104 may be a single beam apparatus or a multi-beam apparatus. As shown in Fig. 2, beam tool 104 includes a motorized sample stage 201, and a wafer holder 202 supported by motorized sample stage 201 to hold a wafer 203 to be inspected. Beam tool 104 further includes an objective lens assembly 204, a charged-particle detector 206 (which includes charged-particle sensor surfaces 206a and 206b), an objective aperture 208, a condenser lens 210, a beam limit aperture 212, a gun aperture 214, an anode 216, and a cathode 218. Objective lens assembly 204, in some embodiments, may include a modified swing objective retarding immersion lens (SORIL), which includes a pole piece 204a, a control electrode 204b, a deflector 204c, and an exciting coil 204d. Beam tool 104 may additionally include an Energy Dispersive X-ray Spectrometer (EDS) detector (not shown) to characterize the materials on wafer 203.

[0037] A primary charged-particle beam 220 (or simply “primary beam 220”), such as an electron beam, is emitted from cathode 218 by applying an acceleration voltage between anode 216 and cathode 218. Primary beam 220 passes through gun aperture 214 and beam limit aperture 212, both of which may determine the size of charged-particle beam entering condenser lens 210, which resides below beam limit aperture 212. Condenser lens 210 focuses primary beam 220 before the beam enters objective aperture 208 to set the size of the charged-particle beam before entering objective lens assembly 204. Deflector 204c deflects primary beam 220 to facilitate beam scanning on the wafer. For example, in a scanning process, deflector 204c may be controlled to deflect primary beam 220 sequentially onto different locations of top surface of wafer 203 at different time points, to provide data for image reconstruction for different parts of wafer 203. Moreover, deflector 204c may also be controlled to deflect primary beam 220 onto different sides of wafer 203 at a particular location, at different time points, to provide data for stereo image reconstruction of the wafer structure at that location. Further, in some embodiments, anode 216 and cathode 218 may generate multiple primary beams 220, and beam tool 104 may include a plurality of deflectors 204c to project the multiple primary beams 220 to different parts / sides of the wafer at the same time, to provide data for image reconstruction for different parts of wafer 203.

[0038] Exciting coil 204d and pole piece 204a generate a magnetic field that begins at one end of pole piece 204a and terminates at the other end of pole piece 204a. A part of wafer 203 being scanned by primary beam 220 may be immersed in the magnetic field and may be electrically charged, which, in turn, creates an electric field. The electric field reduces the energy of impinging primary beam 220 near the surface of wafer 203 before it collides with wafer 203. Control electrode 204b, being electrically isolated from pole piece 204a, controls an electric field on wafer 203 to prevent microarching of wafer 203 and to ensure proper beam focus.

[0039] A secondary charged-particle beam 222 (or “secondary beam 222”), such as secondary electron beams, may be emitted from the part of wafer 203 upon receiving primary beam 220. Secondary beam 222 may form a beam spot on sensor surfaces 206a and 206b of charged-particle detector 206. Charged-particle detector 206 may generate a signal (e.g., a voltage, a current, or the like) that represents an intensity of the beam spot and provide the signal to an image processing system 250. The intensity of secondary beam 222, and the resultant beam spot, may vary according to the external or internal structure of wafer 203. Moreover, as discussed above, primary beam 220 may be projected onto different locations of the top surface of the wafer or different sides of the wafer at a particular location, to generate secondary beams 222 (and the resultant beam spot) of different intensities. Therefore, by mapping the intensities of the beam spots with the locations of wafer 203, the processing system may reconstruct an image that reflects the internal or surface structures of wafer 203.

[0040] Imaging system 200 may be used for inspecting a wafer 203 on motorized sample stage 201 and includes beam tool 104, as discussed above. Imaging system 200 may also include an image processing system 250 that includes an image acquirer 260, storage 270, and controller 109. Image acquirer 260 may include one or more processors. For example, image acquirer 260 may include a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, and the like, or a combination thereof. Image acquirer 260 may connect with a detector 206 of beam tool 104 through a medium such as an electrical conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, or a combination thereof. Image acquirer 260 may receive a signal from detector 206 and may construct an image. Image acquirer 260 may thus acquire images of wafer 203. Image acquirer 260 may also perform various post-processing functions, such as generating contours, superimposing indicators on an acquired image, and the like. Image acquirer 260 may perform adjustments of brightness and contrast, or the like of acquired images. Storage 270 may be a storage medium such as a hard disk, cloud storage, random access memory (RAM), other types of computer readable memory, and the like. Storage 270 may be coupled with image acquirer 260 and may be used for saving scanned raw image data as original images, post-processed images, or other images assisting of the processing. Image acquirer 260 and storage 270 may be connected to controller 109. In some embodiments, image acquirer 260, storage 270, and controller 109 may be integrated together as one control unit.

[0041] In some embodiments, image acquirer 260 may acquire one or more images of a sample based on an imaging signal received from detector 206. An imaging signal may correspond to a scanning operation for conducting charged particle imaging. An acquired image may be a single image including a plurality of imaging areas. The single image may be stored in storage 270. The single image may be an original image that may be divided into a plurality of regions. Each of the regions may include one imaging area containing a feature of wafer 203.

[0042] Consistent with some embodiments of this disclosure, a computer-implemented method of training a machine learning model for defect detection may include obtaining training data that includes an inspection image of a fabricated integrated circuit (IC) and design layout data of the IC. The obtaining operation, as used herein, may refer to accepting, taking in, admitting, gaining, acquiring, retrieving, receiving, reading, accessing, collecting, or any operation for inputting data. An inspection image, as used herein, may refer to an image generated as a result of an inspection process performed by a charged-particle inspection apparatus (e.g., system 100 of Fig. 1 or system 200 of Fig. 2). For example, an inspection image may be an SCPM image generated by image processing system 250 in Fig. 2. A fabricated IC in this disclosure may refer to an IC manufactured on a sample (e.g., a wafer) in a semiconductor manufacturing process (e.g., a photolithography process). For example, the fabricated IC may be manufactured in a die of the sample. Design layout data of an IC, as used herein, may refer to data representing a designed layout of the IC. In some embodiments, the design layout data may include a design layout file in a GDS format (e.g., a GDS layout file). The design layout file may be visualized (also referred to as “rendered”) to be a 2D image (referred to as a “rendered image” herein) that presents the layout of the IC. The rendered image may include various geometric features (e.g., vertices, edges, corners, polygons, holes, bridges, vias, or the like) of the IC.

[0043] In some embodiments, the design layout data of the IC may include an image (e.g., the rendered image) rendered based on GDS clip data of the IC. GDS clip data of an IC, as used herein, may refer to design layout data of the IC that is to be fabricated in a die, which is of the GDS format. In some embodiments, the design layout data of the IC may include only a design layout file (e.g., the GDS clip data) of the IC. In some embodiments, the design layout data of the IC may include only the rendered image of the IC. In some embodiments, the design layout data of the IC may include only a golden image of the IC. In some embodiments, the design layout data may include any combination of the design layout file, the golden image, and the rendered image of the IC.

[0044] Fig. 3 illustrates a schematic diagram of an example multi-beam beam tool 104 (also referred to herein as apparatus 104) and an image processing system 390 that may be configured for use in EBI system 100 (Fig. 1), consistent with embodiments of the present disclosure.

[0045] Beam tool 104 comprises a charged-particle source 302, a gun aperture 304, a condenser lens 306, a primary charged-particle beam 310 emitted from charged-particle source 302, a source conversion unit 312, a plurality of beamlets 314, 316, and 318 of primary charged-particle beam 310, a primary projection optical system 320, a motorized wafer stage 380, a wafer holder 382, multiplesecondary charged-particle beams 336, 338, and 340, a secondary optical system 342, and a charged- particle detection device 344. Primary projection optical system 320 can comprise a beam separator 322, a deflection scanning unit 326, and an objective lens 328. Charged-particle detection device 344 can comprise detection sub-regions 346, 348, and 350.

[0046] Charged-particle source 302, gun aperture 304, condenser lens 306, source conversion unit 312, beam separator 322, deflection scanning unit 326, and objective lens 328 can be aligned with a primary optical axis 360 of apparatus 104. Secondary optical system 342 and charged-particle detection device 344 can be aligned with a secondary optical axis 352 of apparatus 104.

[0047] Charged-particle source 302 can emit one or more charged particles, such as electrons, protons, ions, muons, or any other particle carrying electric charges. In some embodiments, charged- particle source 302 may be an electron source. For example, charged-particle source 302 may include a cathode, an extractor, or an anode, wherein primary electrons can be emitted from the cathode and extracted or accelerated to form primary charged-particle beam 310 (in this case, a primary electron beam) with a crossover (virtual or real) 308. For ease of explanation without causing ambiguity, electrons are used as examples in some of the descriptions herein. However, it should be noted that any charged particle may be used in any embodiment of this disclosure, not limited to electrons. Primary charged-particle beam 310 can be visualized as being emitted from crossover 308. Gun aperture 304 can block off peripheral charged particles of primary charged-particle beam 310 to reduce Coulomb effect. The Coulomb effect may cause an increase in size of probe spots.

[0048] Source conversion unit 312 can comprise an array of image-forming elements and an array of beam-limit apertures. The array of image-forming elements can comprise an array of micro-deflectors or micro-lenses. The array of image-forming elements can form a plurality of parallel images (virtual or real) of crossover 308 with a plurality of beamlets 314, 316, and 318 of primary charged-particle beam 310. The array of beam-limit apertures can limit the plurality of beamlets 314, 316, and 318. While three beamlets 314, 316, and 318 are shown in Fig. 3, embodiments of the present disclosure are not so limited. For example, in some embodiments, the apparatus 104 may be configured to generate a first number of beamlets. In some embodiments, the first number of beamlets may be in a range from 1 to 1000. In some embodiments, the first number of beamlets may be in a range from 200-500. In some embodiments, an apparatus 104 may generate 400 beamlets.

[0049] Condenser lens 306 can focus primary charged-particle beam 310. The electric currents of beamlets 314, 316, and 318 downstream of source conversion unit 312 can be varied by adjusting the focusing power of condenser lens 306 or by changing the radial sizes of the corresponding beam-limit apertures within the array of beam-limit apertures. Objective lens 328 can focus beamlets 314, 316, and 318 onto a wafer 330 for imaging, and can form a plurality of probe spots 370, 372, and 374 on a surface of wafer 330.

[0050] Beam separator 322 can be a beam separator of Wien filter type generating an electrostatic dipole field and a magnetic dipole field. In some embodiments, if they are applied, the force exertedby the electrostatic dipole field on a charged particle (e.g., an electron) of beamlets 314, 316, and 318 can be substantially equal in magnitude and opposite in a direction to the force exerted on the charged particle by magnetic dipole field. Beamlets 314, 316, and 318 can, therefore, pass straight through beam separator 322 with zero deflection angle. However, the total dispersion of beamlets 314, 316, and 318 generated by beam separator 322 can also be non-zero. Beam separator 322 can separate secondary charged-particle beams 336, 338, and 340 from beamlets 314, 316, and 318 and direct secondary charged-particle beams 336, 338, and 340 towards secondary optical system 342.

[0051] Deflection scanning unit 326 can deflect beamlets 314, 316, and 318 to scan probe spots 370, 372, and 374 over a surface area of wafer 330. In response to the incidence of beamlets 314, 316, and 318 at probe spots 370, 372, and 374, secondary charged-particle beams 336, 338, and 340 may be emitted from wafer 330. Secondary charged-particle beams 336, 338, and 340 may comprise charged particles (e.g., electrons) with a distribution of energies. For example, secondary charged-particle beams 336, 338, and 340 may be secondary electron beams including secondary electrons (energies < 50 eV) and backscattered electons (energies between 50 eV and landing energies of beamlets 314, 316, and 318). Secondary optical system 342 can focus secondary charged-particle beams 336, 338, and 340 onto detection sub-regions 346, 348, and 350 of charged-particle detection device 344. Detection sub-regions 346, 348, and 350 may be configured to detect corresponding secondary charged-particle beams 336, 338, and 340 and generate corresponding signals (e.g., voltage, current, or the like) used to reconstruct an inspection image of structures on or underneath the surface area of wafer 330.

[0052] The generated signals may represent intensities of secondary charged-particle beams 336, 338, and 340 and may be provided to image processing system 390 that is in communication with charged-particle detection device 344, primary projection optical system 320, and motorized wafer stage 380. The movement speed of motorized wafer stage 380 may be synchronized and coordinated with the beam deflections controlled by deflection scanning unit 326, such that the movement of the scan probe spots (e.g., scan probe spots 370, 372, and 374) may orderly cover regions of interest on the wafer 330. The parameters of such synchronization and coordination may be adjusted to adapt to different materials of wafer 330. For example, different materials of wafer 330 may have different resistance-capacitance characteristics that may cause different signal sensitivities to the movement of the scan probe spots.

[0053] The intensity of secondary charged-particle beams 336, 338, and 340 may vary according to the external or internal structure of wafer 330, and thus may indicate whether wafer 330 includes defects. Moreover, as discussed above, beamlets 314, 316, and 318 may be projected onto different locations of the top surface of wafer 330, or different sides of local structures of wafer 330, to generate secondary charged-particle beams 336, 338, and 340 that may have different intensities. Therefore, by mapping the intensity of secondary charged-particle beams 336, 338, and 340 with theareas of wafer 330, image processing system 390 may reconstruct an image that reflects the characteristics of internal or external structures of wafer 330.

[0054] In some embodiments, image processing system 390 may include an image acquirer 392, a storage 394, and a controller 396. Image acquirer 392 may comprise one or more processors. For example, image acquirer 392 may comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, or the like, or a combination thereof. Image acquirer 392 may be communicatively coupled to charged-particle detection device 344 of beam tool 104 through a medium such as an electric conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, or a combination thereof. In some embodiments, image acquirer 392 may receive a signal from charged-particle detection device 344 and may construct an image. Image acquirer 392 may thus acquire inspection images of wafer 330. Image acquirer 392 may also perform various post-processing functions, such as generating contours, superimposing indicators on an acquired image, or the like. Image acquirer 392 may be configured to perform adjustments of brightness and contrast of acquired images. In some embodiments, storage 394 may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), other types of computer-readable memory, or the like. Storage 394 may be coupled with image acquirer 392 and may be used for saving scanned raw image data as original images, and postprocessed images. Image acquirer 392 and storage 394 may be connected to controller 396. In some embodiments, image acquirer 392, storage 394, and controller 396 may be integrated together as one control unit.

[0055] In some embodiments, image acquirer 392 may acquire one or more inspection images of a wafer based on an imaging signal received from charged-particle detection device 344. An imaging signal may correspond to a scanning operation for conducting charged particle imaging. An acquired image may be a single image comprising a plurality of imaging areas. The single image may be stored in storage 394. The single image may be an original image that may be divided into a plurality of regions. Each of the regions may comprise one imaging area containing a feature of wafer 330. The acquired images may comprise multiple images of a single imaging area of wafer 330 sampled multiple times over a time sequence. The multiple images may be stored in storage 394. In some embodiments, image processing system 390 may be configured to perform image processing steps with the multiple images of the same location of wafer 330.

[0056] In some embodiments, image processing system 390 may include measurement circuits (e.g., analog-to-digital converters) to obtain a distribution of the detected secondary charged particles (e.g., secondary electrons). The charged-particle distribution data collected during a detection time window, in combination with corresponding scan path data of beamlets 314, 316, and 318 incident on the wafer surface, can be used to reconstruct images of the wafer structures under inspection. The reconstructed images can be used to reveal various features of the internal or external structures of wafer 330, and thereby can be used to reveal any defects that may exist in the wafer.

[0057] In some embodiments, the charged particles may be electrons. When electrons of primary charged-particle beam 310 are projected onto a surface of wafer 330 (e.g., probe spots 370, 372, and 374), the electrons of primary charged-particle beam 310 may penetrate the surface of wafer 330 for a certain depth, interacting with particles of wafer 330. Some electrons of primary charged-particle beam 310 may elastically interact with (e.g., in the form of elastic scattering or collision) the materials of wafer 330 and may be reflected or recoiled out of the surface of wafer 330. An elastic interaction conserves the total kinetic energies of the bodies (e.g., electrons of primary charged-particle beam 310) of the interaction, in which the kinetic energy of the interacting bodies does not convert to other forms of energy (e.g., heat, electromagnetic energy, or the like). Such reflected electrons generated from elastic interaction may be referred to as backscattered electrons (BSEs). Some electrons of primary charged-particle beam 310 may inelastically interact with (e.g., in the form of inelastic scattering or collision) the materials of wafer 330. An inelastic interaction does not conserve the total kinetic energies of the bodies of the interaction, in which some or all of the kinetic energy of the interacting bodies convert to other forms of energy. For example, through the inelastic interaction, the kinetic energy of some electrons of primary charged-particle beam 310 may cause electron excitation and transition of atoms of the materials. Such inelastic interaction may also generate electrons exiting the surface of wafer 330, which may be referred to as secondary electrons (SEs). Yield or emission rates of BSEs and SEs depend on, e.g., the material under inspection and the landing energy of the electrons of primary charged-particle beam 310 landing on the surface of the material, among others. The energy of the electrons of primary charged-particle beam 310 may be imparted in part by its acceleration voltage (e.g., the acceleration voltage between the anode and cathode of charged-particle source 302 in Fig. 3). The quantity of BSEs and SEs may be more or fewer (or even the same) than the injected electrons of primary charged-particle beam 310.

[0058] Fig. 4 is a block diagram of an example server 400, consistent with some embodiments of the disclosure. As shown in Fig. 4, server 400 can include processor 402. When processor 402 executes instructions described herein, server 400 can become a specialized machine. Processor 402 can be any type of circuitry capable of manipulating or processing information. For example, processor 402 can include any combination of any number of a central processing unit (“CPU”), a graphics processing unit (“GPU”), a neural processing unit (“NPU”), a microcontroller unit (“MCU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), or the like. In some embodiments, processor 402 can also be a set of processors grouped as a single logical component. For example, as shown in Fig. 4, processor 402 can include multiple processors, including processor 402a, processor 402b, and processor 402n.

[0059] Server 400 can also include memory 404 configured to store data (e.g., a set of instructions, computer codes, intermediate data, or the like). For example, as shown in Fig. 4, the stored data can include program instructions and data for processing. Processor 402 can access the program instructions and data for processing (e.g., via bus 410), and execute the program instructions to perform an operation or manipulation on the data for processing. Memory 404 can include a highspeed random-access storage device or a non-volatile storage device. In some embodiments, memory 404 can include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or the like. Memory 404 can also be a group of memories (not shown in Fig. 4) grouped as a single logical component.

[0060] Bus 410 can be a communication device that transfers data between components inside server 400, such as an internal bus (e.g., a CPU-memory bus), an external bus (e.g., a universal serial bus port, a peripheral component interconnect express port), or the like.

[0061] For ease of explanation without causing ambiguity, processor 402 and other data processing circuits are collectively referred to as a “data processing circuit” in this disclosure. The data processing circuit can be implemented entirely as hardware, or as a combination of software, hardware, or firmware. In addition, the data processing circuit can be a single independent module or can be combined entirely or partially into any other component of server 400.

[0062] Server 400 can further include network interface 406 to provide wired or wireless communication with a network (e.g., the Internet, an intranet, a local area network, a mobile communications network, or the like). In some embodiments, network interface 406 can include any combination of any number of a network interface controller (NIC), a radio frequency (RF) module, a transponder, a transceiver, a modem, a router, a gateway, a wired network adapter, a wireless network adapter, a Bluetooth adapter, an infrared adapter, a near-field communication (“NFC”) adapter, a cellular network chip, or the like.

[0063] In some embodiments, optionally, server 400 can further include peripheral interface 408 to provide a connection to one or more peripheral devices. As shown in Fig. 4, the peripheral device can include, but is not limited to, a cursor control device (e.g., a mouse, a touchpad, or a touchscreen), a keyboard, a display (e.g., a cathode-ray tube display, a liquid crystal display, or a light-emitting diode display), a video input device (e.g., a camera or an input interface coupled to a video archive), or the like.

[0064] Consistent with some embodiments of this disclosure, the computer-implemented method of obtaining an edge placement error measurement may also include training a machine learning model using the obtained training data. In some embodiments, the machine learning model may be trained by a computer hardware system. In some embodiments, as described elsewhere in this disclosure, the training data may include previously obtained images of the bottom layer or may include simulated images of the bottom layer.

[0065] In some embodiments, machine learning may be employed in the generation of inspection images, reference images, or other images associated with apparatus 100 or apparatus 200. For example, in some embodiments, a machine learning system may be operated in association with, e.g., controller 109, image processing system 250, image acquirer 260, storage 270, image processing system 390, image acquirer 392, or storage 394 of Figs. 1-3. In some embodiments, machine learning may be employed to predict images on a wafer, e.g., method 800 of Fig. 8, method 900 of Fig. 9, or method 1000 of Fig. 10. In some embodiments, a machine learning system may include a discriminative model. In some embodiments, a machine learning system may include a generative model. For example, learning can feature two types of mechanisms: discriminative learning that may be used to create classification and detection algorithms, and generative learning that may be used to actually create models that, in the extreme, can render images. For example, as described further below, a generative model may be configured for generating an image from a design clip that resembles a corresponding location on a wafer in an SCPM image. This may be performed by 1) training the generative model with design clips and the associated actual SCPM images from those locations on the wafer; and 2) using the model in inference mode to feed the model design clips in locations for which simulated SCPM images are desired. Such simulated images can be used as reference images in, e.g., die-to-database inspection.

[0066] If the model(s) include one or more discriminative models, the discriminative model(s) may have any suitable architecture and / or configuration known in the art. Discriminative models, also called conditional models, are a class of models used in machine learning for modeling the dependence of an unobserved variable “y” on an observed variable “x.” Within a probabilistic framework, this may be done by modeling a conditional probability distribution P(ylx), which can be used for predicting y based on x. Discriminative models, as opposed to generative models, may not allow one to generate samples from the joint distribution of x and y. However, for tasks such as classification and regression that do not require the joint distribution, discriminative models may yield superior performance. On the other hand, generative models are typically more flexible than discriminative models in expressing dependencies in complex learning tasks. In addition, most discriminative models are inherently supervised and cannot easily be extended to unsupervised learning. Application specific details ultimately dictate the suitability of selecting a discriminative versus generative model.

[0067] A generative model can be generally defined as a model that is probabilistic in nature. In other words, a “generative” model is not one that performs forward simulation or rule -based approaches and, as such, it may not be necessary to model the physics of the processes involved in generating an actual image or output (for which a simulated image or output is being generated). Instead, the generative model can be learned (in that its parameters can be learned) based on a suitable training set of data. Such generative models may have a number of advantages for the embodiments described herein. In addition, the generative model may be configured to have a deep learningarchitecture in that the generative model may include multiple layers, which may perform a number of algorithms or transformations. The number of layers included in the generative model may depend on the particular use case. For practical purposes, a suitable range of layers is from two layers to a few tens of layers.

[0068] Deep learning is a type of machine learning. Machine learning can be generally defined as a type of artificial intelligence (Al) that provides computers with the ability to learn without being explicitly programmed. Machine learning focuses on the development of computer programs that can teach themselves to grow and change when exposed to new data. Machine learning explores the study and construction of algorithms that can learn from and make predictions on data — such algorithms overcome following strictly static program instructions by making data driven predictions or decisions, through building a model from sample inputs.

[0069] The machine learning described herein may be further performed as described in “Introduction to Statistical Machine Learning,” by Sugiyama, Morgan Kaufmann, 2016, 534 pages; “Discriminative, Generative, and Imitative Learning,” by Jebara, MIT Thesis, 2002, 212 pages; and “Principles of Data Mining (Adaptive Computation and Machine Learning)” by Hand et al., MIT Press, 2001, 578 pages; which are incorporated by reference as if fully set forth herein. The embodiments described herein may be further configured as described in these references.

[0070] In some embodiments, a machine learning system may comprise a neural network. For example, a model may be a deep neural network with a set of weights that model the world according to the data that it has been fed to train it. Neural networks can be generally defined as a computational approach which is based on a relatively large collection of neural units loosely modeling the way a biological brain solves problems with relatively large clusters of biological neurons connected by axons. Each neural unit is connected with many others, and links can be enforcing or inhibitory in their effect on the activation state of connected neural units. These systems are self-learning and trained rather than explicitly programmed and excel in areas where the solution or feature detection is difficult to express in a traditional computer program.

[0071] Neural networks typically consist of multiple layers (e.g., layers 520, 530, and 540 of Fig. 5), and the signal path traverses from front to back. The goal of the neural network is to solve problems in the same way that the human brain would, although several neural networks are much more abstract. Modern neural network projects typically work with a few thousand to a few million neural units and millions of connections. The neural network may have any suitable architecture and / or configuration known in the art.

[0072] In some embodiments, a model may comprise a convolutional and deconvolution neural network. For example, the embodiments described herein can take advantage of learning concepts such as a convolution and deconvolution neural network to solve the normally intractable representation conversion problem (e.g., rendering). The model may have any convolution and deconvolution neural network configuration or architecture known in the art.

[0073] A neural network, as used herein, may refer to a computing model for analyzing underlying relationships in a set of input data by way of mimicking human brains. Similar to a biological neural network, the neural network may include a set of connected units or nodes (referred to as “neurons”), structured as different layers, where each connection (also referred to as an “edge”) may obtain and send a signal between neurons of neighboring layers in a way similar to a synapse in a biological brain. The signal may be any type of data (e.g., a real number). Each neuron may obtain one or more signals as an input and output another signal by applying a non-linear function to the inputted signals. Neurons and edges may typically be weighted by corresponding weights to represent the knowledge the neural network has acquired. During a training process (similar to a learning process of a biological brain), the weights may be adjusted (e.g., by increasing or decreasing their values) to change the strengths of the signals between the neurons to improve the performance accuracy of the neural network. Neurons may apply a thresholding function (referred to as an “activation function”) to its output values of the non-linear function such that a signal is outputted only when an aggregated value (e.g., a weighted sum) of the output values of the non-linear function exceeds a threshold determined by the thresholding function. Different layers of neurons may transform their input signals in different manners (e.g., by applying different non-linear functions or activation functions). The output of the last layer (referred to as an “output layer”) may output the analysis result of the neural network, such as, for example, a categorization of the set of input data (e.g., as in image recognition cases), a numerical result, or any type of output data for obtaining an analytical result from the input data.

[0074] Training of the neural network, as used herein, may refer to a process of improving the accuracy of the output of the neural network. Typically, the training may be categorized into three types: supervised training, unsupervised training, and reinforcement training. In the supervised training, a set of target output data (also referred to as “labels” or “ground truth”) may be generated based on a set of input data using a method other than the neural network. The neural network may then be fed with the set of input data to generate a set of output data that is typically different from the target output data. Based on the difference between the output data and the target output data, the weights of the neural network may be adjusted in accordance with a rule. If such adjustments are successful, the neural network may generate another set of output data more similar to the target output data in a next iteration using the same input data. If such adjustments are not successful, the weights of the neural network may be adjusted again. After a sufficient number of iterations, the training process may be terminated in accordance with one or more predetermined criteria (e.g., the difference between the final output data and the target output data is below a predetermined threshold, or the number of iterations reaches a predetermined threshold). The trained neural network may be applied to analyze other input data.

[0075] In the unsupervised training, the neural network is trained without any external gauge (e.g., labels) to identify patterns in the input data rather than generating labels for them. Typically, theneural network may analyze shared attributes (e.g., similarities and differences) and relationships among the elements of the input data in accordance with one or more predetermined rules or algorithms (e.g., principal component analysis, clustering, anomaly detection, or latent variable identification). The trained neural network may extrapolate the identified relationships to other input data.

[0076] In the reinforcement learning, the neural network is trained without any external gauge (e.g., labels) in a trial-and-error manner to maximize benefits in decision making. The input data sets of the neural network may be different in the reinforcement training. For example, a reward value or a penalty value may be determined for the output of the neural network in accordance with one or more rules during training, and the weights of the neural network may be adjusted to maximize the reward values (or to minimize the penalty values). The trained neural network may apply its learned decisionmaking knowledge to other input data.

[0077] During the training of a neural network, a loss function (or referred to as a “cost function”) may be used to evaluate the output data. The loss function, as used herein, may map output data of a machine learning model (e.g., the neural network) onto a real number (referred to as a “loss” or a “cost”) that intuitively represents a loss or an error (e.g., representing a difference between the output data and target output data) associated with the output data. The training of the neural network may seek to maximize or minimize the loss function (e.g., by pushing the loss towards a local maximum or a local minimum in a loss curve). For example, one or more parameters of the neural network may be adjusted or updated purporting to maximize or minimize the loss function. After adjusting or updating the one or more parameters, the neural network may obtain new input data in a next iteration of its training. When the loss function is maximized or minimized, the training of the neural network may be terminated.

[0078] By way of example, Fig. 5 is a schematic diagram illustrating an example neural network 500, consistent with some embodiments of the present disclosure. As depicted in Fig. 5, neural network 500 may include an input layer 520 that receives inputs, including input 510-1, . . ., input 510-m (m being an integer). For example, an input of neural network 500 may include any structure or unstructured data (e.g., an image). In some embodiments, neural network 500 may obtain a plurality of inputs simultaneously. For example, in Fig. 5, neural network 500 may obtain m inputs simultaneously. In some embodiments, input layer 520 may obtain m inputs in succession such that input layer 520 receives input 510-1 in a first cycle (e.g., in a first inference) and pushes data from input 510-1 to a hidden layer (e.g., hidden layer 530-1), then receives a second input in a second cycle (e.g., in a second inference) and pushes data from input the second input to the hidden layer, and so on. Input layer 520 may obtain any number of inputs in the simultaneous manner, the successive manner, or any manner of grouping the inputs.

[0079] Input layer 520 may include one or more nodes, including node 520-1, node 520-2, . . ., node 520-a (a being an integer). A node (also referred to as a “machine perceptron” or a “neuron”) maymodel the functioning of a biological neuron. Each node may apply an activation function to received inputs (e.g., one or more of input 510-1, . . input 510-m). An activation function may include a Heaviside step function, a Gaussian function, a multiquadratic function, an inverse multiquadratic function, a sigmoidal function, a rectified linear unit (ReLU) function (e.g., a ReLU6 function or a Leaky ReLU function), a hyperbolic tangent (“tanh”) function, or any non-linear function. The output of the activation function may be weighted by a weight associated with the node. A weight may include a positive value between 0 and 1 , or any numerical value that may scale outputs of some nodes in a layer more or less than outputs of other nodes in the same layer.

[0080] As further depicted in Fig. 5, neural network 500 includes multiple hidden layers, including hidden layer 530-1, . . ., hidden layer 530-n (n being an integer). When neural network 500 includes more than one hidden layer, it may be referred to as a “deep neural network” (DNN). Each hidden layer may include one or more nodes. For example, in Fig. 5, hidden layer 530-1 includes node 530-1- 1, node 530-1-2, node 530-1-3, . . ., node 530-1-b (b being an integer), and hidden layer 530-n includes node 530-n-l, node 530-n-2, node 530-n-3, . . ., node 530-n-c (c being an integer). Similar to nodes of input layer 520, nodes of the hidden layers may apply the same or different activation functions to outputs from connected nodes of a previous layer, and weight the outputs from the activation functions by weights associated with the nodes.

[0081] As further depicted in Fig. 5, neural network 500 may include an output layer 540 that finalizes outputs, including output 550-1, output 550-2, . . ., output 550-d (d being an integer). Output layer 540 may include one or more nodes, including node 540-1, node 540-2, . . ., node 540-d. Similar to nodes of input layer 520 and of the hidden layers, nodes of output layer 540 may apply activation functions to outputs from connected nodes of a previous layer and weight the outputs from the activation functions by weights associated with the nodes.

[0082] Although nodes of each hidden layer of neural network 500 are depicted in Fig. 5 to be connected to each node of its previous layer and next layer (referred to as “fully connected”), the layers of neural network 500 may use any connection scheme. For example, one or more layers (e.g., input layer 520, hidden layer 530-1, . . ., hidden layer 530-n, or output layer 540) of neural network 500 may be connected using a convolutional scheme, a sparsely connected scheme, or any connection scheme that uses fewer connections between one layer and a previous layer than the fully connected scheme as depicted in Fig. 5.

[0083] Moreover, although the inputs and outputs of the layers of neural network 500 are depicted as propagating in a forward direction (e.g., being fed from input layer 520 to output layer 540, referred to as a “feedforward network”) in Fig. 5, neural network 500 may additionally or alternatively use backpropagation (e.g., feeding data from output layer 540 towards input layer 520) for other purposes. For example, the backpropagation may be implemented by using long short-term memory nodes (LSTM). Accordingly, although neural network 500 is depicted similar to a convolutional neuralnetwork (CNN), neural network 500 may include a recurrent neural network (RNN) or any other neural network.

[0084] Some embodiments of the present disclosure describe systems and methods for obtaining a relatively low number of images of the wafer and combining the image data with other wafer measurements to predict the image in a different location of the wafer. For example, markings on the wafer may be used with images taken near the markings to train a machine learning model to predict images for other locations on the wafer.

[0085] The markings may be read by an alignment sensor. The alignment sensor may be used to approximate the quality of the printed features (e.g., the local critical dimension uniformity (LCDU) and the critical dimension (CD)). It is noted that while the markings can be read by the alignment sensor, the markings described herein are not used to align different layers of the wafer. For example, the markings may include asymmetric markings. For example, the markings may include a specially designed grating created on the wafer and located alongside each layer’s pattern. For example, the markings may be made up of lines with vertical sides that are perpendicular to the wafer’s surface, with some of the lines being wide features and some of the lines being narrow features. Because of natural manufacturing variations and the asymmetric markings, different colors of light will reflect differently off the features. The markings can be measured at different stages of fabrication and reflects the effect of the process step. Processing may have different effects on the geometry of the markings. For example, the processing may affect the CD and the LCDU, which are components of EPE. The markings may contain enough information relating to EPE that the markings can be used in connection with a few images of the bottom layer to help predict the EPE for other (e.g., non-imaged) locations on the wafer.

[0086] Fig. 6 is a diagram of two example asymmetric markings 640, 660 on a wafer, consistent with some embodiments of the present disclosure. The asymmetric markings 640, 660 are not used to align different layers of the wafer during manufacturing, but may be detected and measured by an alignment sensor. It is noted that the asymmetric markings 640, 660 shown in Fig. 6 are one example of asymmetric markings. Other configurations of asymmetric markings are possible, such as horizontally arranged markings.

[0087] A top-down view 642 of first asymmetric marking 640 shows that the marking has a predetermined spacing. A close-up view 644 of a sub-section of the first asymmetric marking 640 shows a wide vertical feature 646 and several narrow vertical features 648. It is noted that only narrow vertical features 648a, 648b are labeled for clarity and that any number of equally spaced vertical features may be used. A cross section view 650 of the first asymmetric marking 640 shows a base portion 652, the wide vertical feature 646, and the narrow vertical features 648a, 648b.

[0088] A second asymmetric marking 660 as shown in a top-down view 662 looks similar to the first asymmetric marking 640. A close-up view 664 of the second asymmetric marking 660 shows a wide vertical feature 666 and several narrow vertical features 668. It is noted that only narrow verticalfeatures 668a, 668b are labeled for clarity and that any number of equally spaced vertical features may be used. A cross section view 670 of the second asymmetric marking 660 shows a base portion 672, the wide vertical feature 666, and the narrow vertical features 668a, 668b. In some embodiments, the second asymmetric marking 660 may be a mirror image of the first asymmetric marking 640. For example, as shown in Fig. 6, in the first asymmetric marking 640, the wide vertical feature 646 is on the left side whereas in the second asymmetric marking 660, the wide vertical feature 666 is on the right side.

[0089] As shown in Fig. 6, the features 646, 648, 666, and 668 may be measured to obtain data in the x-direction. To obtain data in the y-direction, the features 646, 648, 666, and 668 would need to be rotated by 90 degrees. In some embodiments, other geometries (not shown in Fig. 6) that combine asymmetry and lines that capture both the x-direction and the y-direction may be used.

[0090] Fig. 7A is a top view of a training wafer 700 showing marking measurement locations and image locations, consistent with embodiments of the present disclosure. Marking measurements may be taken by an alignment sensor at various locations on the wafer 700, for example, measurement locations 702a and 702b. It is noted that only measurement locations 702a and 702b are labeled for clarity of illustration. As shown in Fig. 7A, measurements may be taken at N locations on the wafer 700 (shown in Fig. 7A as measurement locations 1-15, N-l, and N). Even though the markings at locations 702a and 702b are not alignment markings, they may be measured by the alignment sensor. It is noted that the measurement locations 702 shown in Fig. 7A are exemplary, are shown for clarity of illustration, and that other locations may be used and a different number of locations may be used. In some embodiments, 50, 100, or more marking measurements may be taken at locations around the wafer 700. In some embodiments, the number of measurements needed may depend on a frequency of EPE fingerprints to be evaluated and may vary between different wafer designs based on a number of locations to be examined.

[0091] Images of the wafer 700 may be taken at image locations 704a and 704b. In some embodiments, the images may include SEM images of the wafer 700 (for example, taken by beam tool 104) at the different image locations 704. In some embodiments, the images may include other image types, such as optical images, x-ray images, soft x-ray images, photon images, ion images, and the like. As shown in Fig. 7A, the image locations 704 are next to the measurement locations 702. In some embodiments, the image locations 704 may be near the measurement locations 702, such that the locations 702 and 704 are not the same location. As used herein, the term “near” may include the locations 702 and 704 being adjacent to each other or separated by a small distance. In some embodiments, the image locations 704 may be on a same layer as the measurement locations 702. For example, the measurements may be taken of the bottom layer and its contribution to the EPE may be determined. For the top layer, dense SEM images may still be needed. In some embodiments, there may be a marking-to-device offset (this may also be referred to as a scribe-to-device offset). The neural network may be trained to learn the offset, and the image locations 704 may be taken inlocations where the marking-to-device offset is a constant value. For example, if EPE is to be inferred in three device locations, then there may be three corresponding asymmetric markings with the same expected marking-to-device offset or one asymmetric marking and a separate trained machine learning model to find the three different marking-to-device offsets.

[0092] An image 706 of a portion of the wafer 700, for example a middle portion of the wafer 700 (shown in Fig. 7A as location 0), may also be taken. The image 706 may be taken at a location at the exact middle of the wafer 700 or at a location near the middle of the wafer 700. In some embodiments, the image 706 may be taken of other portions of the wafer 700. For example, a location used during training the model and testing the model should also be used during inference. There may be small variations of the location from wafer-to-wafer (e.g., on the order of a few tens of nanometers) due to errors in aligning the SEM tool. In some embodiments, a marking measurement 708 (shown in Fig. 7A as location 0) may be taken in the middle of the wafer 700. It is noted that the marking measurement 708 is optional and may provide additional data about the correlation of the marking measurement and the EPE components.

[0093] The marking measurements from measurement locations 702a and 702b, the images from image locations 704a and 704b, and the image 706 of the middle portion of the wafer 700 (and optionally the marking measurement 708) are provided as inputs to train a machine learning model. The trained machine learning model estimates images of the wafer 700 at other locations. Based on the estimated (predicted) images, data may be obtained from the predicted images to provide data for determining the edge placement error. In some embodiments, the trained machine learning model may estimate key performance indicators (KPIs), such as local critical dimension uniformity (LCDU).

[0094] In some embodiments, intrafield measurements and images may be taken of the wafer 700, for example, as shown by enlargement 710 in Fig. 7A. In some embodiments, the intrafield measurements may be in-die (e.g., all measurements are taken within a single die). Intrafield marking measurements may be taken at locations 712a and 712b. It is noted that only measurement locations 712a and 712b are labeled for clarity of illustration. As shown in Fig. 7A, measurements may be taken at multiple locations in a single field (shown in Fig. 7A as measurement locations 15a, 15b, and 15c). It is noted that other locations in a single field may be used and a different number of locations within a single field may be used. In such embodiments, asymmetric markings may be printed on the wafer 700 at the different intrafield locations (e.g., on the scribe lane, the area between different dies on the wafer, because the asymmetric markings are only used for metrology purposes). Intrafield images may be taken at locations near the intrafield measurement locations 712a, 712b, such as image locations 714a, 714b.

[0095] Fig. 7B is a top view of a test wafer 750 showing marking measurement locations and an image location, consistent with embodiments of the present disclosure. Marking measurements may be taken by an alignment sensor at various locations on the wafer 750, for example, measurement locations 752a and 752b. It is noted that only measurement locations 752a and 752b are labeled forclarity of illustration. As shown in Fig. 7B, measurements may be taken at N locations on the wafer 750 (shown in Fig. 7B as measurement locations 1-15, N-l, and N). An image 754 of a portion of the wafer 750, for example a middle portion of the wafer 750, is taken. The image 754 may be taken at a location at the exact middle of the wafer 750 or at a location near the middle of the wafer 750 (shown in Fig. 7B as location 0). In some embodiments, the image 754 may be taken of other portions of the wafer 750. In some embodiments, a marking measurement 756 (shown in Fig. 7B as location 0) may be taken in the middle of the wafer 750. It is noted that the marking measurement 756 is optional and may provide additional data about the correlation of the marking measurement and the EPE components.

[0096] Based on the measurements taken at measurement locations 752 and the image 754 of the portion of the wafer 750 (and optionally the marking measurement 756), the trained machine learning model predicts (e.g., extrapolates) how the images will look at the measurement locations 752.

[0097] In some embodiments, intrafield measurements may be taken of the wafer 750, for example, as shown by enlargement 760 in Fig. 7B. Intrafield marking measurements may be taken at locations 762a and 762b. It is noted that only measurement locations 762a and 762b are labeled for clarity of illustration. As shown in Fig. 7B, measurements may be taken at multiple locations in a single field (shown in Fig. 7B as measurement locations 15a, 15b, and 15c). It is noted that other locations in a single field may be used and a different number of locations within a single field may be used. In such embodiments, asymmetric marks may be printed on the wafer 750 at the different intrafield locations (e.g., on the scribe lane). It is noted that to use the intrafield measurements during testing, the machine learning model needs to be trained on intrafield measurements on the training wafers.

[0098] Fig. 8 is a flowchart of an example method 800 for training a machine learning model to predict images of a wafer, consistent with embodiments of the present disclosure. In some embodiments, the method 800 may be performed by image processing system 250 of Fig. 2 or by the server 400 of Fig. 4.

[0099] At step 802, marking data from multiple locations on the wafer is obtained. For example, the marking data may include marking measurements taken by an alignment sensor from measurement locations 702a and 702b as shown in Fig. 7A. In some embodiments, step 802 may also include obtaining marking measurement 708 (shown in Fig. 7A as location 0).

[0100] At step 804, images of the wafer near the markings are obtained. For example, the images may include images taken by beam tool 104 from image locations 704a and 704b as shown in Fig.7A.

[0101] At step 806, an image of a portion of the wafer, for example a middle portion of the wafer, is obtained. For example, the image of the portion may include image 706 (taken by beam tool 104) as shown in Fig. 7A. It is noted that an image of a different portion of the wafer may be obtained and used in step 806 without affecting the overall operation of the method 800.

[0102] At step 808, a machine learning model is trained using the obtained marking data and the image of the portion of the wafer to predict images of the wafer near the markings. For example, the machine learning model may include the neural network 500 shown in Fig. 5. The parameters of the machine learning model may be adjusted during training such that the machine learning model can generate predicted images of the wafer near the markings that are substantially similar to the obtained images of the wafer near the markings.

[0103] In some embodiments, the machine learning model may be used to predict image data (e.g., SEM image data). In such embodiments, the machine learning model may include an image-to-image translation model such as a CNN or an encoder / decoder. The machine learning model may include an input channel for the alignment data and an image input. For example and referring to Fig. 7A, the machine learning model may be trained to take alignment data from alignment measurement location 702a and image 706 as inputs to predict how the image at image location 704a will look.

[0104] In some embodiments, the machine learning model may be used to predict key performance indicators (KPIs), such as what the local critical dimension uniformity (LCDU) will be in a particular location on the wafer. In such embodiments, the machine learning model may include a regression model (such as a CNN) that maps information from an image to obtain a numerical result.

[0105] After the machine learning model has been trained, the machine learning model may be used to make predictions for the bottom layer. As used herein, the terms “top layer” and “bottom layer” are relative to each other, such that the “top layer” is a layer manufactured on top of the “bottom layer.” To make predictions for the bottom layer, instead of measuring the entire wafer, measurements may be made for a few locations, and then the machine learning model can extrapolate (e.g., make predictions) to the rest of the wafer. By making fewer measurements of the bottom layer, the EPE for the top layer may be determined faster, resulting in faster wafer processing (e.g., faster throughput per inspected wafer). In some embodiments, the approach described herein may result in wafers being processed 20 to 50 times faster than prior approaches that took multiple SEM images of the bottom layer. Images or KPIs for the bottom layer may be predicted because the asymmetric markings are located on the bottom layer.

[0106] The training scheme for the machine learning model is to use the marking data and the images. The machine learning model learns based on the marking data from edge locations of the wafer (not from the middle of the wafer) and an image of the middle of the wafer (or other location of the wafer) to predict how images at different locations of the wafer will look. When the machine learning model is trained in this manner, going to a new location on the wafer or to a new wafer, only the portion of the wafer is measured (e.g., the middle portion of the wafer, to obtain one data point) and based on the marking data, the trained machine learning model can extrapolate to the rest of the wafer how the images will look at different locations.

[0107] For example, with a new wafer, obtaining one measurement in the middle of the wafer (or other single location on the wafer) plus the marking data for the full wafer previously measured maybe used to predict images from various locations on the new wafer. By only obtaining one measurement for the new wafer, time may be saved in determining the EPE for the new wafer.

[0108] In some embodiments, the machine learning model training can be adapted with a few additional measurement points. The training may be adapted because of wafer-to- wafer variations and lot-to-lot variations. For example, on a first wafer, 100 measurements may be taken. Then on a second wafer, five or six measurements may be taken, so training from the first wafer may be partially adopted (a reinforcement learning). For the second wafer and later wafers, the entire wafer does not need to be measured or a fewer number of measurements may be taken relative to the first wafer.

[0109] Fig. 9 is a flowchart of an example method for using a trained machine learning model to predict an image of a new location on a wafer, consistent with embodiments of the present disclosure. In some embodiments, the method 900 may be performed by image processing system 250 of Fig. 2 or by the server 400 of Fig. 4.

[0110] At step 902, marking data is obtained from new locations on the wafer. For example, marking data may be obtained from different portions of the wafer than the portions that were used during training. For example marking measurement locations 752a and 752b as shown in Fig. 7B. In some embodiments, step 902 may also include obtaining marking measurement 756 (shown in Fig. 7B as location 0).

[0111] At step 904, an image of a portion of the wafer, for example a middle portion of the wafer, is obtained. For example, the image of the middle portion may include image 754 as shown in Fig. 7B. In some embodiments, the image obtained in step 904 is part of the test data set and the image obtained in step 806 is part of the training data set.

[0112] At step 906, the marking data from the new locations and the image from the portion of the wafer are provided to the trained machine learning model. For example, the machine learning model may be trained using the method 800.

[0113] At step 908, the machine learning model estimates images of the wafer at the new locations, wherein the new locations correspond to the locations where the alignment data was obtained in step 902.

[0114] Fig. 10 is a flowchart of an example method for using a trained machine learning model to predict an image of a new wafer, consistent with embodiments of the present disclosure. In some embodiments, the method 1000 may be performed by image processing system 250 of Fig. 2 or by the server 400 of Fig. 4.

[0115] At step 1002, marking data is obtained from the test wafer.

[0116] At step 1004, an image of a portion of the new wafer, for example a middle portion of the new wafer, is obtained. For example, the obtained image may be from a similar location on the new wafer as image 754 shown in Fig. 7B.

[0117] At step 1006, the marking data from the test wafer and the image from the portion of the new wafer are provided to the trained machine learning model. For example, the machine learning model may be trained using the method 800.

[0118] At step 1008, the machine learning model estimates images of the new wafer near the marking measurement locations.

[0119] A non-transitory computer readable medium may be provided that stores instructions for a processor of a controller (e.g., controller 109 of FIG. 1) to carry out, among other things, image inspection, image acquisition, stage positioning, beam focusing, electric field adjustment, beam bending, condenser lens adjusting, activating charged particle source, beam deflecting, and methods 800, 900, and 1000. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a Compact Disc Read Only Memory (CD-ROM), any other optical data storage medium, any physical medium with patterns of holes, a Random Access Memory (RAM), a Programmable Read Only Memory (PROM), and Erasable Programmable Read Only Memory (EPROM), a FLASH-EPROM or any other flash memory, Non-Volatile Random Access Memory (NVRAM), a cache, a register, any other memory chip or cartridge, and networked versions of the same.

[0120] The embodiments may further be described using the following clauses:1.A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for training a machine learning model to predict images on a wafer to provide data for determining an edge placement error (EPE) of the wafer, the operations comprising: measuring a plurality of markings on the wafer; obtaining images of the wafer near each of the plurality of markings; obtaining an image of another portion of the wafer; and training a machine learning model using the plurality of markings and the image of the another portion of the wafer to predict the images near each of the plurality of markings, wherein the predicted images near each of the plurality of markings provide data for determining the EPE of the wafer.2. The non-transitory computer readable medium of clause 1 , wherein the plurality of markings include asymmetric markings.3. The non-transitory computer readable medium of clauses 1 or 2, wherein the measuring the plurality of markings includes receiving measurement data from an alignment sensor.4. The non-transitory computer readable medium of any one of clauses 1-3, wherein the images of the wafer near each of the plurality of markings include a scanning electron microscope image.5. The non-transitory computer readable medium of any one of clauses 1-4, wherein the images of the wafer are adjacent to each of the plurality of markings.6. The non-transitory computer readable medium of any one of clauses 1-5, wherein the another portion of the wafer does not include the plurality of markings.7. The non-transitory computer readable medium of any one of clauses 1-6, wherein the image of the another portion of the wafer includes an image of a middle portion of the wafer.8. The non-transitory computer readable medium of any one of clauses 1-7, wherein the image of the another portion of the wafer includes a scanning electron microscope image.9. The non-transitory computer readable medium of any one of clauses 1-8, wherein the machine learning model includes an image to image translation model.10. A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for training a machine learning model to predict key performance indicators (KPIs) on a wafer to provide data for determining an edge placement error (EPE) of the wafer, the operations comprising: measuring a plurality of markings on the wafer; obtaining images of the wafer near each of the plurality of markings; obtaining an image of another portion of the wafer; and training a machine learning model using the plurality of markings and the image of the another portion of the wafer to predict the KPIs near each of the plurality of markings, wherein the KPIs near each of the plurality of markings provide data for determining the EPE of the wafer.11. The non-transitory computer readable medium of clause 10, wherein: the plurality of markings include asymmetric markings; and the measuring the plurality of markings includes receiving measurement data from an alignment sensor.12. The non-transitory computer readable medium of clauses 10 or 11, wherein the KPIs comprise at least one of: a critical dimension or a local critical dimension uniformity.13. A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for using a trained machine learning model to predict images on a wafer to provide data for determining an edge placement error (EPE), the operations comprising: obtaining measurement data from a training wafer, the measurement data corresponding to a plurality of markings on the training wafer; obtaining an image of a portion of a wafer to be examined; and predicting images of the wafer to be examined using the trained machine learning model, the measurement data, and the image of the portion of the wafer to be examined, wherein: each of the predicted images is near one of the plurality of markings; the predicted images provide data for determining the EPE of the wafer to be examined; andthe machine learning model is trained on the training wafer using a plurality of images of the training wafer, each of the plurality of images of the training wafer corresponding to one of the plurality of markings on the training wafer.14. The non-transitory computer readable medium of clause 13, wherein each of the plurality of markings is located near an outer edge of the wafer.15. The non-transitory computer readable medium of clauses 13 or 14, wherein the plurality of markings include asymmetric markings.16. The non-transitory computer readable medium of any one of clauses 13-15, wherein the measurement data is received from an alignment sensor.17. An apparatus for training a machine learning model to predict images on a wafer to provide data for determining an edge placement error (EPE) of the wafer, comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: receiving measurement data from an alignment sensor for a plurality of asymmetric markings on the wafer, wherein each of the plurality of asymmetric markings is located near an outer edge of the wafer; obtaining images of the wafer near each of the plurality of asymmetric markings; obtaining an image of another portion of the wafer, wherein the another portion of the wafer does not include any of the plurality of markings; and training a machine learning model using the plurality of asymmetric markings and the image of the another portion of the wafer to predict the images near each of the plurality of asymmetric markings, wherein the predicted images near each of the plurality of asymmetric markings provide data for determining the EPE of the wafer.18. The apparatus of clause 17, wherein: the images of the wafer near each of the plurality of asymmetric markings include a scanning electron microscope image; and the image of the another portion of the wafer includes a scanning electron microscope image.19. The apparatus of clauses 17 or 18, wherein the images of the wafer are adjacent to each of the plurality of asymmetric markings.20. The apparatus of any one of clauses 17-19, wherein the image of the another portion of the wafer includes an image of a middle portion of the wafer.

[0121] Block diagrams in the figures may illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In some embodiments, a non- transitory computer-readable medium is provided and can include instructions to perform the functions described in connection with any one or more of Figs. 5-10. In this regard, each block in aschematic diagram may represent certain arithmetical or logical operation processing that may be implemented using hardware such as an electronic circuit. Blocks may also represent a module, segment, or portion of code that comprises one or more executable instructions for implementing the specified logical functions. It should be understood that in some alternative implementations, functions indicated in a block may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed or implemented substantially concurrently, or two blocks may sometimes be executed in reverse order, depending upon the functionality involved. Some blocks may also be omitted. It should also be understood that each block of the block diagrams, and combination of the blocks, may be implemented by special purpose hardware -based systems that perform the specified functions or acts, or by combinations of special purpose hardware and computer instructions.

[0122] It will be appreciated that the embodiments of the present disclosure are not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The present disclosure has been described in connection with various embodiments, and other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the technology disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims

CLAIMS1. A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for training a machine learning model to predict images on a wafer to provide data for determining an edge placement error (EPE) of the wafer, the operations comprising: measuring a plurality of markings on the wafer; obtaining images of the wafer near each of the plurality of markings; obtaining an image of another portion of the wafer; and training a machine learning model using the plurality of markings and the image of the another portion of the wafer to predict the images near each of the plurality of markings, wherein the predicted images near each of the plurality of markings provide data for determining the EPE of the wafer.

2. The non-transitory computer readable medium of claim 1 , wherein the plurality of markings include asymmetric markings.

3. The non-transitory computer readable medium of claim 1, wherein the measuring the plurality of markings includes receiving measurement data from an alignment sensor.

4. The non-transitory computer readable medium of claim 1 , wherein the images of the wafer near each of the plurality of markings include a scanning electron microscope image.

5. The non-transitory computer readable medium of claim 1, wherein the images of the wafer are adjacent to each of the plurality of markings.

6. The non-transitory computer readable medium of claim 1 , wherein the another portion of the wafer does not include the plurality of markings.

7. The non-transitory computer readable medium of claim 1, wherein the image of the another portion of the wafer includes an image of a middle portion of the wafer.

8. The non-transitory computer readable medium of claim 1, wherein the image of the another portion of the wafer includes a scanning electron microscope image.

9. A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operationsfor training a machine learning model to predict key performance indicators (KPIs) on a wafer to provide data for determining an edge placement error (EPE) of the wafer, the operations comprising: measuring a plurality of markings on the wafer; obtaining images of the wafer near each of the plurality of markings; obtaining an image of another portion of the wafer; and training a machine learning model using the plurality of markings and the image of the another portion of the wafer to predict the KPIs near each of the plurality of markings, wherein the KPIs near each of the plurality of markings provide data for determining the EPE of the wafer.

10. The non-transitory computer readable medium of claim 9, wherein: the plurality of markings include asymmetric markings; and the measuring the plurality of markings includes receiving measurement data from an alignment sensor.

11. The non-transitory computer readable medium of claim 9, wherein the KPIs comprise at least one of: a critical dimension or a local critical dimension uniformity.

12. An apparatus for training a machine learning model to predict images on a wafer to provide data for determining an edge placement error (EPE) of the wafer, comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: receiving measurement data from an alignment sensor for a plurality of asymmetric markings on the wafer, wherein each of the plurality of asymmetric markings is located near an outer edge of the wafer; obtaining images of the wafer near each of the plurality of asymmetric markings; obtaining an image of another portion of the wafer, wherein the another portion of the wafer does not include any of the plurality of markings; and training a machine learning model using the plurality of asymmetric markings and the image of the another portion of the wafer to predict the images near each of the plurality of asymmetric markings, wherein the predicted images near each of the plurality of asymmetric markings provide data for determining the EPE of the wafer.

13. The apparatus of claim 12, wherein: the images of the wafer near each of the plurality of asymmetric markings include a scanning electron microscope image; and the image of the another portion of the wafer includes a scanning electron microscope image.

14. The apparatus of claim 12, wherein the images of the wafer are adjacent to each of the plurality of asymmetric markings.

15. The apparatus of claim 12, wherein the image of the another portion of the wafer includes an image of a middle portion of the wafer.

Images