Method for preparing a thin layer of single-domain ferroelectric material

Abstract

The invention relates to a method for preparing a single-domain thin film made of ferroelectric material, the method comprising transferring the layer from a donor substrate to a receiver substrate, followed by a heat treatment (Stab) and then thinning (Thin), the heat treatment comprising: increasing the temperature to a high temperature of between 400°C and the Curie temperature of the ferroelectric material forming the layer; maintaining the temperature for a time of 30 min or more; then lowering the temperature, wherein the temperature increase is carried out by a temperature ramp at a heating rate greater than 7°C / min, such that the transferred ferroelectric layer reaches a temperature between 400°C and the Curie temperature at the end of the ramp.

Description

METHOD FOR PREPARING A THIN LAYER OF SINGLE-DOMAIN FERROELECTRIC MATERIAL FIELD OF INVENTION

[0001] The present invention relates to a method for preparing a thin film of ferroelectric material. More particularly, it relates to a preparation method that ensures the single-domain character of the ferroelectric material in the thin film of the final product. This preparation method is used, for example, in the fields of microelectronics, micromechanics, photonics, etc. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] As a preliminary point, it is important to remember that a ferroelectric material is a material that possesses an electrical polarization in its natural state, a polarization that can be reversed by the application of an external electric field. A ferroelectric domain is defined as each contiguous region of the material in which the polarization is uniform (all dipole moments are aligned parallel to each other in a given direction). A ferroelectric material can therefore be characterized as "single-domain" if it consists of a single region with uniform polarization, or as "multi-domain" if it comprises multiple regions with potentially different polarities.

[0003] The present invention relates more particularly to the preparation of a ferroelectric thin film obtained by applying the Smart Cut™ technology, according to which a thin film is extracted from a substrate, possibly a bulk substrate, made of ferroelectric material by fracturing it at a weak zone (or embrittlement plane) formed in the substrate by implanting so-called "light" species, such as helium or hydrogen. A specific example of the implementation of this process can be found in document EP3646374B1.

[0004] After the layer has been sampled using this process, it is often necessary to apply treatments to improve its surface condition, crystalline quality, or modify its thickness. However, the applicant observed that these preparation steps, when applied to a ferroelectric thin film deposited on a silicon substrate, can lead to the formation of multiple ferroelectric domains in a superficial portion of the thin film. This portion can be on the order of 150 nm to 200 nm thick, or even thicker, on the free face of the thin film, thus giving it a surface multidomain character. Such a characteristic renders the layer unsuitable for its intended use, as it affects the performance of devices intended to be formed on or within the thin film, such as surface acoustic wave (SAW) devices.

[0005] Document FR2914492 describes a process for manufacturing a thin film of ferroelectric material using Smart Cut technology, in which the extracted layer is transferred to a substrate and prepared by subjecting it to an electric field to improve or restore its ferroelectric properties. This treatment requires a pair of electrodes positioned on either side of the ferroelectric layer to be treated, for example, in electrical contact with it. It is not always possible to have such a pair of electrodes, particularly when the ferroelectric layer is transferred to an electrically insulating substrate or to a layer of electrical insulation.

[0006] For this reason, it may be preferable to thin the ferroelectric layer, for example by chemical polishing. However, removing a relatively large thickness of material by polishing tends to degrade the thickness uniformity of the polished layer. For example, removing a thickness on the order of 100 nm results in a layer whose thickness uniformity (i.e., the difference between the greatest and thinnest thicknesses when this thickness measurement is performed, for example by reflectometry or ellipsometry, at multiple measurement points across the entire extent of the layer) is degraded by approximately 10 nm. This thickness variability is unacceptable because it prevents the collective fabrication, from such a layer, of devices with all the required characteristics.

[0007] Alternatives exist to chemical polishing for thinning. One option is to thin the ferroelectric thin film using ion etching, for example, reactive ion etching (RIE). RIE is a type of dry etching that uses a plasma of chemically reactive ions to remove the surface material from a wafer. The plasma is generated under low pressure by an electromagnetic field. The high-energy ions of the plasma attack the surface of the layer and react with it to pulverize it, thus progressively thinning it. This approach is described in document FR3129033.

[0008] However, whether implemented by mechanochemical polishing or by ion etching, the removal of a relatively large thickness of material to eliminate the multi-domain surface portion of the sampled layer is a drawback of the prior art processes, as this step tends to make the manufacturing process longer and more complex to implement.

[0009] This removal step also requires extracting a relatively thick layer from the ferroelectric material substrate, necessitating the implantation of light species with significant energy. Beyond a certain threshold thickness, the energy required to define the extracted layer is beyond the reach of existing implantation equipment. Furthermore, increasing the implantation energy leads to greater heating of the plate, which is accompanied by the appearance of localized or widespread defects.

[0010] We therefore see that the known processes for preparing a single-domain thin film in ferroelectric material have limitations that it is desirable to overcome. SUBJECT OF THE INVENTION

[0011] One object of the invention is to provide a method for preparing a thin film of ferroelectric material that addresses at least some of the aforementioned limitations. More particularly, one object of the invention is to provide a method for preparing a thin film of ferroelectric material in which the thickness of material removed to eliminate the multi-domain surface portion of the extracted layer is reduced compared to the thickness removed in prior art methods. BRIEF DESCRIPTION OF THE INVENTION

[0012] With a view to achieving one of these goals, the object of the invention proposes a method for preparing a single-domain thin film of ferroelectric material, the method comprising: a step of implanting a so-called "light" species via a first face of a donor substrate so as to form a weakening plane in the donor substrate; a step of assembling the first face of the donor substrate to a device substrate so as to form an intermediate assembly; a step of fracturing the intermediate assembly at the level of the weakening plane, this step leading to equipping the device substrate with a ferroelectric layer transferred from the donor substrate and having a free face;a finishing step of the transferred ferroelectric layer comprising a heat treatment step and, after the heat treatment step, a thinning step of the transferred ferroelectric layer so as to form the single-domain thin film, in which the heat treatment comprises: a temperature rise of the transferred ferroelectric layer up to a high temperature between 400°C and the Curie temperature of the ferroelectric material forming the transferred ferroelectric layer; then a holding of the transferred ferroelectric layer at a temperature between the high temperature and said Curie temperature, for a period greater than or equal to 30 min; then a temperature fall of the transferred ferroelectric layer, from the high temperature;

[0013] the temperature rise of the transferred ferroelectric layer comprising a temperature ramp carried out at a rate of temperature change greater than 7°C / min, preferably greater than or equal to 10°C / min, such that the transferred ferroelectric layer reaches a temperature between 400°C and the Curie temperature at the end of the ramp.

[0014] Compared to conventional processes, the process according to the invention results in a reduction of the thickness on which a multi-domain ferroelectric structure is likely to form in a surface region of the ferroelectric layer transferred from a donor substrate to a device substrate.

[0015] Consequently, a first advantage of the invention is a reduction in the thickness of the layer to be removed, and therefore an improvement in the uniformity of the thickness of the remaining layer, uniformity typically degrading with the thickness of the layer removed.

[0016] A second advantage is that it is possible to transfer a thinner ferroelectric layer than in conventional processes, as a thinner thickness of the transferred layer needs to be removed to extract the multi-domain portion.

[0017] A third advantage is the simplification and shortening of the slimming process itself.

[0018] A fourth advantage is the reduction in heat treatment time.

[0019] According to additional, non-limiting features of the first aspect of the invention, considered individually or in any technically feasible combination:

[0020] - the temperature ramp of the transferred ferroelectric layer can be parameterized to cause a temperature rise of at least 350°C, preferably 400°C, even more preferably 450°C, of ​​the transferred ferroelectric layer;

[0021] - the temperature ramp of the transferred ferroelectric layer can be set to start at a temperature between ambient temperature and the high temperature, and result in a temperature rise of at least 100°C;

[0022] - the thinning step can consist of removing a thickness of the transferred ferroelectric layer of less than 200 nm, preferably less than 150 nm;

[0023] - the device substrate equipped with the transferred ferroelectric layer can be placed directly in a furnace while it is at high temperature;

[0024] - the device substrate with the transferred ferroelectric layer can be placed in a furnace while it is at a first low temperature and removed from the furnace while it is at a second low temperature, the first low temperature and the second low temperature each being between the ambient temperature and the high temperature, preferably between 100°C and 500°C, even more preferably between 300°C and 400°C;

[0025] - the single-domain thin film can be made of a single-crystal piezoelectric material, such as lithium tantalate or lithium niobate;

[0026] - the donor substrate can be made of a bulk ferroelectric material;

[0027] - the donor substrate may include a support substrate supporting a layer of ferroelectric material, a material forming the donor substrate being distinct from a ferroelectric material forming the layer of ferroelectric material;

[0028] - the finishing step of the transferred ferroelectric layer may include a surface treatment step designed to remove a lithium-rich surface layer, and / or eliminate or prevent the appearance of dendrites;

[0029] - The finishing step of the transferred ferroelectric layer may include a surface treatment step designed to introduce hydrogen onto the surface of the transferred ferroelectric layer in such a way as to produce a hydrogen concentration greater than 2.10 21 atoms / cm3 in a surface thickness of the transferred ferroelectric layer less than 200 nm deep;

[0030] - the process may further include a step of forming at least one interlayer, on at least one of a face of the donor substrate and of a face of the device substrate, formed of silicon oxide, silicon nitride, and / or silicon oxynitride;

[0031] - the process may further include a step of forming an electrical charge trapping layer on a surface of the device substrate, intended to be assembled with the donor substrate.

[0032] Other features and advantages of the invention will become apparent from the detailed description of the invention which follows with reference to the accompanying figures in which:

[0033] Laillustre un processus de préparation de un thin ferroelectric unidomaine selon la invention;

[0034] This is a diagram summarizing the preparation process of the;

[0035] Larepresents temperature profile graphs illustrating heat treatments according to the invention;

[0036] Laillustre des variations du processus illustré par la ;

[0037] Laillustre is a variant of the process illustrated by the ;

[0038] Lamontre of the topographies obtained by AFM after a thickness of 125 nm was removed from a layer and for different thermal treatments;

[0039] Laillustre provides topographical data for two heat treatments and two shrinkage thicknesses; and

[0040] Laest is a graph of a temperature profile illustrating a heat treatment according to the invention.

[0041] The figures are schematic representations which, for the sake of clarity, are not to scale. In particular, the thicknesses of the layers are not to scale relative to the lateral dimensions of those layers. DETAILED DESCRIPTION OF THE INVENTION

[0042] The invention relates to a method for preparing a single-domain DevLay thin film of a ferroelectric material transferred from a single-crystal donor substrate DonSub onto a DevSub device substrate by a transfer technique including the implantation of light species in the donor substrate DonSub. Several embodiments of this thin-film delivery step exist.

[0043] According to an embodiment illustrated in Figures 1 to 4, a donor substrate DonSub is provided during a step 110Don of process 100. The donor substrate DonSub consists of a solid, single-crystal, single-domain block of ferroelectric material, for example, LiTaO3, LiNbO3, LiAlO3, BaTiO3, PbZrTiO3, KNbO3, BaZrO3, CaTiO3, PbTiO3, or KTaO3. The donor substrate DonSub may be in the form of a circular wafer of standardized dimensions, for example, 150 mm or 200 mm in diameter. However, the invention is not limited to these dimensions or this shape. The donor substrate may have been extracted from an ingot of ferroelectric material, such extraction having been carried out in such a way that the donor substrate DonSub has a predetermined crystal orientation. The orientation is chosen according to the intended application.Thus, it is common to choose an orientation between 30° and 60°RY, or between 40° and 50°RY, when it is desired to exploit the properties of a LiTaO3 thin film to form a SAW filter. However, the invention is by no means limited to a particular crystal orientation.

[0044] Regardless of the crystalline orientation of the DonSub donor substrate, the process includes the introduction into the DonSub donor substrate of at least one so-called "light" species, notably chosen from inert gases, helium, and hydrogen, during a step 120 Don This introduction can correspond to an implantation, that is to say an ionic bombardment of a top flat face DonTop of the donor substrate DonSub by ions of the chosen light species or species such as hydrogen and / or helium ions.

[0045] As is known in itself, and as illustrated by (A), the implanted ions are intended to form a weakening plane Frgl, which will subsequently serve to separate the donor substrate into a layer of material between the implantation surface and the weakening plane.

[0046] The nature and dose of the implanted species, as well as the implantation energy, are chosen according to the thickness of the layer to be separated from the donor substrate (DonSub) and the latter's physicochemical properties. In the case of a LiTaO3 donor substrate (DonSub), a hydrogen dose of between 1 E 16 and 5 E 17 at / cm² with an energy between 30 and 300keV to form the embrittlement plane at a depth of approximately 200 to 2000 nm.

[0047] At stage 110 DevAs illustrated in Figure (B), the DevSub device substrate is provided to support the DevLay single-domain thin film. The DevSub device substrate is so named because it is designed to receive, after transfer of the DevLay single-domain thin film, devices such as surface elastic wave (SAW) devices. This substrate can have the same dimensions and shape as the donor substrate, SubDon. For reasons of availability and cost, the DevSub device substrate is typically a silicon wafer, either monocrystalline or polycrystalline. However, more generally, the DevSub device substrate can be made of any material, such as silicon, sapphire, or glass, and can have any shape.

[0048] At an assembly step 130, illustrated by (C) and subsequent to step 120 Don, we assemble the upper flat face DonTop of the donor substrate DonSub to an upper flat face DevTop of the device substrate DevSub.

[0049] Prior to the assembly stage, it is possible to prepare the surfaces of the substrates to be assembled by a cleaning, brushing, drying, polishing, or activation step, for example by plasma.

[0050] The assembly step may correspond to the intimate contact of the donor substrate DonSub with the device substrate DevSub by molecular adhesion and / or electrostatic bonding.

[0051] At the end of this assembly step, we have a Set resulting from the assembly of the donor substrate DonSub and the device substrate DevSub, the DonTop face of the donor substrate DonSub adhering to the DevTop face of the device substrate DevSub.

[0052] At a step 140, the entire Set is processed to leave on the DevSub device substrate only a DonSub1 layer from the donor substrate DonSub, for example by cleaving the donor substrate at the level of the embrittlement plane Frgl.

[0053] This detachment step may therefore include applying heat treatment to the entire Set assembly within a temperature range of approximately 80°C to 300°C to enable the transfer of the DonSub1 layer to the DevSub device substrate. As an alternative or complement to heat treatment, this step may include applying a sheet or jet of gaseous or liquid fluid to the embrittlement plane Frgl.

[0054] La(D) illustrates this operation, with the separation of the donor substrate DonSub into two parts DonSub1 and DonSub2 at the level of the embrittlement plane, the part DonSub1 forming a layer remaining fixed to the device substrate DevSub.

[0055] An alternative could be to thin the donor substrate to a desired thickness. However, this option is costly and inefficient, as the entire donor substrate is destroyed except for the DonSub1 layer, whereas with cleavage separation, the donor substrate can be refreshed and reused to form new layers on other device substrates.

[0056] Regardless of the implementation method chosen, and as stated in the introduction to this application, finishing steps for the DonSub1 layer are then necessary to improve its crystalline and surface quality and provide a DevLay layer with a thickness that matches, or approaches, a target thickness. These finishing steps, schematically represented by step 150 implemented to transition from (D) to (E), aim in particular to eliminate a multidomain, hardened, and rough surface layer resulting from the cleavage and detachment of the DonSub1 thin layer from the rest of the donor substrate.

[0057] Reducing the thinning of the DonSub1 layer is advantageous in several ways. A primary benefit is the increased uniformity of the DevLay layer achieved by thinning the DonSub1 layer. This uniformity stems from a reduction in the formation thickness of a multi-domain structure, and consequently, a reduction in the layer thickness that needs to be eliminated to get rid of the multi-domain structure and recover a single-domain structure.

[0058] A second advantage is the simplification and shortening of the slimming process itself.

[0059] A third advantage is the reduction in the required thickness of the DonSub1 layer transferred from the donor substrate DonSub to the device substrate DevSub.

[0060] A fourth advantage is the reduction in heat treatment time.

[0061] However, the applicant was able to determine that, surprisingly and unexpectedly, the temperature ramp of the heat treatment, which is usually part of the finishing step of the DonSub1 layer, influences the thickness of the multi-domain layer. As explained below, it is possible to reduce the thickness of the multi-domain layer, and therefore reduce the thinning required for the DonSub1 layer, by using a sufficiently steep temperature ramp.

[0062] Conventionally, a layer transferred from a donor substrate to a receiving substrate—the device substrate mentioned above—undergoes heat treatment with several objectives: (1) to strengthen the bond between the layer and the receiving substrate, and (2) to improve the quality of the transferred layer itself by repairing, for example, crystalline defects induced by the transfer process and, to some extent, improving its surface finish. Ideally, the heat treatment would be carried out immediately at a temperature as high as possible compatible with the materials constituting the layer and the receiving substrate. However, it is necessary to take into account, for example, the differences in thermal expansion between the transferred layer and its substrate, avoiding excessive thermal shock, which could, for example, break the bond between the transferred layer and its substrate.It would be possible to place the assembly in a furnace at ambient temperature and gradually raise the temperature to a treatment temperature of, for example, 500 or 600°C. However, this method has the drawback of requiring the furnace to be idle for an extended period (the temperature reduction also follows a long, downward ramp). Therefore, a compromise is generally used, which involves placing the assembly to be treated in a furnace (a so-called "boat-in" operation) already at a temperature of around 350°C, then gradually raising the temperature to a plateau maintained for a certain time, lowering the furnace temperature to approximately 350°C, and removing the treated assembly from the furnace (a so-called "boat-out" operation). In this way, furnace downtime is minimized without damaging the assembly undergoing heat treatment.

[0063] As part of studies on the thickness of the multi-domain layer, the applicant carries out characterizations according to the following principle. Following a heat treatment applied to a DonSub1 layer transferred according to the process explained above, the layer is thinned by chemical mechanical polishing (CMP) and then the topography of the exposed face is measured: a strong topography indicates the multi-domain quality of the material whose face is exposed and, on the contrary, a weak topography indicates the single-domain quality of the material whose face is revealed.

[0064] Indeed, the rate of chemical or physicochemical etching of the DonSub1 layer during polishing is variable depending on the polarity of the ferroelectric material being removed: the Z- side of this layer etches much faster than the Z+ side. Consequently, polishing a single-domain layer will result in a much lower surface topography than polishing a multi-domain layer.

[0065] Therefore, according to the proposed characterization technique, by evaluating the topography of the exposed face of the thin film after it has been thinned to a specific thickness, it is possible to easily determine whether the multi-domain layer extends to a depth greater than the specified thickness (indicated by a significant topography) or to a thickness less than the specified thickness (indicated by a shallow topography). This somewhat crude characterization of the multi-domain thickness nevertheless allows for an overall assessment of this thickness by repeating the topographic measurement at multiple locations, sampling the entire extent of the layer.

[0066] Using this technique, the applicant evaluated the thickness of the multi-domain zone of DonSub1 layers for different heat treatments.

[0067] Laillustre des topographies obtained by atomic force microscopy (AFM for Atomic Force Microscopy in English terminology) for DonSub1 layers after a thickness of 125 nm was removed by CMP following the application of test heat treatments.

[0068] Figures 6(A) to 6(E) illustrate topographies after removal of approximately 125 nm of thickness, for different thermal treatments. The images on the left represent the topographies for measurements on 5 µm x 5 µm fields, and the images on the right represent the topographies for measurements on 30 µm x 30 µm fields.

[0069] Figures 6 illustrate (A) to (D) topographies for different heat treatments involving boat-in (insertion into the furnace) at 350°C, temperature ramp-up to 500°C, a one-hour holding period, and then a return to 350°C for boat-out (removal from the furnace). The temperature ramp rates were set at 1°C / min, 5°C / min, 7°C / min, and 10°C / min, respectively. For temperature ramp rates of 7°C / min or less, domains are observed, visible as bright spots in the images. Conversely, for temperature ramp rates exceeding 7°C / min, and particularly for 10°C / min, the multi-domain structure is no longer observed at the exposed surface of the layer.

[0070] Laillustrate in (E) the topographies for a heat treatment without a temperature ramp, with a boat-in (insertion into the furnace) at 500°C, a one-hour holding period, then a boat-out. Here too, no multi-domain structure was observed. The temperature rise of the DonSub1 layer is considered to be greater than 10°C / min.

[0071] In all cases, given the low thermal inertia of the surface of the DonSub1 layer, we can consider that its thermalization to the oven temperature is almost instantaneous and that the oven temperature is therefore representative of that of this layer.

[0072] Figures 6(A) to (D) illustrate topographies for two heat treatments and two shrinkage thicknesses: approximately 125 nm of thinning for (A) and (C) and approximately 105 nm of thinning for (B) and (D). Figures 6(A) and (B) illustrate topographies for DonSub1 layers subjected to a heat treatment similar to that of Figures 6(A) to (D), with boat-in (insertion into the furnace) in a 350°C furnace, a temperature ramp up to 500°C, a one-hour holding period, then a drop back down to 350°C for boat-out (removal from the furnace). The temperature ramps were set at 10°C / min. Laillustrates in (C) and (D) topographies for DonSub1 layers subjected to heat treatment with a boat-in (insertion into the furnace) in a 500°C furnace, a one-hour holding period, and then a boat-out. These topographies indicate that, in all cases, a multi-domain structure is observable at a depth of 105 nm but not at 125 nm.It can therefore be deduced that, for temperature ramps of speeds greater than 10°C / min, the thickness of the multi-domain layer to be eliminated is between 105 nm and 125 nm.

[0073] For comparison, it should be noted that in the case of ramps of 1°C / min, as in case (A), the thickness of the multi-domain layer is typically on the order of 200 nm. Reducing this thickness to a thickness between 105 and 125 nm constitutes a significant improvement.

[0074] Finishing treatment of the transferred layer

[0075] The finishing step 150, to be applied to the DonSub1 layer, can comprise three steps applied successively in this order: a surface treatment step 150A following step 140; a heat stabilization step 150B; and a thinning step 150C. Based on the above observations, steps 150B and 150C can be optimized.

[0076] Step 150A of applying a SurfTreat surface treatment is optional, but can advantageously contribute to improving the quality of the DonSub1 layer.

[0077] A first type of surface treatment can be used to remove a lithium-rich surface layer, typically composed of Li₂CO₃. This may involve brushing the free face of the first layer while simultaneously dispensing deionized water onto this free face. It is also possible to complement this lithium removal step with a step to remove lithium-rich dendrites or to prevent / limit their formation. These dendrites, which have an amorphous structure, are rich in lithium and hydrogen and are susceptible to nucleation on the free face of the DonSub1 layer when it lacks the lithium-rich surface layer. See patent document WO2024022723A1.One variation of the dendrite removal step involves allowing the dendrites to develop and stabilize on the surface for at least 50 hours, preferably at least 75 hours, at room temperature after the lithium removal step, to ensure that dendrite development is effectively stabilized. Alternatively, the DonSub1 layer can be exposed to a temperature above room temperature to promote dendrite development and reduce the waiting time to less than 50 hours. The dendrites then need to be removed, for example, by a wet cleaning step of the free face, such as a cleaning step similar to that used to remove the surface layer of Li2CO3. A second variation involves treating the free face of the DonSub1 layer to prevent dendrite formation.This second preparation step is therefore applied less than 50 hours, preferably less than 10 hours, after the removal of the lithium-rich surface layer. It may involve exposing the free side of the first layer to a plasma, for example, a plasma chosen from a list consisting of an O2 plasma, an N2 plasma, and a fluorine-based plasma, such as an SF6 or CxHyFz plasma, or a combination of these plasmas. For example, a 30-second RF (13.55 MHz) nitrogen (N2) plasma, with a power of 150 W and a pressure of 50 mT, in a nitrogen flow of 75 SCCM, has proven particularly effective. Similarly, a 30-second RF plasma sequence (at 13.55 MHz), with a power of 150W and a pressure of 50mT, in an oxygen flow of 75 SCCM and SF6 of 3 SCCM, was also shown to be effective in treating the free face of the DonSub1 layer and preventing the appearance of dendrites.

[0078] A second type of surface treatment involves introducing hydrogen onto the surface of the DonSub1 layer. Indeed, as stated in international patent application PCT / EP2024 / 059520, introducing a sufficient dose of hydrogen into a surface thickness of the transferred layer, prior to heat treatment, tends to reduce the thickness of the multi-domain surface portion exposed during that heat treatment. Therefore, it is advantageous to treat the free face of the DonSub1 layer with a hydrogen concentration greater than 2 x 10⁻³. 21 atoms / cm 3 in a surface thickness of the DonSub1 layer, for example less than 200 nm deep. For example, a dose of hydrogen greater than or equal to 2 x 10⁻³ can be introduced into the layer. 16 atoms / cm 2 or carry out wet cleaning treatments.

[0079] Step 150B, applying a stabilizing Stab heat treatment to the transferred layer from the donor substrate DonSub to the device substrate DevSub, follows optional step 150A.

[0080] As mentioned above, and explained for example in patent document WO2020200986, this heat treatment heals crystalline defects present in the DonSub1 transferred layer and even reduces the roughness of its free face. Furthermore, it helps strengthen its adhesion to the DevSub device substrate. The heat treatment raises the entire Set to a temperature between 300°C and the Curie temperature of the ferroelectric material for a duration of between 30 minutes and 10 hours. This heat treatment is carried out, at least partially, in a temperature-controlled furnace, preferably by exposing the free face of the DonSub1 layer to an oxidizing or neutral gaseous atmosphere, i.e., without covering this face of the thin film with a protective layer.

[0081] A heat treatment according to the invention is illustrated in Figures 3 and 8. The Stab heat treatment of the transferred layer DonSub1 comprises three successive phases: (i) a temperature ramp TmpRs up to a high temperature HT between 400°C and the Curie temperature of the ferroelectric material forming the DonSub1 layer; (ii) a holding period Stp at the high temperature HT for a duration Δt greater than or equal to 30 min; and (iii) a temperature ramp from the high temperature HT. The ramp-up phase TmpRs includes a rising temperature Rmp1 of the transferred layer, carried out at a rate of temperature change greater than 7°C / min, preferably greater than or equal to 10°C / min.

[0082] Respecting this rate of temperature change is optional for the temperature descent, additional experiments have shown that it is respecting this rate of temperature change during the temperature rise that allows the reduction of the thickness on which a multi-domain ferroelectric structure is likely to form.

[0083] The heat treatment profile imposed on the DonSub1 layer is not particularly limited, as long as the temperature rise of this layer leading to its maintenance at temperature Stp (whose temperature is not necessarily fixed, as long as it remains above the indicated high temperature) includes a temperature ramp Rmp1 of the transferred layer with a slope greater than 7°C / min, preferably greater than or equal to 10°C / min, resulting in a temperature rise preferably of at least 100°C, preferably 200°C, more preferably 350°C, even more preferably 400°C and at most preferably of at least 450°C of the temperature of the transferred layer, the temperature ramp Rmp1 leading to a temperature of the layer between 400°C and the Curie temperature.

[0084] Such conditions can be ensured through multiple methods, described below.

[0085] The first method, illustrated in (A) of Figure 1, consists of placing the entire Set assembly directly into the oven while it is at the high temperature HT and removing it from the oven while it is still at the high temperature. Figure 1 (A) is a graph schematically showing the evolution of the temperature T° of the DonSub1 layer as a function of time t. In this situation, the temperature rise of Rmp1 occurs from the ambient temperature T Am b From the moment t0 of insertion into the furnace, already at the high temperature HT, until the moment t1 when the layer reaches the high temperature HT, between 400°C and the Curie temperature of the material forming the DonSub1 layer. The high temperature is maintained for temperature stabilization Stp. The temperature decrease Rmp2 occurs from the high temperature HT at the moment t2 of removal from the furnace, until the moment t3 when the layer returns to ambient temperature T AmbThe time interval Δt between times t1 and t2 corresponds to the duration of maintenance at a temperature equal to or greater than the upper temperature HT, and lower than the Curie temperature of the material forming the transferred layer. In this case, times t0 and t1 on the one hand, and t2 and t3 on the other, are practically identical, due to the rapid thermalization of the DonSub1 layer. It is understood that the temperature rise of this layer is rapid here, well above 10°C / min.

[0086] This method has the advantage of simplicity and speed. However, it may not be suitable for all types of device substrates, ferroelectric materials, or their specific combinations.

[0087] The second method is more universal than the first, in that, by imposing a less abrupt thermal stress, it is applicable to a wider range of substrates and ferroelectric materials. However, it requires more time. In this second method, illustrated in (B) by a graph similar to that of the first method, the set at room temperature T Ambis placed in the oven at time t0 when it is at a first low temperature LT1 and removed from the oven at time t5 when it is at a second low temperature LT2, producing a temperature ramp Rmp1 between times t0 and t1 and a temperature ramp Rmp2 from time t5 onwards, which can have the characteristics of the ramps Rmp1 and Rmp2 from example (A) respectively. Temperature ramps Rmp1' and Rmp2' are carried out in a controlled manner between the high temperature HT of the oven and the low temperatures LT1 and LT2, between times t1 and t2 and times t3 and t4, respectively. These Rmp1' and Rmp2' ramps can exhibit lower temperature variations and rates of temperature variation than the Rmp1 and Rmp2 temperature ramps (but nevertheless greater than 7°C / min for the Rmp1' temperature ramp), limiting the thermal stress imposed on the transferred layer.In this way, the magnitude of the abrupt temperature change applied to the transferred layer upon its entry and exit from the furnace is also limited compared to case (A). The time interval Δt between times t2 and t3 corresponds to the duration for which the transferred layer is held at the high temperature HT. The first low temperature LT1 can be between ambient temperature and the high temperature HT, preferably between 100°C and 500°C, and even more preferably between 300°C and 400°C. The temperature LT2 can be between ambient temperature and the high temperature HT, preferably between 100°C and 500°C, and even more preferably between 300°C and 400°C. LT1 and LT2 can be equal or different from each other.

[0088] In this scenario, times t0 and t1 are almost identical, due to the rapid thermalization of the DonSub1 layer. It is understood that the temperature rise Rmp1 of this layer is rapid here, well above 10°C / min.

[0089] The oven is configured to impose a rapid temperature ramp, greater than 7°C / min, on the layer transferred during the Rmp1' temperature ramp, possibly slower than the Rmp1 temperature ramp.

[0090] The 150C thinning step is implemented after the 150B stabilization treatment step. This step aims to remove the multi-domain surface portion of the DonSub1 layer, which was created during the previous heat treatment step. It also aims to provide a single-domain DevLay device thin film with a thickness corresponding to a target thickness, as previously discussed. This thinning can generally involve polishing the first free face of the DonSub1 layer, for example, using mechanical or mechanochemical thinning techniques. It can also involve thinning achieved through ion etching, such as reactive ion etching.

[0091] In all cases, this thinning is carried out in such a way as to eliminate at least the thickness of the multi-domain portion of DonSub1, this thickness being typically less than 125 nm in the process described above. Figure (E) illustrates the structure obtained after these treatments, with a single-domain DevLay thin film deposited on the DevSub device substrate.

[0092] Thus, even taking into account margins of error regarding the thickness of the multi-domain portion to be removed and the thickness actually removed, the 150C thinning step can be planned to remove 300 nm or less, 200 nm or less, preferably 170 nm or less, more preferably 150 nm or less and even more preferably 125 nm or less of the DonSub1 layer thickness.

[0093] Variants

[0094] The process described above by means of Figures 1 to 3 describes a simple case to which the invention is not limited. Figures 4, 5 and 8 illustrate alternative configurations that can be used alone or in combination as variants of the process 100 described above.

[0095] Laillustre en (A) the possibility of forming, during step 110 DonA superficial interlayer layer, Inter, has the advantage of facilitating the assembly of the two substrates, DonSub and DevSub, particularly when they are joined by direct bonding. At least one Interlayer layer can be formed prior to assembly, either on the DonTop face of the donor substrate, on the DevTop face of the DevSub device substrate, or on both. This interlayer layer can, for example, consist of one or more layers of silicon oxide, silicon nitride, and / or silicon oxynitride. It can have a thickness ranging from a few nanometers to a few microns and optionally have an amorphous structure.

[0096] An interlayer with a low hydrogen concentration or one that acts as a barrier to hydrogen diffusion will be preferred, in accordance with the guidelines of document WO2020200986, thus limiting the formation of a multi-domain zone at the DonSub1 layer. The interlayer can be fabricated using various state-of-the-art techniques, such as oxidation or nitriding heat treatments, chemical deposition (PECVD, LPCVD, etc.).

[0097] Laillustre en (B) the possibility of forming a TrapLay layer for trapping electrical charges on the DevTop surface of the DevSub device substrate during step 110 Dev The trapping layer, as is well known in itself, can be formed from a layer of polycrystalline silicon, and typically have a thickness between 500nm and 10 microns.

[0098] Laillustre en (C) la structure de l'ensemble Set en l'ensemble Set en l'affaire où une couche intercalaire est forme sur le substrat don DonSub, une couche de piège en charge électrique est forme sur le substrat de dispositif DevSub, et ces deux substrats forme le ensemble Set obtenir par assemblage des visages DonTop et DevTop de ces substrats.

[0099] Laillustre en (D) the final structure obtained by implementation of step 150 to the set Set, with the trapping layer TrapLay, the intercalated layer Inter and the single-domain ferroelectric layer DevLay formed in that order on the device substrate DevSub.

[0100] Laillustrates a variant in which the donor substrate DonSub is a hybrid structure comprising a support substrate CarSub supporting a single-crystal, single-domain ferroelectric layer FerroLay from which the DonSub1 layer is obtained during step 140 of process 100. Laillustrates more specifically the implementation of step 120Don of realization of the embrittlement plane Frgl by ion implantation through the DonTop surface, which is the free face of the FerroLay layer.

[0101] This variant is particularly suited to the situation in which the DonSub1 layer has a coefficient of thermal expansion (in the principal plane defining this layer) that is very different from that of the DevSub device substrate, for example showing a difference of more than 10% (at room temperature).

[0102] The CarSub support substrate is advantageously made of a material (or a plurality of materials) that gives it a coefficient of thermal expansion close to that of the DevSub device substrate. By "close," we mean that the difference between the coefficients of thermal expansion of the CarSub support substrate and the DevSub device substrate is less, in absolute value, than the difference in thermal expansion between (i) the DevSub device substrate and (ii) the donor substrate when it is made entirely of the ferroelectric material constituting the DonSub1 layer.

[0103] Preferably, the CarSub support substrate and the DevSub device substrate have the same coefficient of thermal expansion. During assembly of the CarSub support substrate and the DevSub device substrate in step 130, a Set assembly can thus be formed that can withstand heat treatment at a relatively high temperature. For ease of implementation, this can be achieved by choosing the CarSub support substrate to be made of the same material as the DevSub device substrate, for example, monocrystalline silicon.

[0104] To form the DonSub substrate of this variant, a solid block of ferroelectric material is first bonded to the CarSub carrier substrate, for example, using a molecular adhesion technique as previously described or with an adhesive layer. The carrier substrate is chosen for its coefficient of thermal expansion to be close to that of the DevSub device substrate and can, for example, be made of single-crystal silicon. The FerroLay ferroelectric material layer is then formed by thinning, for example, by grinding and / or chemical polishing and / or etching. Before assembly, an adhesive layer (for example, by depositing silicon oxide and / or silicon nitride, or an adhesive layer such as a polymer) can be applied to one or both of the contacting surfaces.The assembly may include the application of a low temperature heat treatment (for example between 50 and 300°C, typically 100°C) to sufficiently increase the bonding energy to allow the next thinning step.

[0105] The CarSub substrate is chosen to have a thickness roughly equivalent to that of the DevSub device substrate. The thinning step is carried out so that the FerroLay layer is sufficiently thin to reduce the stresses generated during the subsequent heat treatments. At the same time, this thickness is sufficient to allow for the removal of the DonSub1 layer, or a plurality of such layers. This thickness can, for example, range from 5 to 400 microns.

[0106] This implementation method is advantageous because the assembly formed by the donor substrate DonSub and the support substrate CarSub can be exposed to a much higher temperature than that applied when the donor substrate DonSub is made of a solid ferroelectric material, without risk of uncontrolled fracture of either substrate or delamination of the DonsSub1 layer. The balanced structure, in terms of the coefficient of thermal expansion of this assembly, thus facilitates the detachment step of the DonSub1 layer by exposing the assembly to a relatively high temperature, for example, between 100 and 500 °C.

[0107] Figures 3(A) and (B) illustrate examples in which a steep temperature ramp is imposed on the transferred layer from ambient temperature.

[0108] Conversely, this illustrates another example of heat treatment, with an initial temperature rise SlRmp1 that can be slow, but in reality has an arbitrary slope, bringing the transferred layer DonSub1 from ambient temperature T Amb At time t0, the transferred layer is at a low temperature LT1 located between ambient temperature and the high temperature HT at time t'1. This is followed by a rapid temperature ramp Rmp1, bringing the transferred layer to the high temperature HT at time t1. The high temperature is between 400°C and the Curie temperature of the material forming the layer. The high temperature is maintained for a holding period Stp until time t2, before a first temperature ramp Rmp2 to a low temperature LT2 at time t'2, followed by a second temperature ramp SlRmp2 to return to ambient temperature at time t3.

[0109] Unless otherwise specified, the characteristics of the LT2 temperature, the Rmp1 and Rmp2 ramp velocities, and the Stp temperature maintenance can be the same as those described in relation to Figures 3(A) and (B). The SlRmp1 and SlRmp2 ramps have arbitrary slopes, but can be less steep than those of the Rmp1 and Rmp2 ramps, respectively.

[0110] Preferably, the Rmp1 ramp causes a temperature rise in the layer of at least 100°C and leads to a temperature of at least 400°C and below the Curie temperature of the ferroelectric material, so that the effects of this ramp become clearly apparent within the crystalline structure of the DonSub1 layer.

[0111] Lan'est is just one example in addition to those in Figures 3(A) and 3(B), and the temperature profiles of the heat treatments in these examples are not particularly limited, as long as they contain a holding range above 400°C and below the Curie temperature of the transferred layer material for at least 30 min, and a rapid temperature ramp of the transferred layer, of at least 7°C / min, resulting in a temperature rise of the transferred layer, preferably, of at least 100°C, preferably 200°C, more preferably 300°C, and even more preferably 400°C, the rapid temperature ramp being such that the transferred ferroelectric layer reaches a temperature between 400°C and the Curie temperature at the end of the ramp.

[0112] Thus, in general, the 150B heat treatment involves a temperature ramp TmpRs, consisting of the Rmp1 ramp for case A, comprising the Rmp1 and Rmp1' ramps for case B, and comprising the SlRmp1 and Rmp1 ramps for case C. It appears from all the tests carried out by the inventor that the effect of reducing the thickness over which a multi-domain ferroelectric structure is likely to form in a surface region of the transferred ferroelectric layer is obtained on the condition that a sufficiently rapid ramp leading to a sufficiently high temperature is applied to the layer. These conditions can also be met for a gentle temperature ramp from room temperature, provided that a rapid temperature ramp leading to a sufficiently high temperature, and therefore having a significant effect on the crystalline lattice of the layer, is subsequently applied.

[0113] In this document, the expression "ambient temperature" refers to the temperature of a room in which human operators work without special equipment, typically between 15 and 25°C.

[0114] Of course the invention is not limited to the described method of implementation and alternative embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

Process for preparing a single-domain thin film (DevLay) in ferroelectric material, the process comprising: - a step (120 Don- implantation of a so-called "light" species via a first face (DonTop) of a donor substrate (DonSub) so as to form a weakening plane (Frgl) in the donor substrate (DonSub); - a step (130) of assembling the first face (DonTop) of the donor substrate (DonSub) to a device substrate (DevSub) so as to form an intermediate assembly (Set); - a step (140) of fracturing the intermediate assembly (Set) at the level of the weakening plane (Frgl), this step resulting in equipping the device substrate (DevSub) with a ferroelectric layer (DonSub1) transferred from the donor substrate (DonSub) and having a free face (FrFac); - a step (150) of finishing the transferred ferroelectric layer (DonSub1) comprising a heat treatment step (150B) and, after the heat treatment step (150B) (Stab),a step (150C) of thinning (Thin) of the transferred ferroelectric layer (DonSub1) so as to form the single-domain thin film (DevLay), the preparation process being characterized in that the heat treatment (Stab) comprises:- a temperature rise (TmpRs) of the transferred ferroelectric layer (DonSub1) up to a high temperature (HT) between 400°C and the Curie temperature of the ferroelectric material forming the transferred ferroelectric layer (DonSub1); then- a holding (Stp) of the transferred ferroelectric layer at a temperature between the high temperature (HT) and said Curie temperature, for a duration (Δt) greater than or equal to 30 min; then- a temperature drop (Rmp2) of the transferred ferroelectric layer (DonSub1), from the high temperature (HT), in which the temperature rise (TempRs) of the transferred ferroelectric layer (DonSub1) includes a ramp (Rmp1,Rmp1') of temperature ramp carried out at a temperature rate greater than 7°C / min, preferably greater than or equal to 10°C / min, such that the transferred ferroelectric layer reaches a temperature between 400°C and the Curie temperature at the end of the ramp (Rmp1, Rmp1').

2. Method according to claim 1, wherein the temperature ramp of the transferred ferroelectric layer (DonSub1) is parameterized to cause a temperature rise of at least 350°C, preferably 400°C, even more preferably 450°C, of ​​the transferred ferroelectric layer (DonSub1).

3. Method according to claim 1 or 2, wherein the temperature ramp of the transferred ferroelectric layer (DonSub1) is parameterized to start at a temperature (LT1) located between ambient temperature and the high temperature (HT), and cause a temperature rise of at least 100°C.

4. A method according to any one of claims 1 to 3,wherein the thinning step (150C) consists of removing a thickness of the transferred ferroelectric layer (DonSub1) of less than 200 nm, preferably less than 150 nm.

5. A method according to any one of claims 1 to 4, wherein the device substrate (DevSub) equipped with the transferred ferroelectric layer (DonSub1) is placed directly into a furnace while the furnace is at the high temperature (HT).

6. A method according to any one of claims 1 to 4, wherein the device substrate (DevSub) equipped with the transferred ferroelectric layer (DonSub1) is placed into a furnace while the furnace is at a first low temperature (LT1) and removed from the furnace while the furnace is at a second low temperature (LT2), the first low temperature (LT1) and the second low temperature (LT2) each being between ambient temperature and the high temperature, preferably between 100°C and 500°C.even more preferably between 300°C and 400°C.

7. A method according to any one of claims 1 to 6, wherein the single-domain thin film (DevLay) is made of a single-crystal piezoelectric material, such as lithium tantalate or lithium niobate.

8. A method according to any one of claims 1 to 7, wherein the donor substrate (DonSub) is made of a bulk ferroelectric material.

9. A method according to any one of claims 1 to 7, wherein the donor substrate (DonSub) comprises a support substrate (CarSub) supporting a layer (FerroLay) of ferroelectric material, a material forming the donor substrate being distinct from a ferroelectric material forming the layer (FerroLay) of ferroelectric material.

10. A method according to any one of claims 1 to 9,wherein the finishing step (150) of the transferred ferroelectric layer (DonSub1) comprises a surface treatment step (150A) intended to remove a lithium-rich surface layer, and / or remove or prevent the formation of dendrites.

11. A method according to any one of claims 1 to 10, wherein the finishing step (150) of the transferred ferroelectric layer (DonSub1) comprises a surface treatment step (150A) intended to introduce hydrogen onto the surface of the transferred ferroelectric layer (DonSub1) so as to produce a hydrogen concentration greater than 2.10, 21 atoms / cm 3 in a surface thickness of the transferred ferroelectric layer (DonSub1) of less than 200 nm depth.

12. Method according to any one of claims 1 to 11, further comprising a step (110 Don) of forming at least one interlayer (Inter), on at least one face (DonTop) of the donor substrate (DonSub) and one face (DevTop) of the device substrate (DevSub), formed of silicon oxide, silicon nitride, and / or silicon oxynitride.

13. A method according to any one of claims 1 to 12, further comprising a step (110 Dev ) of formation of a layer (TrapLay) of electrical charge trapping on a surface (DevTop) of the device substrate (DevSub), intended to be assembled with the donor substrate (DonSub).

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