Semiconductor die, interposer, and semiconductor device

Abstract

A semiconductor die (10) comprises: a first body (11) having a first surface (12); a plurality of first signal pads (131) and a plurality of second signal pads (132) disposed on the first surface (12); and a plurality of first power supply pads (133) and a plurality of second power supply pads (134) disposed on the first surface (12). The plurality of first signal pads (131) are disposed at positions where the first signal pads are connectable to a first pad (341) via a single bump, the plurality of second signal pads (132) are disposed at positions where the second signal pads are connectable to a second pad (342) via a single bump, the plurality of first power supply pads (133) are disposed at positions where the first power supply pads are connectable to a third pad (343) via a single bump, and the plurality of second power supply pads (134) are disposed at positions where the second power supply pads are connectable to a fourth pad (344) via a single bump.

Description

Semiconductor die, interposer, and semiconductor device

[0001] The present disclosure relates to semiconductor dies and the like.

[0002] In recent years, SoCs (System on Chip), which incorporate various functions such as a CPU, GPU, or memory on a single semiconductor chip, have become widely used. Known SoC manufacturing techniques include fabricating the CPU, GPU, or memory as individual chips (i.e., semiconductor dies) from different wafers and then electrically connecting these chips on a package substrate. Techniques for electrically connecting the semiconductor die to the package substrate include a method in which the semiconductor die is directly mounted on the package substrate and a method in which the semiconductor die is mounted on the package substrate via an interposer.

[0003] When the semiconductor die is directly mounted on the package substrate, C4 (Controlled Collapsed Chip Connection) bumps are arranged on the surface of the package substrate, and the semiconductor die is connected to the package substrate via the C4 bumps (see Patent Document 1).

[0004] When a semiconductor die is mounted on a package substrate via an interposer, microbumps that are smaller in size and spaced closer together than C4 bumps are placed on the surface of the interposer, and the semiconductor die is connected to the interposer via these microbumps (see Patent Document 2).

[0005] Patent No. 3694546 Patent No. 6670749

[0006] The semiconductor die mounted by the method described in Patent Document 1 has the same function as the semiconductor die mounted by the method described in Patent Document 2, but has a different pad layout. Specifically, the pad layout of the former semiconductor die is spaced at intervals for C4 bumps, while the pad layout of the latter semiconductor die is spaced at intervals for microbumps, which is a narrower spacing than the former.

[0007] In other words, when semiconductor dies having the same function are mounted, it is necessary to use semiconductor dies with different pad spacings depending on whether the semiconductor die is mounted directly on the package substrate or mounted on the package substrate via an interposer. In other words, with conventional semiconductor dies, the pad layout of one type cannot be used for both mounting methods.

[0008] The present disclosure has been made to solve such problems, and aims to provide a semiconductor die or the like that can accommodate both mounting methods with a single pad layout.

[0009] In order to achieve the above object, one aspect of a semiconductor die according to the present disclosure is a semiconductor die connectable to a package substrate having first and second pads for transmitting and receiving signals and third and fourth pads for transmitting and receiving power, the semiconductor die comprising: a first body having a planar first surface; a plurality of first signal pads and a plurality of second signal pads arranged on the first surface; and a plurality of first power supply pads and a plurality of second power supply pads arranged on the first surface, wherein the plurality of first signal pads are arranged in positions where they can be connected to the first pads via a single bump, the plurality of second signal pads are arranged in positions where they can be connected to the second pads via a single bump, the plurality of first power supply pads are arranged in positions where they can be connected to the third pads via a single bump, and the plurality of second power supply pads are arranged in positions where they can be connected to the fourth pads via a single bump.

[0010] In order to achieve the above goal, one aspect of the semiconductor device according to the present disclosure comprises the above semiconductor die, and a package substrate having the first pad and the second pad for transmitting and receiving signals, and the third pad and the fourth pad for transmitting and receiving power, wherein the plurality of first signal pads are bump-connected to the first pads, the plurality of second signal pads are bump-connected to the second pads, the plurality of first power supply pads are bump-connected to the third pads, and the plurality of second power supply pads are bump-connected to the fourth pads.

[0011] In order to achieve the above goal, one aspect of a semiconductor device according to the present disclosure comprises the above-mentioned semiconductor die; and an interposer having a plurality of third signal pads and a plurality of fourth signal pads for transmitting and receiving signals, and a plurality of third power supply pads and a plurality of fourth power supply pads for transmitting and receiving power, wherein the plurality of first signal pads are bump-connected to the plurality of third signal pads, the plurality of second signal pads are bump-connected to the plurality of fourth signal pads, the plurality of first power supply pads are bump-connected to the plurality of third power supply pads, and the plurality of second power supply pads are bump-connected to the plurality of fourth power supply pads, and the semiconductor die further comprises a monitor circuit that measures a current flowing between the semiconductor die and the interposer when the semiconductor die transmits and receives signals, and a determination circuit that determines a connection state between the semiconductor die and the interposer based on the current value measured by the monitor circuit.

[0012] To achieve the above object, one aspect of a semiconductor die according to the present disclosure includes a first body having a planar first surface, a plurality of first signal pads and a plurality of second signal pads arranged on the first surface for transmitting and receiving signals, a plurality of first power supply pads and a plurality of second power supply pads arranged on the first surface for transmitting and receiving power, a fifth pad and a sixth pad arranged on the first surface for transmitting and receiving signals, and a seventh pad and an eighth pad arranged on the first surface for transmitting and receiving power, wherein the fifth pad in a plan view of the first surface a dimension of the sixth pad in the plan view of the first surface is larger than a dimension of each of the plurality of first signal pads in the plan view of the first surface, a dimension of the sixth pad in the plan view of the first surface is larger than a dimension of each of the plurality of second signal pads in the plan view of the first surface, a dimension of the seventh pad in the plan view of the first surface is larger than a dimension of each of the plurality of first power supply pads in the plan view of the first surface, and a dimension of the eighth pad in the plan view of the first surface is larger than a dimension of each of the plurality of second power supply pads in the plan view of the first surface. the dimensions of the first signal pads are larger than the dimensions of each of the first and second signal pads, the first signal pads are arranged within a third distance from a third signal virtual point, the fifth pad is arranged within the third distance from the third signal virtual point and is arranged at a position not overlapping any of the first signal pads, the second signal pads are arranged within the third distance from a fourth signal virtual point, and the sixth pad is arranged within the third distance from the fourth signal virtual point and is arranged at a position not overlapping any of the second signal pads. the plurality of first power supply pads are arranged within a fourth distance from a third power supply virtual point, the seventh pad is arranged within the fourth distance from the third power supply virtual point and is arranged at a position not overlapping any of the plurality of first power supply pads, the plurality of second power supply pads are arranged within the fourth distance from a fourth power supply virtual point, and the eighth pad is arranged within the fourth distance from the fourth power supply virtual point and is arranged at a position not overlapping any of the plurality of second power supply pads.

[0013] In order to achieve the above goal, one aspect of a semiconductor device according to the present disclosure comprises the above semiconductor die, and a package substrate having first and second pads for transmitting and receiving signals, and third and fourth pads for transmitting and receiving power, wherein the fifth pad is bump-connected to the first pad, the sixth pad is bump-connected to the second pad, the seventh pad is bump-connected to the third pad, and the eighth pad is bump-connected to the fourth pad.

[0014] In order to achieve the above goal, one aspect of a semiconductor device according to the present disclosure comprises the above semiconductor die, and an interposer having a plurality of third signal pads and a plurality of fourth signal pads for transmitting and receiving signals, and a plurality of third power supply pads and a plurality of fourth power supply pads for transmitting and receiving power, wherein the plurality of first signal pads are bump-connected to the plurality of third signal pads, the plurality of second signal pads are bump-connected to the plurality of fourth signal pads, the plurality of first power supply pads are bump-connected to the plurality of third power supply pads, and the plurality of second power supply pads are bump-connected to the plurality of fourth power supply pads.

[0015] In order to achieve the above-mentioned object, one aspect of the interposer according to the present disclosure is an interposer connectable to a package substrate having first and second pads for transmitting and receiving signals and third and fourth pads for transmitting and receiving power, and connectable to a semiconductor die having ninth and tenth pads for transmitting and receiving signals and eleventh and twelfth pads for transmitting and receiving power, the interposer comprising: a second body having planar second and third surfaces; a plurality of fifth signal pads and a plurality of sixth signal pads arranged on the second surface; a plurality of fifth power supply pads and a plurality of sixth power supply pads arranged on the second surface; and a first pad for transmitting and receiving signals arranged on the third surface. the second surface is a plane opposite to the third surface, the fifth signal pads are arranged in positions where they can be connected to the ninth pad via a plurality of microbumps, the sixth signal pads are arranged in positions where they can be connected to the tenth pad via a plurality of microbumps, the fifth power supply pads are arranged in positions where they can be connected to the eleventh pad via a plurality of microbumps, and the sixth power supply pads are arranged in positions where they can be connected to the twelfth pad via a plurality of microbumps.

[0016] In order to achieve the above goal, one aspect of the semiconductor device according to the present disclosure comprises the above interposer, and a semiconductor die having the ninth and tenth pads for transmitting and receiving signals and the eleventh and twelfth pads for transmitting and receiving power, wherein the fifth signal pads are bump-connected to the ninth pads, the sixth signal pads are bump-connected to the tenth pads, the fifth power supply pads are bump-connected to the eleventh pads, and the sixth power supply pads are bump-connected to the twelfth pads.

[0017] According to the present disclosure, a semiconductor die or the like is provided that can accommodate both mounting methods with a single pad layout.

[0018] FIG. 1 is a schematic diagram illustrating an example of the structure of a semiconductor die according to a first embodiment. FIG. 2 is a plan view of the semiconductor die in a plan view of the bottom surface. FIG. 3 is a schematic diagram illustrating an example of a semiconductor device obtained by directly mounting the semiconductor die illustrated in FIG. 1 on a package substrate. FIG. 4 is a schematic diagram illustrating an example of a circuit used by the semiconductor device illustrated in FIG. 3 to determine a connection state between the semiconductor die and the package substrate. FIG. 5 is a flowchart illustrating a processing procedure performed by the semiconductor device illustrated in FIG. 3 to determine a connection state between the semiconductor die and the package substrate. FIG. 6 is a schematic diagram illustrating an example of a semiconductor device obtained by mounting the semiconductor die illustrated in FIG. 1 on a package substrate via an interposer. FIG. 7 is a schematic diagram illustrating an example of a circuit used by the semiconductor device illustrated in FIG. 6 to determine a connection state between the semiconductor die and the interposer. FIG. 8 is a flowchart illustrating a processing procedure performed by the semiconductor device illustrated in FIG. 6 to determine a connection state between the semiconductor die and the interposer. FIG. 9 is a schematic diagram illustrating an example of the structure of a semiconductor die according to a second embodiment. FIG. 10 is a plan view of the semiconductor die in a plan view of the bottom surface. Fig. 11 is a schematic diagram showing an example of a semiconductor device obtained by directly mounting the semiconductor die shown in Fig. 9 on a package substrate. Fig. 12 is a schematic diagram showing an example of a semiconductor device obtained by mounting the semiconductor die shown in Fig. 9 on a package substrate via an interposer. Fig. 13 is a schematic diagram showing an example of a structure of a semiconductor die according to a third embodiment. Fig. 14 is a schematic diagram showing an example of a structure of an interposer according to the third embodiment. Fig. 15 is a plan view of the semiconductor die in a top plan view. Fig. 16 is a schematic diagram showing an example of a semiconductor device obtained by directly mounting the semiconductor die shown in Fig. 13 on a package substrate. Fig. 17 is a schematic diagram showing an example of a semiconductor device obtained by mounting the semiconductor die shown in Fig. 13 on a package substrate via the interposer shown in Fig. 14.

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below represents a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, the arrangement and connection of the components, processes (steps), and the order of the processes shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Therefore, among the components in the following embodiments, components that are not described in the independent claims that represent the superordinate concept of the present disclosure will be described as optional components.

[0020] Note that each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, the scales and the like do not necessarily match in each figure. Furthermore, in each figure, substantially the same configuration is assigned the same reference numeral, and duplicate explanations are omitted or simplified. Furthermore, in this specification, the terms "up" and "down" do not necessarily refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition.

[0021] Furthermore, in this specification, terms indicating the relationship between elements, such as orthogonal and parallel, terms indicating the shape of elements, such as rectangle, and numerical ranges are not expressions that express only the strict meaning, but are expressions that mean that a substantially equivalent range, for example, a difference of about a few percent, is also included.

[0022] In each drawing, the direction in which semiconductor dies are stacked is defined as the Z direction, and two directions that are included in a plane perpendicular to the Z direction and are orthogonal to each other are defined as the X direction and the Y direction.

[0023] (Embodiment 1) [Semiconductor Die] Fig. 1 is a schematic diagram showing an example of the structure of a semiconductor die 10 according to an embodiment. Note that the wirings 141, 142, 143, and 144 shown in Fig. 1 are not lines showing precise wiring paths, and this also applies to the following drawings. Furthermore, although not shown in Fig. 1, the wirings 141, 142, 143, and 144 may be wirings that pass through elements such as transistors.

[0024] 1, the semiconductor die 10 is a semiconductor chip such as a CPU, GPU, or memory that has a rectangular structure when viewed in a direction parallel to the Y direction. Note that the shape of the semiconductor die 10 when viewed in a direction parallel to the Y direction may be other than rectangular.

[0025] The semiconductor die 10 is a semiconductor chip connectable to a package substrate having first and second pads for transmitting and receiving signals and third and fourth pads for transmitting and receiving power (i.e., pads for connecting a plurality of C4 bumps). The semiconductor die 10 is also a semiconductor chip connectable to an interposer having a plurality of third and fourth signal pads for transmitting and receiving signals and a plurality of third and fourth power supply pads for transmitting and receiving power (i.e., pads for connecting a plurality of microbumps). In this specification, the dimensions of the C4 bumps are described as being 100 μm or more and 130 μm or less, and the dimensions of the microbumps are described as being 25 μm or more and 55 μm or less.

[0026] The semiconductor die 10 also includes a main body 11, a plurality of first signal pads 131, a plurality of second signal pads 132, a plurality of first power supply pads 133, a plurality of second power supply pads 134, wiring 141, 142, 143, and 144, monitor circuits 151 and 152, and judgment circuits 161 and 162.

[0027] The main body 11 is, for example, an element including a semiconductor, and has elements such as transistors and wiring 141 therein. The main body 11 also has a bottom surface 12. In this specification, the main body 11 may be referred to as a "first main body 11."

[0028] The lower surface 12 is one of the surfaces of the main body 11, and is one of the planes perpendicular to the Z direction. In this specification, the lower surface 12 may be referred to as the "first surface 12."

[0029] A plurality of first signal pads 131, a plurality of second signal pads 132, a plurality of first power supply pads 133, and a plurality of second power supply pads 134 are arranged on the lower surface 12 (first surface 12).

[0030] The first signal pads 131 are pads used for bump connection with a package substrate or an interposer, and are pads for transmitting and receiving first signals to and from the package substrate or the interposer. Here, each of the first signal pads 131 is a pad for microbump connection.

[0031] The second signal pads 132 are pads used for bump connection with a package substrate or an interposer, and are pads for transmitting and receiving second signals to and from the package substrate or the interposer. Here, each pad constituting the second signal pads 132 is a pad for microbump connection. The second signal may be the same as the first signal, or may be a different signal.

[0032] The first power supply pads 133 are pads used for bump connection with a package substrate or an interposer, and are pads for transmitting and receiving first power to and from the package substrate or the interposer. Here, each of the first power supply pads 133 is a pad for microbump connection.

[0033] The second power supply pads 134 are pads used for bump connection with the package substrate or interposer, and are pads for transmitting and receiving second power to and from the package substrate or interposer. Here, each pad constituting the second power supply pads 134 is a pad for microbump connection. The second power may be the same as or different from the first power.

[0034] The microbump connection pads are smaller than the C4 bump connection pads. For example, the dimensions of the microbump connection pads may be 55 μm or less. The dimensions of the C4 bump connection pads may be 130 μm or less.

[0035] Here, in order to provide a detailed description of the plurality of first signal pads 131, the plurality of second signal pads 132, the plurality of first power supply pads 133, and the plurality of second power supply pads 134, a description will be made with reference to Fig. 2. Fig. 2 is a plan view of semiconductor die 10 in a plan view of bottom surface 12.

[0036] 2, the first signal pads 131 are arranged within a first distance r1 (i.e., inside the two-dot chain line) from the first signal imaginary point TS1. Although the number of the first signal pads 131 is four in FIG. 2, it is sufficient that the number is at least two.

[0037] The second signal pads 132 are arranged within a first distance r1 (i.e., inside the two-dot chain line) from the second signal imaginary point TS2. Although the number of the second signal pads 132 is four in FIG. 2, it is sufficient that the number is at least two.

[0038] The linear distance d1 between the first signal imaginary point TS1 and the second signal imaginary point TS2 is greater than twice the first distance r1. In other words, the first signal pads 131 and the second signal pads 132 are arranged so that the two-dot chain lines do not contact or intersect with each other.

[0039] The plurality of first power supply pads 133 are arranged within a second distance r2 from the first power supply virtual point TE1 (i.e., inside the two-dot chain line). Although the number of the plurality of first power supply pads 133 is six in FIG. 2, it is sufficient that the number is at least two.

[0040] The second power supply pads 134 are arranged within a second distance r2 from the second power supply virtual point TE2 (i.e., inside the two-dot chain line). Although the number of the second power supply pads 134 is six in FIG. 2, it is sufficient that the number is at least two.

[0041] The linear distance d2 between the first power supply virtual point TE1 and the second power supply virtual point TE2 is greater than twice the second distance r2. In other words, the first power supply pads 133 and the second power supply pads 134 are arranged so that the two-dot chain lines do not contact or intersect with each other.

[0042] The linear distance d3 between the first signal virtual point TS1 and the first power supply virtual point TE1 is greater than twice the first distance r1 and greater than twice the second distance r2. That is, the first signal pads 131 and the first power supply pads 133 are arranged so that the two-dot chain lines do not contact or intersect with each other. Furthermore, the first signal pads 131, the second signal pads 132, the first power supply pads 133, and the second power supply pads 134 are arranged so that the above relationship holds regardless of the linear distance between any signal virtual point and any power supply virtual point.

[0043] The first distance r1 is set so that the plurality of first signal pads 131 or the plurality of second signal pads 132 can contact and bond with one C4 bump. In other words, the plurality of first signal pads 131 are positioned so that they can be connected to the first pads of the package substrate via C4 bumps, and the plurality of second signal pads 132 are positioned so that they can be connected to the second pads of the package substrate via C4 bumps. Note that if the dimensions of the C4 bumps used to bond with the first pads differ from the dimensions of the C4 bumps used to bond with the second pads, the first distance r1 is determined taking into account the size of the smaller C4 bump. As described above, the plurality of first signal pads 131 or the plurality of second signal pads 132 can contact with one C4 bump. On the other hand, the first pad is connected to one C4 bump which is connected to the plurality of first signal pads 131, and the second pad is connected to one C4 bump which is connected to the plurality of second signal pads 132. Because the plurality of first signal pads 131, one C4 bump, and the first pads are connected in the above-described manner, the dimensions of the plurality of first signal pads 131 are generally smaller than the dimensions of the first pads. Similarly, the dimensions of the plurality of second signal pads are smaller than the dimensions of the second pads.

[0044] Furthermore, for example, the first distance r1 may be the sum of the dimensions of the plurality of first signal pads 131 and half the dimensions of the first pads, or the sum of the dimensions of the plurality of second signal pads 132 and half the dimensions of the second pads. Furthermore, the first distance r1 may be the sum of the dimensions of the plurality of first signal pads 131 and half the dimensions of one C4 bump, or the sum of the dimensions of the plurality of second signal pads 132 and half the dimensions of one C4 bump.

[0045] The second distance r2 is set so that the multiple first power supply pads 133 or the multiple second power supply pads 134 can contact and be bonded to one C4 bump. In other words, the multiple first power supply pads 133 are positioned so that they can be connected to the third pads of the package substrate via C4 bumps, and the multiple second power supply pads 134 are positioned so that they can be connected to the fourth pads of the package substrate via C4 bumps. If the dimensions of the C4 bumps used to bond the third pads and the C4 bumps used to bond the fourth pads differ, the second distance r2 is determined taking into account the size of the smaller C4 bump. As described above, the multiple first power supply pads 133 or the multiple second power supply pads 134 can contact one C4 bump. Meanwhile, the third pad is connected to one C4 bump connected to the multiple first power supply pads 133, and the fourth pad is connected to one C4 bump connected to the multiple second power supply pads 134. Since the first power supply pads 133, one C4 bump, and the third pad are connected as described above, the dimensions of the first power supply pads 133 are generally smaller than the dimensions of the third pad. Similarly, the dimensions of the second power supply pads 134 are smaller than the dimensions of the fourth pad.

[0046] Furthermore, for example, the second distance r2 may be the total length of the dimensions of the plurality of first power supply pads 133 and half the dimension of the third pad, or the total length of the dimensions of the plurality of second power supply pads 134 and half the dimension of the fourth pad. Furthermore, the second distance r2 may be the total length of the dimensions of the plurality of second power supply pads 134 and half the dimension of one C4 bump, or the total length of the dimensions of the plurality of second power supply pads 134 and half the dimension of one C4 bump.

[0047] Although the semiconductor die 10 has a plurality of first signal pads 131 and a plurality of second signal pads 132 for transmitting and receiving the first signal and the second signal in the above embodiment, it may have a plurality of signal pads, for example, three or more. Also, although the semiconductor die 10 has a plurality of first power supply pads 133 and a plurality of second power supply pads 134 for transmitting and receiving the first power and the second power in the above embodiment, it may have a plurality of power supply pads, for example, three or more.

[0048] Furthermore, since the amount of current that flows during power transmission is greater than that during signal transmission, it is preferable that the number of first power supply pads 133 be equal to or greater than the number of first signal pads 131 and equal to or greater than the number of second signal pads 132. For the same reason, it is preferable that the number of second power supply pads 134 be equal to or greater than the number of first signal pads 131 and equal to or greater than the number of second signal pads 132.

[0049] 2 shows the case where the first signal pads 131 are arranged concentrically around the first signal virtual point TS1, but they may be arranged within the first distance r1 from the first signal virtual point TS1. The same applies to the second signal pads 132, the first power supply pads 133, and the second power supply pads 134.

[0050] 2 shows the case where the first signal pads 131 are circular, the first signal pads 131 may be polygonal, for example, as long as they can be connected to the first pads of the package substrate via C4 bumps. The same applies to the second signal pads 132, the first power supply pads 133, and the second power supply pads 134.

[0051] 2 shows the case where the first signal pads 131 are all identical in size and shape, but they do not have to be identical. The same applies to the second signal pads 132, the first power supply pads 133, and the second power supply pads 134.

[0052] Furthermore, since the first signal pads 131 are arranged within the first distance r1, each of the first signal pads 131 can be brought into contact with a C4 bump probe at the same time. This makes it possible to determine whether the semiconductor die 10 is defective even using a C4 bump probe that is generally used in chip inspection. The same is true for the second signal pads 132, the first power supply pads 133, and the second power supply pads 134.

[0053] Furthermore, the first distance r1 may be the same as the second distance r2, or may be different from the second distance r2.

[0054] Returning to the explanation of FIG. 1, the wiring 141 is a wiring that is electrically connected to the plurality of first signal pads 131 .

[0055] The wiring 142 is electrically connected to the plurality of second signal pads 132 .

[0056] The wiring 143 is electrically connected to the plurality of first power supply pads 133 .

[0057] The wiring 144 is electrically connected to the plurality of second power supply pads 134 .

[0058] When the semiconductor die 10 is directly mounted on a package substrate, the monitor circuit 151 measures the current flowing between the semiconductor die 10 and the package substrate when the semiconductor die 10 exchanges signals. When the semiconductor die 10 is mounted on the package substrate via an interposer, the monitor circuit 151 measures the current flowing between the semiconductor die 10 and the interposer when the semiconductor die 10 exchanges signals. The monitor circuit 152 has the same function as the monitor circuit 151.

[0059] 1 also shows a case where the semiconductor die 10 includes monitor circuits 151 and 152. Specifically, the monitor circuit 151 is connected to the wiring 141 and measures the current flowing through the plurality of first signal pads 131. The monitor circuit 152 is connected to the wiring 142 and measures the current flowing through the plurality of second signal pads 132.

[0060] When the semiconductor die 10 is directly mounted on the package substrate, the determination circuit 161 determines the connection state between the semiconductor die 10 and the package substrate based on the current value measured by the monitor circuit 151 or the monitor circuit 152. When the semiconductor die 10 is mounted on the package substrate via an interposer, the determination circuit 161 determines the connection state between the semiconductor die 10 and the interposer based on the current value measured by the monitor circuit 151 or the monitor circuit 152. The determination circuit 162 has the same function as the determination circuit 161.

[0061] Furthermore, the determination circuit 161 outputs the determination result to an external device, thereby notifying the user of the connection state between the semiconductor die 10 and the package substrate or the connection state between the semiconductor die 10 and the interposer.

[0062] 1 also shows a case where the semiconductor die 10 includes determination circuits 161 and 162. Specifically, the determination circuit 161 is connected to the monitor circuit 151. The determination circuit 162 is connected to the monitor circuit 152.

[0063] The semiconductor die 10 only needs to include one or more monitor circuits so that, when transmitting and receiving signals, the currents flowing through each of the plurality of first signal pads 131 and the plurality of second signal pads 132 can be measured. The semiconductor die 10 only needs to include the same number of determination circuits as the number of monitor circuits.

[0064] [Semiconductor Device (When the Semiconductor Die is Directly Mounted on the Package Substrate)] The structure of a semiconductor device obtained by directly mounting the above-described semiconductor die 10 on a package substrate 30 will be described with reference to Fig. 3. Fig. 3 is a schematic diagram showing an example of a semiconductor device 20 obtained by directly mounting the semiconductor die 10 shown in Fig. 1 on a package substrate 30.

[0065] 3 , semiconductor device 20 is composed of semiconductor die 10 and package substrate 30. Semiconductor device 20 is an SoC in which semiconductor die 10 is directly mounted on package substrate 30 via a plurality of C4 bumps 50.

[0066] The C4 bumps 50 are made of a metal material such as Cu, Ag, Ni, or solder materials such as Sn--Ag--Cu, Sn--Pb, etc. The dimensions of the C4 bumps 50 are between 100 μm and 130 μm.

[0067] The package substrate 30 is a substrate that protects a semiconductor chip such as the semiconductor die 10 and electrically connects it to an external printed wiring board.

[0068] The package substrate 30 includes a main body 31, a first pad 341, a second pad 342, a third pad 343, a fourth pad 344, and C4 bump pads 351, 352, 353, and 354. The first pad 341, the second pad 342, the third pad 343, the fourth pad 344, and the C4 bump pads 351, 352, 353, and 354 are pads for connecting C4 bumps.

[0069] The first pad 341 and the second pad 342 are signal pads, and the third pad 343 and the fourth pad 344 are power supply pads.

[0070] The main body 31 is, for example, an element including a semiconductor, and contains elements such as transistors, wiring, etc. The main body 31 also has an upper surface 32 and a lower surface 33.

[0071] The upper surface 32 is one of the surfaces of the main body 31 and is one of the planes perpendicular to the Z direction.

[0072] The lower surface 33 is one of the surfaces of the main body 31 and is one of the planes perpendicular to the Z direction. The lower surface 33 is also a surface opposite to the upper surface 32.

[0073] The first pad 341 , the second pad 342 , the third pad 343 , and the fourth pad 344 are disposed on the upper surface 32 .

[0074] The first pad 341 is a pad used for bump connection with the semiconductor die 10 or an interposer (described later), and is a pad for transmitting and receiving a first signal with the semiconductor die 10 or the interposer. The first pad 341 is also bump-connected to a plurality of first signal pads 131 via one C4 bump 50.

[0075] The second pad 342 is a pad used for bump connection with the semiconductor die 10 or the interposer, and is a pad for transmitting and receiving a second signal with the semiconductor die 10 or the interposer. The second pad 342 is also bump-connected to a plurality of second signal pads 132 via one C4 bump 50.

[0076] The third pad 343 is a pad used for bump connection with the semiconductor die 10 or the interposer, and is a pad for transmitting and receiving first power to and from the semiconductor die 10 or the interposer. The third pad 343 is also bump-connected to the plurality of first power supply pads 133 via one C4 bump 50.

[0077] The fourth pad 344 is a pad used for bump connection with the semiconductor die 10 or the interposer, and is a pad for transmitting and receiving second power to and from the semiconductor die 10 or the interposer. The fourth pad 344 is also bump-connected to the plurality of second power supply pads 134 via one C4 bump 50.

[0078] Bump pads 351 , 352 , 353 , and 354 are disposed on the lower surface 33 .

[0079] The bump pads 351 are pads used for bump connection with a printed wiring board, and are pads for transmitting and receiving first signals to and from the printed wiring board.

[0080] The bump pads 352 are pads used for bump connection with a printed wiring board, and are pads for transmitting and receiving second signals to and from the printed wiring board.

[0081] The bump pads 353 are pads used for bump connection with a printed wiring board, and are pads for transmitting and receiving first power to and from the printed wiring board.

[0082] The bump pads 354 are pads used for bump connection with a printed wiring board, and are pads for transmitting and receiving second power to and from the printed wiring board.

[0083] The package substrate 30 may have signal pads and bump pads according to the number of signals to be exchanged with the semiconductor die 10. The package substrate 30 may also have power supply pads and bump pads according to the number of power sources to be exchanged with the semiconductor die 10.

[0084] 3 shows an example in which multiple C4 bumps 50 are used for bump connection between semiconductor die 10 and package substrate 30, but multiple microbumps may be used for the bump connection. For example, first pad 341 may be bump-connected to multiple first signal pads 131 via multiple microbumps.

[0085] Next, the operations performed by the semiconductor device 20 described above will be described with reference to FIGS.

[0086] Fig. 4 is a schematic diagram showing an example of a circuit used by the semiconductor device 20 shown in Fig. 3 when determining the connection state between the semiconductor die 10 and the package substrate 30. Note that Fig. 4 only shows the circuit used when the semiconductor die 10 sends and receives signals. Furthermore, the circuit shown in Fig. 4 does not show lines indicating an accurate wiring path, but may instead show wiring that passes through other elements, for example.

[0087] 4 , monitor circuit 151 is electrically connected to a plurality of first signal pads 131, which are bump-connected to first pads 341, via wiring 141. Furthermore, first pads 341 are electrically connected to bump pads 351 via wiring 361. By having the above-described wiring in semiconductor device 20, monitor circuit 151 can measure the current flowing between semiconductor die 10 and package substrate 30 when a first signal is input from bump pad 351.

[0088] Furthermore, monitor circuit 152 is electrically connected to a plurality of second signal pads 132 that are bump-connected to second pads 342 via wiring 142. Second pads 342 are electrically connected to bump pads 352 via wiring 362. By having the above-described wiring in semiconductor device 20, monitor circuit 152 can measure the current flowing between semiconductor die 10 and package substrate 30 when a second signal is input from bump pad 352.

[0089] 5 is a flowchart showing the processing steps executed by the semiconductor device 20 shown in FIG. 3 when determining the connection state between the semiconductor die 10 and the package substrate 30. Note that, although FIG. 5 explains the processing steps executed by the monitor circuit 151 and the determination circuit 161, in each step, the "monitor circuit 151" may be replaced with the "monitor circuit 152," and the "determination circuit 161" may be replaced with the "determination circuit 162."

[0090] First, the monitor circuit 151 starts measuring the current for all connections to be monitored (S101). In the example shown in Fig. 3, the monitor circuit 151 measures the current for the connections between the plurality of first signal pads 131 and the first pad 341, and the monitor circuit 152 measures the current for the connections between the plurality of second signal pads 132 and the second pad 342.

[0091] The monitor circuit 151 measures the current flowing between the semiconductor die 10 and the package substrate 30 for one connection (S102) and stores the current value measured in S102 in a memory or the like (not shown) possessed by the semiconductor die 10 (S103).

[0092] If the monitor circuit 151 has not yet measured the current for all connections that are the subject of monitoring (S104), the process returns to S101, and the current measurement is repeated (S101 to S103).

[0093] When the monitor circuit 151 has measured the current for all connections to be monitored, the monitor circuit 151 starts measuring the current for all connections to be monitored at the timing to determine the connection state between the semiconductor die 10 and the package substrate 30 (S105). The timing to determine the connection state may be the timing when power is supplied to the semiconductor device 20, or may be at predetermined intervals.

[0094] The monitor circuit 151 measures the current flowing between the semiconductor die 10 and the package substrate 30 for one connection (S106).

[0095] The determination circuit 161 reads out the current value stored in S103 and compares it with the current value measured in S106 (S107). For example, the determination circuit 161 calculates the difference between the former current value and the latter current value.

[0096] The determination circuit 161 identifies the number of abnormal connections based on the result of the comparison in S107 (S108) and stores the number of abnormal connections identified in S108 in a memory or the like included in the semiconductor die 10 (S109). In the example shown in Fig. 3, the determination circuit 161 identifies the number of abnormal connections among the connections between the multiple first signal pads 131 and the first pad 341, and the determination circuit 162 identifies the number of abnormal connections among the connections between the multiple second signal pads 132 and the second pad 342. Furthermore, for example, the determination circuit 161 converts the current value stored in S103 into a current value per pad and calculates how many times the converted current value corresponds to the difference in the current values ​​calculated in S107, thereby identifying the number of abnormal connections.

[0097] If the monitor circuit 151 has not yet measured the current for all connections that are the subject of monitoring (S110), the process returns to S105, and the current measurement and connection state determination are repeated (S105 to S109).

[0098] When the monitor circuit 151 has measured the current for all connections that are the targets of monitoring, the determination circuit 161 performs processing according to the number of abnormal connections for each target of monitoring (S111). For example, if the number of abnormal connections for each target of monitoring is zero, the determination circuit 161 terminates its operation. Furthermore, for example, if the number of abnormal connections for each target of monitoring exceeds a predetermined number, the determination circuit 161 outputs the results to an external device and issues a warning to the user.

[0099] The semiconductor device 20 may execute S101 to S104 only once in advance, and execute S105 to S111 at any timing (for example, when power is supplied to the semiconductor device 20 or at predetermined intervals).

[0100] Furthermore, steps S105 to S111 may be performed on the semiconductor device 20 before the semiconductor device 20 is mounted on a printed wiring board, thereby enabling the semiconductor device 20 to notify the user whether the semiconductor device 20 is defective or not before the user mounts the semiconductor device 20 on a printed wiring board, thereby improving yield.

[0101] Furthermore, semiconductor device 20 may execute steps S105 to S111 at any timing after being mounted on a printed wiring board, thereby enabling semiconductor device 20 to show the user the change over time in the connection state between semiconductor die 10 and package substrate 30, thereby providing the user with information necessary for predicting failures.

[0102] [Semiconductor Device (When a Semiconductor Die is Mounted on a Package Substrate via an Interposer)] The structure of a semiconductor device obtained by mounting the above-described semiconductor die 10 on a package substrate 30 via an interposer 40 will be described with reference to Fig. 6. Fig. 6 is a schematic diagram showing an example of a semiconductor device 20 obtained by mounting the semiconductor die 10 shown in Fig. 1 on a package substrate 30 via an interposer 40. Note that components similar to those in the semiconductor device 20 shown in Fig. 3 have already been described and are therefore assigned the same reference numerals, and their description will be omitted. The following description will focus on the differences from the semiconductor device 20 shown in Fig. 3.

[0103] The semiconductor device 20 is composed of at least a semiconductor die 10 and an interposer 40. As shown in Fig. 6, the semiconductor device 20 may also include a package substrate 30 and a semiconductor die 100. Instead of the semiconductor die 100, a semiconductor chip having the same configuration as the semiconductor die 10 may be used.

[0104] Furthermore, the semiconductor device 20 is a SoC in which the semiconductor die 10 is mounted on the interposer 40 via a plurality of microbumps 60, and the interposer 40 is mounted on the package substrate 30 via a plurality of C4 bumps 50.

[0105] The microbumps 60 are made of a metal material such as Cu, Ag, Ni, or solder-based materials such as Sn--Ag--Cu, Sn--Pb, etc. The dimensions of the microbumps 60 are 25 μm or more and 55 μm or less.

[0106] Semiconductor die 100 is a conventional semiconductor chip that is used when mounted on package substrate 30 via interposer 40 .

[0107] The semiconductor die 100 includes a body 110 and a plurality of eighth signal pads 135. The eighth signal pads 135 are pads for microbump connection.

[0108] The main body 110 is, for example, an element including a semiconductor, and contains elements such as transistors, wiring, etc. The main body 110 also has a bottom surface 120.

[0109] The lower surface 120 is one surface of the main body 110 and is one of the planes perpendicular to the Z direction.

[0110] The eighth signal pads 135 are pads used for bump connection with the interposer 40, and are pads for transmitting and receiving a third signal to and from the interposer. The eighth signal pads 135 are also arranged on the lower surface 120.

[0111] The interposer 40 is a substrate that electrically connects the semiconductor die 10 or the semiconductor die 100 to the package substrate 30 .

[0112] The interposer 40 includes a main body 41, a plurality of third signal pads 441, a plurality of fourth signal pads 442, a plurality of third power supply pads 443, a plurality of fourth power supply pads 444, a plurality of seventh signal pads 445, a thirteenth pad 451, a fourteenth pad 452, a fifteenth pad 453, a sixteenth pad 454, and a seventeenth pad 455. Note that the interposer 40 does not necessarily have to include the seventh signal pads 445 and the seventeenth pad 455.

[0113] The third signal pads 441, the fourth signal pads 442, the third power supply pads 443, the fourth power supply pads 444, and the seventh signal pads 445 are pads for microbump connection, and the thirteenth pad 451, the fourteenth pad 452, the fifteenth pad 453, the sixteenth pad 454, and the seventeenth pad 455 are pads for C4 bump connection.

[0114] The thirteenth pad 451, the fourteenth pad 452, and the seventeenth pad 455 are signal pads, and the fifteenth pad 453 and the sixteenth pad 454 are power supply pads.

[0115] The main body 41 is, for example, an element including a semiconductor, and has elements such as transistors and wiring therein. The main body 41 also has an upper surface 42 and a lower surface 43. In this specification, the main body 41 may be referred to as a "second main body 41."

[0116] The top surface 42 is one of the surfaces of the main body 41, and is one of the planes perpendicular to the Z direction. In this specification, the top surface 42 may be referred to as the "second surface 42."

[0117] The lower surface 43 is one of the surfaces of the main body 41, and is one of the planes perpendicular to the Z direction. The lower surface 43 is also a surface opposite to the upper surface 42. In this specification, the lower surface 43 may be referred to as the "third surface 43."

[0118] A plurality of third signal pads 441, a plurality of fourth signal pads 442, a plurality of third power supply pads 443, a plurality of fourth power supply pads 444, and a plurality of seventh signal pads 445 are arranged on the upper surface 42.

[0119] The plurality of third signal pads 441 are pads used for bump connection with the semiconductor die 10, and are pads for transmitting and receiving first signals to and from the semiconductor die 10. The plurality of third signal pads 441 are also bump-connected to the plurality of first signal pads 131 via the plurality of microbumps 60.

[0120] The plurality of fourth signal pads 442 are pads used for bump connection with the semiconductor die 10, and are pads for transmitting and receiving second signals to and from the semiconductor die 10. The plurality of fourth signal pads 442 are also bump-connected to the plurality of second signal pads 132 via the plurality of microbumps 60.

[0121] The plurality of third power supply pads 443 are pads used for bump connection with the semiconductor die 10, and are pads for transmitting and receiving first power to and from the semiconductor die 10. The plurality of third power supply pads 443 are also bump-connected to the plurality of first power supply pads 133 via the plurality of microbumps 60.

[0122] The plurality of fourth power supply pads 444 are pads used for bump connection with the semiconductor die 10, and are pads for transmitting and receiving second power to and from the semiconductor die 10. The plurality of fourth power supply pads 444 are also bump-connected to the plurality of second power supply pads 134 via the plurality of microbumps 60.

[0123] The seventh signal pads 445 are pads used for bump connection with the semiconductor die 100, and are pads for transmitting and receiving a third signal to and from the semiconductor die 100. The seventh signal pads 445 are also connected to the eighth signal pads 135 via the microbumps 60.

[0124] The thirteenth pad 451 , the fourteenth pad 452 , the fifteenth pad 453 , the sixteenth pad 454 , and the seventeenth pad 455 are disposed on the lower surface 43 .

[0125] The thirteenth pad 451 is a pad used for bump connection with the package substrate 30 , and is a pad for transmitting and receiving a first signal to and from the package substrate 30 .

[0126] The fourteenth pad 452 is a pad used for bump connection with the package substrate 30 , and is a pad for transmitting and receiving a second signal to and from the package substrate 30 .

[0127] The fifteenth pad 453 is a pad used for bump connection with the package substrate 30 , and is a pad for transmitting and receiving the first power to and from the package substrate 30 .

[0128] The sixteenth pad 454 is a pad used for bump connection with the package substrate 30 , and is a pad for transmitting and receiving second power to and from the package substrate 30 .

[0129] The seventeenth pad 455 is a pad used for bump connection with the package substrate 30 , and is a pad for transmitting and receiving a third signal to and from the package substrate 30 .

[0130] The package substrate 30 further includes an 18th pad 345 disposed on the upper surface 32 and a C4 bump pad 355 disposed on the lower surface 33. The 18th pad 345 and the C4 bump pad 355 are pads for connecting a C4 bump. The 18th pad 345 is a signal pad.

[0131] The first pad 341 is bump-connected to the thirteenth pad 451 via one C4 bump 50 .

[0132] The second pad 342 is bump-connected to the fourteenth pad 452 via one C4 bump 50 .

[0133] The third pad 343 is bump-connected to the fifteenth pad 453 via one C4 bump 50 .

[0134] The fourth pad 344 is bump-connected to the sixteenth pad 454 via one C4 bump 50 .

[0135] The 18th pad 345 is a pad used for bump connection with the interposer 40, and is a pad for transmitting and receiving a third signal to and from the interposer 40. The 18th pad 345 is also connected to the 17th pad 455 via one C4 bump 50.

[0136] The C4 bump pad 355 is a pad used for bump connection with a printed wiring board, and is a pad for sending and receiving a third signal to and from the printed wiring board.

[0137] 3 shows an example in which multiple microbumps 60 are used for bump connection between the semiconductor die 10 and the interposer 40, but multiple C4 bumps 50 may be used for the bump connection. For example, multiple first signal pads 131 may be bump-connected to multiple third signal pads 441 via one C4 bump 50.

[0138] Next, the operation performed by the semiconductor device 20 described above will be described with reference to FIGS.

[0139] Fig. 7 is a schematic diagram showing an example of a circuit used by the semiconductor device 20 shown in Fig. 6 when determining the connection state between the semiconductor die 10 and the interposer 40. Note that Fig. 7 only shows the circuit used when the semiconductor die 10 sends and receives signals. Furthermore, the circuit shown in Fig. 7 does not represent a line showing an accurate wiring path, but may represent, for example, wiring passing through other elements.

[0140] 7 , monitor circuit 151 is electrically connected to a plurality of first signal pads 131, which are bump-connected to a plurality of third signal pads 441, via wiring 141. Furthermore, the plurality of third signal pads 441 are electrically connected to a thirteenth pad 451, which is bump-connected to a first pad 341, via wiring 461. Furthermore, first pad 341 is electrically connected to bump pad 351 via wiring 361. By having the above-described wiring in semiconductor device 20, monitor circuit 151 can measure the current flowing between semiconductor die 10 and interposer 40 when a first signal is input from bump pad 351.

[0141] Furthermore, monitor circuit 152 is electrically connected to a plurality of second signal pads 132, which are bump-connected to a plurality of fourth signal pads 442, via wiring 142. Furthermore, the plurality of fourth signal pads 442 are electrically connected to a plurality of seventh signal pads 445, which are bump-connected to a plurality of eighth signal pads 135, via wiring 462. By having the above-described wiring in semiconductor device 20, monitor circuit 152 can measure the current flowing between semiconductor die 10 and interposer 40 when a signal is exchanged between semiconductor die 10 and semiconductor die 100.

[0142] 8 is a flowchart showing the processing steps executed by the semiconductor device 20 shown in FIG. 6 when determining the connection state between the semiconductor die 10 and the interposer 40. Note that, in FIG. 8, the processing steps executed by the monitor circuit 151 and the determination circuit 161 are explained, but in each step, the "monitor circuit 151" may be replaced with the "monitor circuit 152," and the "determination circuit 161" may be replaced with the "determination circuit 162."

[0143] 6, the monitor circuit 151 measures the current for the connection between the plurality of first signal pads 131 and the plurality of third signal pads 441, and the monitor circuit 152 measures the current for the connection between the plurality of second signal pads 132 and the plurality of fourth signal pads 442.

[0144] The monitor circuit 151 measures the current flowing between the semiconductor die 10 and the interposer 40 for one connection (S202) and stores the current value measured in S202 in a memory or the like (not shown) possessed by the semiconductor die 10 (S203).

[0145] If the monitor circuit 151 has not yet measured the current for all connections that are the subject of monitoring (S204), the process returns to S201, and the current measurement is repeated (S201 to S203).

[0146] When the monitor circuit 151 has measured the current for all connections to be monitored, the monitor circuit 151 starts measuring the current for all connections to be monitored at the timing to determine the connection state between the semiconductor die 10 and the interposer 40 (S205). The timing to determine the connection state may be the timing when power is supplied to the semiconductor device 20, or may be at predetermined intervals.

[0147] The monitor circuit 151 measures the current flowing between the semiconductor die 10 and the interposer 40 for one connection (S206).

[0148] The determination circuit 161 reads out the current value stored in S203 and compares it with the current value measured in S206 (S207). For example, the determination circuit 161 calculates the difference between the former current value and the latter current value.

[0149] The determination circuit 161 identifies the number of abnormal connections based on the result of the comparison in S207 (S208) and stores the number of abnormal connections identified in S208 in a memory or the like included in the semiconductor die 10 (S209). In the example shown in Fig. 6, the determination circuit 161 identifies the number of abnormal connections among the connections between the plurality of first signal pads 131 and the plurality of third signal pads 441, and the determination circuit 162 identifies the number of abnormal connections among the connections between the plurality of second signal pads 132 and the plurality of fourth signal pads 442. Furthermore, for example, the determination circuit 161 converts the current value stored in S203 into a current value per pad and calculates how many times the converted current value corresponds to the difference in the current values ​​calculated in S207, thereby identifying the number of abnormal connections.

[0150] If the monitor circuit 151 has not yet measured the current for all connections that are the subject of monitoring (S210), the process returns to S205, and the current measurement and connection state determination are repeated (S205 to S209).

[0151] When the monitor circuit 151 has measured the current for all connections that are the targets of monitoring, the determination circuit 161 performs processing according to the number of abnormal connections for each target of monitoring (S211). For example, if the number of abnormal connections for each target of monitoring is zero, the determination circuit 161 terminates its operation. Furthermore, for example, if the number of abnormal connections for each target of monitoring exceeds a predetermined number, the determination circuit 161 outputs the results to an external device and issues a warning to the user.

[0152] The semiconductor device 20 may execute S201 to S204 only once in advance, and execute S205 to S211 at any timing (for example, when power is supplied to the semiconductor device 20 or at predetermined intervals).

[0153] Furthermore, steps S205 to S211 may be performed on the semiconductor device 20 before the semiconductor device 20 is mounted on a printed wiring board, thereby enabling the semiconductor device 20 to notify the user whether the semiconductor device 20 is defective or not before the user mounts the semiconductor device 20 on a printed wiring board, thereby improving yield.

[0154] Furthermore, semiconductor device 20 may execute steps S205 to S211 at any timing after being mounted on a printed wiring board, thereby enabling semiconductor device 20 to show the user the change over time in the connection state between semiconductor die 10 and interposer 40, thereby providing the user with information necessary for predicting failures.

[0155] [Effects, etc.] As described above, the semiconductor die 10 according to this embodiment is a semiconductor die 10 connectable to a package substrate 30 having first pads 341 and second pads 342 for transmitting and receiving signals and third pads 343 and fourth pads 344 for transmitting and receiving power, and includes a first body 11 having a planar first surface 12, a plurality of first signal pads 131 and a plurality of second signal pads 132 arranged on the first surface 12, a plurality of first power supply pads 133 and a plurality of second power supply pads 134 arranged on the first surface 12, and a plurality of second power supply pads 135 and a plurality of third power supply pads 136 arranged on the first surface 12. and a power supply pad 134, in which the plurality of first signal pads 131 are arranged at positions where they can be connected to a first pad 341 via one bump, the plurality of second signal pads 132 are arranged at positions where they can be connected to a second pad 342 via one bump, the plurality of first power supply pads 133 are arranged at positions where they can be connected to a third pad 343 via one bump, and the plurality of second power supply pads 134 are arranged at positions where they can be connected to a fourth pad 344 via one bump.

[0156] According to this, when the semiconductor die 10 is mounted directly on the package substrate 30, the plurality of first signal pads 131 are bump-connected to the first pads 341 of the package substrate 30. When the semiconductor die 10 is mounted on the package substrate 30 via the interposer 40, the plurality of first signal pads 131 are bump-connected to the pads for microbump connection (the plurality of third signal pads 441) of the interposer 40. This also applies to the plurality of second signal pads 132, the plurality of first power supply pads 133, and the plurality of second power supply pads 134. Therefore, the semiconductor die 10 can be adapted to both mounting methods with a single pad layout.

[0157] Furthermore, in the semiconductor die 10 according to this embodiment, the plurality of first signal pads 131 are arranged within a first distance r1 from the first signal virtual point TS1, the plurality of second signal pads 132 are arranged within the first distance r1 from the second signal virtual point TS2, the plurality of first power supply pads 133 are arranged within a second distance r2 from the first power supply virtual point TE1, the plurality of second power supply pads 134 are arranged within the second distance r2 from the second power supply virtual point TE2, the linear distance d1 between the first signal virtual point TS1 and the second signal virtual point TS2 is greater than twice the first distance r1, and the linear distance d2 between the first power supply virtual point TE1 and the second power supply virtual point TE2 is greater than twice the second distance r2.

[0158] According to this, since the linear distance d1 is greater than twice the first distance r1 and the linear distance d2 is greater than twice the second distance r2, the semiconductor die 10 is properly bump-connected to either the package substrate 30 or the interposer 40. Therefore, one pad layout can accommodate both mounting methods.

[0159] Furthermore, in the semiconductor die 10 according to this embodiment, the linear distance d3 between the first signal virtual point TS1 and the first power supply virtual point TE1 is greater than twice the first distance r1, and the linear distance d3 between the first signal virtual point TS1 and the first power supply virtual point TE1 is greater than twice the second distance r2.

[0160] According to this, since the linear distance d3 is greater than twice the first distance r1 and greater than twice the second distance r2, the semiconductor die 10 is properly bump-connected to either the package substrate 30 or the interposer 40. Therefore, one pad layout can accommodate both mounting methods.

[0161] Furthermore, in the semiconductor die 10 according to this embodiment, the number of the plurality of first power supply pads 133 is equal to or greater than the number of the plurality of first signal pads 131, the number of the plurality of first power supply pads 133 is equal to or greater than the number of the plurality of second signal pads 132, the number of the plurality of second power supply pads 134 is equal to or greater than the number of the plurality of first signal pads 131, and the number of the plurality of second power supply pads 134 is equal to or greater than the number of the plurality of second signal pads 132.

[0162] As a result, the plurality of first power supply pads 133 can pass a larger current than the plurality of first signal pads 131 and the plurality of second signal pads 132. Similarly, the plurality of second power supply pads 134 can pass a larger current than the plurality of first signal pads 131 and the plurality of second signal pads 132.

[0163] Furthermore, in the semiconductor die 10 according to this embodiment, the plurality of first signal pads 131, the plurality of second signal pads 132, the plurality of first power supply pads 133, and the plurality of second power supply pads 134 are pads for microbump connection, one bump is a C4 bump 50, and the first pad 341, the second pad 342, the third pad 343, and the fourth pad 344 are pads for C4 bump connection.

[0164] According to this, when the semiconductor die 10 is mounted directly on the package substrate 30, the plurality of first signal pads 131 are bump-connected to the first pads 341 of the package substrate 30. When the semiconductor die 10 is mounted on the package substrate 30 via the interposer 40, the plurality of first signal pads 131 are bump-connected to the pads for microbump connection (the plurality of third signal pads 441) of the interposer 40. This also applies to the plurality of second signal pads 132, the plurality of first power supply pads 133, and the plurality of second power supply pads 134. Therefore, the semiconductor die 10 can be adapted to both mounting methods with a single pad layout.

[0165] Furthermore, in the semiconductor die 10 according to this embodiment, the first distance r1 is set so that a plurality of first signal pads 131 and a plurality of second signal pads 132 can contact one C4 bump 50, and the second distance r2 is set so that a plurality of first power supply pads 133 and a plurality of second signal pads 134 can contact one C4 bump 50.

[0166] According to this, the plurality of first signal pads 131 and the plurality of second signal pads 132 are arranged so as to be in contact with one C4 bump 50, and the plurality of first power supply pads 133 and the plurality of second power supply pads 134 are arranged so as to be in contact with one C4 bump 50. Therefore, even when the semiconductor die 10 is directly mounted on the package substrate 30, more accurate mounting can be achieved.

[0167] Furthermore, the semiconductor device 20 according to this embodiment comprises the semiconductor die 10 according to this embodiment, and a package substrate 30 having first pads 341 and second pads 342 for transmitting and receiving signals, and third pads 343 and fourth pads 344 for transmitting and receiving power, wherein the plurality of first signal pads 131 are bump-connected to the first pads 341, the plurality of second signal pads 132 are bump-connected to the second pads 342, the plurality of first power supply pads 133 are bump-connected to the third pads 343, and the plurality of second power supply pads 134 are bump-connected to the fourth pads 344.

[0168] As a result, the semiconductor device 20 achieves the same effects as the semiconductor die 10 according to the present embodiment.

[0169] Furthermore, a semiconductor device 20 according to this embodiment includes a semiconductor die 10 according to this embodiment, and an interposer 40 having a plurality of third signal pads 441 and a plurality of fourth signal pads 442 for transmitting and receiving signals, and a plurality of third power supply pads 443 and a plurality of fourth power supply pads 444 for transmitting and receiving power, wherein the plurality of first signal pads 131 are bump-connected to the plurality of third signal pads 441, and the plurality of second signal pads 132 are bump-connected to the plurality of fourth signal pads 442. The plurality of first power supply pads 133 are bump-connected to the plurality of third power supply pads 443, and the plurality of second power supply pads 134 are bump-connected to the plurality of fourth power supply pads 444. The semiconductor die 10 further includes a monitor circuit 151 that measures the current flowing between the semiconductor die 10 and the interposer 40 when the semiconductor die 10 exchanges signals, and a determination circuit 161 that determines the connection state between the semiconductor die 10 and the interposer 40 based on the current value measured by the monitor circuit 151.

[0170] As a result, the semiconductor device 20 has the same effects as the semiconductor die 10 according to the present embodiment. Furthermore, since the semiconductor device 20 includes the monitor circuit 151 and the determination circuit 161, it is possible to determine the connection state between the semiconductor die 10 and the interposer 40.

[0171] Furthermore, in the semiconductor device 20 according to this embodiment, the judgment circuit 161 determines the number of abnormal connections among the connections between the plurality of first signal pads 131 and the plurality of third signal pads 441, and determines the number of abnormal connections among the connections between the plurality of second signal pads 132 and the plurality of fourth signal pads 442, based on the current value measured by the monitor circuit 151.

[0172] This allows the determination circuit 161 to determine the connection state for each connection point between the semiconductor die 10 and the interposer 40 .

[0173] (Embodiment 2) In embodiment 2, components similar to those of the semiconductor die 10 and semiconductor device 20 of embodiment 1 have already been explained, so they are assigned the same reference numerals and their explanations are omitted, and the explanation focuses on the differences from the semiconductor die 10 and semiconductor device 20 of embodiment 1.

[0174] FIG. 9 is a schematic diagram showing an example of the structure of a semiconductor die 10 according to the second embodiment.

[0175] 9 , the semiconductor die 10 according to the second embodiment differs from the semiconductor die 10 according to the first embodiment in that it further includes a fifth pad 171, a sixth pad 172, a seventh pad 173, and an eighth pad 174. The fifth pad 171, the sixth pad 172, the seventh pad 173, and the eighth pad 174 are disposed on the lower surface 12 (first surface 12). The fifth pad 171, the sixth pad 172, the seventh pad 173, and the eighth pad 174 are pads for connecting C4 bumps. The fifth pad 171 and the sixth pad 172 are signal pads, and the seventh pad 173 and the eighth pad 174 are power supply pads.

[0176] The fifth pad 171 is a pad used for bump connection with the package substrate 30, and is a pad for transmitting and receiving a first signal to and from the package substrate 30. The fifth pad 171 is also electrically connected to the wiring 141.

[0177] The sixth pad 172 is a pad used for bump connection with the package substrate 30, and is a pad for transmitting and receiving a second signal to and from the package substrate 30. The sixth pad 172 is also electrically connected to the wiring 142.

[0178] The seventh pad 173 is a pad used for bump connection with the package substrate 30, and is a pad for transmitting and receiving first power to and from the package substrate 30. The seventh pad 173 is also electrically connected to the wiring 143.

[0179] The eighth pad 174 is a pad used for bump connection with the package substrate 30, and is a pad for transmitting and receiving second power to and from the package substrate 30. The eighth pad 174 is also electrically connected to the wiring 144.

[0180] Here, the fifth pad 171, the sixth pad 172, the seventh pad 173, and the eighth pad 174 will be described in detail with reference to Fig. 10. Fig. 10 is a plan view of the semiconductor die 10 in a plan view of the bottom surface 12.

[0181] As shown in FIG. 10, the first signal pads 131 are arranged within a third distance r3 from a third signal imaginary point TS3 (that is, inside the two-dot chain line).

[0182] The fifth pad 171 is positioned within a third distance r3 from the third signal virtual point TS3 (i.e., inside the dotted line), and is positioned so as not to overlap any of the multiple first signal pads 131.

[0183] Furthermore, the dimensions of the fifth pad 171 in plan view are larger than the dimensions of each of the plurality of first signal pads 131 in plan view.

[0184] The second signal pads 132 are arranged within a third distance r3 from the fourth signal imaginary point TS4 (that is, inside the two-dot chain line).

[0185] The sixth pad 172 is positioned within a third distance r3 from the fourth signal virtual point TS4 (i.e., inside the dotted line), and is positioned so as not to overlap any of the multiple second signal pads 132.

[0186] Furthermore, the dimensions of the sixth pad 172 in plan view are larger than the dimensions of each of the plurality of second signal pads 132 in plan view.

[0187] The linear distance d4 between the third signal imaginary point TS3 and the fourth signal imaginary point TS4 is greater than twice the third distance r3. In other words, the first signal pads 131 and the fifth pads 171, and the second signal pads 132 and the sixth pads 172 are arranged so that their two-dot chain lines do not contact or intersect with each other.

[0188] The plurality of first power supply pads 133 are arranged within a fourth distance r4 from the third power supply virtual point TE3 (that is, inside the two-dot chain line).

[0189] The seventh pad 173 is positioned within a fourth distance r4 from the third power supply virtual point TE3 (i.e., inside the dotted line), and is positioned so as not to overlap any of the multiple first power supply pads 133.

[0190] Furthermore, the dimensions of the seventh pad 173 in plan view are larger than the dimensions of each of the plurality of first power supply pads 133 in plan view.

[0191] The second power supply pads 134 are arranged within a fourth distance r4 from the fourth power supply virtual point TE4 (that is, inside the two-dot chain line).

[0192] The eighth pad 174 is positioned within a fourth distance r4 from the fourth power supply virtual point TE4 (i.e., inside the two-dot chain line), and is positioned so as not to overlap any of the multiple second power supply pads 134.

[0193] Furthermore, the dimensions of the eighth pad 174 in plan view are larger than the dimensions of each of the plurality of second power supply pads 134 in plan view.

[0194] The linear distance d5 between the third power supply virtual point TE3 and the fourth power supply virtual point TE4 is greater than twice the fourth distance r4. In other words, the first power supply pads 133 and the seventh pad 173, and the second power supply pads 134 and the eighth pad 174 are arranged so that their two-dot chain lines do not contact or intersect with each other.

[0195] The linear distance d6 between the third signal virtual point TS3 and the third power supply virtual point TE3 is greater than twice the third distance r3 and greater than twice the fourth distance r4. In other words, the first signal pads 131 and the fifth pad 171, and the first power supply pads 133 and the seventh pad 173 are arranged so that their two-dot chain lines do not contact or intersect with each other. Furthermore, the first signal pads 131, the second signal pads 132, the first power supply pads 133, the second power supply pads 134, the fifth pad 171, the sixth pad 172, the seventh pad 173, and the eighth pad 174 are arranged so that the above relationship holds regardless of the linear distance between any signal virtual point and any power supply virtual point.

[0196] Although the semiconductor die 10 has the fifth pad 171 and the sixth pad 172 for transmitting and receiving the first signal and the second signal in the above embodiment, it may have, for example, three or more signal pads. Also, although the semiconductor die 10 has the seventh pad 173 and the eighth pad 174 for transmitting and receiving the first power and the second power in the above embodiment, it may have, for example, three or more power supply pads.

[0197] Furthermore, as long as the plurality of first signal pads 131 and fifth pads 171 are arranged within the third distance r3 from the third signal virtual point TS3, the arrangement is not limited to that shown in Fig. 10. The same applies to the plurality of second signal pads 132 and sixth pad 172, the plurality of first power supply pads 133 and seventh pads 173, and the plurality of second power supply pads 134 and eighth pads 174.

[0198] 10 shows the case where the fifth pad 171 has a circular shape, the fifth pad 171 may have, for example, a polygonal shape as long as it can be connected to the first pad 341 of the package substrate 30 via a C4 bump. The same applies to the sixth pad 172, the seventh pad 173, and the eighth pad 174.

[0199] Furthermore, the third distance r3 may be the same as or different from the fourth distance r4.

[0200] [Semiconductor Device (When the Semiconductor Die is Directly Mounted on the Package Substrate)] Next, the structure of a semiconductor device obtained by directly mounting the above-described semiconductor die 10 on the package substrate 30 will be described with reference to Fig. 11. Fig. 11 is a schematic diagram showing an example of a semiconductor device 20 obtained by directly mounting the semiconductor die 10 shown in Fig. 9 on the package substrate 30.

[0201] As shown in FIG. 11, semiconductor device 20 is an SoC in which semiconductor die 10 is mounted directly on package substrate 30 via a plurality of C4 bumps 50.

[0202] Specifically, the fifth pad 171 is bump-connected to the first pad 341 via one C4 bump 50, but the multiple first signal pads 131 are not bump-connected to the first pad 341.

[0203] In addition, the sixth pad 172 is bump-connected to the second pad 342 via one C4 bump 50, but the multiple second signal pads 132 are not bump-connected to the second pads 342.

[0204] Furthermore, the seventh pad 173 is bump-connected to the third pad 343 via one C4 bump 50, but the multiple first power supply pads 133 are not bump-connected to the third pad 343.

[0205] Furthermore, the eighth pad 174 is bump-connected to the fourth pad 344 via one C4 bump 50, but the multiple second power supply pads 134 are not bump-connected to the fourth pad 344.

[0206] [Semiconductor Device (When a Semiconductor Die is Mounted on a Package Substrate via an Interposer)] Next, the structure of a semiconductor device 20 obtained by mounting the above-described semiconductor die 10 on a package substrate 30 via an interposer 40 will be described with reference to Fig. 12. Fig. 12 is a schematic diagram showing an example of a semiconductor device 20 obtained by mounting the semiconductor die 10 shown in Fig. 9 on a package substrate 30 via an interposer 40.

[0207] As shown in FIG. 12, the semiconductor device 20 is an SoC in which the semiconductor die 10 is mounted on the interposer 40 via a plurality of microbumps 60 .

[0208] Specifically, the plurality of first signal pads 131 are bump-connected to the plurality of third signal pads 441 via the plurality of microbumps 60, but the fifth pad 171 is not bump-connected to the plurality of third signal pads 441.

[0209] In addition, the plurality of second signal pads 132 are bump-connected to the plurality of fourth signal pads 442 via the plurality of microbumps 60, but the sixth pad 172 is not bump-connected to the plurality of fourth signal pads 442.

[0210] Furthermore, the plurality of first power supply pads 133 are bump-connected to the plurality of third power supply pads 443 via the plurality of microbumps 60, but the seventh pad 173 is not bump-connected to the plurality of third power supply pads 443.

[0211] Furthermore, the plurality of second power supply pads 134 are bump-connected to the plurality of fourth power supply pads 444 via the plurality of microbumps 60, but the eighth pad 174 is not bump-connected to the plurality of fourth power supply pads 444.

[0212] In addition, the semiconductor device 20 of embodiment 2 may execute processing procedures for determining the connection state between the semiconductor die 10 and the package substrate 30, and the connection state between the semiconductor die 10 and the interposer 40, as described in embodiment 1.

[0213] [Effects, etc.] As described above, semiconductor die 10 according to the present embodiment includes first body 11 having planar first surface 12, a plurality of first signal pads 131 and a plurality of second signal pads 132 arranged on first surface 12 and transmitting / receiving signals, a plurality of first power supply pads 133 and a plurality of second power supply pads 134 arranged on first surface 12 and transmitting / receiving power, fifth pad 171 and sixth pad 172 arranged on first surface 12 and transmitting / receiving signals, and seventh pad 173 and eighth pad 174 arranged on first surface 12 and transmitting / receiving power. The dimensions of the fifth pad 171 in the plan view are larger than the dimensions of each of the plurality of first signal pads 131 in the plan view of the first surface 12, the dimensions of the sixth pad 172 in the plan view of the first surface 12 are larger than the dimensions of each of the plurality of second signal pads 132 in the plan view of the first surface 12, the dimensions of the seventh pad 173 in the plan view of the first surface 12 are larger than the dimensions of each of the plurality of first power supply pads 133 in the plan view of the first surface 12, and the dimensions of the eighth pad 174 in the plan view of the first surface 12 are the dimensions of the plurality of first signal pads 131 are larger than the dimensions of each of the plurality of second power supply pads 134 in the figure, the plurality of first signal pads 131 are arranged within a third distance r3 from the third signal virtual point TS3, the fifth pad 171 is arranged within the third distance r3 from the third signal virtual point TS3 and is arranged at a position not overlapping any of the plurality of first signal pads 131, the plurality of second signal pads 132 are arranged within the third distance r3 from the fourth signal virtual point TS4, and the sixth pad 172 is arranged within the third distance r3 from the fourth signal virtual point TS4, the seventh pad 173 is arranged within the fourth distance r4 from the third power supply virtual point TE3 and is arranged at a position where it does not overlap with any of the plurality of first power supply pads 133; the plurality of second power supply pads 134 are arranged within the fourth distance r4 from the fourth power supply virtual point TE4; the eighth pad 174 is arranged within the fourth distance r4 from the fourth power supply virtual point TE4;It is arranged in a position that does not overlap any of the plurality of second power supply pads 134.

[0214] According to this, semiconductor die 10 includes pads for C4 bump connection (i.e., fifth pad 171, sixth pad 172, seventh pad 173, and eighth pad 174) and pads for microbump connection (i.e., a plurality of first signal pads 131, a plurality of second signal pads 132, a plurality of first power supply pads 133, and a plurality of second power supply pads 134) arranged on first surface 12. Therefore, semiconductor die 10 can accommodate both mounting methods with a single pad layout.

[0215] Furthermore, in the semiconductor die 10 according to this embodiment, the linear distance d4 between the third signal virtual point TS3 and the fourth signal virtual point TS4 is greater than twice the third distance r3, and the linear distance d5 between the third power supply virtual point TE3 and the fourth power supply virtual point TE4 is greater than twice the fourth distance r4.

[0216] According to this, since the linear distance d4 is greater than twice the third distance r3 and the linear distance d5 is greater than twice the fourth distance r4, the semiconductor die 10 is properly bump-connected to either the package substrate 30 or the interposer 40. Therefore, one pad layout can accommodate both mounting methods.

[0217] Furthermore, in the semiconductor die 10 according to this embodiment, the straight-line distance d6 between the third signal virtual point TS3 and the third power supply virtual point TE3 is greater than twice the third distance r3, and the straight-line distance d6 between the third signal virtual point TS3 and the third power supply virtual point TE3 is greater than twice the fourth distance r4.

[0218] According to this, since the linear distance d6 is greater than twice the third distance r3 and greater than twice the fourth distance r4, the semiconductor die 10 is properly bump-connected to either the package substrate 30 or the interposer 40. Therefore, one pad layout can accommodate both mounting methods.

[0219] Furthermore, the semiconductor device 20 according to this embodiment includes the semiconductor die 10 according to this embodiment, and a package substrate 30 having a first pad 341 and a second pad 342 for transmitting and receiving signals, and a third pad 343 and a fourth pad 344 for transmitting and receiving power, wherein the fifth pad 171 is bump-connected to the first pad 341, the sixth pad 172 is bump-connected to the second pad 342, the seventh pad 173 is bump-connected to the third pad 343, and the eighth pad 174 is bump-connected to the fourth pad 344.

[0220] As a result, the semiconductor device 20 achieves the same effects as the semiconductor die 10 according to the present embodiment.

[0221] Furthermore, in the semiconductor device 20 according to this embodiment, the plurality of first signal pads 131 are not bump-connected to the first pads 341, the plurality of second signal pads 132 are not bump-connected to the second pads 342, the plurality of first power supply pads 133 are not bump-connected to the third pads 343, and the plurality of second power supply pads 134 are not bump-connected to the fourth pads 344.

[0222] As a result, the semiconductor device 20 achieves the same effects as the semiconductor die 10 according to the present embodiment.

[0223] In addition, the semiconductor device 20 of this embodiment comprises the semiconductor die 10 of this embodiment, and an interposer 40 having a plurality of third signal pads 441 and a plurality of fourth signal pads 442 for transmitting and receiving signals, and a plurality of third power supply pads 443 and a plurality of fourth power supply pads 444 for transmitting and receiving power, wherein the plurality of first signal pads 131 are bump-connected to the plurality of third signal pads 441, the plurality of second signal pads 132 are bump-connected to the plurality of fourth signal pads 442, the plurality of first power supply pads 133 are bump-connected to the plurality of third power supply pads 443, and the plurality of second power supply pads 134 are bump-connected to the plurality of fourth power supply pads 444.

[0224] As a result, the semiconductor device 20 achieves the same effects as the semiconductor die 10 according to the present embodiment.

[0225] Furthermore, in the semiconductor device 20 according to this embodiment, the fifth pad 171 is not bump-connected to the plurality of third signal pads 441, the sixth pad 172 is not bump-connected to the plurality of fourth signal pads 442, the seventh pad 173 is not bump-connected to the plurality of third power supply pads 443, and the eighth pad 174 is not bump-connected to the plurality of fourth power supply pads 444.

[0226] As a result, the semiconductor device 20 achieves the same effects as the semiconductor die 10 according to the present embodiment.

[0227] In the third embodiment, components similar to those of the semiconductor die 10 and semiconductor device 20 according to the first embodiment have already been described, so they are assigned the same reference numerals and their description is omitted, and the description will focus on the differences from the semiconductor die 10 and semiconductor device 20 according to the first embodiment. Note that in the third embodiment, the interposer 40 has the characteristics of the invention.

[0228] [Semiconductor Die] FIG. 13 is a schematic diagram showing an example of the structure of a semiconductor die 10 according to the third embodiment.

[0229] 13 , the semiconductor die 10 according to the third embodiment differs from the semiconductor die 10 according to the first embodiment in that the semiconductor die 10 according to the third embodiment includes a ninth pad 181, a tenth pad 182, an eleventh pad 183, and a twelfth pad 184 instead of the plurality of first signal pads 131, the plurality of second signal pads 132, the plurality of first power supply pads 133, and the plurality of second power supply pads 134. The ninth pad 181, the tenth pad 182, the eleventh pad 183, and the twelfth pad 184 are disposed on the lower surface 12 (first surface 12). The ninth pad 181, the tenth pad 182, the eleventh pad 183, and the twelfth pad 184 are pads for connecting C4 bumps. The ninth pad 181 and the tenth pad 182 are signal pads, and the eleventh pad 183 and the twelfth pad 184 are power supply pads.

[0230] The ninth pad 181 is a pad used for bump connection with the package substrate 30 or the interposer 40, and is a pad for transmitting and receiving a first signal to and from the package substrate 30 or the interposer 40. The ninth pad 181 is also electrically connected to the wiring 141.

[0231] The tenth pad 182 is a pad used for bump connection with the package substrate 30 or the interposer 40, and is a pad for transmitting and receiving a second signal with the package substrate 30 or the interposer 40. The tenth pad 182 is also electrically connected to the wiring 142.

[0232] The eleventh pad 183 is a pad used for bump connection with the package substrate 30 or the interposer 40, and is a pad for transmitting and receiving first power to and from the package substrate 30 or the interposer 40. The eleventh pad 183 is also electrically connected to the wiring 143.

[0233] The twelfth pad 184 is a pad used for bump connection with the package substrate 30 or the interposer 40, and is a pad for transmitting and receiving second power to and from the package substrate 30 or the interposer 40. The twelfth pad 184 is also electrically connected to the wiring 144.

[0234] [Interposer] FIG. 14 is a schematic diagram showing an example of the structure of an interposer 40 according to the third embodiment.

[0235] 14 , the interposer 40 according to the third embodiment includes a plurality of fifth signal pads 446, a plurality of sixth signal pads 447, a plurality of fifth power supply pads 448, and a plurality of sixth power supply pads 449, instead of the plurality of third signal pads 441, the plurality of fourth signal pads 442, the plurality of third power supply pads 443, the plurality of fourth power supply pads 444, and the plurality of seventh signal pads 445. The plurality of fifth signal pads 446, the plurality of sixth signal pads 447, the plurality of fifth power supply pads 448, and the plurality of sixth power supply pads 449 are arranged on the upper surface 42 (second surface 42). The plurality of fifth signal pads 446, the plurality of sixth signal pads 447, the plurality of fifth power supply pads 448, and the plurality of sixth power supply pads 449 are pads for connecting microbumps.

[0236] The plurality of fifth signal pads 446 are pads used for bump connection with the semiconductor die 10, and are pads for transmitting and receiving a first signal to and from the semiconductor die 10. Here, each of the pads constituting the plurality of fifth signal pads 446 is a pad for microbump connection.

[0237] The plurality of sixth signal pads 447 are pads used for bump connection with the semiconductor die 10, and are pads for transmitting and receiving second signals to and from the semiconductor die 10. Here, each of the pads constituting the plurality of sixth signal pads 447 is a pad for microbump connection.

[0238] The plurality of fifth power supply pads 448 are pads used for bump connection with the semiconductor die 10, and are pads for transmitting and receiving first power to and from the semiconductor die 10. Here, each of the pads constituting the plurality of fifth power supply pads 448 is a pad for microbump connection.

[0239] The plurality of sixth power supply pads 449 are pads used for bump connection with the semiconductor die 10, and are pads for transmitting and receiving a second signal to and from the semiconductor die 10. Here, each of the pads constituting the plurality of sixth power supply pads 449 is a pad for microbump connection.

[0240] Here, the plurality of fifth signal pads 446, the plurality of sixth signal pads 447, the plurality of fifth power supply pads 448, and the plurality of sixth power supply pads 449 will be described in detail with reference to Fig. 15. Fig. 15 is a plan view of semiconductor die 10 in plan view of top surface 42.

[0241] 15, the plurality of fifth signal pads 446 are arranged within a fifth distance r5 from the fifth signal imaginary point TS5 (i.e., inside the two-dot chain line). Although the number of the plurality of fifth signal pads 446 is four in FIG. 15, it is sufficient that the number is at least two.

[0242] The sixth signal pads 447 are arranged within a fifth distance r5 from the sixth signal imaginary point TS6 (i.e., inside the two-dot chain line). Although the number of the sixth signal pads 447 is four in FIG. 15, it is sufficient that the number is at least two.

[0243] The linear distance d7 between the fifth signal imaginary point TS5 and the sixth signal imaginary point TS6 is greater than twice the fifth distance r5. In other words, the fifth signal pads 446 and the sixth signal pads 447 are arranged so that the two-dot chain lines do not contact or intersect with each other.

[0244] The plurality of fifth power supply pads 448 are arranged within a sixth distance r6 from the fifth power supply virtual point TE5 (i.e., inside the two-dot chain line). Although the number of the plurality of fifth power supply pads 448 is six in FIG. 15, it is sufficient that the number is at least two.

[0245] The sixth power supply pads 449 are arranged within a sixth distance r6 from the sixth power supply virtual point TE6 (i.e., inside the two-dot chain line). Although the number of the sixth power supply pads 449 is six in FIG. 15, it is sufficient that the number is at least two.

[0246] A linear distance d8 between the fifth power supply virtual point TE5 and the sixth power supply virtual point TE6 is greater than twice the sixth distance r6. In other words, the fifth power supply pads 448 and the sixth power supply pads 449 are arranged so that the two-dot chain lines do not contact or intersect with each other.

[0247] The linear distance d9 between the fifth signal virtual point TS5 and the fifth power supply virtual point TE5 is greater than twice the fifth distance r5 and greater than twice the sixth distance r6. In other words, the fifth signal pads 446 and the fifth power supply pads 448 are arranged so that the two-dot chain lines do not contact or intersect with each other. Furthermore, the fifth signal pads 446, the sixth signal pads 447, the fifth power supply pads 448, and the sixth power supply pads 449 are arranged so that the above relationship holds regardless of the linear distance between any signal virtual point and any power supply virtual point.

[0248] The plurality of fifth signal pads 446 are positioned at positions where they can be bump-connected to the ninth pad 181 on the semiconductor die 10 via a plurality of microbumps 60, and the plurality of sixth signal pads 447 are positioned at positions where they can be bump-connected to the tenth pad 182 on the semiconductor die 10 via a plurality of microbumps 60.

[0249] In addition, the plurality of fifth power supply pads 448 are arranged in positions where they can be bump-connected to the eleventh pads 183 of the semiconductor die 10 via the plurality of microbumps 60, and the plurality of sixth power supply pads 449 are arranged in positions where they can be bump-connected to the twelfth pads 184 of the semiconductor die 10 via the plurality of microbumps 60.

[0250] The fifth distance r5 is set so that the plurality of fifth signal pads 446 or the plurality of sixth signal pads 447 can contact and bond to one C4 bump 50. In other words, the plurality of fifth signal pads 446 are arranged at positions where they can be connected to the ninth pad 181 of the semiconductor die 10 via the C4 bump 50, and the plurality of sixth signal pads 447 are arranged at positions where they can be connected to the tenth pad 182 of the semiconductor die 10 via the C4 bump 50. Note that if the dimensions of the C4 bump 50 used to bond to the ninth pad 181 differ from the dimensions of the C4 bump 50 used to bond to the tenth pad 182, the fifth distance r5 is determined taking into account the size of the smaller C4 bump 50. As described above, the plurality of fifth signal pads 446 or the plurality of sixth signal pads 447 can contact one C4 bump 50. On the other hand, the ninth pad 181 is connected to one C4 bump 50 which is connected to the plurality of fifth signal pads 446, and the tenth pad 182 is connected to one C4 bump 50 which is connected to the plurality of sixth signal pads 447. Since the plurality of fifth signal pads 446, one C4 bump 50, and the ninth pad 181 are connected in the above-described manner, the dimensions of the plurality of fifth signal pads 446 are generally smaller than the dimensions of the ninth pad 181. Similarly, the dimensions of the plurality of sixth signal pads 447 are smaller than the dimensions of the tenth pad 182.

[0251] Furthermore, for example, the fifth distance r5 may be the total length of the dimensions of the plurality of fifth signal pads 446 and half the dimension of the ninth pad 181, or the total length of the dimensions of the plurality of sixth signal pads 447 and half the dimension of the tenth pad 182. Furthermore, the fifth distance r5 may be the total length of the dimensions of the plurality of fifth signal pads 446 and half the dimension of one C4 bump 50, or the total length of the dimensions of the plurality of sixth signal pads 447 and half the dimension of one C4 bump 50.

[0252] Furthermore, the sixth distance r6 is set so that the plurality of fifth power supply pads 448 or the plurality of sixth power supply pads 449 can contact and be bonded to one C4 bump 50. In other words, the plurality of fifth power supply pads 448 are arranged at positions where they can be connected to the eleventh pad 183 of the semiconductor die 10 via the C4 bump 50, and the plurality of sixth power supply pads 449 are arranged at positions where they can be connected to the twelfth pad 184 of the semiconductor die 10 via the C4 bump 50. Note that if the dimensions of the C4 bump 50 used to bond to the eleventh pad 183 differ from the dimensions of the C4 bump 50 used to bond to the twelfth pad 184, the sixth distance r6 is determined taking into account the size of the smaller C4 bump 50. As described above, the plurality of fifth power supply pads 448 or the plurality of sixth power supply pads 449 can contact one C4 bump 50. On the other hand, the eleventh pad 183 is connected to one C4 bump 50 which is connected to a plurality of fifth power supply pads 448, and the twelfth pad 184 is connected to one C4 bump 50 which is connected to a plurality of sixth power supply pads 449. Since the plurality of fifth power supply pads 448, one C4 bump 50, and the eleventh pad 183 are connected in the above-described manner, the dimensions of the plurality of fifth power supply pads 448 are generally smaller than the dimensions of the eleventh pad 183. Similarly, the dimensions of the plurality of sixth power supply pads 449 are smaller than the dimensions of the twelfth pad 184.

[0253] Furthermore, for example, the sixth distance r6 may be the total length of the dimensions of the plurality of fifth power supply pads 448 and half the dimension of the eleventh pad 183, or the total length of the dimensions of the plurality of sixth power supply pads 449 and half the dimension of the twelfth pad 184. Furthermore, the sixth distance r6 may be the total length of the dimensions of the plurality of fifth power supply pads 448 and half the dimension of one C4 bump 50, or the total length of the dimensions of the plurality of sixth power supply pads 449 and half the dimension of one C4 bump 50.

[0254] Although the interposer 40 has a plurality of fifth signal pads 446 and a plurality of sixth signal pads 447 for transmitting and receiving the first signal and the second signal in the above embodiment, it may have a plurality of signal pads, for example, three or more. Also, although the interposer 40 has a plurality of fifth power supply pads 448 and a plurality of sixth power supply pads 449 for transmitting and receiving the first power and the second power in the above embodiment, it may have a plurality of power supply pads, for example, three or more.

[0255] Furthermore, because the amount of current that flows during power transmission is greater than that during signal transmission, the number of the plurality of fifth power supply pads 448 is preferably equal to or greater than the number of the plurality of fifth signal pads 446 and equal to or greater than the number of the plurality of sixth signal pads 447. For the same reason, the number of the plurality of sixth power supply pads 449 is preferably equal to or greater than the number of the plurality of fifth signal pads 446 and equal to or greater than the number of the plurality of sixth signal pads 447.

[0256] 15 shows the case where the plurality of fifth signal pads 446 are arranged concentrically from the fifth signal virtual point TS5, but they may be arranged within a fifth distance r5 from the fifth signal virtual point TS5. The same applies to the plurality of sixth signal pads 447, the plurality of fifth power supply pads 448, and the plurality of sixth power supply pads 449.

[0257] 15 shows the case where the plurality of fifth signal pads 446 are circular, the plurality of fifth signal pads 446 may be polygonal, for example, as long as they can be connected to the ninth pads 181 of the semiconductor die 10. The same applies to the plurality of sixth signal pads 447, the plurality of fifth power supply pads 448, and the plurality of sixth power supply pads 449.

[0258] 15 shows the case where the plurality of fifth signal pads 446 are all identical in size and shape, but they do not have to be identical. The same applies to the plurality of sixth signal pads 447, the plurality of fifth power supply pads 448, and the plurality of sixth power supply pads 449.

[0259] Furthermore, since the plurality of fifth signal pads 446 are arranged within the fifth distance r5, each of the plurality of fifth signal pads 446 can be brought into contact with a C4 bump probe at the same time. This makes it possible to determine whether the semiconductor die 10 is defective even using a C4 bump probe that is generally used in chip inspection. The same is true for the plurality of sixth signal pads 447, the plurality of fifth power supply pads 448, and the plurality of sixth power supply pads 449.

[0260] Furthermore, the fifth distance r5 may be the same as or different from the sixth distance r6.

[0261] [Semiconductor Device (When the Semiconductor Die is Directly Mounted on the Package Substrate)] The structure of the semiconductor device 20 obtained by directly mounting the above-described semiconductor die 10 on the package substrate 30 will be described with reference to Fig. 16. Fig. 16 is a schematic diagram showing an example of the semiconductor device 20 obtained by directly mounting the semiconductor die 10 shown in Fig. 13 on the package substrate 30.

[0262] 16 , semiconductor device 20 is composed of semiconductor die 10 and package substrate 30. Semiconductor device 20 is an SoC in which semiconductor die 10 is directly mounted on package substrate 30 via a plurality of C4 bumps 50.

[0263] Specifically, the ninth pad 181 is bump-connected to the first pad 341 via one C4 bump 50 .

[0264] The tenth pad 182 is bump-connected to the second pad 342 via one C4 bump 50 .

[0265] The eleventh pad 183 is bump-connected to the third pad 343 via one C4 bump 50 .

[0266] The twelfth pad 184 is bump-connected to the fourth pad 344 via one C4 bump 50 .

[0267] 16 shows an example in which multiple C4 bumps 50 are used for bump connection between semiconductor die 10 and package substrate 30, but multiple microbumps 60 may also be used for the bump connection. For example, ninth pad 181 may be bump-connected to first pad 341 via multiple microbumps 60.

[0268] [Semiconductor Device (When a Semiconductor Die is Mounted on a Package Substrate via an Interposer)] The structure of a semiconductor device 20 obtained by mounting the above-described semiconductor die 10 on a package substrate 30 via an interposer 40 will be described with reference to Fig. 17. Fig. 17 is a schematic diagram showing an example of a semiconductor device 20 obtained by mounting the semiconductor die 10 shown in Fig. 13 on a package substrate 30 via the interposer 40 shown in Fig. 14.

[0269] The semiconductor device 20 is composed of at least a semiconductor die 10 and an interposer 40. As shown in FIG.

[0270] Furthermore, the semiconductor device 20 is a SoC in which the semiconductor die 10 is mounted on the interposer 40 via a plurality of microbumps 60 .

[0271] Specifically, the ninth pad 181 is bump-connected to a plurality of fifth signal pads 446 via a plurality of microbumps 60 .

[0272] The tenth pad 182 is bump-connected to a plurality of sixth signal pads 447 via a plurality of microbumps 60 .

[0273] The eleventh pad 183 is bump-connected to a plurality of fifth power supply pads 448 via a plurality of microbumps 60 .

[0274] The twelfth pad 184 is bump-connected to a plurality of sixth power supply pads 449 via a plurality of microbumps 60 .

[0275] 17 shows an example in which multiple microbumps 60 are used for bump connection between the semiconductor die 10 and the interposer 40, but multiple C4 bumps 50 may be used for the bump connection. For example, the ninth pad 181 may be bump-connected to multiple fifth signal pads 446 via one C4 bump 50.

[0276] [Effects, etc.] As described above, interposer 40 according to the present embodiment is an interposer 40 that can be connected to package substrate 30 having first pads 341 and second pads 342 for transmitting and receiving signals and third pads 343 and fourth pads 344 for transmitting and receiving power, and can be connected to semiconductor die 10 having ninth pads 181 and tenth pads 182 for transmitting and receiving signals and eleventh pads 183 and twelfth pads 184 for transmitting and receiving power, and includes second body 41 having planar second surface 42 and third surface 43, a plurality of fifth signal pads 446 and a plurality of sixth signal pads 447 arranged on second surface 42, a plurality of fifth power supply pads 448 and a plurality of sixth power supply pads 449 arranged on second surface 42, and a plurality of sixth power supply pads 449 arranged on third surface 43. the second surface 42 is a plane facing the third surface 43, the plurality of fifth signal pads 446 are arranged at positions where they can be connected to the ninth pad 181 via the plurality of microbumps 60, the plurality of sixth signal pads 447 are arranged at positions where they can be connected to the tenth pad 182 via the plurality of microbumps 60, the plurality of fifth power supply pads 448 are arranged at positions where they can be connected to the eleventh pad 183 via the plurality of microbumps 60, and the plurality of sixth power supply pads 449 are arranged at positions where they can be connected to the twelfth pad 184 via the plurality of microbumps 60.

[0277] This allows interposer 40 to mount semiconductor die 10 even if the semiconductor die 10 has a pad layout intended for direct mounting on package substrate 30. Therefore, interposer 40 allows semiconductor die 10 having one pad layout to be compatible with both mounting methods.

[0278] Furthermore, in the interposer 40 according to this embodiment, the plurality of fifth signal pads 446 are arranged within a fifth distance r5 from the fifth signal virtual point TS5, the plurality of sixth signal pads 447 are arranged within a fifth distance r5 from the sixth signal virtual point TS6, the plurality of fifth power supply pads 448 are arranged within a sixth distance r6 from the fifth power supply virtual point TE5, the plurality of sixth power supply pads 449 are arranged within a sixth distance r6 from the sixth power supply virtual point TE6, the straight-line distance d7 between the fifth signal virtual point TS5 and the sixth signal virtual point TS6 is greater than twice the fifth distance r5, and the straight-line distance d8 between the fifth power supply virtual point TE5 and the sixth power supply virtual point TE6 is greater than twice the sixth distance r6.

[0279] According to this, since linear distance d7 is greater than twice the fifth distance r5 and linear distance d8 is greater than twice the sixth distance r6, interposer 40 can be properly bump-connected even to semiconductor die 10 having a pad layout intended for direct mounting on package substrate 30. Therefore, interposer 40 can enable semiconductor die 10 having one pad layout to be compatible with both mounting methods.

[0280] Furthermore, in the interposer 40 according to this embodiment, the straight-line distance d9 between the fifth signal virtual point TS5 and the fifth power supply virtual point TE5 is greater than twice the fifth distance r5, and the straight-line distance d9 between the fifth signal virtual point TS5 and the fifth power supply virtual point TE5 is greater than twice the sixth distance r6.

[0281] According to this, since linear distance d9 is greater than twice the fifth distance r5 and greater than twice the sixth distance r6, interposer 40 can be properly bump-connected even to semiconductor die 10 having a pad layout intended for direct mounting on package substrate 30. Therefore, interposer 40 can enable semiconductor die 10 having one pad layout to be compatible with both mounting methods.

[0282] Furthermore, in the interposer 40 according to this embodiment, the fifth distance r5 is set so that a plurality of fifth signal pads 446 and a plurality of sixth signal pads 447 can contact one C4 bump 50, and the sixth distance r6 is set so that a plurality of fifth power supply pads 448 and a plurality of sixth power supply pads 449 can contact one C4 bump 50.

[0283] According to this, the plurality of fifth signal pads 446 and the plurality of sixth signal pads 447 are arranged so as to be in contact with one C4 bump 50, and the plurality of fifth power supply pads 448 and the plurality of sixth power supply pads 449 are arranged so as to be in contact with one C4 bump 50. Therefore, interposer 40 can achieve more accurate mounting even for semiconductor die 10 having a pad layout intended for direct mounting on package substrate 30.

[0284] Furthermore, the semiconductor device 20 according to this embodiment comprises the interposer 40 according to this embodiment, and a semiconductor die 10 having a ninth pad 181 and a tenth pad 182 for transmitting and receiving signals, and an eleventh pad 183 and a twelfth pad 184 for transmitting and receiving power, wherein a plurality of fifth signal pads 446 are bump-connected to the ninth pad 181, a plurality of sixth signal pads 447 are bump-connected to the tenth pad 182, a plurality of fifth power supply pads 448 are bump-connected to the eleventh pad 183, and a plurality of sixth power supply pads 449 are bump-connected to the twelfth pad 184.

[0285] As a result, the semiconductor device 20 has the same effects as the interposer 40 according to the present embodiment.

[0286] (Other Modifications) Although the semiconductor die and semiconductor device according to the present disclosure have been described above based on the embodiments, the present disclosure is not limited to the above-described embodiments.

[0287] In addition, this disclosure also includes forms obtained by making various modifications to the above embodiments that a person skilled in the art would think of, and forms realized by arbitrarily combining the components and functions in the embodiments within the scope of the present disclosure.

[0288] Examples of the semiconductor die and semiconductor device according to the present disclosure that have been described based on the above embodiments are given below. The semiconductor die and semiconductor device according to the present disclosure are not limited to the following examples.

[0289] For example, a semiconductor die according to a first aspect of the present disclosure is a semiconductor die connectable to a package substrate having first and second pads for transmitting and receiving signals and third and fourth pads for transmitting and receiving power, the semiconductor die comprising: a first body having a planar first surface; a plurality of first signal pads and a plurality of second signal pads arranged on the first surface; and a plurality of first power supply pads and a plurality of second power supply pads arranged on the first surface, wherein the plurality of first signal pads are arranged in positions where they can be connected to the first pads via a single bump, the plurality of second signal pads are arranged in positions where they can be connected to the second pads via a single bump, the plurality of first power supply pads are arranged in positions where they can be connected to the third pads via a single bump, and the plurality of second power supply pads are arranged in positions where they can be connected to the fourth pads via a single bump.

[0290] Also, for example, a semiconductor die according to a second aspect of the present disclosure is the semiconductor die according to the first aspect, wherein the plurality of first signal pads are arranged within a first distance from a first signal virtual point, the plurality of second signal pads are arranged within the first distance from a second signal virtual point, the plurality of first power supply pads are arranged within a second distance from a first power supply virtual point, and the plurality of second power supply pads are arranged within the second distance from a second power supply virtual point, the straight-line distance between the first signal virtual point and the second signal virtual point is greater than twice the first distance, and the straight-line distance between the first power supply virtual point and the second power supply virtual point is greater than twice the second distance.

[0291] Also, for example, a semiconductor die according to a third aspect of the present disclosure is a semiconductor die according to the second aspect, wherein the straight-line distance between the first signal virtual point and the first power supply virtual point is greater than twice the first distance, and the straight-line distance between the first signal virtual point and the first power supply virtual point is greater than twice the second distance.

[0292] Also, for example, a semiconductor die according to a fourth aspect of the present disclosure is a semiconductor die according to any one of the first to third aspects, wherein the number of the plurality of first power supply pads is equal to or greater than the number of the plurality of first signal pads, the number of the plurality of first power supply pads is equal to or greater than the number of the plurality of second signal pads, the number of the plurality of second power supply pads is equal to or greater than the number of the plurality of first signal pads, and the number of the plurality of second power supply pads is equal to or greater than the number of the plurality of second signal pads.

[0293] Also, for example, a semiconductor die according to a fifth aspect of the present disclosure is a semiconductor die according to any one of the first to fourth aspects, wherein the plurality of first signal pads, the plurality of second signal pads, the plurality of first power supply pads, and the plurality of second power supply pads are pads for microbump connection, the one bump is a C4 bump, and the first pad, the second pad, the third pad, and the fourth pad are pads for C4 bump connection.

[0294] Also, for example, a semiconductor die according to a sixth aspect of the present disclosure is a semiconductor die according to the second or third aspect, wherein the first distance is set so that the plurality of first signal pads and the plurality of second signal pads can contact one C4 bump, and the second distance is set so that the plurality of first power supply pads and the plurality of second power supply pads can contact one C4 bump.

[0295] Furthermore, for example, a semiconductor die according to a seventh aspect of the present disclosure includes a first body having a planar first surface, a plurality of first signal pads and a plurality of second signal pads arranged on the first surface for transmitting and receiving signals, a plurality of first power supply pads and a plurality of second power supply pads arranged on the first surface for transmitting and receiving power, a fifth pad and a sixth pad arranged on the first surface for transmitting and receiving signals, and a seventh pad and an eighth pad arranged on the first surface for transmitting and receiving power, wherein a dimension of the fifth pad in a plan view of the first surface is , a dimension of the sixth pad in the plan view of the first surface is larger than a dimension of each of the plurality of second signal pads in the plan view of the first surface, a dimension of the seventh pad in the plan view of the first surface is larger than a dimension of each of the plurality of first power supply pads in the plan view of the first surface, and a dimension of the eighth pad in the plan view of the first surface is larger than a dimension of each of the plurality of second power supply pads in the plan view of the first surface. the dimensions of the first signal pads are larger than those of the fifth pads, the fifth pad is arranged within the third distance from a third signal imaginary point, the fifth pad is arranged within the third distance from the third signal imaginary point and is arranged at a position not overlapping any of the first signal pads, the second signal pads are arranged within the third distance from a fourth signal imaginary point, and the sixth pad is arranged within the third distance from the fourth signal imaginary point and is arranged at a position not overlapping any of the second signal pads. the plurality of first power supply pads are arranged within a fourth distance from a third power supply virtual point, the seventh pad is arranged within the fourth distance from the third power supply virtual point and is arranged at a position not overlapping any of the plurality of first power supply pads, the plurality of second power supply pads are arranged within the fourth distance from a fourth power supply virtual point, and the eighth pad is arranged within the fourth distance from the fourth power supply virtual point and is arranged at a position not overlapping any of the plurality of second power supply pads.

[0296] Also, for example, a semiconductor die according to an eighth aspect of the present disclosure is a semiconductor die according to the seventh aspect, wherein the straight-line distance between the third signal virtual point and the fourth signal virtual point is greater than twice the third distance, and the straight-line distance between the third power supply virtual point and the fourth power supply virtual point is greater than twice the fourth distance.

[0297] Also, for example, a semiconductor die according to a ninth aspect of the present disclosure is a semiconductor die according to the seventh or eighth aspect, wherein the straight-line distance between the third signal virtual point and the third power supply virtual point is greater than twice the third distance, and the straight-line distance between the third signal virtual point and the third power supply virtual point is greater than twice the fourth distance.

[0298] Furthermore, for example, an interposer according to a tenth aspect of the present disclosure is an interposer connectable to a package substrate having first and second pads for transmitting and receiving signals and third and fourth pads for transmitting and receiving power, and connectable to a semiconductor die having ninth and tenth pads for transmitting and receiving signals and eleventh and twelfth pads for transmitting and receiving power, the interposer comprising: a second body having planar second and third surfaces; a plurality of fifth signal pads and a plurality of sixth signal pads arranged on the second surface; a plurality of fifth power supply pads and a plurality of sixth power supply pads arranged on the second surface; and a thirteenth pad for transmitting and receiving signals arranged on the third surface. The second surface is a plane opposite to the third surface, and the fifth signal pads are arranged in positions where they can be connected to the ninth pad via a plurality of microbumps, the sixth signal pads are arranged in positions where they can be connected to the tenth pad via a plurality of microbumps, the fifth power supply pads are arranged in positions where they can be connected to the eleventh pad via a plurality of microbumps, and the sixth power supply pads are arranged in positions where they can be connected to the twelfth pad via a plurality of microbumps.

[0299] Furthermore, for example, an interposer according to an eleventh aspect of the present disclosure is an interposer according to the tenth aspect, wherein the fifth signal pads are arranged within a fifth distance from a fifth signal virtual point, the sixth signal pads are arranged within the fifth distance from a sixth signal virtual point, the fifth power supply pads are arranged within a sixth distance from a fifth power supply virtual point, the sixth power supply pads are arranged within the sixth distance from a sixth power supply virtual point, the straight-line distance between the fifth signal virtual point and the sixth signal virtual point is greater than twice the fifth distance, and the straight-line distance between the fifth power supply virtual point and the sixth power supply virtual point is greater than twice the sixth distance.

[0300] Also, for example, an interposer according to a twelfth aspect of the present disclosure is an interposer according to the eleventh aspect, wherein the straight-line distance between the fifth signal virtual point and the fifth power supply virtual point is greater than twice the fifth distance, and the straight-line distance between the fifth signal virtual point and the fifth power supply virtual point is greater than twice the sixth distance.

[0301] Furthermore, for example, an interposer according to a thirteenth aspect of the present disclosure is an interposer according to the eleventh or twelfth aspect, wherein the fifth distance is a distance at which the plurality of fifth signal pads and the plurality of sixth signal pads can contact one C4 bump, and the sixth distance is a distance at which the plurality of fifth power supply pads and the plurality of sixth signal pads can contact one C4 bump.

[0302] Also, for example, a semiconductor device according to a fourteenth aspect of the present disclosure comprises a semiconductor die according to any one of the first to sixth aspects, and a package substrate having the first pad and the second pad for transmitting and receiving signals, and the third pad and the fourth pad for transmitting and receiving power, wherein the plurality of first signal pads are bump-connected to the first pads, the plurality of second signal pads are bump-connected to the second pads, the plurality of first power supply pads are bump-connected to the third pads, and the plurality of second power supply pads are bump-connected to the fourth pads.

[0303] Also, for example, a semiconductor device according to a fifteenth aspect of the present disclosure comprises a semiconductor die according to any one of the first to sixth aspects, and an interposer having a plurality of third signal pads and a plurality of fourth signal pads for transmitting and receiving signals, and a plurality of third power supply pads and a plurality of fourth power supply pads for transmitting and receiving power, wherein the plurality of first signal pads are bump-connected to the plurality of third signal pads, the plurality of second signal pads are bump-connected to the plurality of fourth signal pads, the plurality of first power supply pads are bump-connected to the plurality of third power supply pads, and the plurality of second power supply pads are bump-connected to the plurality of fourth power supply pads, and the semiconductor die further comprises a monitor circuit that measures a current flowing between the semiconductor die and the interposer when the semiconductor die transmits and receives signals, and a determination circuit that determines a connection state between the semiconductor die and the interposer based on the current value measured by the monitor circuit.

[0304] Also, for example, a semiconductor device according to a sixteenth aspect of the present disclosure is a semiconductor device according to the fifteenth aspect, wherein the determination circuit identifies the number of abnormal connections among the connections between the plurality of first signal pads and the plurality of third signal pads, and identifies the number of abnormal connections among the connections between the plurality of second signal pads and the plurality of fourth signal pads, based on the current value measured by the monitor circuit.

[0305] Also, for example, a semiconductor device according to a seventeenth aspect of the present disclosure comprises a semiconductor die according to any one of the seventh to ninth aspects, and a package substrate having first and second pads for transmitting and receiving signals, and third and fourth pads for transmitting and receiving power, wherein the fifth pad is bump-connected to the first pad, the sixth pad is bump-connected to the second pad, the seventh pad is bump-connected to the third pad, and the eighth pad is bump-connected to the fourth pad.

[0306] Also, for example, a semiconductor device according to an eighteenth aspect of the present disclosure is a semiconductor device according to the seventeenth aspect, in which the plurality of first signal pads are not bump-connected to the first pads, the plurality of second signal pads are not bump-connected to the second pads, the plurality of first power supply pads are not bump-connected to the third pads, and the plurality of second power supply pads are not bump-connected to the fourth pads.

[0307] Also, for example, a semiconductor device according to a nineteenth aspect of the present disclosure comprises a semiconductor die according to any one of the seventh to ninth aspects, and an interposer having a plurality of third signal pads and a plurality of fourth signal pads for transmitting and receiving signals, and a plurality of third power supply pads and a plurality of fourth power supply pads for transmitting and receiving power, wherein the plurality of first signal pads are bump-connected to the plurality of third signal pads, the plurality of second signal pads are bump-connected to the plurality of fourth signal pads, the plurality of first power supply pads are bump-connected to the plurality of third power supply pads, and the plurality of second power supply pads are bump-connected to the plurality of fourth power supply pads.

[0308] Also, for example, a semiconductor device according to a twentieth aspect of the present disclosure is a semiconductor device according to the nineteenth aspect, in which the fifth pad is not bump-connected to the plurality of third signal pads, the sixth pad is not bump-connected to the plurality of fourth signal pads, the seventh pad is not bump-connected to the plurality of third power supply pads, and the eighth pad is not bump-connected to the plurality of fourth power supply pads.

[0309] Also, for example, a semiconductor device according to a 21st aspect of the present disclosure is an interposer according to any one of the 10th to 13th aspects, comprising the semiconductor die having the 9th pad and the 10th pad for transmitting and receiving signals, and the 11th pad and the 12th pad for transmitting and receiving power, wherein the plurality of fifth signal pads are bump-connected to the 9th pad, the plurality of sixth signal pads are bump-connected to the 10th pad, the plurality of fifth power supply pads are bump-connected to the 11th pad, and the plurality of sixth power supply pads are bump-connected to the 12th pad.

[0310] The semiconductor die and the like according to the present disclosure can be used in various electrical devices that use semiconductor chips.

[0311] 10, 100 Semiconductor die 11, 31, 41, 110 Body 12, 120, 33, 43 Bottom surface 131 Multiple first signal pads 132 Multiple second signal pads 133 Multiple first power supply pads 134 Multiple second power supply pads 135 Multiple eighth signal pads 141, 142, 143, 144, 361, 362, 461, 462 Wiring 151, 152 Monitor circuit 161, 162 Determination circuit 171 Fifth pad 172 Sixth pad 173 Seventh pad 174 Eighth pad 181 Ninth pad 182 Tenth pad 183 Eleventh pad 184 Twelfth pad 20 Semiconductor device 30 Package substrate 32, 42 Top surface 341 First pad 342 Second pad 343 Third pad 344 Fourth pad 345 Eighteenth pad 351, 352, 353, 354, 355 Bump pad 40 Interposer 441 Plurality of third signal pads 442 Plurality of fourth signal pads 443 Plurality of third power supply pads 444 Plurality of fourth power supply pads 445 Plurality of seventh signal pads 446 Plurality of fifth signal pads 447 Plurality of sixth signal pads 448 Plurality of fifth power supply pads 449 Plurality of sixth power supply pads 451 Thirteenth pad 452 Fourteenth pad 453 Fifteenth pad 454 Sixteenth pad 455 Seventeenth pad 50 C4 bump 60 Microbump TS1 First signal virtual point TS2 Second signal hypothetical point TS3 Third signal hypothetical point TS4 Fourth signal hypothetical point TS5 Fifth signal hypothetical point TS6 Sixth signal hypothetical point TE1 First power supply hypothetical point TE2 Second power supply hypothetical point TE3 Third power supply hypothetical point TE4 Fourth power supply hypothetical point TE5 Fifth power supply hypothetical point TE6 Sixth power supply hypothetical point r1 First distance r2 Second distance r3 Third distance r4 Fourth distance r5 Fifth distance r6 Sixth distance d1, d2, d3, d4, d5, d6, d7, d8, d9 Straight-line distance

Claims

A semiconductor die connectable to a package substrate having first and second pads for transmitting and receiving signals, and third and fourth pads for transmitting and receiving power, a first body having a planar first surface; a plurality of first signal pads and a plurality of second signal pads disposed on the first surface; a plurality of first power supply pads and a plurality of second power supply pads disposed on the first surface; the plurality of first signal pads are arranged at positions where they can be connected to the first pad via one bump; the plurality of second signal pads are arranged at positions where they can be connected to the second pads via one bump; the plurality of first power supply pads are arranged at positions where they can be connected to the third pad via one bump; the plurality of second power supply pads are arranged at positions where they can be connected to the fourth pad via one bump; Semiconductor die. 　 the plurality of first signal pads are arranged within a first distance from a first signal virtual point; the plurality of second signal pads are arranged within the first distance from a second signal virtual point; the plurality of first power supply pads are arranged within a second distance from a first power supply virtual point; the plurality of second power supply pads are arranged within the second distance from a second power supply virtual point; a linear distance between the first signal imaginary point and the second signal imaginary point is greater than twice the first distance; a straight-line distance between the first power supply virtual point and the second power supply virtual point is greater than twice the second distance; The semiconductor die of claim 1 . 　 a linear distance between the first signal virtual point and the first power supply virtual point is greater than twice the first distance; a straight-line distance between the first signal virtual point and the first power supply virtual point is greater than twice the second distance; The semiconductor die of claim 2 . 　 the number of the first power supply pads is equal to or greater than the number of the first signal pads; the number of the first power supply pads is equal to or greater than the number of the second signal pads; the number of the second power supply pads is equal to or greater than the number of the first signal pads; the number of the second power supply pads is equal to or greater than the number of the second signal pads; The semiconductor die of claim 1 . 　 the plurality of first signal pads, the plurality of second signal pads, the plurality of first power supply pads, and the plurality of second power supply pads are pads for microbump connection; the one bump is a C4 bump, the first pad, the second pad, the third pad, and the fourth pad are pads for C4 bump connection; The semiconductor die of claim 1 . 　 the first distance is set so that the plurality of first signal pads and the plurality of second signal pads can contact one C4 bump; the second distance is set so that the plurality of first power supply pads and the plurality of second power supply pads can contact one C4 bump; The semiconductor die of claim 2 . 　 a first body having a planar first surface; a plurality of first signal pads and a plurality of second signal pads disposed on the first surface for transmitting and receiving signals; a plurality of first power supply pads and a plurality of second power supply pads disposed on the first surface for receiving and transmitting electric power; a fifth pad and a sixth pad disposed on the first surface for transmitting and receiving signals; seventh and eighth pads disposed on the first surface for transferring power; a dimension of the fifth pad in a plan view of the first surface is larger than a dimension of each of the plurality of first signal pads in a plan view of the first surface; a dimension of the sixth pad in a plan view of the first surface is larger than a dimension of each of the plurality of second signal pads in a plan view of the first surface; a dimension of the seventh pad in a plan view of the first surface is larger than a dimension of each of the plurality of first power supply pads in a plan view of the first surface; a dimension of the eighth pad in a plan view of the first surface is larger than a dimension of each of the plurality of second power supply pads in a plan view of the first surface; the plurality of first signal pads are arranged within a third distance from a third signal virtual point; the fifth pad is arranged within the third distance from the third signal imaginary point and at a position not overlapping any of the plurality of first signal pads; the plurality of second signal pads are arranged within the third distance from a fourth signal virtual point; the sixth pad is arranged within the third distance from the fourth signal imaginary point and at a position not overlapping any of the plurality of second signal pads; the plurality of first power supply pads are arranged within a fourth distance from a third power supply virtual point; the seventh pad is arranged within the fourth distance from the third power supply virtual point and at a position not overlapping any of the plurality of first power supply pads; the plurality of second power supply pads are arranged within the fourth distance from a fourth power supply virtual point; the eighth pad is arranged within the fourth distance from the fourth power supply virtual point and at a position where it does not overlap any of the plurality of second power supply pads; Semiconductor die. 　 a linear distance between the third signal imaginary point and the fourth signal imaginary point is greater than twice the third distance; a straight-line distance between the third power supply virtual point and the fourth power supply virtual point is greater than twice the fourth distance; The semiconductor die of claim 7 . 　 a straight-line distance between the third signal virtual point and the third power supply virtual point is greater than twice the third distance; a straight-line distance between the third signal virtual point and the third power supply virtual point is greater than twice the fourth distance; The semiconductor die of claim 8 . 　 An interposer connectable to a package substrate having first and second pads for transmitting and receiving signals and third and fourth pads for transmitting and receiving power, and connectable to a semiconductor die having ninth and tenth pads for transmitting and receiving signals and eleventh and twelfth pads for transmitting and receiving power, a second body having planar second and third surfaces; a plurality of fifth signal pads and a plurality of sixth signal pads disposed on the second surface; a plurality of fifth power supply pads and a plurality of sixth power supply pads disposed on the second surface; thirteenth and fourteenth pads disposed on the third surface for transmitting and receiving signals; a fifteenth pad and a sixteenth pad disposed on the third surface for receiving and transmitting power; the second surface is a plane facing the third surface, the fifth signal pads are arranged at positions where they can be connected to the ninth pads via a plurality of microbumps; the sixth signal pads are arranged at positions where they can be connected to the tenth pad via a plurality of microbumps; the plurality of fifth power supply pads are arranged at positions where they can be connected to the eleventh pads via a plurality of microbumps; the sixth power supply pads are arranged at positions where they can be connected to the twelfth pads via a plurality of microbumps; Interposer. 　 the plurality of fifth signal pads are arranged within a fifth distance from a fifth signal imaginary point; the sixth signal pads are arranged within the fifth distance from a sixth signal virtual point; the plurality of fifth power supply pads are arranged within a sixth distance from a fifth power supply virtual point; the sixth power supply pads are arranged within the sixth distance from a sixth power supply virtual point; a linear distance between the fifth signal imaginary point and the sixth signal imaginary point is greater than twice the fifth distance; a straight-line distance between the fifth power supply virtual point and the sixth power supply virtual point is greater than twice the sixth distance; The interposer of claim 10. 　 a straight-line distance between the fifth signal virtual point and the fifth power supply virtual point is greater than twice the fifth distance; a straight-line distance between the fifth signal virtual point and the fifth power supply virtual point is greater than twice the sixth distance; The interposer of claim 11 . 　 the fifth distance is a distance that allows the fifth signal pads and the sixth signal pads to come into contact with one C4 bump; the sixth distance is a distance that allows the fifth power supply pads and the sixth signal pads to come into contact with one C4 bump; The interposer of claim 11 . 　 A semiconductor die according to any one of claims 1 to 6; the package substrate having the first pad and the second pad for transmitting and receiving signals, and the third pad and the fourth pad for transmitting and receiving power; the plurality of first signal pads are bump-connected to the first pads; the plurality of second signal pads are bump-connected to the second pads; the plurality of first power supply pads are bump-connected to the third pads; the plurality of second power supply pads are bump-connected to the fourth pad; Semiconductor devices. 　 A semiconductor die according to any one of claims 1 to 6; an interposer having a plurality of third signal pads and a plurality of fourth signal pads for transmitting and receiving signals, and a plurality of third power supply pads and a plurality of fourth power supply pads for transmitting and receiving power; the plurality of first signal pads are bump-connected to the plurality of third signal pads; the plurality of second signal pads are bump-connected to the plurality of fourth signal pads; the plurality of first power supply pads are bump-connected to the plurality of third power supply pads; the second power supply pads are bump-connected to the fourth power supply pads; The semiconductor die a monitor circuit for measuring a current flowing between the semiconductor die and the interposer when the semiconductor die transmits and receives a signal; a determination circuit that determines a connection state between the semiconductor die and the interposer based on the current value measured by the monitor circuit. Semiconductor devices. 　 The determination circuit, based on the current value measured by the monitor circuit, Identifying the number of abnormal connections among the connections between the plurality of first signal pads and the plurality of third signal pads; Identifying the number of abnormal connections among the connections between the plurality of second signal pads and the plurality of fourth signal pads; 16. The semiconductor device of claim 15. 　 A semiconductor die according to any one of claims 7 to 9; a package substrate having first and second pads for transmitting and receiving signals, and third and fourth pads for transmitting and receiving power; the fifth pad is bump-connected to the first pad; the sixth pad is bump-connected to the second pad; the seventh pad is bump-connected to the third pad; the eighth pad is bump-connected to the fourth pad; Semiconductor devices. 　 the plurality of first signal pads are not bump-connected to the first pads; the plurality of second signal pads are not bump-connected to the second pads; the plurality of first power supply pads are not bump-connected to the third pads, the plurality of second power supply pads are not bump-connected to the fourth pads; 18. The semiconductor device of claim 17. 　 A semiconductor die according to any one of claims 7 to 9; an interposer having a plurality of third signal pads and a plurality of fourth signal pads for transmitting and receiving signals, and a plurality of third power supply pads and a plurality of fourth power supply pads for transmitting and receiving power; the plurality of first signal pads are bump-connected to the plurality of third signal pads; the plurality of second signal pads are bump-connected to the plurality of fourth signal pads; the plurality of first power supply pads are bump-connected to the plurality of third power supply pads; the plurality of second power supply pads are bump-connected to the plurality of fourth power supply pads; Semiconductor devices. 　 the fifth pad is not bump-connected to the plurality of third signal pads, the sixth pad is not bump-connected to the plurality of fourth signal pads, the seventh pad is not bump-connected to the plurality of third power supply pads, the eighth pad is not bump-connected to the plurality of fourth power supply pads; 20. The semiconductor device of claim 19. 　 An interposer according to any one of claims 10 to 13; the semiconductor die having the ninth and tenth pads for transmitting and receiving signals, and the eleventh and twelfth pads for transmitting and receiving power; the fifth signal pads are bump-connected to the ninth pad; the sixth signal pads are bump-connected to the tenth pad; the plurality of fifth power supply pads are bump-connected to the eleventh pads; the sixth power supply pads are bump-connected to the twelfth pads; Semiconductor devices.

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