Varistor device and manufacturing method thereof

Abstract

Disclosed are a varistor device and a manufacturing method thereof. The varistor device comprises: a semiconductor layer including a semiconductor material; a graphene layer stacked on a portion of a surface of the semiconductor layer; a first electrode located on a portion of a surface of the graphene layer; and a second electrode connected to the semiconductor layer, wherein the first electrode comprises a metal material that changes a work function of the graphene layer such that the height of a Schottky barrier between the graphene layer and the semiconductor layer is greater than or equal to a predetermined value.

Description

Varistor element and manufacturing method thereof

[0001] An embodiment of the present invention relates to a varistor element and a method for manufacturing the same.

[0002] The present invention is a result of work carried out as part of the “Development of a Baristor-Based High-Sensitivity Shortwave Infrared Sensor” project of the Small and Medium Business Technology Information Promotion Agency (Research and Development Project No. RS-2024-00444122).

[0003] Graphene is being actively researched as a new material that could replace semiconductors. Graphene has a two-dimensional planar crystal structure with a hexagonal honeycomb pattern. Its thinness, light weight, durability, and excellent conductivity make it a versatile material for a wide range of applications. Recently, a new barristor device utilizing graphene has emerged, functionally similar to a transistor but structurally closer to a diode.

[0004] Varistors are devices that control the current flowing through them by controlling the height of the Schottky junction formed at the junction between graphene and a semiconductor. Varistors can be used as switching devices or as various sensors. For example, varistors can be used in biosensors that detect DNA and various viruses, and gas sensors that measure gas concentrations (e.g., NO2).

[0005] The technical problem to be achieved by the embodiment of the present invention is to provide a varistor element and a method for manufacturing the same without an insulating film between a semiconductor layer and a graphene layer.

[0006] In order to achieve the above technical task, an example of a varistor device according to an embodiment of the present invention includes: a semiconductor layer including a semiconductor material; a graphene layer laminated on a portion of a surface of the semiconductor layer; a first electrode positioned on a portion of the surface of the graphene layer; and a second electrode connected to the semiconductor layer; wherein the first electrode includes a metal material that changes the work function of the graphene layer so that the height of a Schottky barrier between the graphene layer and the semiconductor layer is equal to or greater than a predetermined height.

[0007] In order to achieve the above technical problem, an example of a method for manufacturing a varistor element according to an embodiment of the present invention comprises the steps of: preparing a transfer sheet on which a semiconductor layer including a two-dimensional semiconductor material and a graphene layer are laminated; transferring the semiconductor layer and the graphene layer of the transfer sheet to a substrate; etching the graphene layer to form a pattern; and forming a first electrode on one side of the surface of the graphene layer and forming a second electrode on one side of the surface of the semiconductor layer; wherein the first electrode includes a metal material that changes the work function of the graphene layer so that the height of a Schottky barrier between the graphene layer and the semiconductor layer is equal to or greater than a predetermined height.

[0008] According to an embodiment of the present invention, a varistor device can be implemented without an insulating film between a semiconductor layer and a graphene layer. In another embodiment, a transfer paper on which a semiconductor layer and a graphene layer are laminated can be used to simplify the manufacturing process of the varistor device and increase the degree of junction purity between the semiconductor layer and the graphene layer.

[0009] FIG. 1 is a drawing showing one embodiment of a varistor element according to an embodiment of the present invention;

[0010] FIG. 2 and FIG. 3 are drawings showing another embodiment of a varistor element according to an embodiment of the present invention;

[0011] Figures 4 and 5 are diagrams showing examples of energy band diagrams of a depletion region according to the type of metal constituting the electrode of a varistor element using a p-type semiconductor.

[0012] Figures 6 and 7 are diagrams showing examples of energy band diagrams of a depletion region according to the type of metal constituting the electrode of a varistor element using an n-type semiconductor.

[0013] FIG. 8 is a drawing showing another embodiment of a varistor element according to an embodiment of the present invention;

[0014] FIG. 9 is a drawing showing another embodiment of a varistor element according to an embodiment of the present invention, and

[0015] FIG. 10 is a drawing illustrating an example of a method for manufacturing a varistor element according to an embodiment of the present invention.

[0016] Hereinafter, a varistor element according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

[0017] Fig. 1 is a drawing illustrating one embodiment of a varistor element according to an embodiment of the present invention. Fig. 1 illustrates the upper surface and cross-section of the varistor element.

[0018] Referring to FIG. 1, the varistor element (100) includes a semiconductor layer (110), a graphene layer (120), a first electrode (9130), and a second electrode (140). Depending on the embodiment, the varistor element (100) may further include a reaction layer (160). For convenience of explanation, the present embodiment illustrates and describes a varistor element (100) including a reaction layer (160).

[0019] The semiconductor layer (110) may be implemented with a three-dimensional semiconductor material. Examples of three-dimensional semiconductor materials include silicon and germanium. For example, the semiconductor layer (110) may be implemented with a three-dimensional semiconductor material in which silicon is doped with impurities. In addition, various types of existing three-dimensional semiconductor materials may be used in the present embodiment. The semiconductor layer (1100) may be a p-type or n-type semiconductor. In another embodiment, the semiconductor layer (110) may be implemented with a two-dimensional semiconductor material (see FIG. 7). However, for convenience of explanation, the present embodiment is described assuming that the semiconductor layer (110) is implemented with a p-type three-dimensional semiconductor material.

[0020] The semiconductor layer (110) may include a plurality of doping regions (110-1, 110-2) having the same doping concentration or different doping concentrations. In one embodiment, the semiconductor layer (110) may include a first doping region (110-1) having a first doping concentration and contacting the graphene layer (120), and a second doping region (110-2) having a second doping concentration and contacting the second electrode (140). The first doping concentration of the first doping region (110-1) is 1*10 14 / ㎤ ~ 5*10 18 / cm3, and the second doping concentration of the second doping region (110-2) is 10 19 / ㎤ or more. In addition, the first doping concentration and the second doping concentration can be varied depending on the embodiment.

[0021] In one embodiment, the first doped region (110-1) may be formed to be in contact with the graphene layer (120) in an area excluding the lower portion of the first electrode (130) and to have an area smaller than the area of ​​the graphene layer (120). The depth of the first doped region (110-1) may vary depending on the embodiment. The second doped region (110-2) may be formed to surround the first doped region (110-1) and be in contact with the second electrode (140). For example, the remaining area of ​​the semiconductor layer (110) excluding the first doped region (110-1) may be formed as the second doped region (110-2). In addition, the sizes and positions of the first doped region (110-1) and the second doped region (110-2) can be varied and modified depending on the embodiment so that the first doped region (110-1) is in contact with the graphene layer (120) and the second doped region (110-2) is in contact with the second electrode (140). Various modified examples of the doped region are illustrated in FIGS. 2 and 3.

[0022] The graphene layer (120) is laminated on the semiconductor layer (110). The graphene layer (120) may be laminated on the entire surface of the semiconductor layer (110) or on a portion of the surface. This embodiment illustrates a structure in which the graphene layer (120) is laminated on a portion of the surface of the semiconductor layer (110).

[0023] The first electrode (130) is positioned on one side of the graphene layer (120). In other words, the first electrode (130) is laminated on a part of the surface of the graphene layer (120), not the entire surface. The first electrode (130) only contacts the graphene layer (120) and does not contact the semiconductor layer (110). This embodiment shows an example in which the first electrode (130) is formed in the shape of a square fence, but this is only one example, and the shape of the first electrode (130) can be modified in various ways depending on the embodiment.

[0024] The second electrode (140) is connected to the semiconductor layer (110). In one embodiment, the second electrode (140) may be formed on the lower surface of the semiconductor layer (110) to face the graphene layer (120). The second electrode (140) may be made of the same material as the first electrode (130) or may be made of a different material. In another embodiment, the second electrode (140) may be formed on the lower surface of the semiconductor layer (110) in a size corresponding to the area of ​​the first doped region (110-1). In yet another embodiment, the first electrode (130) and the second electrode (140) may be arranged so as not to face each other with the semiconductor layer (110) interposed therebetween. In the present embodiment, the first electrode (130) has a rectangular fence shape, and the second electrode (140) is arranged to correspond to the inner surface of the rectangular fence shape. However, this is only one example, and the shape and arrangement of the first electrode (130) and the second electrode (140) can be modified in various ways depending on the embodiment.

[0025] In another embodiment, the second electrode (140) may be formed by extending to the upper surface (140-2, 140-3) of the semiconductor layer (110) through a through hole (not shown). In this case, an extension line (140-1) or the like, which extends the second electrode formed on the lower surface of the semiconductor layer (110) to the second electrode on the upper surface of the semiconductor layer, may be present on the lower surface of the semiconductor layer (110).

[0026] The reaction layer (160) is laminated on a portion of the surface of the graphene layer (120). In the present embodiment, the reaction layer (160) exists inside the first electrode (130) in the shape of a square fence. Depending on the embodiment, the reaction layer (160) may be omitted. In one embodiment, when the baristor device (100) is implemented as a biosensor, the reaction layer (160) may include a biomolecule (DNA, RNA, antigen, antibody, enzyme, etc.). In another embodiment, the reaction layer (160) may include lead sulfide quantum dots. In yet another embodiment, when the baristor device (100) is implemented as a pressure sensor, the reaction layer (160) may be implemented as a pressure measuring structure. In addition, the reaction layer may be variously modified depending on the embodiment and is not limited to the present embodiment.

[0027] In order to implement a varistor element (100), current must flow through the first electrode (130) and the graphene layer (120) and must not flow to the depletion region (150) below the first electrode (130). To this end, an insulating film is generally formed between the graphene layer (120) located below the first electrode (130) and the semiconductor layer (130). However, the insulating film complicates the manufacturing process of the varistor element (100) and lowers the cleanliness between the graphene layer (120) and the semiconductor layer (130).

[0028] Accordingly, the present embodiment presents a varistor element (100) in which no insulating film exists between a graphene layer (120) and a semiconductor layer (130). The depletion region (150) is a space in which the energy band of the semiconductor layer (110) is bent due to the difference in Fermi levels of the metals constituting the graphene layer (120) and the first electrode (130). In the depletion region (150), there are no mobile charges, and only space charges due to semiconductor doping ions exist, and an electric field is generated and the energy band is bent due to this space charge.

[0029] When a metal comes into contact with graphene, the work function of the graphene changes depending on the type of metal. Depending on the change in the work function of the graphene, the energy band between the junction of the graphene and the semiconductor bends and the Schottky barrier is determined. Therefore, the first electrode (130) is implemented with a metal that can increase the Schottky barrier between the graphene layer (120) and the semiconductor layer (110) so that current does not flow to the depletion region (150) below the first electrode (130) even when there is no insulating film between the graphene layer (120) and the semiconductor layer (110).

[0030] In one embodiment, the first electrode (130) may be formed of Al, Ag, or Cu to increase the Schottky barrier of the p-type semiconductor depletion region (150). When the first electrode (130) is formed of Al, Ag, or Cu, the Schottky barrier of the depletion region (150) increases, resulting in little current flowing in the depletion region (150). However, when the first electrode (130) is formed of Au, Pt, or the like, the Schottky barrier of the depletion region (150) decreases, allowing current to flow smoothly. Examples of various energy band diagrams of the Schottky barrier according to the type of metal constituting the first electrode (130) are illustrated in FIGS. 4 and 5.

[0031] In another embodiment, the first electrode (130) may be formed of Au or Pt to increase the Schottky barrier of the n-type semiconductor depletion region (150). When the first electrode (130) is formed of Au or Pt, the Schottky barrier of the depletion region (150) increases, resulting in little current flowing in the depletion region (150). However, when the first electrode (130) is formed of Al, Ag, or Cu, the Schottky barrier of the depletion region (150) decreases, allowing current to flow smoothly.

[0032] FIG. 2 and FIG. 3 are drawings illustrating another embodiment of a varistor element according to an embodiment of the present invention.

[0033] Referring to FIG. 2, the varistor element (100) includes a semiconductor layer (110), a graphene layer (120), a first electrode (130), and a second electrode (140). The varistor element (100) of FIG. 2 is different from the varistor element (100) of FIG. 1 only in the first doping region (220) and the second doping region (210), and the remaining configurations are all the same.

[0034] The first doped region (220) of the present embodiment has a size corresponding to the entire surface of the graphene layer (120). For example, the first doped region (220) may include a larger area than the graphene layer (120). The second doped region (210) may be formed as a region that surrounds the entire first doped region (220). The first doped region (220) is connected to the graphene layer (110), and the second doped region (210) is connected to the second electrode (140). In addition, the size and depth of the first doped region (220) and the second doped region (210) may be variously modified depending on the embodiment.

[0035] Referring to FIG. 3, the varistor element (100) includes a semiconductor layer (110), a graphene layer (120), a first electrode (130), and a second electrode (140). The varistor element (100) of FIG. 3 is different from the varistor element (100) of FIG. 1 in that the first doped region (300) and the second doped region (310) are different, and further, the varistor element (100) does not include a configuration (140-2, 140-3) in which the second electrode (140) extends onto the surface of the semiconductor layer (110).

[0036] The first doped region (300) of the present embodiment is configured to have a larger area than the graphene layer (120), similar to the first doped region (220) of the varistor element of FIG. 2. However, the second doped region (310) is not formed to completely surround the first doped region (300), but is partially formed between the lower portion of the first doped region (300) and the second electrode (140).

[0037] FIG. 4 and FIG. 5 are drawings showing examples of energy band diagrams of a depletion region according to the type of metal constituting the electrode of a varistor element using a p-type semiconductor.

[0038] Referring to FIG. 4, an energy band diagram of a depletion region (150) that appears when the first electrode (130) of a varistor element (100) including a p-type semiconductor is implemented with Au or Pt is illustrated. When the first electrode (130) is implemented with Au or Pt, the Fermi level of the graphene layer (120) shifts in the positive (+) direction, and as a result, the Schottky barrier of the depletion region (150) is lowered to a level where current can flow smoothly (400).

[0039] Referring to FIG. 5, an energy band diagram of a depletion region that appears when the first electrode (130) of a varistor element (100) including a p-type semiconductor is implemented with Al, Ag, or Cu is illustrated. When the first electrode (130) is Al, Ag, or Cu, the Fermi level of the graphene layer (120) shifts in the negative (-) direction, and as a result, the Schottky barrier of the depletion region (150) increases. Therefore, current does not flow well through the depletion region (150) (500). The high Schottky barrier acts as an insulating film between the graphene layer (120) and the semiconductor layer (130).

[0040] FIG. 6 and FIG. 7 are drawings showing examples of energy band diagrams of a depletion region according to the type of metal constituting the electrode of a varistor element using an n-type semiconductor.

[0041] Referring to FIG. 6, an energy band diagram of a depletion region (150) that appears when the first electrode (130) of a varistor element (100) including an n-type semiconductor is implemented with Al, Ag, or Cu is illustrated. When the first electrode (130) is implemented with Al, Ag, or Cu, the Fermi level of the graphene layer (120) shifts in the negative (-) direction, and as a result, the Schottky barrier of the depletion region (150) is lowered to a level where current can flow smoothly (600).

[0042] Referring to FIG. 7, an energy band diagram of a depletion region that appears when the first electrode (130) of a varistor element (100) including an n-type semiconductor is implemented with Au or Pt is illustrated. When the first electrode (130) is Au or Pt, the Fermi level of the graphene layer (120) shifts in the positive (+) direction, and as a result, the Schottky barrier of the depletion region (150) increases. Therefore, current does not flow well through the depletion region (150) (700). The high Schottky barrier acts as an insulating film between the graphene layer (120) and the semiconductor layer (130).

[0043] FIG. 8 is a drawing illustrating another embodiment of a varistor element according to an embodiment of the present invention.

[0044] Referring to FIG. 8, the varistor element (100) includes a semiconductor layer (110), a graphene layer (120), a first electrode (130), and a second electrode (140). The graphene layer (120), the first electrode (130), and the second electrode (140) of the varistor element (100) of FIG. 8 are the same as those of the varistor element (100) of FIG. 1. The first doped region (810) and the second doped region (820) constituting the semiconductor layer (110) of the present embodiment are similar to the first doped region (110-1) and the second doped region (110-2) of the semiconductor layer (110) of FIG. 1.

[0045] However, the present embodiment includes an intrinsic area (800) rather than a depletion area (150 in FIG. 1) below the first electrode (130). That is, a portion of the semiconductor layer (110) located below the first electrode (130) may be formed as an intrinsic area (800) that is not doped with impurities, thereby preventing current from flowing to the semiconductor layer below the first electrode (130). In order to locally form different doping areas (810, 820) and an intrinsic area (800) in the semiconductor layer (110), the semiconductor layer (110) may be implemented as a three-dimensional semiconductor.

[0046] Fig. 9 is a drawing illustrating another embodiment of a varistor element according to an embodiment of the present invention. Fig. 9 illustrates a top surface and a cross-section of the varistor element.

[0047] Referring to FIG. 9, the varistor element (900) includes a semiconductor layer (920), a graphene layer (930), a first electrode (940), and a second electrode (950). According to an embodiment, the varistor element (900) may be formed on a substrate (910).

[0048] The semiconductor layer (920) is implemented using a two-dimensional semiconductor material. In one embodiment, the semiconductor layer (920) may be implemented using a thin film structure. Various existing two-dimensional semiconductor materials, such as transition metal chalcogenides, may be used in this embodiment.

[0049] A graphene layer (930) is laminated on a portion of the surface of a semiconductor layer (920). A first electrode (940) is positioned on a portion of the surface of the graphene layer (930), and a second electrode (950) is positioned on one side of the semiconductor layer (920) without being in contact with the graphene layer. That is, the first electrode (940) is connected to the graphene layer (730), and the second electrode (950) is connected to the semiconductor layer (920). A junction region (970) of the graphene layer and the semiconductor layer exists between the first electrode (940) and the second electrode (950).

[0050] This embodiment has a structure in which no insulating film exists between the graphene layer (930) and the semiconductor layer (920). In order to increase the Schottky barrier of the depletion region (960) so that current does not flow through the depletion region (960) at the lower part of the first electrode (940), if the semiconductor is p-type, the first electrode (940) can be implemented with Al, Ag, or Cu as shown in FIG. 5. If the semiconductor is n-type, the first electrode (940) can be implemented with Au or Pt as shown in FIG. 7.

[0051] When the semiconductor layer (930) is implemented as a thin film structure, the varistor element can be easily manufactured using a roll-to-roll method, and the manufacturing method is examined again in FIG. 10.

[0052] FIG. 10 is a drawing illustrating an example of a method for manufacturing a varistor element according to an embodiment of the present invention.

[0053] Referring to FIGS. 9 and 10, a transfer sheet is prepared by stacking a thin semiconductor layer (920) implemented as a two-dimensional semiconductor material and a graphene layer (930) thereon. For example, a semiconductor layer (920), a graphene layer (930), and a polymer support (not shown), all implemented as thin films, may be bonded together using a roller to create a transfer sheet. In one embodiment, the transfer sheet may be prepared in a form wound around a roller. In addition, the transfer sheet may be prepared in advance in various forms. This embodiment assumes that the transfer sheet is prepared in advance.

[0054] The semiconductor layer (920) and the graphene layer (930) of the transfer paper are transferred to the substrate (910). In one embodiment, the transfer paper is attached to the substrate using a roller, and then the polymer support is removed to transfer the semiconductor layer (920) and the graphene layer (930) to the substrate (910). In addition, various methods for transferring the semiconductor layer (920) and the graphene layer (930) of the transfer paper to the substrate can be applied to this embodiment.

[0055] After transferring the semiconductor layer (920) and the graphene layer (930) to the substrate (910), the graphene layer (930) is etched. In the present embodiment, the semiconductor layer (920) and the graphene layer (930) are prepared in advance and then transferred to the substrate (910) as is, thereby resolving the problem of impurities remaining between the semiconductor layer (920) and the graphene layer (930) during the etching process, and maintaining a high level of cleanliness in the bonding area.

[0056] After etching, a first electrode (940) is formed on one side of the graphene layer (930), and a second electrode (950) is formed on one side of the semiconductor layer (920).

[0057] As seen in Fig. 9, in order to prevent current from flowing below the first electrode (940) even when the graphene layer (930) and the semiconductor layer (920) are joined, the first electrode (940) is implemented with Al, Ag, or Cu when the semiconductor layer (920) is a p-type semiconductor, and the first electrode (940) is implemented with Au or Pt when the semiconductor layer (920) is an n-type semiconductor, thereby increasing the Schottky barrier. Therefore, there is no need to form an insulating film between the graphene layer (930) located below the first electrode (940) and the semiconductor layer (920), or to etch a portion of the semiconductor layer (920) below the graphene layer (930) where the first electrode (940) is located. Since a varistor element can be formed through one transfer process and one etching process using a transfer paper in which a semiconductor layer (920) and a graphene layer (930) are laminated, the number of processes can be significantly reduced compared to the process of a conventional varistor element.

[0058] The present invention has been described above, focusing on preferred embodiments thereof. Those skilled in the art will appreciate that the present invention can be implemented in modified forms without departing from its essential characteristics. Therefore, the disclosed embodiments should be considered illustrative rather than limiting. The scope of the present invention is set forth in the claims, not the foregoing description, and all differences within the scope equivalent thereto should be construed as being encompassed by the present invention.

Claims

1. A semiconductor layer containing a semiconductor material; A graphene layer laminated on a portion of the surface of the semiconductor layer; A first electrode positioned on a portion of the surface of the graphene layer; A second electrode connected to the semiconductor layer; A varistor element characterized in that the first electrode includes a metal material that changes the work function of the graphene layer so that the height of the Schottky barrier between the graphene layer and the semiconductor layer is a certain level or more.

2. In paragraph 1, A varistor element characterized in that the metal material of the first electrode includes one of Al, Ag, and Cu when the semiconductor layer is p-type, and includes Au or Pt when the semiconductor layer is n-type.

3. In paragraph 1, A varistor element characterized in that the semiconductor layer is implemented with a three-dimensional semiconductor material.

4. In the first paragraph, the semiconductor layer, A first doping region in contact with the graphene layer and doped with a first doping concentration; and A varistor element characterized by including a second doping region doped with a second doping concentration and in contact with the second electrode.

5. In paragraph 4, The above first doping concentration is 1*10 14 / ㎤ ~ 5*10 18 / ㎤, The above second doping concentration is 10 19 A varistor element characterized by having a / ㎤ or more.

6. In the first paragraph, the semiconductor layer, A varistor element characterized by including an intrinsic region formed on the lower portion of the graphene layer corresponding to the first electrode.

7. In paragraph 1, A baristor device characterized by further comprising a reaction layer present on the graphene layer and including a biomaterial, a pressure measuring structure, or a quantum dot.

8. In paragraph 1, A varistor element characterized in that the second electrode is located on the lower surface of the semiconductor layer facing the graphene layer.

9. In paragraph 1, A varistor element characterized in that the second electrode extends to the upper surface of the semiconductor layer through a through hole.

10. In paragraph 1, A varistor element characterized in that the second electrode is implemented with the same material as the first electrode.

11. In paragraph 1, A varistor element characterized in that the semiconductor layer is a thin film structure implemented with a two-dimensional semiconductor material.

12. In paragraph 11, The second electrode is located on one side of the surface of the semiconductor layer, A varistor element characterized in that a junction region of a semiconductor layer and a graphene layer exists between the first electrode and the second electrode. A step of preparing a transfer paper in which a semiconductor layer including a 13.2-dimensional semiconductor material and a graphene layer are laminated; A step of transferring the semiconductor layer and graphene layer of the above transfer paper to a substrate; A step of forming a pattern by etching the graphene layer; and A step of forming a first electrode on one side of the surface of the graphene layer and forming a second electrode on one side of the surface of the semiconductor layer; A method for manufacturing a varistor element, characterized in that the first electrode includes a metal material that changes the work function of the graphene layer so that the height of the Schottky barrier between the graphene layer and the semiconductor layer is a certain level or more.

14. In paragraph 13, A method for manufacturing a varistor element, characterized in that the metal material of the first electrode includes one of Al, Ag, and Cu when the semiconductor layer is p-type, and includes Au or Pt when the semiconductor layer is n-type.

15. In the 13th paragraph, the step of preparing the transfer paper is as follows: A method for manufacturing a varistor element, comprising: a step of creating a transfer sheet by attaching a semiconductor layer, a graphene layer, and a polymer support having a thin film structure realized with a two-dimensional semiconductor material using a roller; 16. In paragraph 15, the step of transferring, A method for manufacturing a varistor element, characterized by comprising the step of transferring a semiconductor layer and a graphene layer of the transfer paper to the substrate using a roller.

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