Electrostatic discharge cell characterization for electrostatic discharge rule checking

Abstract

This application discloses a computing system to identify a first portion of an electrostatic discharge path in a physical design layout describing an electronic device is within at least one electrostatic discharge cell of the electronic device, and to access a library including the at least one electrostatic discharge cells to identify a first resistance corresponding to the first portion of the electrostatic discharge cell. The computing system also can determine a second resistance of a second portion of the electrostatic discharge path, generate a path resistance for the electrostatic discharge path by aggregating the first resistance and the second resistance, and perform an electrostatic discharge design rule check using the path resistance of the electrostatic discharge path and electrostatic discharge design rules.

Description

202413368 ELECTROSTATIC DISCHARGE CELL CHARACTERIZATION FOR ELECTROSTATIC DISCHARGE RULE CHECKING RELATED APPLICATION

[0001] This patent application claims priority to U.S. Provisional Patent Application No.63 / 677,680, filed July 31, 2024, which is incorporated by reference herein. TECHNICAL FIELD

[0002] This application is generally related to electronic design automation and, morespecifically, to electrostatic discharge cell characterization for electrostatic discharge rule checking. BACKGROUND

[0003] In a design flow for fabricating integrated circuits, a physical design of an integratedcircuit can describe specific geometric elements, often referred to as a layout design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the integrated circuit. Typically, a designer will select groups of geometric elements representing circuit device components, e.g., contacts, gates, etc., and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines are then placed202413368 between these geometric elements according to the predetermined route. These lines will form the wiring used to interconnect the electronic devices.

[0004] Descriptions for physical designs of integrated circuits can be provided inmany different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional (2D) graphical circuit layout data. Among other features, it contains a hierarchy of structures, each structure including layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway, EDDM, and Open Artwork System Interchange Standard (OASIS). These various industry formats are used to define the geometrical information in layout designs that are employed to manufacture integrated circuits. Once the design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the circuit using a photolithographic process.

[0005] Many foundries generate design connectivity rules, which can be used to ensurethe connectivity in the layout designs has appropriate characteristics. For example, when utilizing the design connectivity rules to check electrostatic discharge (ESD) paths in the layout designs, designers can determine whether a resistance along each ESD path in the layout design falls below an acceptable threshold. During ESD events, the ESD paths in layout designs allow excess charge to traverse through an integrated circuit from a pad of the integrated circuit (IC) chip to an ESD protection device within an ESD cell. Typically, the resistance of an ESD path can be measured from a pin of the ESD protection device to the pad of the IC chip. However, with the advancement of integrated circuit technology and implementation, such as in three-dimensional integrated circuits (3DIC) applications202413368 having multiple IC chip designs or in advanced semiconductor process nodes where an IC chip design has large numbers of transistors and pads, measuring these electrostatic discharge path resistances can be impractical due to the long runtimes and peak consumption of memory resources. To combat this impracticality, designers have begun measuring resistances along a portion of the electrostatic discharge path, i.e., from a port of the ESD cell to the pad of the IC chip design, which provides an inaccurate resistance calculation for the electrostatic discharge path but does so within a practical timeframe and with a practical computing resource utilization. SUMMARY

[0006] This application discloses a computing system to identify a first portion of anelectrostatic discharge path in a physical design layout describing an electronic device is within at least one electrostatic discharge cell of the electronic device, and to access a library including the at least one electrostatic discharge cells to identify a first resistance corresponding to the first portion of the electrostatic discharge cell. The computing system also can determine a second resistance of a second portion of the electrostatic discharge path, generate a path resistance for the electrostatic discharge path by aggregating the first resistance and the second resistance, and perform an electrostatic discharge design rule check using the path resistance of the electrostatic discharge path and electrostatic discharge design rules. Embodiments of will be described below in greater detail. DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 and 2 illustrate an example of a computer system of the type that may beused to implement various embodiments.202413368

[0008] Figure 3 illustrates an example of reliability verification system having a cellcharacterization system may be implemented according to various embodiments.

[0009] Figure 4 illustrates a flowchart showing an example implementation of electrostaticdischarge cell characterization according to various examples.

[0010] Figure 5 illustrates an example implementation of parasitic extraction according tovarious embodiments.

[0011] Figure 6 illustrates a flowchart showing an example implementation of resistancemeasurement for electrostatic discharge paths for electrostatic discharge rule checking according to various examples.

[0012] Figures 7A-7D illustrate example configurations according to various examples.DETAILED DESCRIPTION Illustrative Operating Environment

[0013] Various examples may be implemented through the execution of softwareinstructions by a computing device 101, such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processor unit 105 and a system memory 107. The processor unit 105 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the202413368 read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processor unit 105.

[0014] The processor unit 105 and the system memory 107 are connected, either directlyor indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 115-123. For example, the processor unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117, which can be magnetic and / or removable, a removable optical disk drive 119, and / or a flash memory card. The processor unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101, one or more of the peripheral devices 115-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-123 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0015] With some implementations, the computing unit 103 may be directly or indirectlyconnected to a network interface 115 for communicating with other devices making up a network. The network interface 115 can translate data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination202413368 of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0016] It should be appreciated that the computing device 101 is illustrated as anexample only, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device 101 illustrated in Figure 1, which include only a subset of the components illustrated in Figure 1, or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0017] With some implementations, the processor unit 105 can have more than oneprocessor core. Accordingly, Figure 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments. As seen in this figure, the processor unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its202413368 corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and / or instructions for execution.

[0018] Each processor core 201A and 201B is connected to an interconnect 207. Theparticular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 105. With some processor cores 201A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201A and 201B communicate through the interconnect 207 with an input / output interface 209 and a memory controller 210. The input / output interface 209 provides a communication interface to the bus 113. Similarly, the memory controller 210 controls the exchange of information to the system memory 107. With some implementations, the processor unit 105 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201A and 201B. It also should be appreciated that the description of the computer network illustrated in Figure 1 and Figure 2 is provided as an example only, and is not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments. Electrostatic Discharge Cell Characterization for Electrostatic Discharge Rule Checking

[0019] Figure 3 illustrates an example of reliability verification system 300 having a cellcharacterization system 310 may be implemented according to various embodiments.202413368 Figure 4 illustrates a flowchart showing an example implementation of electrostatic discharge cell characterization according to various examples. Referring to Figures 3 and 4, the reliability verification system 300 can receive a physical design layout 302 that, for example, can describe an electronic device in terms of planar geometric shapes corresponding to patterns of metal, oxide, or semiconductor layers that make up components of the electronic device. The physical design layout 302 can include one or more electrostatic discharge design cells 301 that describe circuitry including electrostatic discharge protection devices utilized to protect the electronic device from excess electrostatic charge. The reliability verification system 300 also can receive the electrostatic discharge design cells 301, for example, from a cell library, implemented in the physical design layout 302. In some embodiments, the electrostatic discharge design cells 301 and the physical design layout 302 can describe or model electronic devices in a Graphic Data System II (GDSII) format, an Open Access format, a Milkyway format, an EDDM format, an Open Artwork System Interchange Standard (OASIS) format, or the like.

[0020] The reliability verification system 300 can include a cell characterization system 310to characterize the electrostatic discharge design cells 301. In some embodiments, the cell characterization system 310 can analyze the electrostatic discharge design cells 301 from the cell library to determine a resistance from pins of electrostatic discharge protection device within the electrostatic discharge design cells 301 to the ports of the electrostatic discharge design cells 301.

[0021] The cell characterization system 310 can include a connectivity system 312 that, in ablock 401 of Figure 4, can determine a connectivity of the electrostatic discharge design202413368 cells 301, such as an identification of interfaces of the electrostatic discharge design cells 301, identification of electrostatic discharge protection devices within the electrostatic discharge design cells 301, and the connectivity within the electrostatic discharge design cells 301. The connectivity system 312 can provide the electrostatic discharge design cells 301 to a device extraction system 330, for example, as one or more design files 304. The device extraction system 330 can analyze the electrostatic discharge design cells 301 to identify ports of the electrostatic discharge design cells 301, identify a presence of the electrostatic discharge protection devices in the electrostatic discharge design cells 301, and the connectivity between the ports of the electrostatic discharge design cells 301 and pins of the electrostatic discharge protection devices. In some embodiments, the device extraction system 330 can be a Layout Versus Schematic (LVS) tool to generate a schematic of the electrostatic discharge cells 301 from the design file 304, which includes a device connectivity 331 within the electrostatic discharge cells 301. The device extraction system 330 can provide the device connectivity 331 to the connectivity system 312.

[0022] The connectivity system 312 can identify the ports of the electrostatic dischargedesign cells 301 and pins of the electrostatic discharge protection devices from the device connectivity 331. The connectivity system 312, in a block 402 of Figure 4, can identify one or more paths in the electrostatic discharge design cells 301 that couple the ports of the electrostatic discharge design cells 301 and pins of the electrostatic discharge protection devices from the device connectivity 331.

[0023] The cell characterization system 310 can include a measurement system 314, in ablock 403 in Figure 4, can determine resistances of the paths between the ports of the electrostatic discharge design cells 301 and pins of the electrostatic discharge protection202413368 devices in the electrostatic discharge design cells 301. In some embodiments, the measurement system 314 can provide a parasitic extraction system 340 with the circuit designs 305, such as the electrostatic discharge design cells 301 or a portion thereof. The parasitic extraction system 340 can perform parasitic extraction on the electrostatic discharge design cells 301 to generate parasitic netlists 341 corresponding to the electrical connectivity in the electrostatic discharge design cells 301. For example, the parasitic extraction system 340 can convert the electrostatic discharge design cells 301 or a portion thereof into an electrical representation, such as a group of electrically-independent parasitic models, and generate the parasitic netlist 341 including the electrical representation of the electrostatic discharge design cells 301. In some embodiments, the parasitic netlist 341 can describe or model the electronic device in a Standard Parasitic Exchange Format (SPEF), or the like. Examples of parasitic extraction will be described below in greater detail with reference to Figure 5.

[0024] Figure 5 illustrates an example implementation of parasitic extraction according tovarious embodiments. Referring to Figure 5, a physical design layout 510 can describe an electronic device in terms of planar geometric shapes corresponding to patterns of metal, oxide, or semiconductor layers that make up components of the electronic device. In some embodiments, the physical design layout 510 can describe or model the electronic device in in a Graphic Data System II (GDSII) format, an Open Access format, a Milkyway format, an EDDM format, an Open Artwork System Interchange Standard (OASIS) format, or the like.

[0025] The physical design layout 510, in some embodiments, can include an array ofstandard cells 511, each including circuitry, such as a group of one or more transistors and202413368 interconnect structures to provide, for example, Boolean logic, storage, or the like, and at least one pins coupled to the circuitry. The physical design layout 510 can include nets 513A-513F to describe wires or electrical paths between pins in the physical design layout 304, for example, to interconnect circuitry in the standard cells 511. The physical design layout 510 also can include additional metal layers, such as metal traces 512, and vias 514 to interconnect different layers of the physical design layout 510.

[0026] During parasitic extraction, a parasitic extraction tool can extract nets from thephysical design layout 510 and convert the nets 513 into one or more corresponding electrical representations. For simplicity, Figure 5 shows the parasitic extraction of nets 513A and 513B and their conversion into a parasitic electrical model 530. The parasitic electrical model 530 can include an electrical representation of net 513A coupled to an electrical representation of net 513B with coupling capacitors CC.

[0027] Referring back to Figures 3 and 4, the measurement system 314 can identifyresistance networks 306 from the parasitic netlists 341 that correspond to the paths in the electrostatic discharge cells 301. In some embodiments, the measurement system 314 can parse the parasitic netlist 341 to identify resistive nets associated with the paths in the electrostatic discharge cells 301 and construct the resistive networks 306 from the identified resistive nets associated with the paths in the electrostatic discharge cells 301.

[0028] The measurement system 314 can provide the resistance networks 306 to asimulator 350, which can perform a simulation of signals on the resistance networks 306 to determine effective resistances 351 of the resistance networks 306. The effective202413368 resistances 351 of the resistance networks 306 determined from the simulation can correspond to resistances of the paths in the electrostatic discharge design cells 301.

[0029] The cell characterization system 310 can include a library system 316 that, in ablock 404 of Figure 4, can modify the electrostatic discharge design cells 301 to include an identification of the effective resistances of the paths between the pins of the electrostatic discharge protection devices and the ports of the electrostatic discharge design cells 301. In some embodiments, the electrostatic discharge design cells 301 can be included in a cell library, and the library system 316 can access each of the electrostatic discharge cells 301 in the cell library and annotate them with the effective resistances of the paths.

[0030] Figure 6 illustrates a flowchart showing an example implementation of resistancemeasurement for electrostatic discharge paths for electrostatic discharge rule checking according to various examples. Referring to Figures 3 and 6, the reliability verification system 300 includes an electrostatic discharge system 320 to identify electrostatic discharge paths in the physical design layout 302 and to determine path resistances 307 associated with each of the identify electrostatic discharge paths.

[0031] The electrostatic discharge system 320 can include a path identification system 322that, in a block 601 of Figure 6, can identify the electrostatic discharge paths in a physical design layout 302. In some embodiments, the path identification system 322 can determine a connectivity of the physical design layout 302, such as an identification of pads in one or more integrated circuit dies described by the physical design layout 302, an identification of the electrostatic discharge design cells 301 within the physical design layout 302, and the202413368 connectivity of the electrostatic discharge design cells 301 to each other and to the pads in one or more integrated circuit dies described by the physical design layout 302.

[0032] The path identification system 322 can provide the physical design layout 302 to thedevice extraction system 330, for example, as one or more of the design files 304. The device extraction system 330 can perform device-level extraction on the physical design layout 302 to identify ports of the electrostatic discharge design cells 301, electrostatic discharge protection devices within the electrostatic discharge design cells 301, pins of the electrostatic discharge protection devices, identify pads in one or more integrated circuit dies, and the connectivity of the pins of the electrostatic discharge protection devices to each other, the ports of the electrostatic discharge design cells 301 to each other and the pads in one or more integrated circuit dies. In some embodiments, the device extraction system 330 can be a Layout Versus Schematic (LVS) tool to generate a schematic of the physical design layout 302 from the design files 304 and determine the connectivity in the physical design layout 302. The device extraction system 330 can provide a device connectivity 331 of the physical design layout 302 to the path identification system 322.

[0033] The path identification system 322 can identify one or more electrostatic dischargepaths in the physical design layout 302, which can have at least one of their endpoints as corresponding to the pins of the electrostatic discharge protection devices. The path identification system 322 can move the endpoints of the electrostatic discharge paths from the pins of the electrostatic discharge protection devices to the ports of the electrostatic discharge design cells 301 that include the electrostatic discharge protection devices. The movement of the endpoints of the electrostatic discharge paths from the pins of the electrostatic discharge protection devices to the ports of the electrostatic discharge design202413368 cells 301 can allow the electrostatic discharge system 320 to determine path resistances 307 for the electrostatic discharge paths by measuring the electrostatic discharge paths from the ports of the electrostatic discharge design cells 301 and utilize the characterized electrostatic discharge design cells 301 for the resistances between the pins and the ports, which can reduce runtime computational resources without sacrificing accuracy of the path resistance 307. In some embodiments, the electrostatic discharge system 320 can measure a path resistance 307 of an electrostatic discharge path from the port of the electrostatic discharge design cell 301 instead of a pin of an electrostatic discharge protection device, which can consume fewer computing resources, but at the cost of measurement accuracy for the path resistance 307. In other embodiments, the electrostatic discharge system 320 can allow for selective reversion of the endpoint of the electrostatic discharge path back to the pin of the electrostatic discharge protection device, for example, for critical electrostatic discharge paths, which can allow for a more accurate resistance measurement for those selected paths, but with some additional runtime computational resource utilization.

[0034] The path identification system 322, in a block 602 of Figure 6, can determine a firstportion of the electrostatic discharge path is within at least one electrostatic discharge cell in the physical design layout 302, while also determining a second portion of the electrostatic discharge path is outside of the electrostatic discharge cells in the physical design layout 302. In some embodiments, the path identification system 322 can determine the first portion of the electrostatic discharge path is within at least one electrostatic discharge cell when at least one of the endpoints of the electrostatic discharge path is within at least one of the electrostatic discharge design cells 301, such as at a pin of an electrostatic discharge protection device in an electrostatic discharge design cell. Examples202413368 of different integrated circuit configurations with electrostatic discharge paths will be described below with reference to Figures 7A-7D.

[0035] Figures 7A-7D illustrate example integrated circuit configurations with electrostaticdischarge paths according to various examples. Referring to Figures 7A, an integrated circuit die 710 can include integrated circuitry having an electrostatic discharge path to allow excess charge to traverse from a pad 715 of the integrated circuit die 710 to an electrostatic discharge (ESD) device 712 within an ESD cell 711. A resistance of the electrostatic discharge path can be measured in two parts, for example, a first resistance 716 of a portion of the electrostatic discharge path between a cell port 713 of the ESD cell 711 and a device pin 714 of the ESD device 712, and a second resistance 717 of another portion of the electrostatic discharge path between the cell port 713 and the pad 715. The resistance of the electrostatic discharge path can correspond to a sum of the first resistance 716 and the second resistance 717.

[0036] Referring to Figures 7B, an integrated circuit die 720 can include integratedcircuitry having an electrostatic discharge path to allow excess charge to traverse from an electrostatic discharge (ESD) device 722A within an ESD cell 721A to an ESD device 722B within an ESD cell 721B. A resistance of the electrostatic discharge path can be measured in three parts, for example, a first resistance 725 of a portion of the electrostatic discharge path between a cell port 723A of the ESD cell 721A and a device pin 724A of the ESD device 722A, a second resistance 726 of another portion of the electrostatic discharge path between the cell port 723A and a cell port 723B of the ESD cell 721B, and a third resistance 727 of another portion of the electrostatic discharge path between the cell port 723B and a device pin 724B of the ESD device 722B. The resistance of the electrostatic discharge path can202413368 correspond to a sum of the first resistance 725, the second resistance 726, and the third resistance 727.

[0037] Referring to Figures 7C, a pair of integrated circuit dies 730 and 740 can includeintegrated circuitry having an electrostatic discharge path to allow excess charge to traverse from an electrostatic discharge (ESD) device 732 within an ESD cell 731 of the integrated circuit die 730 to an ESD device 742 within an ESD cell 741 of the integrated circuit die 740. A resistance of the electrostatic discharge path can be measured in five parts, for example, a first resistance 736 of a portion of the electrostatic discharge path between a cell port 733 of the ESD cell 731 and a device pin 734 of the ESD device 732, a second resistance 737 between the cell port 733 and a pad 735 of the integrated circuit die 730, a third resistance 738 between the pad 735 of the integrated circuit die 730 and a pad 745 of the integrated circuit die 740, a fourth resistance 746 between a cell port 743 of the ESD cell 741 and a pad 745, and a fifth resistance 747 between a cell port 743 of the ESD cell 741 and a device pin 744 of the ESD device 742. The resistance of the electrostatic discharge path can correspond to a sum of the first resistance 736, the second resistance 737, the third resistance 738, the fourth resistance 746, and the fifth resistance 747.

[0038] Referring to Figures 7D, a pair of integrated circuit dies 750 and 760 can includeintegrated circuitry having an electrostatic discharge path to allow excess charge to traverse from a bump 763 of the integrated circuit die 760 to an electrostatic discharge (ESD) device 752 within an ESD cell 751 of the integrated circuit die 750. A resistance of the electrostatic discharge path can be measured in four parts, for example, a first resistance 756 of a portion of the electrostatic discharge path between a cell port 753 of the ESD cell 751 and a device pin 754 of the ESD device 752, a second resistance 757 between202413368 the cell port 753 and a pad 755 of the integrated circuit die 750, a third resistance 758 between the pad 755 of the integrated circuit die 750 and a micro bump 762 of the integrated circuit die 760, a fourth resistance 764 between the micro bump 762 and the bump 763 through an interposer 761. The resistance of the electrostatic discharge path can correspond to a sum of the first resistance 756, the second resistance 757, the third resistance 758, and the fourth resistance 764.

[0039] Referring back to Figures 3 and 6, the electrostatic discharge system 320 can includea path resistance system 324 that, in a block 604 of Figure 6, can access a cell library including the electrostatic discharge cell to identify resistances corresponding to the first portion of the electrostatic discharge path located within the electrostatic discharge cell. In some embodiments, the resistance corresponding to the first portion of the electrostatic discharge path can be the effective resistance of the path determined by the cell characterization system 310.

[0040] The path resistance system 324, in a block 604 of Figure 6, can determine aresistance of the second portion of the electrostatic discharge path. In some embodiments, the path resistance system 324 can determine resistances of the second portion of the electrostatic discharge paths by providing the physical design layout 302 to the parasitic extraction system 340. The parasitic extraction system 340 can perform parasitic extraction on the physical design layout 302 to generate parasitic netlists 341 corresponding to the electrical connectivity in the physical design layout 302. For example, the parasitic extraction system 340 can convert the physical design layout 302 into an electrical representation, such as a group of electrically-independent parasitic models, and generate the parasitic netlist 341 including the electrical representation of the physical202413368 design layout 302. In some embodiments, the parasitic netlist 341 can describe or model the electronic device in a Standard Parasitic Exchange Format (SPEF), or the like.

[0041] The path resistance system 324 can identify resistance networks 306 from theparasitic netlists 341 that correspond to the second portion of the electrostatic paths in the physical design layout 302. In some embodiments, the path resistance system 324 can parse the parasitic netlist 341 to identify resistive nets associated with the second portion of the electrostatic paths in the physical design layout 302 and construct the resistive networks 306 from the identified resistive nets associated with the paths in the physical design layout 302.

[0042] The path resistance system 324 can provide the resistance networks 306 to thesimulator 350, which can perform a simulation of signals on the resistance networks 306 to determine effective resistances 351 of the resistance networks 306. The effective resistances 351 of the resistance networks 306 determined from the simulation can correspond to resistances of the second portion of the electrostatic discharge paths in the physical design layout 302.

[0043] The path resistance system 324, in a block 605 of Figure 6, can determine a pathresistance 307 of the electrostatic discharge path from the resistances of the first portion of the electrostatic discharge path accessed from the cell library and the second portion of the electrostatic discharge path measured by the path resistance system 324. In some embodiments, the path resistance system 324 can aggregate the identified resistance of the first portion of the electrostatic discharge path and the measured resistance of the second portion of the electrostatic discharge path, which can correspond to the path resistance 307.202413368

[0044] The electrostatic discharge system 320 can output the path resistances 307 to adesign rule checking system 360. The design rule checking system 360, in a block 606 of Figure 6, can perform an electrostatic discharge design rule check using the path resistances 307 of the electrostatic discharge paths in the physical design layout 302. The design rule checking system 360 can utilize the path resistances 307 to determine whether the electrostatic discharge paths in the physical design layout 302 conform to design connectivity rules 303. The design rule checking system 360 can generate a violation report 308, which can annunciate when the electrostatic discharge paths in the physical design layout 302 have path resistances 307 fail to conform to the design connectivity rules 303. In some embodiments, the violation report 308 can identify when path resistances 307 exceed a threshold level of allowable resistance on an electrostatic discharge path, which can prompt modification to the physical design layout 302. For example, the physical design layout 302 can be altered so that at least a portion of the electrostatic discharge path has a route in parallel, which would drop the overall path resistance for the electrostatic discharge path.

[0045] The system and apparatus described above may use dedicated processor systems,micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.202413368

[0046] The processing device may execute instructions or "code" stored in memory. Thememory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0047] The processor memory may be integrated together with the processing device, forexample RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I / O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine- readable" and may be readable by a processing device.

[0048] Operating instructions or commands may be implemented or embodied in tangibleforms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage202413368 medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long as the stored information may be "read" by an appropriate processing device. The term "computer- readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini-computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

[0049] A program stored in a computer-readable storage medium may comprise a computerprogram product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries. Conclusion

[0050] While the application describes specific examples of carrying out embodiments of theinvention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims. For example, while specific terminology has been employed above to refer to design processes, it should be appreciated202413368 that various examples of the invention may be implemented using any desired combination of electronic design automation processes.

[0051] One of skill in the art will also recognize that the concepts taught herein can betailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0052] Although the specification may refer to “an”, “one”, “another”, or “some” example(s)in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

Claims

202413368 CLAIMS 1. A method comprising: identifying, by a computing system, a first portion of an electrostatic discharge path in a physical design layout describing an electronic device is within at least one electrostatic discharge cell of the electronic device; accessing, by the computing system, a library including the at least one electrostatic discharge cell to identify a first resistance corresponding to the first portion of the electrostatic discharge path; determining, by the computing system, a second resistance of a second portion of the electrostatic discharge path; generating, by the computing system, a path resistance for the electrostatic discharge path by aggregating the first resistance and the second resistance; and performing, by the computing system, an electrostatic discharge design rule check using the path resistance of the electrostatic discharge path and electrostatic discharge design rules.

2. The method of claim 1, further comprising: determining, by the computing system, the first resistance corresponding to the first portion of the electrostatic discharge path; and annotating, by the computing system, the at least one electrostatic discharge cells in the library with the first resistance.202413368 3. The method of claim 2, wherein determining the first resistance corresponding to the first portion of the electrostatic discharge path further comprising: identifying connectivity between a pin in an electrostatic discharge protection device in the electrostatic discharge cell and a port of the electrostatic discharge cell; performing parasitic extraction on the electrostatic discharge cell to determine a resistive network corresponding the connectivity between the pin in an electrostatic discharge protection device and the port of the electrostatic discharge cell; and determining the first resistance corresponding to the first portion of the electrostatic discharge path based on the resistive network corresponding the connectivity between the pin in an electrostatic discharge protection device and the port of the electrostatic discharge cell.

4. The method of claim 3, wherein determining the first resistance corresponding to the first portion of the electrostatic discharge path further comprises simulating the resistive network to determine an effective resistance of the resistive network, wherein the effective resistance of the resistive network is the first resistance corresponding to the first portion of the electrostatic discharge path.

5. The method of claim 1, wherein determining the second resistance of the second portion of the electrostatic discharge path further comprising: identifying connectivity between a port of the electrostatic discharge cell and another endpoint of the second portion of the electrostatic discharge path; performing parasitic extraction on the physical design layout to determine a resistive network corresponding the connectivity between the port of the electrostatic202413368 discharge cell and the other endpoint of the second portion of the electrostatic discharge path; and determining the second resistance corresponding to the second portion of the electrostatic discharge path based on the resistive network corresponding the connectivity between the port of the electrostatic discharge cell and the other endpoint of the second portion of the electrostatic discharge path.

6. The method of claim 5, wherein the other endpoint of the second portion of the electrostatic discharge path corresponds to at least one of a port of a different electrostatic discharge cell in the physical design layout, a pad of the electronic device described in the physical design layout, a pad of a different electronic device described in the physical design layout, or a port of an electrostatic discharge cell in the different electronic device.

7. The method of claim 1, when the performance of the electrostatic discharge design rule check identifies a violation of the electrostatic discharge design rules, the electrostatic discharge path in the physical design layout associated with the violation is modified to reduce the path resistance.

8. A system comprising: a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to:202413368 identify a first portion of an electrostatic discharge path in a physical design layout describing an electronic device is within at least one electrostatic discharge cell of the electronic device; access a library including the at least one electrostatic discharge cell to identify a first resistance corresponding to the first portion of the electrostatic discharge path; determine a second resistance of a second portion of the electrostatic discharge path; generate a path resistance for the electrostatic discharge path by aggregating the first resistance and the second resistance; and perform an electrostatic discharge design rule check using the path resistance of the electrostatic discharge path and electrostatic discharge design rules.

9. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: determine the first resistance corresponding to the first portion of the electrostatic discharge path; and annotate the at least one electrostatic discharge cells in the library with the first resistance.

10. The system of claim 9, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to determine the first resistance corresponding to the first portion of the electrostatic discharge path by:202413368 identifying connectivity between a pin in an electrostatic discharge protection device in the electrostatic discharge cell and a port of the electrostatic discharge cell; performing parasitic extraction on the electrostatic discharge cell to determine a resistive network corresponding the connectivity between the pin in an electrostatic discharge protection device and the port of the electrostatic discharge cell; and determining the first resistance corresponding to the first portion of the electrostatic discharge path based on the resistive network corresponding the connectivity between the pin in an electrostatic discharge protection device and the port of the electrostatic discharge cell.

11. The system of claim 10, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to determine the first resistance corresponding to the first portion of the electrostatic discharge path by simulating the resistive network to determine an effective resistance of the resistive network, wherein the effective resistance of the resistive network is the first resistance corresponding to the first portion of the electrostatic discharge path.

12. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to determine the second resistance of the second portion of the electrostatic discharge path by: identifying connectivity between a port of the electrostatic discharge cell and another endpoint of the second portion of the electrostatic discharge path; performing parasitic extraction on the physical design layout to determine a resistive network corresponding the connectivity between the port of the electrostatic202413368 discharge cell and the other endpoint of the second portion of the electrostatic discharge path; and determining the second resistance corresponding to the second portion of the electrostatic discharge path based on the resistive network corresponding the connectivity between the port of the electrostatic discharge cell and the other endpoint of the second portion of the electrostatic discharge path.

13. The system of claim 12, wherein the other endpoint of the second portion of the electrostatic discharge path corresponds to at least one of a port of a different electrostatic discharge cell in the physical design layout, a pad of the electronic device described in the physical design layout, a pad of a different electronic device described in the physical design layout, or a port of an electrostatic discharge cell in the different electronic device.

14. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising: identifying a first portion of an electrostatic discharge path in a physical design layout describing an electronic device is within at least one electrostatic discharge cell of the electronic device; accessing a library including the at least one electrostatic discharge cell to identify a first resistance corresponding to the first portion of the electrostatic discharge path; determining a second resistance of a second portion of the electrostatic discharge path;202413368 generating a path resistance for the electrostatic discharge path by aggregating the first resistance and the second resistance; and performing an electrostatic discharge design rule check using the path resistance of the electrostatic discharge path and electrostatic discharge design rules.

15. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising: determining the first resistance corresponding to the first portion of the electrostatic discharge path; and annotating the at least one electrostatic discharge cells in the library with the first resistance.

16. The apparatus of claim 15, wherein determining the first resistance corresponding to the first portion of the electrostatic discharge path further comprises: identifying connectivity between a pin in an electrostatic discharge protection device in the electrostatic discharge cell and a port of the electrostatic discharge cell; performing parasitic extraction on the electrostatic discharge cell to determine a resistive network corresponding the connectivity between the pin in an electrostatic discharge protection device and the port of the electrostatic discharge cell; and determining the first resistance corresponding to the first portion of the electrostatic discharge path based on the resistive network corresponding the connectivity between the pin in an electrostatic discharge protection device and the port of the electrostatic discharge cell.202413368 17. The apparatus of claim 16, wherein determining the first resistance corresponding to the first portion of the electrostatic discharge path further comprises simulating the resistive network to determine an effective resistance of the resistive network, wherein the effective resistance of the resistive network is the first resistance corresponding to the first portion of the electrostatic discharge path.

18. The apparatus of claim 14, wherein determining the second resistance of the second portion of the electrostatic discharge path further comprises: identifying connectivity between a port of the electrostatic discharge cell and another endpoint of the second portion of the electrostatic discharge path; performing parasitic extraction on the physical design layout to determine a resistive network corresponding the connectivity between the port of the electrostatic discharge cell and the other endpoint of the second portion of the electrostatic discharge path; and determining the second resistance corresponding to the second portion of the electrostatic discharge path based on the resistive network corresponding the connectivity between the port of the electrostatic discharge cell and the other endpoint of the second portion of the electrostatic discharge path.

19. The apparatus of claim 18, wherein the other endpoint of the second portion of the electrostatic discharge path corresponds to at least one of a port of a different electrostatic discharge cell in the physical design layout, a pad of the electronic device described in the physical design layout, a pad of a different electronic device described in202413368 the physical design layout, or a port of an electrostatic discharge cell in the different electronic device.

20. The apparatus of claim 14, when the performance of the electrostatic discharge design rule check identifies a violation of the electrostatic discharge design rules, the electrostatic discharge path in the physical design layout associated with the violation is modified to reduce the path resistance.

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