Methods for finish polishing semiconductor substrates with ethylenediamine

Abstract

Methods for reducing defects during finish polishing sequences. The front surface of the structure is contacted with a polishing pad in the presence of a polishing slurry. The polishing slurry includes colloidal silica, a hydroxide. and ethylenediamine. The concentration of ethylenediamine in the polishing slurry may be less than 0.4 wt%.

Description

METHODS FOR FINISH POLISHING SEMICONDUCTOR SUBSTRATES WITH ETHYLENEDIAMINECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 676,498, filed July 29, 2024, which is incorporated herein by reference it its entirety.TECHNICAL FIELD

[0002] The field of the disclosure relates to methods for polishing semiconductor substrates and, in particular, methods for reducing defects during finish polishing operations.BACKGROUND

[0003] Semiconductor wafers are used in the production of semiconductor devices such as integrated circuit (IC) chips, silicon-on-insulator (SOI) wafers, and radio frequency-SOI (RF-SOI) wafers. Typically, the rough surface of the semiconductor wafer needs to be further processed to have characteristics that meet the strict parameters for production of semiconductor devices, such as IC chips, SOI wafers, and RF-SOI wafers.

[0004] Typically, surfaces of semiconductor wafers are polished to improve surface characteristics including polycrystalline layer roughness and microdefects. One way to polish a semiconductor wafer is referred to as chemicalmechanical polishing (CMP). CMP processes often use a circular polishing pad. The pad is rotated and the wafer is brought into contact with and forced against the pad as a slurry is applied to the pad.

[0005] Final or “finish” polished wafers may have a high defect count, e.g., under Surfscan SP7 15nm inspection. These defects are identified as shallow polish-induced defect (PID) by SEM. These PIDs are mostly from the firstprocess step in the final polish process and are difficult to eliminate in subsequent process steps.

[0006] A need exits for methods for final polishing semiconductor structures which reduce defect counts such as defects detected under 15 nm inspection.

[0007] This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.SUMMARY

[0008] One aspect of the present disclosure is directed to a method for polishing a semiconductor substrate having a front surface and a back surface generally parallel to the front surface. The front surface of the substrate is contacted with a polishing pad in the presence of a polishing slurry in a polishing step. The polishing slurry includes colloidal silica, a hydroxide, and ethylenediamine. The concentration of ethylenediamine in the polishing slurry is less than 0.4 wt%.

[0009] Various refinements exist of the features noted in relation to the above-mentioned aspects of the present disclosure. Further features may also be incorporated in the above-mentioned aspects of the present disclosure as well. These refinements and additional features may exist individually or in any combination. For instance, various features discussed below in relation to any of the illustrated embodiments of the present disclosure may be incorporated into any of the abovedescribed aspects of the present disclosure, alone or in any combination.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a block diagram of an embodiment for final polishing a semiconductor structure;

[0011] FIG. 2 is a schematic of an embodiment of a wafer polishing system;

[0012] FIG. 3 is a flow diagram showing an embodiment of a method of processing a semiconductor wafer;

[0013] FIG. 4 is a block diagram of an embodiment of a method for polishing a semiconductor structure on a plurality of substrate polishing apparatus.

[0014] Corresponding reference characters indicate corresponding parts throughout the drawings.DETAILED DESCRIPTION

[0015] Provisions of the present disclosure relate to methods for polishing semiconductor substrates. Examples of substrates that may be polished according to the methods described herein include silicon substrates such as single crystal silicon semiconductor substrates. In some embodiments, the substrate is a layered substate such as a substrate having a layer of single crystal silicon therein. Single crystal silicon semiconductor substrates may be used to prepare electronic devices such as integrated circuit (IC) chips, silicon-on-insulator (SOI) wafers, and radio frequency-SOI (RF-SOI) wafers.

[0016] Referring now to FIG. 1 of the application, an embodiment of a polishing method 100 of the present disclosure is shown. The method 100 involves polishing the front surface of the substrate to achieve a desired surface roughness. The polishing step may be a single-side polish (i.e., the back surface is not polished) or “finish polish.” The single-side polish may reduce the surface roughness of the wafer to less than about 2.0 A as measured by atomic force microscopy (AFM) at scan sizes of about 10 pm x about 10 pm to about 100 pm x about 100 pm. The single-sidepolish may even reduce the surface roughness to less than about 1.5 A or less than about 1.2 A at scan sizes of about 10 pm x about 10 pm to about 100 pm x about 100 pm. The single-side polish may result in removal of at least about 1 pm of material from the front surface of the substrate.

[0017] The single-side polish may be achieved by, for example, chemical-mechanical planarization (CMP). CMP typically involves the immersion of the wafer in an abrasive slurry and polishing of the wafer by a polymeric pad. Through a combination of chemical and mechanical means the surface of the wafer is smoothed. Typically the polish is performed until a chemical and thermal steady state is achieved and until the wafers have achieved their targeted shape and flatness.

[0018] Suitable polishers for the single-side polish may be obtained from Lapmaster SFT (e.g., LGP-708, Chiyoda-Ku, Japan). In accordance with embodiments of the present disclosure, the pad used for single-side polishing is a suede-type pad (also referred to as a polyurethane foam pad) such as a SURFIN pad from Fujimi (Kiyoso, Japan), a CIEGAL pad from Chiyoda KK (Osaka, Japan) or a SPM pad from Rohm and Haas. Polyurethane impregnated polyethylene pads such as SUBA pads available from Rohm and Haas may also be used.

[0019] The single-side polish 100 (i.e., the combination of all steps) may occur for at least 30 seconds, 60 seconds or even at least 120 seconds, at least 180 seconds, or at least 240 seconds or more. The slurry flow rate may range from about 100 ml / min to about 1,000 ml / min and the pad pressure may range from about 75 g / cm2to about 125 g / cm2; however, it should be understood that other polish times, pad pressures and slurry flow rates may be used without departing from the scope of the present disclosure.

[0020] Referring to FIG. 1, the polishing method involves a first polishing step 110 in which the front surface of the substrate is contacted with a polishing pad in the presence of a first polishing slurry. In a second step 120, the front surface of the substrate is contacted with a polishing pad in the presence of a second polishing slurry (i.e., the second step is subsequent to the first step in that the secondpolishing step commences after the flow of the first polishing slurry has been stopped or is commensurate therewith). In a third step 130, the front surface of the substrate is contacted with a polishing pad in the presence of a third polishing slurry. In a fourth step 140, the front surface of the substrate is contacted with a polishing pad in the presence of a fourth polishing slurry.

[0021] Each polishing slurry is generally a poly disperse colloid in which the solid-phase silica particles are dispersed in a liquid phase. Suitable liquid phases include aqueous solutions. The slurry may include additional components typical of polishing slurries used to polish single crystal silicon wafers. The slurry may be diluted with water (i.e., DI water).

[0022] In the first polishing step 110, the polishing slurry includes colloidal silica, a hydroxide such as KOH, and ethylenediamine (EDA). The concentration of ethylenediamine in the polishing slurry is less than 0.4 wt%. In other embodiments, the concentration of ethylenediamine is less than 0.3 wt%, less than 0.25 wt%, from 0.05 wt% to 0.4 wt%, from 0.1 wt% to 0.4 wt%, from 0.1 wt% to 0.25 wt%, or from 0.15 wt% to 0.25 wt%. In some embodiments, the first polishing slurry consists essentially of colloidal silica, a hydroxide, ethylenediamine, and water (e.g., does not contain a polymer).

[0023] In some embodiments, ethylenediamine and caustic are premixed and added together to the polishing pad (i.e., lowering the concentration of EDA causes the concentration of KOH to be reduced). In other embodiments, ethylenediamine and caustic are separately added to the polishing slurry.

[0024] The silica particles of each of the first and second polishing slurries have an average particle size. The average diameters of the particles of both slurries may be less than about 100 nm, less than about 50 nm, from about 10 nm to about 50 nm, from about 20 nm to about 40 nm or from about 30 nm to about 40 nm.

[0025] In some embodiments, the silica particles of the first slurry are individually polymer encapsulated. The polymer-encapsulated silica particles may comprise at least about 50 wt% silica. The polymers used for encapsulation for thesilica particles may be any of the polymers conventionally used in the field of substrate polishing and, in particular, silicon wafer polishing. The polymer may be a water-soluble polymer such as cellulose, substituted-cellulose, modified starches or xanthan gum.

[0026] In the second polishing step 120, the front surface of the substrate is contacted with a polishing pad in the presence of a second polishing slurry. The second polishing step 120 commences after the first polishing step 110. The second polishing slurry includes colloidal silica (e.g., polymer encapsulated) but does not comprise ethylenediamine. In some embodiments, the second slurry does not include caustic.

[0027] In some embodiments, the first and second polishing steps110, 120 use the same polishing pad (i.e., are performed on the same platen). In other embodiments, different pads may be used in the first and second polishing steps 110, 120.

[0028] The third polishing step 130 commences after the second polishing step 120. The third polishing slurry of the third polishing step includes colloidal silica but does not contain ethylenediamine. In some embodiments, the third polishing slurry is free of caustic.

[0029] The fourth polishing step 140 commences after the third polishing step 130. The fourth polishing slurry of the fourth polishing step 140 includes colloidal silica but does not contain ethylenediamine. In some embodiments, the fourth polishing slurry is free of caustic.

[0030] The third and fourth polishing steps 130, 140 may be performed with a different polishing pad than the first and second polishing steps 110, 120 (e.g., a different polishing platen). The polishing pads of the third 130 and fourth steps 140 may also be different (i.e., different platen).

[0031] After the single-side polish is complete, the wafers may be rinsed and dried. In addition, the wafers may be subjected to a wet bench or spincleaning. Wet bench cleaning may include contacting the wafer with a SC-1 cleaning solution (i.e., ammonium hydroxide and hydrogen peroxide), optionally, at elevated temperatures (e.g., about 50°C to about 80°C). Spin cleaning includes contact with a HF solution and ozonated water and may be performed at room temperature.

[0032] The polishing steps described above may generally include an amount of overlap (e.g., the second polishing slurry begins to be applied while the first slurry is being turned off). However, generally each step involves a period of time in which only the respective slurry is introduced to the polishing pad (e.g., first slurry but not second slurry in the first polishing step).

[0033] In some embodiments, in addition to the polishing method 100 of embodiments of the present disclosure referenced above, the semiconductor structure may be processed in additional steps and / or on additional polishing apparatus. For example, the substrate may be polished in a polishing system 200 (FIG. 2) having a first polishing apparatus 202A, a second polishing apparatus 202B, and third polishing apparatus 202C. While each apparatus 202A, 202B, 202C is shown in an integrated system 200, any one of the apparatus 202A, 202B, 202C may be a standalone unit. While three apparatus 202A, 202B, 202C are shown and described, the polishing system 200 may include more or less apparatus.

[0034] As shown in FIG. 3, each substrate polishing apparatus 202A, 202B, 202C includes a polishing pad 204 mounted on a pivotable table or platen 206 and a substrate mounting device 208 having a rotatable head 210 for mounting a semiconductor substrate 100 on the polishing pad 204. Rings 211 facilitate positioning the substrate 100 in relation to the polishing pad 204. In suitable embodiments, the substrate polishing apparatus 202 may include any number of polishing pads 204, substrate mounting devices 208, and rings 211. In the illustrated embodiment, each substrate polishing apparatus 202 includes two substrate mounting devices 208. The substrate mounting device 208 holds the substrate 100 and brings the substrate 100 into contact with the polishing pad 204 as both the substrate 100 and the polishing pad 204 are rotated. The polishing pad 204 polishes a front surface 212of the wafer 100 through abrasion and with a polishing slurry 214 which is applied to a surface 216 of the polishing pad 204.

[0035] In the illustrated embodiment, each substrate polishing apparatus 202 includes a nozzle 218 for dispensing the polishing slurry 214. Each apparatus 202 may include multiple nozzles for dispensing multiple slurries or liquids to the polishing pad 204. Additionally or in addition, different slurries 214 may be dispensed from any single nozzle 218 during the polishing process.

[0036] During polishing, polishing slurry 214 is present while contacting the front surface of the substrate with the polishing pad 204 to help polish the front surface 212 of the substrate 100. When the polishing pad 204 is pressed against the substrate 100, the polishing pad 204 works slurry 214 against the front surface 212 of the substrate 100 to concurrently and uniformly remove material from the front surface 212 of the substrate 100 and help improve the overall smoothness of the substrate 100. As the front surface 212 of the substrate 100 is polished, silicon is removed and some minor damage is created on the surface 212 by the abrasive action of the slurry 214.

[0037] FIG. 4 is a flow chart of an example method 20 for polishing semiconductor substrates by use of the system 200 shown in FIG. 2 or a similar system. The method 20 generally includes positioning a substate 100 (FIG. 3) on a first wafer polishing apparatus 202A (FIG. 2) for an initial “rough” polish 50. The substrate 100 may be polished on the first wafer polishing apparatus 202A for any amount of time suitable for a portion of substrate 100 to be abraded and / or a desired smoothness to be achieved. In some embodiments, the substrate 100 is polished on the first wafer polishing apparatus 202A such that thickness is decreased by an amount in the range between about 1 pm and 10 pm, or from 6 pm and 7 pm. As a result, the warp and / or bow of substrate 100 is reduced.

[0038] In the example embodiment, the substrate 100 is transferred from the first polishing apparatus 202A to the second polishing apparatus 202B for additional polishing such as the single side polishing method 100 described above(e.g., method 100 of FIG. 1). As described above, in some embodiments of the polishing method 100, the substrate 100 is polished on the second wafer polishing apparatus 202B such that thickness is reduced by an amount in the range between about 1 pm and 10 pm, or from 3 pm to about 4 pm. The substrate 100 may be polished on the second polishing apparatus 202B for any amount of time suitable for a portion of the substate 100 to be abraded and / or a desired smoothness achieved.

[0039] In the polishing method 20, after polishing is complete on the second apparatus 202B, the substrate 100 is transferred to the third polishing apparatus 202C. On the third polishing apparatus 202C, a polishing slurry is applied to the polishing pad 204 during a final “touch” or “flash” polish of the substrate 100 to improve submicrometer roughness and substantially eliminate minor defects remaining on the surface 212 of the substrate 100. The final polish also maintains the substrate flatness while imparting a smooth, specular finish to the surface 212 of the substate 100 that is typical for polished wafers and desired by many device manufactures. This type of final polish generally removes less than about 1 pm of material or between about 0.25 pm and about 0.5 pm of material from surface 212 of the substrate 100.

[0040] Compared to conventional methods for finish polishing, the polishing methods of the present disclosure have several advantages. By reducing ethylenediamine concentration, polish-induced defects can be improved. By reducing ethylenediamine concentration, less 15nm polish-induced defects are produced. Removal rate and edge roll-off can be compensated by process time or other process parameter to keep same removal profile as the process of record.EXAMPLES

[0041] The processes of the present disclosure are further illustrated by the following Examples, and these Examples should not be viewed in a limiting sense.Example 1: Finish Polish Test

[0042] A test (table 1) was performed on a 3 platen single side polish machine (Micro engineering LGP708). Platenl stepl used polishing slurry mixed with KOH-EDA to remove native oxide and to control removal profile, flatness and edge roll-off. Platenl step2, platen2 and platen3 processes used formulation slurry diluted with DI water to achieve low defect and low haze surface condition.Table 1 : Polishing Steps in Finish Polish

[0043] Different test conditions were applied on platenl stepl.Condition 1 is the process of record (POR). In Conditions 2, 3 and 4, EDA concentration was reduced to 50% of POR, removal rate reduced with EDA, and defect counts slightly decreased. Defect performance of pure colloidal slurry DVSTS029 is better than water-soluble polymer adding slurry Glanzox2104 when mixing with KOH- EDA. In Conditions 5 and 6, EDA concentration was reduced to 25% of POR. Defect counts were reduced with EDA, especially on condition 5 where defect counts were reduced from 100 to 58. In Conditions 7 and 8, process time was increased to compensate lower removal rate. Defect performance was comparable with Condition 5 and 6. In Condition 9, without KOH-EDA adding in process stepl, insufficient removal on native oxide caused abnormal haze pattern and extremely high defect counts.Table 2: Process Conditions of First Polishing Step

[0044] As used herein, the terms “about,” “substantially,” “essentially” and “approximately” when used in conjunction with ranges of dimensions, concentrations, temperatures or other physical or chemical properties or characteristics is meant to cover variations that may exist in the upper and / or lower limits of the ranges of the properties or characteristics, including, for example, variations resulting from rounding, measurement methodology or other statistical variation.

[0045] When introducing elements of the present disclosure or the embodiment(s) thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," “containing,” and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. The use of terms indicating a particular orientation (e.g., "top," "bottom," "side," etc.) is for convenience of description and does not require any particular orientation of the item described.

[0046] As various changes could be made in the above constructions and methods without departing from the scope of the disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawing[s] shall be interpreted as illustrative and not in a limiting sense.

Claims

WHAT IS CLAIMED IS:

1. A method for polishing a semiconductor substrate having a front surface and a back surface generally parallel to the front surface, the method comprising: contacting the front surface of the substrate with a polishing pad in the presence of a polishing slurry in a polishing step, the polishing slurry comprising: colloidal silica; a hydroxide; and ethylenediamine, wherein the concentration of ethylenediamine in the polishing slurry is less than 0.4 wt%.

2. The method as set forth in claim 1 wherein the concentration of ethylenediamine is less than 0.3 wt%, less than 0.25 wt%, from 0.05 wt% to 0.4 wt%, from 0.1 wt% to 0.4 wt%, from 0.1 wt% to 0.25 wt%, or from 0.15 wt% to 0.25 wt%.

3. The method as set forth in claim 1 or claim 2 wherein the hydroxide is potassium hydroxide.

4. The method as set forth in any one of claims 1 to 3 wherein the polishing step is a first polishing step, the method comprising contacting the front surface of the substrate with a polishing pad in the presence of a second polishing slurry in a second polishing step, the second polishing step commencing after the first polishing step, the second polishing slurry comprising colloidal silica, the second polishing slurry not comprising ethylenediamine.

5. The method as set forth in claim 4 wherein the second polishing slurry is free of caustic.

6. The method as set forth in claim 4 or claim 5 wherein the first and second polishing step use the same polishing pad.

7. The method as set forth in any one of claims 4 to 6 comprising contacting the front surface of the substrate with a polishing pad in the presence of a third polishing slurry in a third polishing step, the third polishing step commencing after the second polishing step, the third polishing slurry comprising colloidal silica, the third polishing slurry not comprising ethylenediamine.

8. The method as set forth in claim 7 wherein the third polishing slurry is free of caustic.

9. The method as set forth in claim 7 or claim 8 comprising contacting the front surface of the substrate with a polishing pad in the presence of a fourth polishing slurry in a fourth polishing step, the fourth polishing step commencing after the third polishing step, the fourth polishing slurry comprising colloidal silica, the fourth polishing slurry not comprising ethylenediamine.

10. The method as set forth in claim 9 wherein the fourth polishing slurry is free of caustic.

11. The method as set forth in any one of claims 7 to 10 wherein the third polishing step is performed with a different polishing pad than the first and second polishing steps.

12. The method as set forth in claim 11 wherein the fourth polishing step is performed with a different polishing pad than the first, second and third polishing steps.

13. The method as set forth in any one of claims 1 to 12 wherein the first polishing slurry consists essentially of colloidal silica, a hydroxide, ethylenediamine, and water.

14. The method as set forth in any one of claims 1 to 13 wherein the back surface is not polished while polishing the front surface and wherein at least about 1 pm of material is removed from the front surface of the substrate.

Images