Systems and methods for wafer lift pin mark detection and quantitative analysis

Abstract

A computer device includes at least one processor in communication with at least one memory device. The at least one processor is programmed to: a) receive scan data of an object to be analyzed; b) smooth the scan data to create a smoothed image; c) detect contours for dark pixels in the smoothed image; d) generate a rendered image based on the detected contours for dark pixels; e) detect rendered contours in the rendered image; f) identify marks based on the rendered contours; and g) determine and report attributes of marks based on the identified marks.

Description

SYSTEMS AND METHODS FOR WAFER LIFT PIN MARK DETECTION AND QUANTITATIVE ANALYSISCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Provisional Application No. 63 / 676,962, filed July 30, 2024, which application is hereby incorporated by reference in its entirety.FIELD

[0002] The field of the disclosure generally relates to semiconductor wafer analysis, and more particularly, to systems and methods for quantitative detection and analysis of wafer pin mark defects.BACKGROUND

[0003] Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is processed to remove the seed cone and the end cone and then trimmed, optionally cropped, and ground to have one or more flats or notches for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers.

[0004] Semiconductor wafers are commonly used in the production of electronic devices (e.g., transistors and integrated circuit chips) on which circuitry are printed. The circuitry is first printed in miniaturized form onto surfaces of the wafer. The wafer is then broken into circuit chips. To ensure that this miniaturized circuitry can be properly printed over the entire surface of the wafer, the front and back surfaces of the wafer must generally be free from defects, extremely flat, and parallel with each other. The continuously shrinking size of modem electronic devices impose strict and challenging requirements related to the quality of the wafer and acceptable wafer surface and flatness parameters. For example, wafer surface defects, even on a back surface of the wafer, are very critical for < 5 nanometer (nm) processes.

[0005] A need exists for systems and methods for accurately detecting and analyzing defects on a surface of a wafer that can be used for process monitoring and / or process control to reduce or eliminate the defects, which provide adequate image resolution in a cost-effective and efficient manner and enable increasing throughput during wafer production.

[0006] This Background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.BRIEF DESCRIPTION

[0007] In one aspect, a system includes a computing device that may include at least one processor in communication with at least one memory device. The at least one processor may be configured to: a) receive scan data of an object to be analyzed; b) smooth the scan data to create a smoothed image; c) detect contours for dark pixels in the smoothed image; d) generate a rendered image based on the detected contours for dark pixels; e) detect rendered contours in the rendered image; f) identify marks based on the rendered contours; and / or g) determine and report attributes of marks based on the identified marks. The system may have additional, less, or alternate functionalities, including those discussed elsewhere herein.

[0008] In another aspect, a computer-implemented method may be performed by a computer device including at least one processor in communication with at least one memory device. The method may include a) receiving scan data of an object to be analyzed; b) smoothing the scan data to create a smoothed image; c) detecting contours for dark pixels in the smoothed image; d) generating a rendered image based on the contours for dark pixels; e) detecting rendered contours in the rendered image; f) identifying marks based on the rendered contours; and / or g) determining and reporting attributes of marks based on the identified marks. Themethod may have additional, less, or alternate functionalities, including those discussed elsewhere herein.

[0009] In a further aspect, a computer device includes at least one processor in communication with at least one memory device. The at least one processor may be configured to: a) receive scan data of an object to be analyzed; b) smooth the scan data to create a smoothed image; c) detect contours for dark pixels in the smoothed image; d) generate a rendered image based on the detected contours for dark pixels; e) detect rendered contours in the rendered image; f) identify marks based on the rendered contours; and / or g) determine and report attributes of marks based on the identified marks. The computer device may have additional, less, or alternate functionalities, including those discussed elsewhere herein.

[0010] In another aspect, at least one non-transitory computer- readable media having computer-executable instructions embodied thereon, when executed by a computing device including at least one processor in communication with at least one memory device, the computer-executable instructions may cause the at least one processor to: a) receive scan data of an object to be analyzed; b) smooth the scan data to create a smoothed image; c) detect contours for dark pixels in the smoothed image; d) generate a rendered image based on the detected contours for dark pixels; e) detect rendered contours in the rendered image; f) identify marks based on the rendered contours; and / or g) determine and report attributes of marks based on the identified marks. The non-transitory computer-readable media may have additional, less, or alternate functionalities, including those discussed elsewhere herein.

[0011] In one aspect, a system includes a computing device that may include at least one processor in communication with at least one memory device. The at least one processor may be configured to: a) receive an image of an object to be analyzed; b) apply a mask to the image based on a shape of the object to be analyzed to generate a masked image; c) detect contours in the masked image; d) sort the detected contours to generate a plurality of sorted contours; e) select a first mark position based upon the plurality of sorted contours; f) detect a plurality of other marks based on the first mark position; and / or g) report locations of the first mark and the plurality of othermarks. The system may have additional, less, or alternate functionalities, including those discussed elsewhere herein.

[0012] In another aspect, a computer-implemented method may be performed by a computer device including at least one processor in communication with at least one memory device. The method may include a) receiving an image of an object to be analyzed; b) applying a mask to the image based on a shape of the object to be analyzed to generate a masked image; c) detecting contours in the masked image; d) sorting the detected contours to generate a plurality of sorted contours; e) selecting a first mark position based upon the plurality of sorted contours; f) detecting a plurality of other marks based on the first mark position; and / or g) reporting locations of the first mark and the plurality of other marks. The method may have additional, less, or alternate functionalities, including those discussed elsewhere herein.

[0013] In a further aspect, a computer device includes at least one processor in communication with at least one memory device. The at least one processor may be configured to: a) receive an image of an object to be analyzed; b) apply a mask to the image based on a shape of the object to be analyzed to generate a masked image; c) detect contours in the masked image; d) sort the detected contours to generate a plurality of sorted contours; e) select a first mark position based upon the plurality of sorted contours; f) detect a plurality of other marks based on the first mark position; and / or g) report locations of the first mark and the plurality of other marks. The computer device may have additional, less, or alternate functionalities, including those discussed elsewhere herein.

[0014] In another aspect, at least one non-transitory computer- readable media having computer-executable instructions embodied thereon, when executed by a computing device including at least one processor in communication with at least one memory device, the computer-executable instructions may cause the at least one processor to: a) receive an image of an object to be analyzed; b) apply a mask to the image based on a shape of the object to be analyzed to generate a masked image; c) detect contours in the masked image; d) sort the detected contours to generate a plurality of sorted contours; e) select a first mark position based upon the plurality of sortedcontours; f) detect a plurality of other marks based on the first mark position; and / or g) report locations of the first mark and the plurality of other marks. The non-transitory computer-readable media may have additional, less, or alternate functionalities, including those discussed elsewhere herein.

[0015] Advantages will become more apparent to those skilled in the art from the following description of the preferred embodiments which have been shown and described by way of illustration. As will be realized, the present embodiments may be capable of other and different embodiments, and their details are capable of modification in various respects. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The Figures described below depict various aspects of the systems and methods disclosed. Each Figure depicts an embodiment of a particular aspect of the disclosed systems and methods, and that each of the Figures is intended to accord with a possible embodiment. Further, wherever possible, the following description refers to the reference numerals included in the following Figures, in which features depicted in multiple Figures are designated with consistent reference numerals.

[0017] Figure 1 illustrates a cross-section view of one embodiment showing a wafer process chamber with a wafer and lift pins.

[0018] Figure 2 illustrates scanning electron microscope (SEM) and atomic force microscopy (AFM) images of pin mark defects on a surface of a wafer shown in Figure 1.

[0019] Figure 3 depicts a Near Infrared (NIR) detection system operable to capture macro defects on bare silicon wafers shown in Figure 1.

[0020] Figures 4A and 4B illustrate NIR images of potential anomalies, defects, and / or marks shown in Figure 3.

[0021] Figures 5A-5C illustrate an example of an NIR inspection result of an epitaxy silicon wafer shown in Figure 1, showing three (3) lift pin marks shown in Figure 3 on the wafer 102.

[0022] Figure 6 illustrates a process for quantitative detection and analysis of wafer pin marks using the system shown in Figure 3.

[0023] Figure 7 illustrates an applied mask on a NIR defect map.

[0024] Figure 8 illustrates a process for quantitative detection and analysis of wafer pin mark defects using the system shown in Figure 3.

[0025] Figure 9A illustrates a raw NIR image, such as captured by capture device shown in Figure 3.

[0026] Figures 10A and 10B illustrate an example of detecting three pin mark positions in accordance with the techniques shown in processes shown in Figures 6 and 8, respectively.

[0027] FIGS. 11-14 compare different pin mark defect position detections between NIR images, according to the present disclosure, and dark field images.

[0028] FIG. 15 plots correlation between pin marks for NIR transmission images vs. dark field images.

[0029] Figure 16 depicts an example configuration of a user computer device.

[0030] Like reference symbols in the various drawings indicate like elements.DETAILED DESCRIPTION

[0031] The field of the disclosure generally relates to semiconductor wafer analysis, and more particularly, to systems and methods for quantitative detection and analysis of wafer pin mark defects.

[0032] Embodiments described relate to systems and methods for quantitative detection, identification, and analysis of wafer lift pin mark defects, also referred to as lift pin marks, using near infrared (NIR) transmission images. In some embodiments, the systems and methods are used to detect, identify, and analyze wafer lift pin marks on the back surface of the wafer, which is supported by lift pins in a heated process chamber (e.g., an epitaxy, chemical vapor deposition, or rapid thermal anneal apparatus). In some embodiments, the wafer is an epitaxial wafer. The systems and methods of the present disclosure can be implemented for process monitoring and / or process control to minimize wafer lift mark defects on the surface (e.g., back surface) of the wafer.

[0033] In this disclosure, NIR transmission images are used to detect, identify, and wafer lift pin marks. A NIR transmission image inspection tools can also be used to detect pinhole or air pocket defects inside a bare semiconductor (i.e., silicon) wafer. Advantageously, the NIR transmission image is able to be generated without rotating the wafer, and is suitable for hardware-assisted virtualization (HVM). In embodiments, an NIR transmission image inspection system exports a wafer defect map and defect images that account for the entire surface or surfaces of the wafer, and these maps and images are reprocessed to report lift pin position and size.

[0034] Those having ordinary skill in the art would understand that although the present systems and methods are described in view of semiconductor wafers, the present systems and methods may also be applied to other surfaces in need of analysis, such as, but not limited to, mechanically machined surfaces. Furthermore, while reference will be made herein to semiconductor wafers constructed from silicon, other materials may be used to prepare semiconductor wafers, such as germanium, silicon carbide, silicon germanium, gallium arsenide, and other alloys of Group III andGroup V elements, such as gallium nitride or indium phosphide, or alloys of Group II and Group VI elements, such as cadmium sulfide or zinc oxide.

[0035] Figure 1 illustrates a cross-section view of one embodiment showing an epitaxy reactor or wafer process chamber 100 with a wafer 102 and lift pins 106. In the example embodiment, wafer process chamber 100 may be used with a chemical vapor deposition reactor for performing an epitaxy process on semiconductor wafers.

[0036] Furthermore, Figure 1 illustrates a condition where a pin lift 112, a susceptor support 108, a susceptor 104, and the wafer 102 have translated down 111 to place a wafer 102 level with a transfer slit 101 (slit) for wafer 102 transfer. The wafer process chamber 100 can contain lift pins 106 that pass through holes 120 in the susceptor 104 and through holes 124 in a susceptor support structure 108 to contact a moveable pin lift 112 for translating the wafer 102 off and onto the susceptor 104. The diameters of the lift pins 106 are smaller than the through hole 124 diameters in the susceptor support structure 108 and the susceptor through holes 120 such that the lift pins 106 are free to translate up 110 and down 111. The susceptor 104, attached to the susceptor support 108, can provide a fixed platform for holding the wafer 102 during processing.

[0037] The pin lift 112 and the susceptor 104 / susceptor support 108 can both translate in both up 110 and down 1 11 directions. To add and / or remove a wafer 102 from the process chamber 100, the wafer 102, the lift pins 106, the pin lift 112, the susceptor 104, and the susceptor support 108 structures can be lowered to a point where the pin lift 112 stops and the susceptor 104 / susceptor support 108 continues to translate down 111. This method of translation up 110 and down 111 can both drop the wafer 102 to be level with the slit 101 and lift the wafer 102 off of the susceptor 104.

[0038] A direct link now exists between the pin lift 112 and the wafer 102 and any further upward 110 movement by the pin lift 112 will translate the wafer 102 upward 110. For this embodiment, once the direct link is made, a distancetranslated by the pin lift 112 is equal to the distance translated by the wafer 102, however, this may not be true for other embodiments. The lift pins 106 can be raised 110 until the wafer 102 is approximately level with a slit 101 that is mid- level in the process chamber 100. From this raised wafer position, the wafer 102 can be transferred to and from the process chamber 100 by a robot (not shown). The contact points 107 on the pin lift 112 can be local flat areas as shown or can be a continuous feature such as, for example, a ring (not shown).

[0039] The use of epitaxial wafers is one primary solution to provide a defect- free wafer surface for end device manufacturers. Epitaxial wafers are produced using an epitaxy process, such as epitaxial chemical vapor deposition (CVD), in which a thin layer of material is grown on a surface of the semiconductor wafer so that the lattice structure is identical to that of the wafer. Epitaxial CVD is widely used in semiconductor wafer production to build up epitaxial layers such that devices can be fabricated (e.g. , circuitry can be printed) directly on the epitaxial layer. During epitaxial CVD, a polished semiconductor wafer 102 may be heated to a relatively high temperature in a deposition chamber of an epitaxial reactor, and deposition gases (e.g. , a vaporous silicon source gas, such as silane or a chlorinated silane) may be passed through the chamber 100 to deposit and grow an epitaxial layer of material on the front surface of the polished wafer 102. The susceptor 104, which supports the polished wafer 102 in the chamber 100 during the epitaxial deposition, is rotated during the process to allow the epitaxial layer to grow evenly.

[0040] During an epitaxy process, the wafer 102 is placed on the susceptor 104, and wafer lift pins 106 are contacted with the back surface of the wafer 102 directly during wafer loading and unloading from the reaction chamber. An example epitaxy reactor is a Centura CVD reactor available from Applied Materials. As shown in Figure 1, lift pin 106 is installed on pin lift 112, and during wafer loading and unloading from the reactor, the lift pin 106 moves up 110, a robot places wafer 102 on the lift pin 106, then the lift pin 106 moves down 110 slowly and positions the wafer 102 on the susceptor 104. After the epitaxial deposition process is complete, the lift pin 106 moves up 110 slowly and the robot removes the wafer 102 for cooling, and the wafer 102 is returned to a carrier (not shown).

[0041] Wafer lift pins 106 are typically made from high purity quartz, silicon carbide, or another material having suitable strength, thermal stability, and thermal conductivity to withstand the epitaxy process conditions. The lift pins 106 can damage the surface of the wafer 102 when they are brought into direct contact with the surface. The issue can be exacerbated where a double side polished wafer is used, since the polished wafer surface is particularly susceptible to damage. For example, the lift pins 106 may create micro scratches, pits, or silicon particles bonded on the surface of the wafer.

[0042] Various attempts have been made to detect and analyze lift pin mark defects in semiconductor wafers. One approach is the use of a Scanning Infrared Depolarization System (SIRD), but this technique does not have adequate resolution and requires a relatively long inspection duration (about 10 to 30 minutes). Another approach is the use of a Wafersight flatness inspection tool available from KLA-Tencor (Milpitas, CA), in which 2x2 nano-topography can visualize a front side pin mark. However, it is not capable of detecting back surface defects, and the 2x2 nano resolution is not adequate for certain applications. Yet another approach is the use of laser light scattering inspection (e.g., Surfscan SPx), which is the same as dark field light scattering image, and requires rotating the wafer 102 and may have non-pin mark defect (particles) interference.

[0043] Figure 2 illustrates scanning electron microscope (SEM) and atomic force microscopy (AFM) images of pin mark defects on a surface of a wafer, such as the wafer 102 shown in Figure 1. As shown in Figure 2, each pin position contains a cluster of many kinds of defects. For < 5 nm processes, downstream lithography processes can be very sensitive, and lift pin contact point defects can negatively impact (i.e., reduce) device yield.

[0044] Figure 3 depicts a Near Infrared (NIR) detection system 300 operable to capture macro defects on bare silicon wafers 102 (shown in Figure 1). Referring to the drawings, an exemplary detection system 300 is shown in Figure 3. In this embodiment, detection system 300 includes a light source 302, such as a near-IR or near- infrared light source, to direct light toward a material 304, such as wafer 102(shown in Figure 1). The light source 302 is configured to provide light, which defines a wavelength sufficient to penetrate the material 304. In various embodiments, the wavelength of the light from light source 302 (e.g., near-infrared (NIR) light) is selected based on the thickness of the material 304. In one example, the wavelength of the near- IR light emitted from the light source 302 is about 1 to about 2 microns. It is contemplated, however, that light having one or more different wavelengths can be emitted from light source 302.

[0045] On the opposite side of the material 304, the detection system 300 includes a capture device 306 configured to capture the light passing through the material 304. In this example, the image capture device 306 is a camera, such as a silicon-based CCD or CMOS array camera. In another example, the capture device 306 includes an InGaAs MOS array camera. Image arrays contemplated herein are two dimensional. Further, one dimensional line-scan or two dimensional time-delay integration (TDI line-scan) cameras with mechanized scanning may be used to create the two dimensional image arrays, while standard two dimensional array “snapshot” cameras may also be used. Single capture devices 306 may also be employed, which are used to create two dimensional images using a Nipkow disk or other method to scan an image across a single capture devices or series of discrete capture devices. More generally, a variety of different types of capture devices 306 configured to capture light at the particular wavelength emitted by the light source 302 and transmitted through the material 304 are possible for this application. The capture device 306 is provided to generate two dimensional image data, which is substantially in- focus and representative of light passing through the material 304. The image data may be provided in a single image or multiple images. Multiple images can be provided as multiple image slices of the material 304, at different depths of the material 304, or from different perspectives, such as viewing or illumination angle.

[0046] The material 304 may include various different types of materials, such as silicon, germanium, gallium arsenide, or other types of materials formed through a crystalline process. In this embodiment, the single crystal material 304 is a Czochralski (CZ) grown material forming one or more ingot sections, slices, wafers, slugs, slabs, and / or cylinders. The material 304 shown in Figure 3 is nominallyplain parallel, such that the top surface is generally parallel with the bottom surface of the material 304. In other examples, a material may be nearly plain parallel or nonplain parallel, such as cylindrical ingot sections.

[0047] In this embodiment, the single crystal material 304 may be subjected to testing at detection system 300 in a variety of conditions, including, for example, potentially doped with various dopants to some level, crude (such as slabs or slugs or after slicing, grinding, lapping or etching), polished (e.g., SSP wafer having front side only polished, back side in various conditions or DSP wafer having both surfaces polished, with front surface potentially final or kiss polished), and / or coated with an epitaxial layer of the same single crystal material except, potentially, a different doping level. Materials 304 may be provided in a variety of thicknesses, such as, for example, from under 1 mm up to about 10's of mm, or other thickness directly from a growing process or after one or more processing steps.

[0048] Detection system 300 further includes a processor 308 and a memory 310 coupled to the processor 308. Processor 308 may include one or more processing units (e.g., a multi-core configuration). The term processor 308, as used herein, refers to central processing units, microprocessors, microcontrollers, reduced instruction set circuits (RISC), application specific integrated circuits (ASIC), logic circuits, and / or any other circuit or processor capable of executing instructions to perform functions described herein. Further, processor 308 may include separate discrete devices located proximate to one another, and / or remotely from one another.

[0049] Memory 310 is one or more devices operable to enable information such as executable instructions and / or other data to be stored and / or retrieved. Memory 310 may include one or more computer readable media, such as, without limitation, hard disk storage, optical drive / disk storage, removable disk storage, flash memory, non-volatile memory, ROM, EEPROM, random access memory (RAM), etc. In several examples, memory 310 includes one or more non-transitory computer- readable storage media configured to store, without limitation, computer-executable instructions, image data, predetermined thresholds, and / or any other types of data referred to herein, expressly or inherently. Memory 310 may be incorporated intoand / or separate from processor 308, and / or accessible through one or more networks (e.g. , Cloud storage).

[0050] As used herein, the term “region of interest” may refer to any image region, including binary image or gray-scale image regions, that includes one or more image objects or blobs. As used herein, the term “image object” and “blob” may refer to, for example, data units of which at least a portion are being evaluated by the methods and systems described herein. In some embodiments, the term “image object” may refer to data units within a grey-scale image, while the term “blob” may refer to data units within a binary image.

[0051] In use, the single crystal material 304 is positioned between the light source 302 and the capture device 306, such that light from the light source 302 is directed through the material 304, and captured by capture device 306, potentially requiring scanning of the material 304 or the image capture device 306 to produce the captured two dimensional image array. The image data generated by the capture device 306 is provided to processor 308, which stores the image data in memory 310. Example image data of materials captured by capture device 306 is illustrated in Figures 4A and 4B. The systems and methods described herein are provided to process the image data to determine if one or more anomalies, defects, and / or marks 312, such as air pockets and / or particles, are present in the material 304.

[0052] Figures 4A and 4B illustrate NIR images of potential anomalies, defects, and / or marks 312 (shown in Figure 3). Figure 4A illustrates an NIR image of an air pocket in a material 304 (shown in Figure 3). Figure 4B illustrates an NIR image of a particle on or in the material 304.

[0053] Figures 5A-5C illustrate an example of an NIR inspection result of an epitaxy silicon wafer 102 (shown in Figure 1), showing three (3) lift pin marks 312 (shown in Figure 3) on the wafer 102. More specifically, Figure 5A illustrates a schematic of the placement of the three lift pins 106 (shown in Figure 1) on an example wafer 102. Figure 5B illustrates an NIR image of the marks 312 from the lift pins 106, such as from using system 300 (shown in Figure 3). Figure 5C illustratesa Dark Field image of the marks 312 from the lift pins 106, such as from using system 300 (shown in Figure 3). By viewing Figures 5B and 5C, the NIR inspection result can be compared to a dark field light scattering image. This demonstrates the different defect morphology between the two images and that the pin marks 312 are more clearly visualized in the NIR inspection result.

[0054] Figure 6 illustrates a process 600 for quantitative detection and analysis of wafer pin marks using the system 300 (shown in Figure 3). In the example embodiment, the steps of process 600 are performed by the processor 308 (shown in Figure 3). In some other embodiments, the steps of process 600 are performed by an external computer device 1602 (shown in Figure 16).

[0055] First, to determine the position(s) or location(s) of the lift pin marks on the surface of the wafer 102 (shown in Figure 1), the processor 308 receives 605 scan data, such as, but not limited to, an NIR defect map. In some embodiments, the scan data of the wafer 102 is obtained or exported from the detection system 300. In some embodiments, the scan data includes one or more images of the object to be analyzed. A mask is applied 610 to remove the “non-pin” mark areas from the scan data (z.e., the radial locations of the wafer surface that do not contact the lift pins). An example of a mask applied to an NIR defect map is shown in Figure 7. In some embodiments, the brighter ring inner diameter is pin location radius R - r window mm, and the outer diameter is pin location radius R + r window mm, where r window could be 3, 5, 10 or 15 mm, for example.

[0056] After applying the mask, noise defects are removed 615 from the white (unmasked) ring area. In some embodiments, the white ring area is subjected to image threshold (e.g., converted to binary), erode, and dilated effects to eliminate noise defects 615. This can vary depending on the lift pin configuration (e.g., dimensions). For example, where the lift pin mark is between 0.5 millimeters (mm) to 3 mm (in width or in height), the kernel of erode or dilate size is set, for example, at 3x3 or 5x5 or 7x7, and the erode and dilate times is set, for example, to 1, 2, 3, 4, or more, to remove all smaller defects and isolate the lift pin mark defects. One having ordinary skill in the art would understand that other methods may be used to removenoise, as long as they preserver the contours. Next, the contours on the processed unmasked ring area are detected 620. The detected contours are sorted 625 by size. In some embodiments, the detected contours are filtered by a threshold of the size. The largest contour is selected 630 as the first pin mark position as Pl(x,y,r, theta).

[0057] According to the lift pin configuration and the selected first pin mark position P 1 (x,y,r, theta), the remaining pin mark positions are located / detected 635. In one example, the wafer process chamber 100 includes three (3) pins 106 that are spaced 120° apart from one another, such that the remaining pin mark positions (z. e. , the second and third pin mark positions) are located as P2(x,y,r, theta) and P3(x,y,r, theta). A window is defined to locate the second and third pin mark location, for example, using P2(x+ / - window, y+ / - window). The window is 3, 5, 10 mm or larger. By this method, even if wafer 102 is not aligned before moving into reactor or chamber, all pin mark positions can be located.

[0058] The system 300 determines 640 if all pins 106 have been detected. If the pin mark positions have been located / detected 635, the NIR images are to continue 645 for next steps of pin mark analysis, such as shown in process 800 (shown in Figure 8). If all the pin mark positions (e.g., all three pin mark positions) cannot be located 635 based on the selected 630 first pin mark position, then the second largest size contour is selected as the first pin mark position for locating the remaining pin mark positions, as described above, and the process 600 repeats steps 630 through 640 until all pin mark positions are located. In some embodiments, the system 300 continues through Steps 630 through 640 until there are no more detected contours to select. In other embodiments, the system 300 continues through Steps 630 through 640 for a predetermined number of tries or attempts. In still further embodiments, the system 300 continues through Steps 630 through 640 until there are no more contours greater than a predetermined threshold to select 630 as the first pin. If the system 300 determines 650 that it cannot locate 635 all pin mark positions, then the system 300 reports 655 failure and an output is generated to an operator that pin mark analysis failed.

[0059] Figure 7 illustrates an applied mask on a NIR defect map. In some embodiments, the brighter ring inner diameter is pin location radius R - r window mm, and the outer diameter is pin location radius R + r window mm, where r window could be 3, 5,10 or 15mm.

[0060] Figure 8 illustrates a process 800 for quantitative detection and analysis of wafer pin mark defects using the system 300 (shown in Figure 3). In the example embodiment, the steps of process 600 are performed by the processor 308 (shown in Figure 3). In some other embodiments, the steps of process 800 are performed by an external computer device 1602 (shown in Figure 16).

[0061] To perform pin mark analysis to determine the position(s) or location(s) of the lift pin marks on the surface of the wafer 102 (shown in Figure 1), the system 300 receives 805 scan data, such as, but not limited to, an NIR defect map or image. In some embodiments, the scan data of the wafer 102 is obtained or exported from the detection system 300. In some embodiments, the scan data includes one or more images of the object to be analyzed. The image is smoothed 810. In image processing, smoothing is a technique used to reduce noise and fine details in an image by applying a low-pass filter. This filter works by replacing each pixel value with an average value of its neighboring pixels. Smoothing can help to improve the visual quality of an image and make it easier to analyze by reducing the impact of small variations in pixel values. However, too much smoothing can result in the loss of important information, so an appropriate level of smoothing must be selected or applied based on the specific requirements of the application. The NIR image has brighter features due to infrared light refection. The system 300 detects 815 contours for dark pixels which may indicate pin mark defects. This may be performed by applying one or more thresholds.

[0062] In the example embodiment, the system 300 renders 820 the detected contours to generate an image. In rendering pin mark contours, the dilation factor is based on the tuning to correlate with conventional laser light scattering inspection or dark filed image inspection.

[0063] Then the image is scanned to detect 825 contours in the rendered images. These contours will then be reported 830 as pin mark size. The system 300 may also report pin mark position. In some embodiments, the pin mark position is determined and reported by process 600 (shown in Figure 6). In the example embodiment, the system 300 monitors 835 pin conditions. If the pin marks exceed 840 any thresholds, the system 300 may instruct the operators to replace one or more pins 106. In an automated system, the system 300 may replace pins 106 that are outside of thresholds, automatically. If the pin marks do not exceed 840 thresholds, then process 800 continues for the next wafer 102 or surface. In some further embodiments, a process engineer can monitor pin mark defect conditions or perform process tuning or make the decision of pin replacement.

[0064] Figure 9A illustrates a raw NIR image, such as captured by capture device 306 (shown in Figure 3). In some embodiments, the raw NIR image is the image received 605 or 805 to start process 600 or 800 (shown in Figures 6 and 8, respectively). Figure 9B illustrates a smoothed image. The smoothed image may be the result of step 810 (shown in Figure 8). Figure 9C illustrates an example of finding contours in the smoothed NIR image. The contours may be the result of step 815 (shown in Figure 8). Figure 9D illustrates a rendered contour image. The rendered contour image may be the result of step 820 (shown in Figure 8. Figure 9E illustrates a pin mark NIR image. The pin mark NIR image may be the combination of the NIR image shown in Figure 9A and the rendered contour image shown in Figure 9D.

[0065] Figures 10A and 10B illustrate an example of detecting three pin mark positions in accordance with the techniques shown in processes 600 and 800 (shown in Figures 6 and 8, respectively). Pin mark position detection. Compared with dark field image techniques, the reference point PM1 is not needed, since the algorithm is able to search for and locate the pin mark positions (e.g., the triangle of points as shown in Figure 10A) to match the lift pin configuration even if wafer 102 (shown in Figure 1) is not aligned (notch down) before epitaxy deposition.

[0066] When the pin mark positions are determined or located, such as through process 600, pin mark analysis is performed, such as through process 800.First, the NIR defect image is loaded into / received by 805 an NIR image processing system, such as system 300 or computer device 1400. The NIR image is smoothed 810, where the NIR image has special “brighter” feature due to infrared light refection. A threshold is applied, and contours are detected 815 for dark pixels (corresponding to pin mark defects). The system 300 renders 820 the pin mark contours. In some embodiments, the dilation factor is based on the tuning to correlate with conventional laser light scattering inspection or dark filed image inspection. Based on the rendered image, the contours are again located / detected 825. These contours are reported 830 as pin mark size with the pin mark position.

[0067] FIGS. 11-14 compare different pin mark defect position detections between NIR images, according to the present disclosure, and dark field images. FIG. 15 plots correlation between pin marks for NIR transmission images vs. dark field images.

[0068] Figure 16 depicts an example configuration of a user computer device 1602. In the example embodiment, user computer device 1602 may be similar to, or the same as, or include processor 308 and memory 310 (both shown in Figure 3). User computer device 1602 may be operated by a user 1601.

[0069] User computer device 1602 may include a processor 1605 for executing instructions. In some embodiments, executable instructions may be stored in a memory area 1610. Processor 1605 may include one or more processing units (e.g., in a multi-core configuration). Memory area 1610 may be any device allowing information such as executable instructions and / or transaction data to be stored and retrieved. Memory area 1610 may include one or more computer readable media.

[0070] U ser computer device 1602 may also include at least one media output component 1615 for presenting information to user 1601. Media output component 1615 may be any component capable of conveying information to user 1601. In some embodiments, media output component 1615 may include an output adapter (not shown) such as a video adapter and / or an audio adapter. An output adapter may be operatively coupled to processor 1605 and operatively couplable to an outputdevice such as a display device (e.g., a cathode ray tube (CRT), liquid crystal display (LCD), light emitting diode (LED) display, or “electronic ink” display) or an audio output device (e.g., a speaker or headphones).

[0071] In some embodiments, media output component 1615 may be configured to present a graphical user interface (e.g., a web browser and / or a client application) to user 1601. A graphical user interface may include, for example, an interface for viewing items of information provided by the processor 308. In some embodiments, user computer device 1602 may include an input device 1620 for receiving input from user 1601. User 1601 may use input device 1620 to, without limitation, submit information either through speech or typing.

[0072] Input device 1620 may include, for example, a keyboard, a pointing device, a mouse, a stylus, a touch sensitive panel (e.g., a touch pad or a touch screen), a gyroscope, an accelerometer, a position detector, a biometric input device, and / or an audio input device. A single component such as a touch screen may function as both an output device of media output component 1615 and input device 1620.

[0073] User computer device 1602 may also include a communication interface 1625, communicatively coupled to a remote device such as processor 308. Communication interface 1625 may include, for example, a wired or wireless network adapter and / or a wireless data transceiver for use with a mobile telecommunications network.

[0074] Stored in memory area 1610 are, for example, computer readable instructions for providing a user interface to user 1601 via media output component 1615 and, optionally, receiving and processing input from input device 1620. A user interface may include, among other possibilities, a web browser and / or a client application. Web browsers enable users, such as user 1601, to display and interact with media and other information typically embedded on a web page or a website. A client application may allow user 1601 to interact with, for example, processor 308. For example, instructions may be stored by a cloud service, and the output of the execution of the instructions sent to the media output component 1615.

[0075] Processor 1605 may execute computer-executable instructions for implementing aspects of the disclosure. In some embodiments, the processor 1605 may be transformed into a special purpose microprocessor by executing computerexecutable instructions or by otherwise being programmed. For example, the processor 1605 may be programmed with the instruction such as illustrated in Figures 6 and 8.

[0076] At least one of the technical problems addressed by this system may include: (i) improve analysis of wafers; (ii) decreased loss of material due to malfunction; (iii) earlier determination of wafer quality; (iv) increased accuracy in wafer analysis; and / or (v) increased accuracy in wafer analysis.ADDITIONAL CONSIDERATIONS

[0077] As will be appreciated based upon the foregoing specification, the above-described embodiments of the disclosure may be implemented using computer programming or engineering techniques including computer software, firmware, hardware or any combination or subset thereof. Any such resulting program, having computer-readable code means, may be embodied or provided within one or more computer-readable media, thereby making a computer program product, i.e., an article of manufacture, according to the discussed embodiments of the disclosure. The computer-readable media may be, for example, but is not limited to, a fixed (hard) drive, diskette, optical disk, magnetic tape, semiconductor memory such as read-only memory (ROM), and / or any transmitting / receiving medium such as the Internet or other communication network or link. The article of manufacture containing the computer code may be made and / or used by executing the code directly from one medium, by copying the code from one medium to another medium, or by transmitting the code over a network.

[0078] These computer programs (also known as programs, software, software applications, “apps,” or code) include machine instructions for a programmable processor and can be implemented in a high-level procedural and / or object-oriented programming language, and / or in assembly / machine language. As used herein, the terms “machine-readable medium” “computer-readable medium” refers toany computer program product, apparatus and / or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine -readable signal. The “machine-readable medium” and “computer-readable medium,” however, do not include transitory signals. The term “machine-readable signal” refers to any signal used to provide machine instructions and / or data to a programmable processor.

[0079] As used herein, the terms “processor” and “computer” and related terms, e.g., “processing device”, “computing device”, and “controller” are not limited to just those integrated circuits referred to in the art as a computer, but broadly refers to a microcontroller, a microcomputer, a programmable logic controller (PLC), a reduced instruction set circuit (RISC), an application specific integrated circuit (ASIC), logic circuits, and any other circuit or processor capable of executing the functions described herein. The above examples are example only and are thus not intended to limit in any way the definition and / or meaning of the term “processor.”

[0080] As used herein, the terms “software” and “firmware” are interchangeable, and include any computer program stored in memory for execution by a processor, including RAM memory, ROM memory, EPROM memory, EEPROM memory, and non-volatile RAM (NVRAM) memory. The above memory types are example only, and are thus not limiting as to the types of memory usable for storage of a computer program.

[0081] As used herein, the term “database” can refer to either a body of data, a relational database management system (RDBMS), or to both. As used herein, a database can include any collection of data including hierarchical databases, relational databases, flat file databases, object-relational databases, object-oriented databases, and any other structured collection of records or data that is stored in a computer system. The above examples are example only, and thus are not intended to limit in any way the definition and / or meaning of the term database. Examples of RDBMS’ include, but are not limited to including, Oracle® Database, MySQL, IBM® DB2, Microsoft® SQL Server, Sybase®, and PostgreSQL. However, any database canbe used that enables the systems and methods described herein. (Oracle is a registered trademark of Oracle Corporation, Redwood Shores, California; IBM is a registered trademark of International Business Machines Corporation, Armonk, New York; Microsoft is a registered trademark of Microsoft Corporation, Redmond, Washington; and Sybase is a registered trademark of Sybase, Dublin, California.)

[0082] In another example, a computer program is provided, and the program is embodied on a computer-readable medium. In an example, the system is executed on a single computer system, without requiring a connection to a server computer. In a further example, the system is being run in a Windows® environment (Windows is a registered trademark of Microsoft Corporation, Redmond, Washington). In yet another example, the system is run on a mainframe environment and a UNIX® server environment (UNIX is a registered trademark of X / Open Company Limited located in Reading, Berkshire, United Kingdom). In a further example, the system is run on an iOS® environment (iOS is a registered trademark of Cisco Systems, Inc. located in San Jose, CA). In yet a further example, the system is run on a Mac OS® environment (Mac OS is a registered trademark of Apple Inc. located in Cupertino, CA). In still yet a further example, the system is run on Android® OS (Android is a registered trademark of Google, Inc. of Mountain View, CA). In another example, the system is run on Linux® OS (Linux is a registered trademark of Linus Torvalds of Boston, MA). The application is flexible and designed to run in various different environments without compromising any major functionality.

[0083] As used herein, an element or step recited in the singular and proceeded with the word “a” or “an” should be understood as not excluding plural elements or steps, unless such exclusion is explicitly recited. Furthermore, references to “example” or “one example” of the present disclosure are not intended to be interpreted as excluding the existence of additional examples that also incorporate the recited features. Further, to the extent that terms “includes,” “including,” “has,” “contains,” and variants thereof are used herein, such terms are intended to be inclusive in a manner similar to the term “comprises” as an open transition word without precluding any additional or other elements.

[0084] Furthermore, as used herein, the term “real-time” refers to at least one of the time of occurrence of the associated events, the time of measurement and collection of predetermined data, the time to process the data, and the time of a system response to the events and the environment. In the examples described herein, these activities and events occur substantially instantaneously.

[0085] In some embodiments, the system includes multiple components distributed among a plurality of computer devices. One or more components may be in the form of computer-executable instructions embodied in a computer-readable medium. The systems and processes are not limited to the specific embodiments described herein. In addition, components of each system and each process can be practiced independent and separate from other components and processes described herein. Each component and process can also be used in combination with other assembly packages and processes. The present embodiments may enhance the functionality and functioning of computers and / or computer systems.

[0086] The computer-implemented methods discussed herein can include additional, less, or alternate actions, including those discussed elsewhere herein. The methods can be implemented via one or more local or remote processors, transceivers, servers, and / or sensors (such as processors, transceivers, servers, and / or sensors mounted on vehicles or mobile devices, or associated with smart infrastructure or remote servers), and / or via computer- executable instructions stored on non- transitory computer-readable media or medium. Additionally, the computer systems discussed herein can include additional, less, or alternate functionality, including that discussed elsewhere herein. The computer systems discussed herein can include or be implemented via computer-executable instructions stored on non-transitory computer- readable media or medium.

[0087] As used herein, the term “non-transitory computer-readable media” is intended to be representative of any tangible computer-based device implemented in any method or technology for short-term and long-term storage of information, such as, computer-readable instructions, data structures, program modules and sub-modules, or other data in any device. Therefore, the methods described hereincan be encoded as executable instructions embodied in a tangible, non-transitory, computer readable medium, including, without limitation, a storage device and / or a memory device. Such instructions, when executed by a processor, cause the processor to perform at least a portion of the methods described herein. Moreover, as used herein, the term “non-transitory computer-readable media” includes all tangible, computer- readable media, including, without limitation, non-transitory computer storage devices, including, without limitation, volatile and nonvolatile media, and removable and nonremovable media such as a firmware, physical and virtual storage, CD-ROMs, DVDs, and any other digital source such as a network or the Internet, as well as yet to be developed digital means, with the sole exception being a transitory, propagating signal.

[0088] The patent claims at the end of this document are not intended to be construed under 35 U.S.C. § 112(f) unless traditional means-plus-function language is expressly recited, such as “means for” or “step for” language being expressly recited in the claim(s).

[0089] This written description uses examples to disclose the disclosure, including the best mode, and also to enable any person skilled in the art to practice the disclosure, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

Claims

WHAT IS CLAIMED IS:

1. A computer device comprising at least one processor in communication with at least one memory device, wherein the at least one processor is programmed to: receive scan data of an object to be analyzed; smooth the scan data to create a smoothed image; detect contours for dark pixels in the smoothed image; generate a rendered image based on the detected contours for dark pixels; detect rendered contours in the rendered image; identify marks based on the rendered contours; and determine and report attributes of marks based on the identified marks.

2. The computer device of Claim 1, wherein the object to be analyzed is a semiconductor wafer.

3. The computer device of Claim 1, wherein the scan data is a near infrared (NIR) image of the object to be analyzed.

4. The computer device of Claim 1, wherein the marks indicate locations of a plurality of pins that previously contacted the object to be analyzed.

5. The computer device of Claim 1, wherein a tuned dilation factor is used for generating the rendered image.

6. The computer device of Claim 1 , wherein the attributes of marks include at least one of size and position of the marks.

7. The computer device of Claim 1, wherein the at least one processor is further programmed to determine whether or not to adjust one or more devices based on the determination.

8. The computer device of Claim 1, wherein the scan data includes one or more received images, and wherein the at least one processor is further programmed to combine the rendered contours with the received image to generate a final image to indicate marks.

9. A computer-implemented method for analyzing an object, the computer-implemented method implemented by a computing device including at least one processor in communication with at least one memory device, the method comprising: receiving scan data of an object to be analyzed; smoothing the scan data to create a smoothed image; detecting contours for dark pixels in the smoothed image; generating a rendered image based on the contours for dark pixels; detecting rendered contours in the rendered image; identifying marks based on the rendered contours; and determining and reporting attributes of marks based on the identified marks.

10. The computer-implemented method of Claim 9, wherein the object to be analyzed is a semiconductor wafer.

11. The computer-implemented method of Claim 9, wherein the scan data is a near infrared (NIR) image of the object to be analyzed.

12. The computer-implemented method of Claim 9, wherein the marks indicate locations of a plurality of pins that previously contacted the object to be analyzed.

13. The computer-implemented method of Claim 9, wherein a tuned dilation factor is used for generating the rendered image.

14. The computer-implemented method of Claim 9, wherein the attributes of marks include at least one of size and position of the marks.

15. The computer-implemented method of Claim 9 further comprising determining whether or not to adjust one or more devices based on the determination.

16. The computer-implemented method of Claim 9, wherein the scan data includes one or more received images, and further comprising combining the rendered contours with the received image to generate a final image to indicate marks.

17. A computer device comprising at least one processor in communication with at least one memory device, wherein the at least one processor is programmed to: receive an image of an object to be analyzed; apply a mask to the image based on a shape of the object to be analyzed to generate a masked image; detect contours in the masked image; sort the detected contours to generate a plurality of sorted contours; select a first mark position based upon the plurality of sorted contours; detect a plurality of other marks based on the first mark position; and report locations of the first mark and the plurality of other marks.

18. The computer device of Claim 17, wherein the at least one processor is further programmed to remove noise from the masked image.

19. The computer device of Claim 17, wherein the at least one processor is further programmed to detect the plurality of other marks based upon predetermined known relative positions of the plurality of others marks in relation to the first mark position.

20. The computer device of Claim 17, wherein the at least one processor is further programmed to: determine one or more of the plurality of other marks are not detected; select a replacement first mark position based on the plurality of sorted contours; and detect the plurality of other marks based on the replacement first mark position.

21. The computer device of Claim 20, wherein the replacement first mark position is a next largest contour of the plurality of sorted contours.

22. The computer device of Claim 17, wherein the first mark position is selected from a largest contour of the plurality of sorted contours.

23. The computer device of Claim 17, wherein the object to be analyzed is a semiconductor wafer.

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