Method for designing main circuit parameters for transformer-free multi-terminal flexible interconnection apparatus

Abstract

The present invention relates to the technical fields of alternating current power grid power flow control and power electronics. Disclosed is a method for designing main circuit parameters for a transformer-free multi-terminal flexible interconnection apparatus, comprising: carrying out MTSNOP main circuit parameter design by means of a series converter design and a parallel converter design; the series converter design comprises a design for a voltage and quantity, and a capacitance value, of a sub-module of a PFCM and a PBCM, and a bridge arm inductance design and an AC-side equivalent filter inductance design of the PFCM and the PBCM; the parallel converter design comprises a parallel CMI capacity design and sub-module voltage and quantity design, a parallel CMI sub-module capacitance value design, and a parallel CMI connection inductance design. The method of the present invention adopts a modular design with easy port expandability, allowing for adaptability to power systems of different scales. The reasonable parameter design effectively improves system transmission capacity, mitigates heavily loaded line problems, optimizes transmission power flow, effectively suppresses voltage fluctuations, and improves voltage quality.

Description

A transformerless multi-terminal flexible interconnection device main loop parameter design method TECHNICAL FIELD

[0001] The present application relates to the field of alternating current power grid flow control, in particular to a transformerless multi-terminal flexible interconnection device main loop parameter design method and system. BACKGROUND

[0002] With the global economic integration and the growth of power demand, power systems are developing towards high voltage, large capacity and long distance power transmission. However, large-scale power systems face many challenges, including line overload, voltage fluctuation, power transmission bottleneck, etc. The power industry faces three major challenges: the increase in power demand and the uneven geographical distribution of power sources limit the construction of new power lines, requiring the transmission capacity of existing lines to be improved and maintained at the stable limit; the uneven distribution of line parameters causes system overload and voltage quality degradation, which requires optimization of the power transmission capacity of the power system without affecting safety and stability; frequent power changes in the system increase the complexity of grid control, requiring optimization of power transmission and global consideration of power system operation mode.

[0003] Existing flexible interconnection devices have problems such as high cost, large size, and low operating efficiency, which limit their application in power transmission grids. In order to solve these problems, researchers have proposed a transformerless multi-terminal flexible interconnection device (MTSNOP). MTSNOP is composed of series converters and parallel cascaded multi-level converters (CMI), and has the advantages of no transformer, light weight, high efficiency, low cost, and easy expansion of ports. The selection of MTSNOP main loop parameters is the key to system design, and reasonable parameters can effectively improve system performance, reduce cost, and improve economy. Currently, there is no MTSNOP main loop parameter design scheme at home and abroad, so it is of great significance to explore the technical and economic advantages of MTSNOP under complex grid structure, and it is necessary to study the main loop parameter design method of transformerless multi-terminal flexible interconnection device.

[0004] SUMMARY

[0005] This section is intended to summarize some aspects of the embodiments of the present application and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the abstract and title of the specification to avoid obscuring the purpose of this section, abstract and title, and such simplifications or omissions cannot be used to limit the scope of the present application.

[0006] In view of the above problems, the present application is proposed.

[0007] Therefore, the present application solves the technical problems of poor transmission capacity, low voltage quality in the prior art, and how to design a transformerless multi-terminal flexible interconnection device main circuit parameter method.

[0008] To solve the above technical problems, the present application provides the following technical solutions: a transformerless multi-terminal flexible interconnection device main circuit parameter design method, including dividing the MTSNOP main circuit parameter design into series converter design and parallel converter design; designing the submodule voltage and quantity, capacitor capacity, bridge arm inductance, and AC side equivalent filter inductance of PFCM and PBCM in the series converter design; and designing the capacity of parallel CMI, submodule voltage and quantity, capacitor capacity, and connecting inductance in the parallel converter design.

[0009] As a preferred scheme of the transformerless multi-terminal flexible interconnection device main circuit parameter design method, the series converter design includes that the PBCM structure in the series converter is the same as the PFCM structure, PFCM and PBCM share a common DC bus, and the PBCM parameter design method is the same as the PFCM.

[0010] As a preferred scheme of the transformerless multi-terminal flexible interconnection device main circuit parameter design method, the series converter design further includes PFCM submodule voltage and quantity and capacitor capacity design, the PFCM submodule voltage and quantity are set to be 0.1 times the phase voltage amplitude of the AC component amplitude of the series voltage, and are expressed as:

[0011] wherein, is the PFCM output voltage fundamental component, V phase is the line phase voltage;

[0012] The PFCM is a single-phase MMC structure, the AC side output voltage amplitude is half of the DC bus voltage, the DC bus voltage is equal to the product of the number of PFCM bridge arm submodules and the submodule capacitor voltage value, and the number of submodules and the submodule capacitor voltage value are constrained, and are expressed as:

[0013] wherein, N is the number of PFCM bridge arm submodules, V c is the PFCM submodule capacitor voltage;

[0014] Based on the submodule capacitor voltage value, the working voltage of the IGBT is selected to be 50% to 70% of the rated voltage, and the submodule capacitor voltage rating is constrained, and is expressed as:

[0015] wherein, V IGBT is the rated voltage of the IGBT, The capacitor voltage rating of the PFCM sub-module;

[0016] The working current of the switching device in the PFCM is consistent with the bridge arm current, including the base frequency alternating current and the direct current, and is represented as:

[0017] Wherein, I IGBT is the rated current of the IGBT, I N is the line current, is the direct current component of the bridge arm current;

[0018] Based on the number of sub-modules and the constraints of the capacitor voltage value in the sub-module, the capacitor voltage rating of the sub-module, and after selecting the switching device that meets the requirements, the switching frequency is selected according to the product data book of the device, and is recorded as f PFCM ;

[0019] The capacitor value of the PFCM sub-module is designed to include the capacitor suppression effect on the direct current voltage ripple, and the capacitor voltage fluctuation is constrained within the specified range to limit the voltage stress of the device. The bridge arm current of the PFCM is calculated and represented as:

[0020] Wherein, i cl (t) is the instantaneous value of the PFCM bridge arm current connected to the line l, i l (t) is the instantaneous value of the line l current, I l is the current of the lth line, is the direct current component of the PFCM bridge arm current connected to the lth line, p l is the current phase of the lth line, and w is the base frequency angle frequency, and t is the time;

[0021] The switching function of the PFCM bridge arm is constructed and represented as:

[0022] Wherein, M l is the voltage regulation degree, S l is the switching function of the bridge arm, and q cl is the phase of the bridge arm output voltage;

[0023] With the action of the switching device, the current flowing into the sub-module capacitor is represented as:

[0024] Wherein, C is the capacitance value of each sub-module capacitor in the PFCM;

[0025] The direct current component of the current flowing into the capacitor is zero, and the direct current component of the current flowing into the capacitor is represented as:

[0026] The direct current component of the bridge arm current is calculated and represented as:

[0027] The DC component of the bridge arm current is substituted into the current flowing into the submodule capacitor, the current flowing into the submodule capacitor is expressed as:

[0028] The capacitor voltage fluctuation is obtained by the current flowing into the submodule capacitor, and is expressed as:

[0029] Where, ΔV c is the PFCM capacitor voltage fluctuation value;

[0030] The submodule capacitor voltage fluctuation includes fundamental frequency fluctuation and double frequency fluctuation, if the modulation degree is maximum (M l =1), the capacitor voltage fluctuation maximum value is expressed as:

[0031] The constraint of the submodule capacitor capacitance value of the PFCM is designed, and is expressed as:

[0032] When the submodule capacitor capacitance value of the PFCM meets the constraint, the submodule voltage fluctuation in the PFCM will be maintained within the required range.

[0033] As a preferred scheme of the transformerless multi-terminal flexible interconnection device main circuit parameter design method, wherein: the series converter design further includes PFCM bridge arm inductor design and AC side equivalent filter inductor design, the PFCM bridge arm inductor design includes that the inductance of the PFCM meets the requirement of circulating current suppression, the bridge arm voltage and the bridge arm current are added into the double frequency fluctuation, and the total energy of the upper and lower bridge arms is calculated, and is expressed as:

[0034] Where, v clp is the upper bridge arm output voltage, P is the active component transmitted by the bridge arm, W pha (t) is the total energy of the upper and lower bridge arms, ρ 2f is the phase of the double frequency circulating current, V 2f is the double frequency voltage, P is the active component transmitted by the bridge arm, the subscript p is the parameter of the upper bridge arm, the subscript n is the parameter of the lower bridge arm, and L is the bridge arm inductance;

[0035] N submodules in each bridge arm, the double frequency fluctuation is equally divided by 2N bridge arms of the upper and lower bridge arms, and the energy W PFCM stored by each PFCM is expressed as:

[0036] Where, W PFCM is the energy stored by each PFCM, V dc is the DC bus voltage;

[0037] The total energy of the upper and lower bridge arms generated by the double-frequency circulating current is equal to the energy stored in the PFCM capacitor, and the total energy of the upper and lower bridge arms and the energy W stored in each PFCM are equal, which is expressed as: PFCM The double-frequency component in the equation is equal, which is expressed as:

[0038] Wherein, V dc is the DC bus voltage;

[0039] The amplitude of the double-frequency circulating current is calculated, which is expressed as:

[0040] Wherein, I 2f is the amplitude of the double-frequency circulating current;

[0041] The bridge arm inductance is designed, which is expressed as:

[0042] The bridge arm inductance can suppress the rising rate of the DC side short-circuit fault current. If the positive and negative bus of the DC side is short-circuited, the short-circuit current forms a loop through the PFCM. The rising rate of the bridge arm current is calculated, which is expressed as:

[0043] Wherein, i cp is the upper bridge arm current of the PFCM, and i cn is the lower bridge arm current of the PFCM;

[0044] The bridge arm inductance is calculated, which is expressed as:

[0045] Wherein, α is the rising rate of the transient lower bridge arm current;

[0046] The design of the equivalent filter inductance of the AC side of the PFCM includes setting the line current ripple constraint, which is expressed as:

[0047] Wherein, is the rated value of the DC bus voltage, L l is the equivalent filter inductance of the line, f s is the switching frequency, and △I max is the maximum value of the line current ripple;

[0048] The design of the line equivalent filter inductance constraint includes taking the maximum value of the line current ripple as 10% of the rated current amplitude of the line, which is expressed as:

[0049] Wherein, f eqs is the equivalent switching frequency of the PFCM;

[0050] Under the constraint condition of the line equivalent filter inductance, the unit value of the line equivalent filter inductance is set to 0.1, and the line equivalent filter inductance is calculated, which is expressed as:

[0051] wherein S N is the line capacity.

[0052] As a preferred scheme of the transformerless multi-terminal flexible interconnection device main circuit parameter design method, the parallel converter design includes parallel CMI capacity design and sub-module voltage and quantity design, the parallel CMI capacity design includes providing mutual reactive power support among the transmission lines when regulating the power flow of multiple interconnected transmission lines using MTSNOP, and the parallel CMI provides reactive power to achieve reactive compensation of the balanced line, and the parallel CMI reactive compensation capacity is Q N ;

[0053] The design of the parallel CMI sub-module voltage and quantity is related to the number of parallel CMI sub-modules, the sub-resistance value of the IGBT tube, and the line phase voltage, and is constrained by the number of each phase sub-modules, and is expressed as:

[0054] wherein M is the number of each phase sub-modules, and C is the rated value of the sub-module capacitor voltage.

[0055] As a preferred scheme of the transformerless multi-terminal flexible interconnection device main circuit parameter design method, the parallel converter design also includes parallel CMI capacity design and sub-module voltage and quantity design, and the parallel CMI sub-module capacitor capacity design includes suppressing the ripple of the capacitor voltage by selecting the parallel CMI sub-module capacitor capacity, and constructing the average switching function of the output voltage of each sub-module, and is expressed as:

[0056] wherein S c (t) is the average switching function of the output voltage of each sub-module, V p is the fundamental component of the parallel CMI output voltage, θ p is the phase of the parallel CMI output voltage.

[0057] The instantaneous value of the capacitor current flowing into the sub-module is calculated and is expressed as:

[0058] wherein i c (t) is the instantaneous value of the capacitor current flowing into the sub-module, i p (t) is the instantaneous value of the CMI line current, I p is the bridge arm current amplitude.

[0059] The instantaneous value of the capacitor voltage flowing into the sub-module is calculated and is expressed as:

[0060] wherein v c(t) is the instantaneous value of the capacitor voltage flowing into the sub-module, C is the parallel CMI sub-module capacitor capacity value;

[0061] The parallel CMI sub-module capacitor capacity value constraint is designed and represented as:

[0062] Wherein, ΔV c is the fluctuation of the capacitor voltage.

[0063] As a preferred scheme of the transformerless multi-terminal flexible interconnection device main circuit parameter design method, wherein: the parallel converter design further includes parallel CMI connection inductor design, and the parallel CMI connection inductor design includes CMI operating characteristics in steady state, reactive power output in ideal state, and is represented as:

[0064] Wherein, U S is the grid-side voltage, U C is the output voltage of the CMI, N is the phase difference between the grid-side voltage and the output voltage of the CMI, L p is the CMI connection inductor;

[0065] If the constraint on the CMI connection inductor is in terms of reactive power compensation capacity, it is represented as:

[0066] If the constraint on the CMI connection inductor is in terms of three-phase voltage imbalance, it is represented as:

[0067] Wherein, is the three-phase unbalanced voltage;

[0068] If the CMI connection inductor meets the filtering effect of the output current, the inductance unit value is set to 0.1, the CMI connection inductor is represented as:

[0069] The CMI connection inductor design meets the compensation demand of the reactive power under the rated capacity, the stable operation under the grid voltage imbalance condition and the filtering effect on the output current.

[0070] Another object of the present application is to provide a transformerless multi-terminal flexible interconnection device main circuit parameter design system, which can reasonably design the transformerless multi-terminal flexible interconnection device main circuit parameters through the construction of an automatic distribution module, a series converter module and a parallel converter module, and solve the problem of the current transformerless multi-terminal flexible interconnection device main circuit parameter design.

[0071] As a preferred scheme of the transformerless multi-terminal flexible interconnection device main circuit parameter design system, the system comprises an automatic distribution module, a series converter module and a parallel converter module; the automatic distribution module is used for distributing the MTSNOP main circuit parameter design into series converter design and parallel converter design; the series converter module is used for parameter design of voltage and number of PFCM and PBCM sub-modules, capacitance value of PFCM and PBCM sub-modules, bridge arm inductance of PFCM and PBCM and equivalent filter inductance on the alternating current side; and the parallel converter module is used for parameter design of parallel CMI capacity, sub-module voltage and number, parallel CMI sub-module capacitance value and parallel CMI connecting inductance.

[0072] A computer device comprises a memory and a processor, the memory stores a computer program, and the processor executes the computer program to implement the steps of the transformerless multi-terminal flexible interconnection device main circuit parameter design method.

[0073] A computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the transformerless multi-terminal flexible interconnection device main circuit parameter design method.

[0074] The transformerless multi-terminal flexible interconnection device main circuit parameter design method provided by the application has the advantages that: the method adopts modular design, and the port is easy to expand, so that the method can be adapted to power systems of different scales; the voltage and number of PFCM and PBCM sub-modules are designed to affect the amplitude of the equivalent output voltage of the series connection, so as to determine the range of power flow regulation; the capacitance value of PFCM and PBCM sub-modules is designed to affect the amplitude of the capacitance voltage fluctuation, so as to improve the quality of the output voltage; the bridge arm inductance of PFCM and PBCM is designed to improve the stable operation and system performance of PFCM and PBCM; the equivalent filter inductance on the alternating current side of PFCM and PBCM is designed to constrain the filtering effect of the switching frequency current ripple; the voltage and number of parallel CMI sub-modules are designed to constrain the voltage and number relationship of the CMI sub-modules, so that the transformerless multi-terminal flexible interconnection device has simple control, the voltage resistance of a single switching device is reduced, and the manufacturing cost is reduced; the capacitance value of the parallel CMI sub-modules is designed to select appropriate capacitance value to ensure the stable performance of the system; the connecting inductance of the parallel CMI is designed to ensure the stability of the system in combination with the compensation demand of reactive power under the rated capacity, the stable operation under the unbalanced grid voltage condition and the filtering effect on the output current; reasonable parameter design can effectively improve the system transmission capacity, relieve the line overload problem, optimize the power flow, effectively suppress voltage fluctuation and improve voltage quality; and the application achieves better effects in port expansion, transmission capacity improvement, voltage quality improvement and MTSNOP main circuit parameter design. BRIEF DESCRIPTION OF DRAWINGS

[0075] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0076] Fig. 1 is a whole flow chart of a main circuit parameter design method of a transformerless multi-terminal flexible interconnection device provided by a first embodiment of the present application;

[0077] Fig. 2 is a topological structure of a transformerless multi-terminal flexible interconnection device and a system schematic diagram of interconnected multi-transmission lines provided by the first embodiment of the present application;

[0078] Fig. 3 is a system schematic diagram of a transformerless multi-terminal flexible interconnection device connecting three transmission lines provided by the first embodiment of the present application;

[0079] Fig. 4 is a capacitor voltage waveform diagram of a series converter submodule of a transformerless multi-terminal flexible interconnection device provided by a second embodiment of the present application;

[0080] Fig. 5 is a capacitor voltage waveform diagram of a parallel CMI submodule of a transformerless multi-terminal flexible interconnection device provided by the second embodiment of the present application;

[0081] Fig. 6 is a current waveform diagram of a line 1 connected by a transformerless multi-terminal flexible interconnection device provided by the second embodiment of the present application;

[0082] Fig. 7 is a current waveform diagram of a line 2 connected by a transformerless multi-terminal flexible interconnection device provided by the second embodiment of the present application;

[0083] Fig. 8 is a current waveform diagram of a line 3 connected by a transformerless multi-terminal flexible interconnection device provided by the second embodiment of the present application;

[0084] Fig. 9 is a power waveform diagram of each line connected by a transformerless multi-terminal flexible interconnection device provided by the second embodiment of the present application;

[0085] Fig. 10 is a module schematic diagram of a main circuit parameter design system of a transformerless multi-terminal flexible interconnection device provided by a third embodiment of the present application. DETAILED DESCRIPTION

[0086] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the present application.

[0087] Embodiment 1, referring to FIG. 1-3, provides a transformerless multi-terminal flexible interconnection device main circuit parameter design method, including:

[0088] S1: The MTSNOP main circuit parameter design is divided into series converter design and parallel converter design.

[0089] Further, the series converter design includes that the energy balance module (PBCM) structure in the series converter is the same as the power flow control module (PFCM) structure, the PFCM and the PBCM share a DC bus, and the PBCM parameter design method is the same as the PFCM.

[0090] It should be noted that the parameter design of the MTSNOP main circuit is independently designed by respectively targeting the series converter and the parallel converter, which not only improves the flexibility of the design, but also realizes fine adjustment of the system performance through this step-by-step design method, thereby optimizing the efficiency and stability of the overall system. In particular, the consistency of the PBCM structure and the PFCM structure in the series converter, as well as the configuration of them sharing the DC bus, ensures the efficiency of the system in energy transmission and management. At the same time, the same design of the PBCM parameter and the PFCM parameter ensures the compatibility and interchangeability between system components, reduces the maintenance cost and complexity.

[0091] S2: The sub-module voltage and number, capacitor capacitance, bridge arm inductance, and AC side equivalent filter inductance of the PFCM and the PBCM in the series converter design are designed.

[0092] Further, the series converter design also includes PFCM sub-module voltage and number and capacitor capacitance design, which sets the AC component amplitude of the series voltage as 0.1 times the phase voltage amplitude, represented as:

[0093] wherein, is the PFCM output voltage fundamental component, V phase is the line phase voltage.

[0094] PFCM is a single-phase MMC structure, the AC side output voltage amplitude is half of the DC bus voltage, the DC bus voltage is equal to the number of PFCM bridge arm sub-modules multiplied by the sub-module capacitor voltage value, the number of sub-modules and the sub-module capacitor voltage value are constrained, expressed as:

[0095] Where, N is the number of sub-modules of a bridge arm of PFCM, V c is the PFCM sub-module capacitor voltage.

[0096] Based on the sub-module capacitor voltage value, the working voltage of IGBT is selected at 50% to 70% of the rated voltage, the sub-module capacitor voltage rating constraint is expressed as:

[0097] Where, V IGBT is the rated voltage of IGBT, is the rated value of PFCM sub-module capacitor voltage.

[0098] The working current of the switching device in PFCM is consistent with the bridge arm current, including the fundamental frequency AC and DC, expressed as:

[0099] Where, I IGBT is the rated current of IGBT, I N is the line current, is the DC component of the bridge arm current.

[0100] Based on the constraints of the number of sub-modules and the capacitor voltage value in the sub-module, the rated value of the sub-module capacitor voltage, and the selected switching device that meets the requirements, according to the product data book of the device, the switching frequency is selected, denoted as f PFCM .

[0101] It should be noted that the design of PFCM sub-module capacitor value includes the suppression effect of capacitor on DC voltage ripple, which limits the voltage stress of the device by constraining the capacitor voltage fluctuation within a specified range, and calculates the bridge arm current of PFCM, expressed as:

[0102] Where, i cl (t) is the instantaneous value of the PFCM bridge arm current connected to the line l, i l (t) is the instantaneous value of the line l current, I l is the current of the lth line, is the DC component of the PFCM bridge arm current connected to the lth line, ρ l is the current phase of the lth line, ω is the fundamental frequency angle, t is the time.

[0103] The switching function of PFCM bridge arm is constructed, expressed as:

[0104] where M l is the modulation index, S l is the switching function of the bridge leg, θ cl is the phase of the bridge leg output voltage.

[0105] The current flowing into the sub-module capacitor is expressed as:

[0106] where C is the capacitance of each sub-module capacitor in the PFCM.

[0107] The DC component of the current flowing into the capacitor is zero, and the AC component of the current flowing into the capacitor is expressed as:

[0108] The DC component of the bridge leg current is calculated and expressed as:

[0109] The DC component of the bridge leg current is substituted into the current flowing into the sub-module capacitor, and the current flowing into the sub-module capacitor is expressed as:

[0110] The capacitor voltage fluctuation is obtained from the current flowing into the sub-module capacitor and is expressed as:

[0111] where ΔV c is the capacitor voltage fluctuation value of the PFCM.

[0112] The sub-module capacitor voltage fluctuation includes a fundamental frequency fluctuation and a double frequency fluctuation, and if the modulation index is maximum (M l = 1), the maximum capacitor voltage fluctuation is expressed as:

[0113] The constraint of the sub-module capacitor capacitance of the PFCM is designed and expressed as:

[0114] When the sub-module capacitor capacitance of the PFCM meets the constraint, the sub-module voltage fluctuation in the PFCM will be maintained within the required range.

[0115] It should also be noted that the series converter design also includes the bridge leg inductance design of the PFCM and the equivalent filter inductance design on the AC side, the bridge leg inductance design of the PFCM includes that the inductance of the PFCM meets the requirement of circulating current suppression, the bridge leg voltage and the bridge leg current are added to the double frequency fluctuation, the total energy of the upper and lower bridge legs is calculated and expressed as:

[0116] where v clp is the output voltage of the upper bridge leg, P is the active component transmitted by the bridge leg, and W pha(t) is the total energy of upper and lower arms, ρ 2f is the phase of the second harmonic circulating current, V 2f is the second harmonic voltage, P is the active component transmitted by the bridge arm, the subscript p is the parameter of the upper arm, the subscript n is the parameter of the lower arm, and L is the bridge arm inductance.

[0117] N sub-modules in each bridge arm, 2N bridge arms of upper and lower arms are equally divided into second harmonic fluctuations, and the energy W PFCM stored by each PFCM is represented as:

[0118] where W PFCM is the energy stored by each PFCM, V dc is the DC bus voltage.

[0119] The total energy of the upper and lower arms generated by the second harmonic circulating current is equal to the energy stored in the PFCM capacitor, and the total energy of the upper and lower arms is equal to the second harmonic component in the energy W PFCM stored by each PFCM, which is represented as:

[0120] where V dc is the DC bus voltage.

[0121] The amplitude of the second harmonic circulating current is calculated, which is represented as:

[0122] where I 2f is the amplitude of the second harmonic circulating current;

[0123] The bridge arm inductance is designed, which is represented as:

[0124] The bridge arm inductance can suppress the rising rate of the short-circuit fault current on the DC side. If the positive and negative bus of the DC side is short-circuit fault, the short-circuit current forms a loop through the PFCM. The rising rate of the bridge arm current is calculated, which is represented as:

[0125] where i cp is the PFCM upper arm current, i cn is the PFCM lower arm current.

[0126] The bridge arm inductance is calculated, which is represented as:

[0127] where α is the rising rate of the transient lower arm current.

[0128] The equivalent filter inductance design of the AC side of the PFCM includes setting the line current ripple constraint, which is represented as:

[0129] where, L is the line equivalent filter inductance, f is the switching frequency, ΔI is the line current ripple variation, and I is the line current. l L is the line equivalent filter inductance, f is the switching frequency, ΔI is the line current ripple variation, and I is the line current. s L is the line equivalent filter inductance, f is the switching frequency, ΔI is the line current ripple variation, and I is the line current. max L is the line equivalent filter inductance, f is the switching frequency, ΔI is the line current ripple variation, and I is the line current.

[0130] The line equivalent filter inductance constraint is designed to take the maximum value of the line current ripple as 10% of the line current amplitude, which is expressed as:

[0131] L is the line equivalent filter inductance, f is the switching frequency, ΔI is the line current ripple variation, and I is the line current. eqs L is the line equivalent filter inductance, f is the switching frequency, ΔI is the line current ripple variation, and I is the line current.

[0132] Under the constraint condition of the line equivalent filter inductance, the unit value of the line equivalent filter inductance is set to 0.1, and the line equivalent filter inductance is calculated, which is expressed as:

[0133] L is the line equivalent filter inductance, f is the switching frequency, ΔI is the line current ripple variation, and I is the line current. N L is the line equivalent filter inductance, f is the switching frequency, ΔI is the line current ripple variation, and I is the line current.

[0134] It should also be noted that the voltage and number of PFCM and PBCM sub-modules directly determine the amplitude of the series equivalent output voltage, and thus the range of power flow regulation. The number of PFCM and PBCM sub-modules directly depends on the selection of sub-module capacitor voltage and the relationship between series voltages. In order to ensure the reliability of the device, a certain margin is usually reserved when selecting the number of sub-modules. When the selected sub-module capacitor voltage value is too large, higher voltage switch devices are required, and the corresponding manufacturing cost will also increase sharply. In addition, the output voltage level of fewer sub-modules is low, and the harmonic characteristics are poor. If the selected sub-module capacitor voltage value is too low, although the manufacturing cost of the required switch device is greatly reduced, too many sub-modules make the control complex and the overall size of the device large. Therefore, when selecting the number of sub-modules and the sub-module capacitor voltage value, the performance, reliability, cost and technical feasibility should also be considered comprehensively according to the actual application scenario. Because the device loss will increase greatly when the working voltage is too high, and the utilization rate of the device is insufficient when the working voltage is too low, it is necessary to ensure that the switch device meets its withstand voltage V IGBT and current I IGBTIGBT's working voltage is selected between 50% to 70% of the rated voltage. The capacitance of PFCM and PBCM affects the amplitude of the capacitor voltage fluctuation, thus affecting the quality of the output voltage. In addition, the bridge arm inductance in the series converter plays a key role in the power transmission of PFCM and PBCM, reducing the output current fluctuation, etc. When designing the bridge arm inductance, the parameter design needs to be considered from the aspects of meeting the circulating current suppression, fault current suppression, etc. The bridge arm inductance, as part of the internal circulating current loop between PFCM and PBCM, has a significant effect on suppressing internal circulating current. Therefore, the design of the bridge arm inductance is of great significance to the stable operation of PFCM and PBCM and the performance of the system. In the design of the equivalent filter inductance, if the internal impedance of the system considering the actual existence of the power grid is considered, the equivalent filter inductance can be appropriately reduced.

[0135] S3: design the capacity of parallel CMI, the voltage and number of sub-modules, the capacitance value, and the connecting inductance in the design of parallel converter.

[0136] Further, the parallel converter design includes the design of parallel CMI capacity and sub-module voltage and number, the design of parallel CMI capacity includes providing reactive power support between transmission lines when using MTSNOP to regulate the power flow of multiple interconnected transmission lines, and the parallel CMI provides reactive power to balance the reactive compensation of the line, and the reactive compensation capacity of the parallel CMI is Q N .

[0137] Designing the voltage and number of parallel CMI sub-modules includes designing the number of sub-modules per phase based on the number of parallel CMI sub-modules, the withstand voltage of IGBT tube, and the line phase voltage, and is represented as:

[0138] wherein M is the number of sub-modules per phase, Vc is the rated value of the sub-module capacitor voltage.

[0139] It should be noted that the parallel converter design also includes the design of parallel CMI capacity and sub-module voltage and number, and the design of parallel CMI sub-module capacitance value includes the selection of parallel CMI sub-module capacitance value to suppress the ripple of the capacitor voltage, and the average switching function of the output voltage of each sub-module is constructed and is represented as:

[0140] wherein S c (t) is the average switching function of the output voltage of each sub-module, V p is the fundamental component of the output voltage of the parallel CMI, θ p is the phase of the output voltage of the parallel CMI.

[0141] The instantaneous value of the capacitor current flowing into the sub-module is calculated and is represented as:

[0142] where, i c (t) is the instantaneous value of the capacitor current flowing into the submodule, i p (t) is the instantaneous value of the CMI line current, I p is the amplitude of the bridge arm current.

[0143] The instantaneous value of the capacitor voltage flowing into the submodule is calculated and denoted as:

[0144] where, v c (t) is the instantaneous value of the capacitor voltage flowing into the submodule, C is the capacitance value of the parallel CMI submodule.

[0145] The capacitance value constraint of the parallel CMI submodule is designed and denoted as:

[0146] where, ΔV c is the fluctuation of the capacitor voltage.

[0147] It should also be noted that the design of the parallel converter also includes the design of the parallel CMI connecting inductance, which includes the operating characteristics of the CMI in steady state, the reactive power output in the ideal state, and is denoted as:

[0148] where, U S is the grid-side voltage, U C is the output voltage of the CMI, δ is the phase difference between the grid-side voltage and the output voltage of the CMI, L p is the CMI connecting inductance.

[0149] If the constraint on the CMI connecting inductance is considered from the perspective of reactive power compensation capacity, it is denoted as:

[0150] If the constraint on the CMI connecting inductance is considered in the case of three-phase voltage imbalance, it is denoted as:

[0151] where, is the three-phase unbalanced voltage.

[0152] If the CMI connecting inductance meets the filtering effect of the output current, the inductance unit value is set to 0.1, and the CMI connecting inductance is denoted as:

[0153] The design of the CMI connecting inductance is based on meeting the compensation demand of reactive power under rated capacity, stable operation in the case of grid voltage imbalance, and filtering effect on the output current.

[0154] It should also be noted that in the parallel CMI sub-module voltage and quantity design, similar to the PFCM bridge arm sub-module voltage design, when the designed sub-module capacitor voltage is too low, the more sub-modules required, the more complex the control, the bulkier the volume; on the contrary, when the sub-module capacitor voltage is designed too high, the number of sub-modules required is less, but the single switching device needs to withstand a higher voltage, and the manufacturing cost is high. Therefore, the selection of the rated voltage of the sub-module capacitor needs to be selected after considering the actual situation. Considering the reliability of the system, the selection of the number of sub-modules usually retains some redundancy. In addition, the number of sub-modules suitable for the modulation mode needs to be considered. In the parallel CMI sub-module voltage and quantity design, the selection of the capacitor value can improve the following performance of the system, but the selection of the capacitor value is too low, which will affect the stability of the DC side voltage; the selection of the capacitor value can ensure the stability of the system, but the selection of the capacitor value is too large, and the cost will also be large. In the parallel CMI connection inductance design, δ is the phase difference between the grid side voltage and the output voltage of the CMI, which is usually about 6°.

[0155] Embodiment 2, referring to FIGS. 4-9, provides a transformerless multi-terminal flexible interconnection device main circuit parameter design method for an embodiment of the application. In order to verify the beneficial effects of the application, economic benefit calculation and simulation experiments are carried out for scientific demonstration.

[0156] The MATLAB / Simulink software is used for simulation verification of the system. The power flow of each line in the simulation is shown in Table 1, and the simulation parameters are shown in Table 2.

[0157] Referring to Table 1, the experimental data are compared and analyzed.

[0158] Table 1: Power flow conditions of each line

[0159] Table 2: Simulation parameters

[0160] FIG. 4 is the sub-module capacitor voltage of PFCM and PBCM in MTSNOP series converter, in which the PFCM connected with line 1 operates under rated conditions, and its capacitor voltage fluctuation is about 8%. Since the capacitor parameters are designed according to the maximum value of the base frequency and the two-frequency voltage fluctuation superposition relationship, some margin is left, so the capacitor fluctuation of 8% meets the design requirements. FIG. 5 is the sub-module capacitor voltage of parallel CMI, and the voltage fluctuation is consistent with the designed value of about 5%. FIGS. 6-8 are the current waveforms of each line. FIG. 9 is the active power waveform and reactive power waveform of each line.

[0161] The simulation results show that the main loop parameter design method based on MTSNOP can realize high-efficiency and stable operation of the device, and the effectiveness of the design method is verified in the results, so the application has inventiveness.

[0162] Embodiment 3, referring to FIG. 10, provides a main loop parameter design method system of a transformerless multi-terminal flexible interconnection device, including an automatic distribution module, a series converter module and a parallel converter module.

[0163] The automatic distribution module is used for dividing the MTSNOP main loop parameter design into series converter design and parallel converter design; the series converter module is used for parameter design of voltage and number of PFCM and PBCM sub-modules, capacitance value of PFCM and PBCM sub-modules, bridge arm inductance of PFCM and PBCM and equivalent filter inductance on the alternating current side; and the parallel converter module is used for parameter design of parallel CMI capacity, sub-module voltage and number, parallel CMI sub-module capacitance value and parallel CMI connecting inductance.

[0164] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the application or the parts of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0165] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered a list of executable instructions for implementing logic functions, and can be specifically embodied in any computer-readable medium for use by an instruction execution system, device or apparatus, such as a computer-based system, a system including a processor, or other system that can fetch the instructions from the instruction execution system, device or apparatus and execute the instructions, or in conjunction with these instructions execution systems, devices or apparatus. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate or transport a program for use by or in connection with an instruction execution system, device or apparatus, or in conjunction with these instruction execution systems, devices or apparatus.

[0166] More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can also be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example, via an optical scanner, then compiled, interpreted, or otherwise processed, and stored in a computer memory in a form that is then reproducible into a computer readable medium.

[0167] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the embodiments described above, various steps or methods can be implemented, for example in software or firmware, stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, and in another embodiment, any of the following technologies, known in the art, or combinations thereof, can be used: discrete logic circuitry having logic gates for implementing logic functions upon an application of data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), and so forth. It should be appreciated that the foregoing examples have been given for illustrative purposes only and are not intended to limit the techniques of the present application, as described herein, in that as persons skilled in the art will recognize from this disclosure that other configurations comprising substitutions, combinations and / or additions of some of the disclosed features, can also be used to implement the techniques of the present application without unduly compromising its spirit and scope.

[0168] It should be understood that the foregoing examples have been given for illustrative purposes only and are not intended to limit the techniques of the present application, as described herein, in that as persons skilled in the art will recognize from this disclosure that other configurations comprising substitutions, combinations and / or additions of some of the disclosed features, can also be used to implement the techniques of the present application without unduly compromising its spirit and scope.

Claims

1. A transformerless multi-terminal flexible interconnection device main circuit parameter design method, characterized by, The method comprises the following steps: The MTSNOP main circuit parameter design is divided into series converter design and parallel converter design; The sub-module voltage and number, capacitor capacity, bridge arm inductance, and AC side equivalent filter inductance of PFCM and PBCM in the series converter design are designed; The capacity of parallel CMI, sub-module voltage and number, sub-module capacitor capacity, and parallel CMI connecting inductance in the parallel converter design are designed.

2. The transformerless multi-terminal flexible interconnection device (MTFID) main loop parameter design method of claim 1, wherein: The series converter design comprises that the PBCM structure in the series converter is the same as the PFCM structure, PFCM and PBCM share a DC bus, and the PBCM parameter design method is the same as the PFCM.

3. The transformerless multi-terminal flexible interconnection device (MTFID) main loop parameter design method of claim 2, wherein: The series converter design also includes PFCM submodule voltage and quantity and capacitor value design, sets the AC component amplitude of the series voltage to 0.1 times the phase voltage amplitude, expressed as: wherein Vpfc is the PFCM output voltage fundamental component, phase V is the line phase voltage; The PFCM is a structure of a single-phase MMC, the amplitude of the AC side output voltage is half of the DC bus voltage, the DC bus voltage is equal to the number of PFCM bridge arm sub-modules multiplied by the sub-module capacitor voltage value, the number of sub-modules and the constraint of the sub-module capacitor voltage value are represented as: Wherein, N is the number of sub-modules of one bridge arm of PFCM, V c is the voltage of the capacitor of the sub-module of PFCM; Based on the sub-module capacitor voltage value, the working voltage of the IGBT is selected at 50% to 70% of the rated voltage, and the sub-module capacitor voltage rating is constrained, expressed as: wherein V IGBT is the rated voltage of the IGBT, The sub-module capacitor voltage rating of PFCM is The working current of the switching device in the PFCM is consistent with the bridge arm current, including the fundamental frequency alternating current and the direct current, and is expressed as: where I IGBT is the rated current of the IGBT, I N is the line current, The DC component of the bridge arm current is Based on the number of sub-modules and the constraints of the capacitor voltage value within the sub-modules, the sub-module capacitor voltage rating constraints, after selecting the required switch device, according to the product data book of the device, the switching frequency is selected, denoted as f PFCM ; The capacitance value of the PFCM sub-module is designed to include the effect of suppressing the DC voltage ripple of the capacitor, constrain the voltage fluctuation of the capacitor within a specified range to limit the voltage stress of the device, calculate the bridge arm current of the PFCM, and is expressed as: where i cl (t) is the PFCM bridge arm current time value, i l (t) is the line l current instantaneous value, I l is the current of the lth line, DC component of the current of the PFCM bridge arm connected to the lth line, p l current phase of the lth line, ω is the fundamental angular frequency, and t is time The switching function of the PFCM bridge arm is constructed and is expressed as: wherein M l is the voltage modulation degree, S l is the switching function of the bridge arm, θ cl is the phase of the bridge arm output voltage; With the action of the switching device, the current flowing into the submodule capacitor is expressed as: Wherein, C is the capacity of each sub-module capacitor in PFCM. The DC component of the inrush capacitive current is zero, the DC component of the inrush capacitive current is represented as: The DC component of the bridge arm current is calculated, denoted as: The DC component of the bridge arm current is substituted into the current flowing into the sub-module capacitor, and the current flowing into the sub-module capacitor is represented as: The capacitor voltage fluctuation is derived from the current flowing into the sub-module capacitor, expressed as: wherein ΔV c is the PFCM capacitor voltage fluctuation value; The sub-module capacitor voltage fluctuation includes a fundamental frequency fluctuation and a double frequency fluctuation. If the modulation degree is maximum (M l = 1), the capacitor voltage fluctuation maximum value is expressed as: The constraint of the sub-module capacitor value of the PFCM is designed, which is expressed as: When the sub-module capacitor capacity of PFCM meets the constraint, the sub-module voltage fluctuation in PFCM will be maintained within the required range.

4. The transformerless multi-terminal flexible interconnection device (MTFID) main loop parameter design method of claim 3, wherein: The series converter design also includes a bridge arm inductance design of the PFCM and an AC side equivalent filter inductance design. The bridge arm inductance design of the PFCM includes that the inductance of the PFCM meets the requirement of circulating current suppression, the bridge arm voltage and the bridge arm current are added into the double-frequency fluctuation, and the total energy of the upper and lower bridge arms is calculated and expressed as: where v clp is the output voltage of the upper bridge arm, P is the active component transferred by the bridge arm, W pha (t) is the total energy of the upper and lower bridge arms, p 2f is the phase of the double-frequency circulating current, V 2f is the double-frequency voltage, P is the active component transferred by the bridge arm, the subscript p is the parameter of the upper bridge arm, the subscript n is the parameter of the lower bridge arm, and L is the bridge arm inductance; N sub-modules in each bridge arm, 2N bridge arms are divided by twice frequency fluctuation, each PFCM stores energy W PFCM , is expressed as: where W PFCM is the energy stored in each PFCM, V dc is the DC bus voltage; The total energy of the upper and lower bridge arms generated by the double-frequency circulating current is equal to the energy stored in the PFCM capacitor. The total energy of the upper and lower bridge arms and the energy W stored in each PFCM are equal, represented as: PFCM The double-frequency component in the equation is represented as: Vbus= Vdc+ Vout dc Vbus= Vdc+ Vout The amplitude of the second harmonic circulating current is calculated and expressed as: where I 2f is the amplitude of the doubled circulating current; The bridge arm inductor is designed, denoted as: The bridge arm current can inhibit the rising rate of the short-circuit fault current of the DC side. If the positive and negative bus of the DC side is short-circuit fault, the short-circuit current passes through the PFCM to form a loop, and the rising rate of the bridge arm current is calculated and expressed as: wherein, i cp is the PFCM upper bridge arm current, i cn is the PFCM lower bridge arm current; The bridge arm inductance is calculated and expressed as: Wherein, α is the rise rate of the bridge arm current in transient state. The PFCM AC side equivalent filter inductance design includes setting a line current ripple constraint, expressed as: wherein Vdc is the DC bus voltage rating, L l L is the line equivalent filter inductance, f s f is the switching frequency, ΔI max ΔI is the maximum line current ripple variation; The design line equivalent filter inductance constraint includes taking the line current ripple maximum value as 10% of the line rated current amplitude, which is expressed as: where f eqs is the PFCM equivalent switching frequency; Under the constraint condition of the line equivalent filter inductance, the line equivalent filter inductance is calculated, which is expressed as: where S N is the line capacity.

5. The transformerless multi-terminal flexible interconnection device (MTFID) main loop parameter design method of claim 4, wherein: The parallel converter design includes a parallel CMI capacity design and a sub-module voltage and number design, the parallel CMI capacity design includes providing mutual reactive power support between power transmission lines when regulating the power flow of multiple interconnected power transmission lines using MTSNOP, and the parallel CMI provides reactive power to achieve reactive compensation of the balanced line, and the reactive compensation capacity of the parallel CMI is Q N ; The parallel CMI sub-module voltage and quantity are designed, including the number of parallel CMI sub-modules, the sub-resistance value of IGBT, the line phase voltage, the constraint of the number of each phase sub-module, and represented as: wherein M is the number of submodules per phase, The sub-module capacitor voltage rating is 6. The transformerless multi-terminal flexible interconnection device (MTFID) main loop parameter design method of claim 5, wherein: The parallel converter design also includes a parallel CMI capacitance design and a sub-module voltage and number design. The parallel CMI sub-module capacitance value design includes suppressing the voltage ripple of the capacitance by selecting the parallel CMI sub-module capacitance value, and constructing an average switching function of the output voltage of each sub-module, expressed as: where S c (t) is the average switching function of the output voltage of each sub-module, V p is the fundamental component of the parallel CMI output voltage, θ p is the phase of the parallel CMI output voltage; The capacitive current instantaneous value of the inflow sub-module is calculated and expressed as: wherein, i c (t) is the instantaneous value of the capacitor current flowing into the sub-module, i p (t) is the instantaneous value of the CMI line current, I p is the bridge arm current amplitude; The capacitive voltage instantaneous value of the inflow sub-module is calculated and expressed as: wherein v c (t) is the instantaneous value of the capacitor voltage of the inflow sub-module, C is the capacitor capacitance value of the parallel CMI sub-module; The parallel CMI sub-module capacitance value constraint is designed and expressed as: where ΔV c is the fluctuation of the capacitor voltage.

7. The transformerless multi-terminal flexible interconnection device (MTFID) main loop parameter design method of claim 6, wherein: The parallel converter design also includes a parallel CMI connected inductor design, which includes the operating characteristics of the CMI in steady state, the reactive power output in the ideal state, expressed as: wherein U S is the grid-side voltage, U C is the output voltage of the CMI, δ is the phase difference between the grid-side voltage and the output voltage of the CMI, L p is the CMI connecting inductance; If the constraint on the CMI connecting inductance is expressed in terms of the reactive power compensation capacity, it is given by: If the constraint on the CMI connecting inductance in case of three-phase voltage unbalance is expressed as: wherein, The three-phase unbalanced voltage is If the CMI connection inductance meets the filtering effect of the output current, the inductance unit value is set to 0.1, and the CMI connection inductance is represented as: The CMI connecting inductance design is based on meeting the compensation demand of reactive power under the rated capacity, the stable operation under the grid voltage imbalance condition, and the filtering effect on the output current.

8. A system using the transformerless multi-terminal flexible interconnection device main loop parameter design method according to any one of claims 1 to 7, characterized in that: The method comprises an automatic distribution module, a series converter module, and a parallel converter module. The automatic distribution module is used for dividing the MTSNOP main circuit parameter design into series converter design and parallel converter design. The series converter module is used for the parameter design of the voltage and number of PFCM and PBCM sub-modules, the capacitor capacity of PFCM and PBCM sub-modules, the bridge arm inductance of PFCM and PBCM, and the AC side equivalent filter inductance. The parallel converter module is used for the parameter design of the capacity of parallel CMI, the sub-module voltage and number, the sub-module capacitor capacity of parallel CMI, and the connecting inductance of parallel CMI. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8 when the computer program is executed by the processor. The processor executes the computer program to realize the steps of the main circuit parameter design method of the transformerless multi-terminal flexible interconnection device according to any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to realize the steps of the main circuit parameter design method of the transformerless multi-terminal flexible interconnection device according to any one of claims 1 to 7.

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