Multi-target data writing method

Abstract

A multi-target data writing method, which is based on an interface system. The interface system comprises a main controller, an interface module, and a plurality of functional modules, wherein the main controller is connected to the interface module, and the interface module is connected to the plurality of functional modules. In a data transmission method based on the interface system, a single I2C interface or a single SPI interface can transmit data in parallel to multiple target devices, and the selection of the multiple target devices can be configured.

Description

Multi-target data writing method TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to an interface system and a multi-target data writing method. BACKGROUND

[0002] I2C bus is a simple, bidirectional serial bus developed by Philips Company. The device connected by I2C bus is called I2C device, and the interface of I2C device accessing I2C bus is called I2C interface. I2C bus has become a de facto international standard, and the design specification of I2C bus and its protocol (referred to as standard I2C specification) is generally described in the document THE I2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000.

[0003] I2C interface includes I2C clock line (generally named SCL) and I2C data line (generally named SDA), I2C master controller connects one or more I2C slave devices of I2C slave device through I2C clock line and I2C data line, I2C master controller drives I2C clock line, initiates I2C write operation or read operation, and judges whether the data is sent successfully through response bit, and the bit error on the bus caused by signal interference cannot be recognized by I2C slave device.

[0004] The electrical characteristics of I2C interface require that the devices participating in I2C communication are "common ground", otherwise it cannot be transmitted, so I2C communication is not suitable for application scenarios with long transmission distance or large signal interference. In order to solve this problem, a device for forwarding I2C data is usually added on the I2C bus, but introducing the forwarding device also has new problems:

[0005] The communication mechanism of I2C requires that I2C slave device replies a response bit for each byte sent by I2C master controller, and the response bit level is low for I2C ACK and high for I2C NAK; in the prior art, each byte sent by I2C master controller is transmitted to the module (referred to as functional module in the present application) which finally receives data, and the response bit is generated by the functional module and returned to the I2C master controller, the response speed of the transmission system is slow, which leads to slow transmission speed.

[0006] SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus that uses only four pins on a chip, saving pins and simplifying PCB layout. SPI typically has four signal lines: SPI_CSN, SPI_CK, SPI_MOSI, and SPI_MISO. The SPI master controller connects to the SPI interface module via these four signal lines; the SPI master controller is the SPI master, and the SPI interface module is the SPI slave. The SPI master controller drives the SPI_CSN, SPI_CK, and SPI_MOSI signal lines, which are received by the SPI interface module. The SPI interface module drives the SPI_MISO signal line, which is received by the SPI master controller. The SPI interface module receives and samples data driven by the SPI master controller on the SPI_MOSI signal line at the rising or falling edge of the SPI_CK signal line. Similarly, the SPI master controller receives and samples data driven by the SPI interface module on the SPI_MISO signal line at the rising or falling edge of the SPI_CK signal line. In the SPI protocol, the SPI master controller drives the SPI_CK signal line and generates a clock edge on it. Both the SPI master controller and the SPI interface module sample data on the SPI_MISO and SPI_MOSI signal lines at the rising or falling edge of the clock on the SPI_CK signal line, enabling bidirectional data transmission between them. The SPI_CSN signal line is a selection signal; in the SPI protocol, data transmission only occurs when the SPI_CSN signal line is low. One SPI master controller can connect to multiple SPI interface modules, meaning one SPI master device can connect to multiple SPI slave devices. The SPI master controller and multiple SPI interface modules share the SPI_CK, SPI_MOSI, and SPI_MISO signal lines. However, each SPI interface module has an independent SPI_CSN signal line input. When the SPI_CSN signal line of an SPI interface module is high, this SPI interface module does not drive the SPI_MISO signal line (the driver connected to the SPI_MISO signal line outputs a Hi-Z state). An SPI interface module only drives the SPI_MISO signal line when its SPI_CSN signal line is low. When one SPI master controller connects to multiple SPI interface modules, at any given time, only one SPI interface module's SPI_CSN signal line is low, thus avoiding conflicts caused by multiple SPI interface modules simultaneously driving the SPI_MISO signal line.

[0007] When one SPI master controller is connected with one SPI interface module, the SPI interface module can drive the SPI_MISO signal line at any time without causing conflict, in this case, the SPI master controller and the SPI interface module can have no SPI_CSN signal line, that is, when one SPI master controller is connected with one SPI interface module, the SPI master controller and the SPI interface module can be connected only through the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line.

[0008] When data transmission of a long distance is performed, a mode based on sending a command package and then receiving a feedback package is generally performed, the feedback package contains state information of the executed command, and when it is a read command, the feedback package can also contain read data. In the existing SPI protocol, data bidirectional transmission between the SPI master controller and the SPI interface module is realized by sampling the data on the SPI_MISO signal line and the SPI_MOSI signal line on the rising edge or the falling edge of the clock on the SPI_CK signal line, but this data transmission can be considered as a kind of data stream transmission, and is not suitable for data transmission of a long distance.

[0009] In the prior art, whether it is the existing I2C protocol or the SPI protocol, one I2C interface or one SPI interface generally supports data transmission to a single target device at a single time. The I2C has the ability of broadcasting, but the broadcasting is directed to all the devices connected on the I2C bus, and the target device cannot be selected. At present, a method for parallel data transmission of a single I2C interface or a single SPI interface to multiple target devices is needed in the market, and the selection of the multiple target devices can be configured. SUMMARY

[0010] The present application provides a method for parallel data transmission of a single I2C interface or a single SPI interface to multiple target devices, and the selection of the multiple target devices can be configured, and one purpose of the present application is to provide a multiple-target data writing method based on an interface system, the interface system comprising a master controller, an interface module and multiple functional modules, the master controller being connected with the interface module, and the interface module being connected with the multiple functional modules, characterized in that,

[0011] The master controller sends a write command package to the interface module, and when the interface module receives the write command package, the interface module sends the write command package to one or more functional modules,

[0012] The functional module receiving the write command package executes one or more write commands contained in the write command package, and returns a write state package to the interface module, comprising:

[0013] When the execution result of each write command contained in the write command package is success, the function module returns a write status package with success status information to the interface module,

[0014] When the execution result of at least one write command contained in the write command package is failure, the function module returns a write status package with failure status information to the interface module,

[0015] The interface module receives the write status package from each function module from which the write command package is sent, and returns the status information of the write status package to the host controller.

[0016] Preferably, the host controller is an I2C host controller, and the interface module is an I2C interface module,

[0017] The I2C host controller connects the I2C interface module through an I2C clock line and an I2C data line, initiates an I2C write operation to send a write command package to the I2C interface module, and the I2C interface module pulls down the I2C clock line after receiving the write command package, and sends the write command package to one or more function modules,

[0018] The function module receiving the write command package returns the write status package to the I2C interface module, and the I2C interface module receives the write status package from each function module from which the write command package is sent, and returns the status information of the write status package to the I2C host controller.

[0019] Further, when the I2C interface module receives the write status package from each function module from which the write command package is sent, and the status information of each write status package is success, the I2C interface module stops pulling down the I2C clock line, and returns an I2C ACK to the I2C host controller,

[0020] When the I2C interface module receives the write status package from each function module from which the write command package is sent, and the status information of at least one write status package is failure, the I2C interface module stops pulling down the I2C clock line, and returns an I2C NAK to the I2C host controller.

[0021] Further, when the I2C interface module receives the write status package from each function module from which the write command package is sent, the I2C interface module stops pulling down the I2C clock line, and returns an I2C ACK or an I2C NAK to the I2C host controller,

[0022] If the subsequent I2C operation initiated by the I2C host controller is an I2C read operation, the I2C interface module returns the status information of the write status package to the I2C host controller.

[0023] Preferably, the main controller is an I2C master controller, and the interface module is an I2C interface module,

[0024] The I2C master controller connects the I2C interface module through an I2C clock line and an I2C data line, and initiates an I2C write operation to send the write command package to the I2C interface module. After receiving the write command package, the I2C interface module sends the write command package to one or more functional modules,

[0025] The functional module receiving the write command package returns the write status package to the I2C interface module,

[0026] After the I2C interface module receives the write command package,

[0027] If the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, and the I2C interface module receives the write status package from each functional module from which the write command package is sent, the I2C interface module returns the status information of the write status package to the I2C master controller.

[0028] Further, the subsequent I2C operation initiated by the I2C master controller is an I2C write operation,

[0029] If the I2C interface module receives the write status package from each functional module from which the write command package is sent, and the status information of each write status package is successful, the I2C interface module receives the subsequent I2C write operation initiated by the I2C master controller,

[0030] If the I2C interface module receives the write status package from each functional module from which the write command package is sent, and the status information of at least one write status package is failed, the I2C interface module returns an I2C NAK to the I2C master controller.

[0031] Preferably, the main controller is an SPI master controller, and the interface module is an SPI interface module. The SPI master controller connects the SPI interface module through an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MISO signal line,

[0032] The SPI master controller generates a clock edge on the SPI_CK signal line, and sends the write command package to the SPI interface module through the SPI_MOSI signal line. The write command package starts with a first identifier. After receiving the write command package from the SPI_MOSI, the SPI interface module sends the write command package to one or more functional modules,

[0033] The function module receiving the write command package returns the write status package to the SPI interface module, the SPI interface module receives the write status package from each function module sending the write command package, and returns the state information of the write status package to the SPI master controller, including:

[0034] After the SPI interface module receives the write status package from each function module sending the write command package, when the SPI master controller generates a clock edge on the SPI_CK, the SPI interface module sends a write feedback package to the SPI master controller through the SPI_MISO signal line, the write feedback package starts with a second identifier, and the write feedback package contains the state information contained in the write status package.

[0035] Further, the SPI master controller generates a clock edge on the SPI_CK signal line, and reads the write feedback package through the SPI_MISO signal line,

[0036] When the SPI interface module does not receive the write status package from each function module sending the write command package, the SPI interface module sends data that cannot be identified as the write feedback package to the SPI master controller through the SPI_MISO signal line.

[0037] Further, the SPI master controller generates a clock edge on the SPI_CK signal line, and sends the write command package to the SPI interface module through the SPI_MOSI signal line,

[0038] Then the SPI master controller generates a clock edge on the SPI_CK signal line, and reads the write feedback package through the SPI_MISO signal line, after the SPI interface module sends the write feedback package through the SPI_MISO signal line, it can continue to receive subsequent command packages.

[0039] Further, the write feedback package is divided into a write success feedback package and a write failure feedback package,

[0040] The SPI master controller generates a clock edge on the SPI_CK signal line, and reads the write feedback package through the SPI_MISO signal line,

[0041] When the SPI interface module receives the write status package from each function module sending the write command package, and the state information contained in each write status package is success, the SPI interface module sends the write success feedback package through the SPI_MISO signal line, the write success feedback package starts with a third identifier,

[0042] When the SPI interface module receives the write status package from each of the functional modules from which it sends the write command package and at least one write status package contains the status information of failure, the SPI interface module sends the write failure feedback package through the SPI_MISO signal line, and the write failure feedback package starts with the fourth identifier.

[0043] Preferably, the functional module receiving the write command package is connected with a remote I2C slave device, and after the functional module receiving the write command package receives the write command package from the interface module, the functional module executes one or more write commands contained in the write command package, and the method for executing each write command is:

[0044] The functional module sends I2C START to the remote I2C slave device, then the functional module sends a remote I2C address byte to the remote I2C slave device, and then the functional module sends a write command to the remote I2C slave device,

[0045] For each byte sent by the functional module to the remote I2C slave device, the functional module receives an I2C response bit sent by the remote I2C slave device and determines the execution result of the write command.

[0046] Further, the functional module receiving the write command package contains a remote I2C address register, and the I2C address contained in the remote I2C address byte sent by the functional module receiving the write command package to the remote I2C slave device is the remote I2C address stored in the remote I2C address register.

[0047] Further, the write command package contains a remote I2C address, and the I2C address contained in the remote I2C address byte sent by the functional module receiving the write command package to the remote I2C slave device is the remote I2C address contained in the write command package.

[0048] Further, the functional module receiving the write command package contains a remote I2C address register, and the functional module receiving the write command package further contains a remote I2C address selection module, and the I2C address contained in the remote I2C address byte sent by the functional module receiving the write command package to the remote I2C slave device is selected according to the indication of the remote I2C address selection module, from the remote I2C address stored in the remote I2C address register or from the remote I2C address contained in the write command package.

[0049] Another object of the present application is to provide a multi-target data writing method based on an interface system, wherein the interface system comprises an I2C master controller, an I2C interface module, and a plurality of functional modules, the I2C master controller is connected with the I2C interface module, and the I2C interface module is connected with the plurality of functional modules, and the method comprises the following steps:

[0050] The I2C master controller initiates an I2C write operation to send a write command package to the I2C interface module, and then the I2C master controller initiates a subsequent I2C read operation to read the state information,

[0051] The I2C interface module pulls down the I2C clock line after receiving the address byte of the subsequent I2C read operation, and sends the received write command package to one or more functional modules,

[0052] The functional module receiving the write command package executes one or more write commands contained in the write command package, and returns a write state package to the I2C interface module, including:

[0053] When the execution result of each write command contained in the write command package is successful, the functional module returns a write state package with successful state information to the I2C interface module,

[0054] When the execution result of at least one write command contained in the write command package is failed, the functional module returns a write state package with failed state information to the I2C interface module,

[0055] After the I2C interface module receives the write state package from each functional module from which the write command package is sent, the I2C interface module stops pulling down the I2C clock line, and returns the state information of the write state package to the I2C master controller.

[0056] The application provides a multi-target data writing method, which has fast data transmission speed, and a single I2C interface or a single SPI interface can perform parallel data transmission on multiple target devices, and the selection of the multiple target devices can be configured. BRIEF DESCRIPTION OF DRAWINGS

[0057] In order to more clearly illustrate the specific embodiments of the application or the technical solutions in the prior art, the drawings needed in the specific embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0058] Fig. 1 schematically shows the structure block diagram of an interface system of the application.

[0059] Fig. 2 shows the data structure diagram of a write command package of the application.

[0060] Fig. 3 shows the structure block diagram of an interface system of the application, in which the master controller is an I2C master controller, and the interface module is an I2C interface module.

[0061] Fig. 4 shows the timing diagram of an I2C write operation of the application.

[0062] Figure 5 shows a timing diagram of an I2C read operation of the present application.

[0063] Figure 6 shows a timing diagram of an I2C continuous read-write operation of the present application.

[0064] Figure 7 shows a timing diagram of sending a write command packet (or a read command packet) to initiate an I2C write operation of the present application.

[0065] Figure 8 shows a timing diagram of sending a write command packet to initiate an I2C write operation and a status information of a write status packet being success, and a timing diagram of sending a write command packet to initiate an I2C write operation and a status information of a write status packet being failure, in an embodiment of the present application.

[0066] Figure 9 shows a timing diagram of sending a write command packet to initiate an I2C write operation and a subsequent I2C operation being an I2C read operation, in an embodiment of the present application.

[0067] Figure 10 shows a timing diagram of sending a write command packet to initiate an I2C write operation and a subsequent I2C operation being an I2C read operation, in another embodiment of the present application.

[0068] Figure 11 shows a timing diagram of sending a write command packet to initiate an I2C write operation and a status information of a write status packet being success, in another embodiment of the present application.

[0069] Figure 12 shows a timing diagram of sending a write command packet to initiate an I2C write operation and a status information of a write status packet being failure, in another embodiment of the present application.

[0070] Figure 13 shows a structure block diagram of an interface system of the present application, in which a master controller is a SPI master controller and an interface module is a SPI interface module.

[0071] Figure 14 shows a data structure of a write command packet when a master controller is a SPI master controller and an interface module is a SPI interface module of the present application.

[0072] Figure 15 shows a timing diagram of a first embodiment of SPI data write of the present application.

[0073] Figure 16 shows a timing diagram of a second embodiment of SPI data write of the present application.

[0074] Figure 17 shows a timing diagram of a third embodiment of SPI data write of the present application.

[0075] Figure 18 shows a timing diagram of a fourth embodiment of SPI data write of the present application.

[0076] Figure 19 shows a timing diagram of a fifth embodiment of SPI data write of the present application.

[0077] Figure 20 shows a structure block diagram of a functional module of an interface system of the present application, which is connected to a remote I2C slave device.

[0078] Figure 21 shows a diagram of a write status packet with a success status returned by the function module to the interface module.

[0079] Figure 22 shows a write status packet with a failure status returned by the function module to the interface module in one embodiment of the present application.

[0080] Figure 23 shows a write status packet with a failure status returned by the function module to the interface module in another embodiment of the present application.

[0081] The meanings of the text labels in the above figures are as follows: 100: main controller; 100a: I2C main controller; 100b: SPI main controller; 200: interface module; 200a: I2C interface module; 200b: SPI interface module; SDA: I2C data line; SCL: I2C clock line; S: indicates I2C START signal, and the corresponding I2C bus state is that SDA appears a jump from high level to low level when SCL is high; P: indicates I2C STOP signal, and the corresponding I2C bus state is that SDA appears a jump from low level to high level when SCL is high; Sr: the corresponding I2C bus state is the same as S; Sr / P: the corresponding I2C bus state is Sr or P; ADDR: I2C address; R / W: indicates read-write operation indication bit, and when the bit is R, it indicates that the current is I2C read operation, and when the bit is W, it indicates that the current is I2C write operation; R: indicates read operation indication bit, and the corresponding I2C bus state is that SDA is high during SCL is high; W: indicates write operation indication bit, and the corresponding I2C bus state is that SDA is low during SCL is high; BYTE: write operation data or read operation data, which is usually a multi-byte sequence, and the content in the bracket behind the byte indicates the serial number of the byte in the sequence, a write command package or a read command package is sent through the write operation data, read data or status information is read through the read operation data, and the byte with a smaller serial number value is sent first; A: indicates I2C ACK, and the corresponding I2C bus state is that SDA is always low during SCL is high; N: indicates I2C NAK, and the corresponding I2C bus state is that SDA is always high during SCL is high; STATUS: byte containing status information and sequence of I2C ACK / I2C NAK between bytes; A / N: the corresponding I2C bus state is that SDA is always high or always low during SCL is high; HOLD: SCL is a continuous low level; IDLE: the corresponding I2C bus state includes the following two possibilities: (1) SCL and SDA are both high; (2) SCL and SDA can appear other level states, but the combination of these level states does not appear a legal I2C operation, and SCL and SDA are both high when IDLE is about to end; SPI_CK: SPI_CK signal line; SPI_MOSI: SPI_MOSI signal line; SPI_MISO: SPI_MISO signal line; SPI_CSN: SPI_CSN signal line. DETAILED DESCRIPTION

[0082] In order to make the above and other features and advantages of the present application more comprehensible, the present application will be further described below with reference to the drawings. It should be understood that the specific embodiments given herein are by way of example only and are not meant to be limiting.

[0083] As shown in Fig. 1, according to an embodiment of the present application, an interface system is provided, characterized in that the interface system comprises a main controller 100, an interface module 200, and a plurality of function modules 300. The main controller 100 is connected to the interface module 200, the interface module 200 is connected to the plurality of function modules 300, and the function modules 300 are numbered from 1 to N.

[0084] According to an embodiment of the present application, a multi-target data writing method is provided, comprising:

[0085] The main controller 100 sends a write command package to the interface module 200, and the interface module 200 sends the write command package to one or more function modules 300 after receiving the write command package.

[0086] As shown in Fig. 2, the write command package of the present application comprises one or more write commands, and an exemplary write command package comprises write command 1, write command 2, …, and write command N.

[0087] The function module 300 receiving the write command package executes one or more write commands contained in the write command package and returns a write status package with status information to the interface module 200, comprising:

[0088] When the execution result of each write command contained in the write command package is successful, the function module 300 returns a write status package with successful status information to the interface module 200.

[0089] When the execution result of at least one write command contained in the write command package is failed, the function module 300 returns a write status package with failed status information to the interface module 200.

[0090] The interface module 200 receives the write status package from each function module 300 from which the write command package is sent, and returns the status information of the write status package to the main controller 100.

[0091] In one embodiment, the function module 300 receiving the write command package receives the write command package and executes one or more write commands contained in the write command package, when the execution result of a write command is failed, the function module 300 stops executing subsequent write commands, and the function module 300 returns a write status package with failed status information to the interface module 200.

[0092] When the interface module 200 receives the write command package, the interface module 200 sends the write command package to one or more functional modules 300, the target functional module 300 to which the interface module 200 sends the write command package can be configured, in an embodiment, the host controller 100 can send target functional module configuration information before sending the write command package, and the interface module 200 sends the write command package to one or more target functional modules 300 indicated by the target functional module configuration information according to the target functional module configuration information, in another embodiment, the host controller 100 can also send the target functional module configuration information to the interface module 200 in the write command package, and the interface module 200 sends the write command package to one or more target functional modules 300 indicated by the target functional module configuration information according to the target functional module configuration information after receiving the write command package.

[0093] The configuration of the target functional module can be dynamic, that is, the target functional module configuration information can be selected and modified before sending the write command package, when the target functional module configuration information is included in the write command package, the target functional module configuration information in different write command packages can be different, and the configuration of the target functional module can also be static, that is, the target functional module configuration information can be pre-set and not modified during system operation. The present application does not limit the configuration means or method of the target functional module, and any configuration means or method is within the protection scope of the present application, and the present application also does not limit whether the configuration of the target functional module is dynamic or static.

[0094] In the present application, the number of target functional modules indicated by the target functional module configuration information can be equal to or less than the number of functional modules 300 connected to the interface module 200, that is, the target functional modules indicated by the target functional module configuration information can be all the functional modules 300 connected to the interface module 200, or can be a subset of all the functional modules 300 connected to the interface module 200.

[0095] As shown in FIG. 3, in an embodiment, the host controller 100 is an I2C host controller 100a, and the interface module 200 is an I2C interface module 200a.

[0096] The I2C host controller 100a is connected to the I2C interface module 200a through an I2C clock line (SCL) and an I2C data line (SDA), the I2C host controller 100a initiates an I2C write operation to send a write command package to the I2C interface module 200a, and the I2C interface module 200a pulls down the I2C clock line (SCL) level after receiving the write command package, and sends the write command package to one or more functional modules 300.

[0097] The function module 300 receiving the write command package executes one or more write commands contained in the write command package, and the function module 300 receiving the write command package returns a write status package to the I2C interface module 200a, the I2C interface module 200a receives the write status package from each function module 300 sending the write command package, and returns the status information of the write status package to the I2C master controller 100a, including:

[0098] When the I2C interface module 200a receives the write status package from each function module 300 sending the write command package and the status information of each write status package is success, the I2C interface module 200a stops pulling down the I2C clock line (SCL) level, and returns I2C ACK to the I2C master controller 100a.

[0099] When the I2C interface module 200a receives the write status package from each function module 300 sending the write command package and the status information of at least one write status package is failure, the I2C interface module 200a stops pulling down the I2C clock line (SCL) level, and returns I2C NAK to the I2C master controller 100a.

[0100] As shown in FIG. 4, the I2C write operation contains a write address byte and one or more write operation data bytes (BYTE(1), …, BYTE(N) with shading), the write address byte is the first transmitted byte, and the write address byte includes an I2C address (ADDR) and a write operation indication bit (W). According to the standard I2C specification, the write operation indication bit (W) is low.

[0101] In this embodiment, the write address byte and the write operation data byte are both 8 bits, wherein the write address byte contains 7 bits of the I2C address (ADDR) and 1 bit of the write operation indication bit (W). The present application does not limit the number of bits of the write address byte and the write operation data byte, and in other embodiments, the write address byte and the write operation data byte can be other numbers of bits.

[0102] When the I2C master controller 100a initiates the I2C write operation, the I2C master controller 100a first drives the I2C clock line (SCL) and the I2C data line (SDA) according to the standard I2C specification to generate an I2C START signal (S), and then transmits the write address byte. After receiving the write address byte, the I2C interface module 200a drives the I2C data line (SDA) to generate a response bit. According to the standard I2C specification, the response bit can be I2C ACK (I2C data line level low) or I2C NAK (I2C data line level high).

[0103] When the response bit of the write address byte is I2C ACK, the I2C master controller 100a can send one or more write operation data bytes, and the I2C interface module 200a drives the I2C data line (SDA) to generate a response bit after receiving each write operation data byte, the response bit of the write operation data byte can be I2C ACK (the I2C data line is low) or I2C NAK (the I2C data line is high).

[0104] According to the standard I2C specification, when sending the write address byte and one or more write operation data bytes, the I2C master controller 100a sends the number of bits contained in the write address byte and the write operation data byte by driving the I2C data line (SDA), and for each bit contained in the write address byte and the write operation data byte, the I2C master controller 100a drives the I2C clock line (SCL) to generate a clock pulse.

[0105] According to the standard I2C specification, the I2C master controller 100a also drives the I2C clock line (SCL) to generate a clock pulse corresponding to the response bit of the write address byte and the response bit of the write operation data byte. The I2C master controller 100a ends the current write operation by sending the I2C STOP signal (P) or the I2C START signal (S) defined in the standard I2C specification.

[0106] As shown in FIG. 5, the I2C read operation includes a read address byte and one or more read operation data bytes (BYTE(1), …, BYTE(N), no shading), the read address byte is the first byte sent by the I2C master controller 100a, and the one or more read operation data bytes are sent by the I2C interface module 200a, the read address byte contains an I2C address (ADDR) and a read operation indication bit (R), and according to the standard I2C specification, the read operation indication bit (R) is high.

[0107] In this embodiment, the read address byte and the read operation data byte are both 8 bits, and the read address byte contains a 7-bit I2C address (ADDR) and a 1-bit read operation indication bit (R). The present application does not limit the number of bits of the read address byte and the read operation data byte, and in other embodiments, the read address byte and the read operation data byte can have other bit numbers.

[0108] When the I2C master controller 100a initiates an I2C read operation, the I2C master controller 100a first drives the I2C clock line and the I2C data line according to the standard I2C specification to generate an I2C START signal (S), and then sends a read address byte. After receiving the read address byte, the I2C interface module 200a drives the I2C data line to generate a response bit. According to the standard I2C specification, the response bit can be an I2C ACK (the I2C data line is at low level) or an I2C NAK (the I2C data line is at high level).

[0109] When the response bit of the read address byte is an I2C ACK, the I2C interface module 200a can return one or more read operation data bytes by driving the I2C data line. After receiving each read operation data byte, the I2C master controller 100a drives the I2C data line to generate a response bit. The response bit of the read operation data byte can be an I2C ACK (the I2C data line is at low level) or an I2C NAK (the I2C data line is at high level).

[0110] According to the standard I2C specification, when the I2C master controller 100a sends a read address byte and the I2C interface module 200a returns one or more read operation data bytes, the I2C master controller 100a sends the number of bits contained in the read address byte by driving the I2C data line, and the I2C interface module 200a returns the number of bits contained in the read operation data byte by driving the I2C data line. For each bit contained in the read address byte and the read operation data byte, the I2C master controller 100a drives the I2C clock line to generate a clock pulse.

[0111] According to the standard I2C specification, for the response bit of the read address byte and the response bit of the read operation data byte, the I2C master controller 100a also drives the I2C clock line to generate a clock pulse. The I2C master controller 100a ends the current read operation by sending an I2C STOP signal (P) or an I2C START signal (S) defined in the standard I2C specification.

[0112] An I2C write operation or an I2C read operation cycle is started by an I2C START signal (S), but there are two ways to end it. The first way is to end with an I2C STOP signal (P), and the timing is shown in FIG. 4 and FIG. 5.

[0113] The second way is to generate a new I2C START signal (S) to enter the next I2C write operation or I2C read operation, and the timing is shown in FIG. 6. The dashed line (such lines in other figures) between the response bit (A / N) and the I2C START signal (Sr) in FIG. 6 is because the timing diagram is too long to be described in the same row, so it is split into multiple rows, indicating that there is a connection relationship between the two timing diagrams.

[0114] The end of the method for multi-target data writing of the present application is not affected by any of the above ending manners. For the convenience of description, the end of an I2C operation (I2C write operation or I2C read operation) is described in the manner of I2C STOP signal (P) in this embodiment.

[0115] The write command packet of the present application is sent through write operation data bytes (BYTE(1), …, BYTE(N), with shadow), as shown in FIG. 2, four embodiments of the write command packet are given:

[0116] The write command packet can only contain write command 1, write command 2, …, write command N.

[0117] The write command packet can also contain write command packet length field and write command 1, write command 2, …, write command N.

[0118] The write command packet can also contain remote I2C address and write command 1, write command 2, …, write command N.

[0119] The write command packet can also contain write command packet length field, remote I2C address and write command 1, write command 2, …, write command N.

[0120] The write command packet can also contain target function module configuration information (not shown in FIG. 2) for indicating one or more target function modules 300.

[0121] It should be noted that the present application does not limit the format of the write command packet, that is, the format of the write command packet in the present application is not limited to the four embodiments of the write command packet shown in FIG. 2, and the I2C master controller 100a and the I2C interface module 200a can agree on other write command packet formats.

[0122] The write command packet of the present application is used to distinguish the read command packet, the write command packet is used to realize data writing, and the read command packet is used to realize data reading, and the present application does not limit the method of reading data through the read command packet.

[0123] For example, when the I2C master controller 100a initiates the write command packet, the I2C master controller 100a initiates the I2C write operation to send the write address byte and one or more write operation data bytes (BYTE(1), …, BYTE(N), with shadow) containing the write command packet to the I2C interface module 200a.

[0124] The I2C interface module 200a has a logic circuit of an I2C interface, and the I2C interface module 200a receives and responds to data from the I2C master controller 100a. The I2C interface module 200a and the I2C master controller 100a are interconnected through an I2C bus (an I2C clock line and an I2C data line), one I2C master controller 100a is connected with one or more I2C interface modules 200a, and each I2C interface module 200a has a unique I2C address (ADDR) on the I2C bus (the I2C clock line and the I2C data line) where the I2C interface module 200a is located. According to the standard I2C specification, each I2C write operation or I2C read operation except for I2C write broadcast is only for one I2C address (ADDR), and the I2C interface module 200a using other I2C addresses does not participate in the I2C write operation or I2C read operation.

[0125] As shown in FIG. 7, in a specific embodiment, the I2C interface module 200a has an I2C address 0x50 (corresponding to a write address byte 0xA0 or a binary value 1010000) with a length of 7 bits, and the I2C master controller 100a initiates an I2C write operation to sequentially write 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61, a total of 7 bytes of write operation data to the I2C interface module 200a, and the 7 bytes of write operation data contain a write command package. The 0xA0 byte corresponds to a write address byte, the high 7 bits of which correspond to the I2C address (ADDR) of the I2C interface module 200a, and the low 1 bit is a write operation indication bit (W), and the value of the write operation indication bit (W) is 0, indicating that the current is a write operation, and the value of the byte is a binary number 10100000, i.e., a hexadecimal number 0xA0.

[0126] In this example, the write command package format can be one of the four write command package embodiments shown in FIG. 2, or other write command package formats agreed between the I2C master controller 100a and the I2C interface module 200a.

[0127] In the present application, the I2C interface module 200a receives the write operation data received by the I2C interface module 200a to contain a complete write command package. As shown in the embodiment of FIG. 7, the 7 bytes of write operation data 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61 contain a complete write command package, so

[0128] When the I2C interface module 200a receives the last bit of the 0x61 byte, the I2C interface module 200a receives the write command package.

[0129] As shown in FIG. 2, the write command package can contain a write command package length field, and the I2C interface module 200a can determine whether the received write operation data contains a complete write command package based on the write command package length field (or part of the write command package length field) according to an agreement between the I2C interface module 200a and the I2C master controller 100a. As shown in FIG. 2, the write command package can also not contain a write command package length field. In this case, the I2C interface module 200a can determine whether the received write operation data contains a complete write command package according to an agreement between the I2C interface module 200a and the I2C master controller 100a (which is not based on the write command package length field).

[0130] In the embodiment shown in FIG. 7, the I2C interface module 200a receives the last bit of the 0x61 byte, receives the write command package, and then pulls down the I2C clock line to the I2C bus to the HOLD state (a sustained low level state). The I2C interface module 200a sends the write command package to one or more functional modules 300. The functional module 300 that receives the write command package receives the write command package and executes one or more write commands contained in the write command package, i.e., write command 1, write command 2, …, write command N, and then returns a write status package to the I2C interface module 200a, including:

[0131] When the execution result of each write command contained in the write command package is successful, the functional module 300 returns a write status package with successful status information to the I2C interface module 200a;

[0132] When the execution result of at least one write command contained in the write command package is unsuccessful, the functional module 300 returns a write status package with unsuccessful status information to the I2C interface module 200a.

[0133] In the present application, the I2C interface module 200a can modify, add, or delete the contents in the write command package when sending the write command package to the functional module 300, and the present application does not limit or regulate this.

[0134] According to the embodiment of the present application, when the I2C interface module 200a receives a write status package from each functional module 300 from which the write command package is sent and the status information of each write status package is successful, the I2C interface module 200a stops pulling down the I2C clock line and returns I2C ACK to the I2C master controller 100a.

[0135] When the I2C interface module 200a receives a write status package from each functional module 300 from which the write command package is sent and the status information of at least one write status package is unsuccessful, the I2C interface module 200a stops pulling down the I2C clock line and returns I2C NAK to the I2C master controller 100a.

[0136] The subsequent I2C operation referred to in the present application is relative to the I2C operation before it, which can be an I2C write operation or an I2C read operation.

[0137] As shown in Fig. 8, the case when the I2C interface module 200a receives the write status package from each functional module 300 from which the write command package is sent and the status information of each write status package is success, and the case when the I2C interface module 200a receives the write status package from each functional module 300 from which the write command package is sent and the status information of at least one write status package is failure, are described respectively as examples.

[0138] The I2C master controller 100a initiates an I2C operation (I2C write operation) with serial number m (m is a natural number), and the I2C operation initiated by the I2C master controller 100a with serial number m+1 is a subsequent I2C operation (relative to the I2C operation with serial number m).

[0139] In one embodiment shown in Fig. 8, the I2C master controller 100a sends the write command package through the I2C write operation with serial number m, and the I2C interface module 200a pulls down the I2C clock line after receiving the write command package (after receiving BYTE(N)).

[0140] At the first time, the I2C interface module 200a receives the write status package from each functional module 300 from which the write command package is sent and the status information of each write status package is success, and the I2C interface module 200a stops pulling down the I2C clock line and terminates the HOLD state (terminates the persistent low level state).

[0141] At the second time, the I2C interface module 200a returns the I2C ACK to the I2C master controller 100a, and the I2C master controller 100a terminates the I2C operation (I2C write operation) with serial number m and initiates the I2C operation (subsequent I2C operation) with serial number m+1, which is an I2C write operation or an I2C read operation.

[0142] After the I2C interface module 200a returns the I2C ACK in the I2C operation with the serial number m, it continues to receive the subsequent I2C operation initiated by the I2C master controller 100a (i.e. returns the I2C ACK after receiving the read address byte or the write address byte in the I2C operation with the serial number m+1 and continues the I2C operation with the serial number m+1), if the subsequent I2C operation is the I2C write operation, the I2C interface module 200a returns the I2C ACK after receiving the write address byte and continues to receive the write operation byte, if the subsequent I2C operation is the I2C read operation, the I2C interface module 200a returns the I2C ACK after receiving the read address byte and continues to return the status information (STATUS) of the write status packet (the part of the subsequent I2C operation after the read address byte or the write address byte is not shown in Fig. 8).

[0143] In another embodiment shown in Fig. 8, the I2C master controller 100a sends the write command packet through the I2C write operation with the serial number m, and the I2C interface module 200a pulls down the I2C clock line after receiving the write command packet (after receiving the BYTE(N)).

[0144] At the first time, the I2C interface module 200a receives the write status packet from each functional module 300 which sends the write command packet and the status information of at least one write status packet is failure, the I2C interface module 200a stops pulling down the I2C clock line and terminates the HOLD state (terminates the continuous low level state).

[0145] At the second time, the I2C interface module 200a returns the I2C NAK to the I2C master controller 100a, and the I2C master controller 100a terminates the I2C operation (the I2C write operation) with the serial number m.

[0146] If the I2C master controller 100a initiates a subsequent I2C operation after the I2C interface module 200a returns the I2C NAK in the I2C operation with the serial number m, and the subsequent I2C operation is an I2C write operation, the I2C interface module 200a returns the I2C NAK to the I2C master controller 100a after receiving the write address byte, so that the subsequent I2C operation (I2C write operation) is terminated. If the I2C master controller 100a initiates a subsequent I2C operation after the I2C interface module 200a returns the I2C NAK in the I2C operation with the serial number m, and the subsequent I2C operation is an I2C read operation, the I2C interface module 200a returns the I2C ACK to the I2C master controller 100a after receiving the read address byte, and continues to return the status information (STATUS) of the write status packet. After completing the subsequent I2C operation (I2C read operation), the I2C interface module 200a can continue to receive a further subsequent I2C operation initiated by the I2C master controller 100a (part of the subsequent I2C operation is not shown in FIG. 8).

[0147] In the present application, the status information (STATUS) can include success or failure information contained in the write status packet, or can include other information contained in the write status packet. In an embodiment, the status information (STATUS) can include success or failure information contained in each write status packet received by the I2C interface module 200a. After receiving the status information, the I2C master controller 100a can learn the execution of the write command packet by each functional module 300 receiving the write command packet, and can further perform subsequent processing according to the execution. As shown in the embodiment of FIG. 8, when the I2C interface module 200a receives the write status packet from each functional module 300 sending the write command packet, the I2C interface module 200a stops pulling down the I2C clock line, and returns the I2C ACK (when the status information of each write status packet is success) or the I2C NAK (when the status information of at least one write status packet is failure) to the I2C master controller 100a. If the I2C master controller 100a initiates a subsequent I2C operation after the I2C interface module 200a returns the I2C NAK in the I2C operation with the serial number m, and the subsequent I2C operation is an I2C read operation, the I2C interface module 200a returns the I2C ACK to the I2C master controller 100a after receiving the read address byte, and continues to return the status information (STATUS) of the write status packet.

[0148] As shown in the embodiment of Fig. 9, the I2C master controller 100a sends a write command package through an I2C write operation with serial number m, and the I2C interface module 200a pulls down the I2C clock line after receiving the write command package (after receiving the BYTE(N)), stops pulling down the I2C clock line after receiving the write status package from each functional module 300 which sends the write command package, and returns an I2C ACK or an I2C NAK to the I2C master controller 100a. In this case, the I2C master controller 100a and the I2C interface module 200a can agree on the specific meaning of the I2C ACK or the I2C NAK. After the I2C interface module 200a stops pulling down the I2C clock line and returns the I2C ACK or the I2C NAK to the I2C master controller 100a, if the I2C master controller 100a initiates a subsequent I2C operation and the subsequent I2C operation is an I2C write operation, the I2C interface module 200a returns an I2C NAK to the I2C master controller 100a after receiving a write address byte, so that the subsequent I2C operation (I2C write operation) is terminated. If the I2C master controller 100a initiates a subsequent I2C operation and the subsequent I2C operation is an I2C read operation, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a after receiving a read address byte, and continues to return the status information (STATUS) of the write status package. After completing the subsequent I2C operation (I2C read operation), the I2C interface module 200a can continue to receive a further subsequent I2C operation initiated by the I2C master controller 100a (part of the subsequent I2C operation which is an I2C write operation is not shown in Fig. 9).

[0149] According to an embodiment of the present application, the I2C master controller 100a connects the I2C interface module 200a through the I2C clock line and the I2C data line, the I2C master controller 100a initiates an I2C write operation to send a write command package to the I2C interface module 200a, and the I2C interface module 200a sends the write command package to one or more functional modules 300 after receiving the write command package.

[0150] The functional module 300 receiving the write command package executes one or more write commands contained in the write command package, i.e., write command 1, write command 2, …, write command N, and then returns a write status package with successful status information to the I2C interface module 200a.

[0151] When the execution result of each write command contained in the write command package is successful, the functional module 300 returns a write status package with successful status information to the I2C interface module 200a.

[0152] When the execution result of at least one write command in the write command package is failure, the function module 300 returns a write status package with the status information of failure to the I2C interface module 200a.

[0153] In the present application, when the I2C interface module 200a sends the write command package to the function module 300, the content in the write command package can be modified, added or deleted, which is not limited or regulated in the present application.

[0154] The function module 300 receiving the write command package returns a write status package to the I2C interface module 200a, and the I2C interface module 200a returns the status information of the write status package to the I2C master controller 100a, including:

[0155] After the I2C interface module 200a receives the write command package,

[0156] If the subsequent I2C operation initiated by the I2C master controller 100a is I2C read operation, and the I2C interface module 200a receives the write status package from each function module 300 from which the write command package is sent, the I2C interface module 200a returns the status information of the write status package to the I2C master controller 100a.

[0157] If the subsequent I2C operation initiated by the I2C master controller 100a is I2C write operation, and the I2C interface module 200a receives the write status package from each function module 300 from which the write command package is sent and the status information of each write status package is success, the I2C interface module 200a receives the subsequent I2C write operation initiated by the I2C master controller 100a;

[0158] If the subsequent I2C operation initiated by the I2C master controller 100a is I2C write operation, and the I2C interface module 200a receives the write status package from each function module 300 from which the write command package is sent and the status information of at least one write status package is failure, the I2C interface module 200a returns I2C NAK to the I2C master controller 100a.

[0159] As shown in FIG. 10, the I2C operation with the serial number m initiated by the I2C master controller 100a is I2C write operation, and the write command package is sent to the I2C interface module 200a. For the first N-1 write operation data bytes (BYTE(1), …, BYTE(N-1)), the I2C interface module 200a returns I2C ACK to the I2C master controller 100a after each write operation data byte is sent.

[0160] After the I2C interface module 200a receives the Nth write operation data byte (BYTE(N)), that is, after the I2C interface module 200a receives the complete write command package, the I2C interface module 200a can return an I2C ACK or an I2C NAK to the I2C master controller 100a, which is selected by an agreement between the I2C master controller 100a and the I2C interface module 200a. The I2C master controller 100a and the I2C interface module 200a can agree that, after the Nth write operation data byte (BYTE(N)), whether the I2C ACK or the I2C NAK indicates the successful reception of the Nth write operation data byte (that is, the complete write command package). In the following description of the present application, after the Nth write operation data byte (BYTE(N)), whether the I2C interface module 200a returns the I2C ACK or the I2C NAK to the I2C master controller 100a indicates the successful reception of the Nth write operation data byte (that is, the complete write command package).

[0161] After the I2C master controller 100a completes the sending of the Nth write operation data byte (BYTE(N)), whether the I2C interface module 200a returns the I2C ACK or the I2C NAK to the I2C master controller 100a, the I2C master controller 100a terminates the I2C operation (I2C write operation) with the serial number m and can select to initiate the I2C operation (subsequent I2C operation) with the serial number m+1.

[0162] When the I2C operation (subsequent I2C operation) with the serial number m+1 is an I2C read operation, if the I2C interface module 200a receives the write status package (the write status package corresponding to the I2C operation with the serial number m) from each functional module 300 from which the write command package is sent, after the I2C master controller 100a sends the read address byte, the I2C interface module 200a returns the I2C ACK to the I2C master controller 100a and returns the status information (STATUS) of the write status package.

[0163] As shown in FIGS. 11 and 12, the I2C operation (I2C write operation) with the serial number m initiated by the I2C master controller 100a sends the write command package to the I2C interface module 200a. For the first N-1 write operation data bytes (BYTE(1), …, BYTE(N-1)), after each write operation data byte is sent, the I2C interface module 200a returns the I2C ACK to the I2C master controller 100a.

[0164] After the I2C interface module 200a receives the Nth write operation data byte (BYTE(N)), i.e. after the I2C interface module 200a receives the complete write command package, the I2C interface module 200a can return an I2C ACK or an I2C NAK to the I2C master controller 100a.

[0165] After the I2C master controller 100a completes the transmission of the Nth write operation data byte (BYTE(N)), regardless of whether the I2C interface module 200a returns an I2C ACK or an I2C NAK to the I2C master controller 100a, the I2C master controller 100a terminates the I2C operation (I2C write operation) with sequence number m and can select to initiate an I2C operation (subsequent I2C operation) with sequence number m+1.

[0166] When the I2C operation (subsequent I2C operation) with sequence number m+1 is an I2C write operation, if the I2C interface module 200a receives a write status package (corresponding write status package in the process of the I2C operation with sequence number m) from each functional module 300 that transmits a write command package and the status information of each write status package is success, after the I2C master controller 100a transmits a write address byte, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a, and the I2C interface module 200a receives the write operation data byte transmitted by the I2C master controller 100a initiating the I2C operation (subsequent I2C operation / I2C write operation) with sequence number m+1, as shown in FIG. 11.

[0167] If the I2C interface module 200a receives a write status package (corresponding write status package in the process of the I2C operation with sequence number m) from each functional module 300 that transmits a write command package and the status information of at least one write status package is failure, after the I2C master controller 100a transmits a write address byte, the I2C interface module 200a returns an I2C NAK to the I2C master controller 100a, and the master controller 100a terminates the initiation of the I2C operation (subsequent I2C operation / I2C write operation) with sequence number m+1, as shown in FIG. 12.

[0168] As shown in FIG. 13, in one embodiment, the master controller 100 is an SPI master controller 100b, and the interface module 200 is an SPI interface module 200b. The SPI master controller 100b is connected to the SPI interface module 200b through an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MISO signal line.

[0169] The SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends a write command package to the SPI interface module 200b through the SPI_MOSI signal line, the write command package starts with a first identifier, and the SPI interface module 200b sends the write command package to one or more functional modules 300 after receiving the write command package from the SPI_MOSI.

[0170] The functional module 300 receiving the write command package executes one or more write commands contained in the write command package, i.e., write command 1, write command 2, …, write command N, and then returns a write status package to the SPI interface module 200b, including:

[0171] When the execution result of each write command contained in the write command package is successful, the functional module 300 returns a write status package with successful status information to the SPI interface module 200b;

[0172] When the execution result of at least one write command contained in the write command package is failed, the functional module 300 returns a write status package with failed status information to the SPI interface module 200b.

[0173] In the present application, the SPI interface module 200b can modify, add or delete the content in the write command package when sending the write command package to the functional module 300, and the present application does not limit or regulate this.

[0174] The functional module 300 receiving the write command package returns a write status package to the SPI interface module 200b, and the SPI interface module 200b receives the write status package from each functional module 300 sending the write command package, and returns the status information of the write status package to the SPI master controller 100b, including:

[0175] After the SPI interface module 200b receives the write status package from each functional module 300 sending the write command package, when the SPI master controller 100b generates a clock edge on the SPI_CK, the SPI interface module 200b sends a write feedback package to the SPI master controller 100b through the SPI_MISO signal line, the write feedback package starts with a second identifier, and the write feedback package contains the status information contained in the write status package.

[0176] As shown in the embodiment of FIG. 14, when the master controller 100 is the SPI master controller 100b and the interface module 200 is the SPI interface module 200b, the data structure of the write command package. The embodiment exemplarily gives four write command package embodiments:

[0177] The write command package can contain the first identifier and the write command 1, the write command 2, …, the write command N, and start with the first identifier.

[0178] The write command packet can also include the first identifier, a write command packet length field, the remote I2C address, write command 1, write command 2, …, and write command N, and starts with the first identifier.

[0179] The write command packet can also include the first identifier, a write command packet length field, the remote I2C address, write command 1, write command 2, …, and write command N, and starts with the first identifier.

[0180] The write command packet can also include the first identifier, a write command packet length field, the remote I2C address, write command 1, write command 2, …, and write command N, and starts with the first identifier.

[0181] The first identifier, the write command packet length field (if present), the remote I2C address (if present), write command 1, write command 2, …, and write command N included in the write command packet are composed of binary bit sequences, and the present application does not limit the length of the binary bit sequences of the first identifier, the write command packet length field (if present), the remote I2C address (if present), write command 1, write command 2, …, and write command N.

[0182] It should be noted that the present application does not limit the format of the write command packet, that is, the format of the write command packet in the present application is not limited to the four write command packet embodiments shown in FIG. 14. The SPI master controller 100b and the SPI interface module 200b can agree on other write command packet formats.

[0183] In the present application, the SPI interface module 200b receives the data received by the SPI interface module 200b from the SPI_MOSI signal line, and the data includes a complete write command packet. As shown in FIG. 14, the write command packet can include a write command packet length field, and the SPI interface module 200b can determine whether the received data includes a complete write command packet based on the write command packet length field (or part of the write command packet length field) according to the agreement between the SPI master controller 100b and the SPI interface module 200b. As shown in FIG. 14, the write command packet can also not include a write command packet length field. In this case, the SPI interface module 200b determines whether the received data includes a complete write command packet according to the agreement between the SPI master controller 100b and the SPI interface module 200b (which is not based on the write command packet length field).

[0184] The SPI master controller 100b drives the SPI_CK signal line, and the SPI master controller 100b samples the data on the SPI_MISO signal line through the clock rising edge or falling edge on the SPI_CK signal line. The SPI interface module 200b samples the data on the SPI_MOSI signal line through the clock rising edge or falling edge on the SPI_CK signal line, to realize bidirectional transmission of data between the SPI master controller 100b and the SPI interface module 200b.

[0185] The present application is not limited to sampling the data on the SPI_MISO signal line and the SPI_MOSI signal line at the rising edge of the clock on the SPI_CK signal line, in the embodiments described below, the data on the SPI_MISO signal line and the SPI_MOSI signal line is sampled at the rising edge of the clock on the SPI_CK signal line, i.e. the rising edge of the clock on the SPI_CK signal line is the sampling clock edge in the embodiments described below. In other embodiments of the present application, the data on the SPI_MISO signal line and the SPI_MOSI signal line can also be sampled at the falling edge of the clock on the SPI_CK signal line, i.e. the falling edge of the clock on the SPI_CK signal line is the sampling clock edge in these embodiments.

[0186] As shown in FIG. 15, the SPI master controller 100b generates a clock edge on the SPI_CK signal line while driving the SPI_MOSI signal line to send a write command packet to the SPI interface module 200b through the SPI_MOSI signal line, the write command packet contains N bytes, each byte is 8-bit binary data, the first byte is a first identifier, the 8-bit binary data of the first byte is represented by C 10 , C 11 ...C 17 , the Nth byte of the write command packet is the last byte of the write command packet, and the 8-bit binary data of the Nth byte of the write command packet is represented by C N0 , C N1 ...C N7 .

[0187] The SPI interface module 200b samples the data on the SPI_MOSI signal line at the rising edge of the clock on the SPI_CK signal line, and receives the write command packet from the SPI_MOSI signal line. When the SPI interface module 200b samples C N7 bit, the data received from the SPI_MOSI signal line contains a complete write command packet, and the SPI interface module 200b receives the write command packet.

[0188] After the SPI interface module 200b receives the write command packet from the SPI_MOSI signal line, the write command packet is sent to the functional module 300. In the present application, when the SPI interface module 200b sends the write command packet to the functional module 300, the content in the write command packet can be modified, added or deleted, and the present application does not limit or regulate this.

[0189] The functional module 300 receiving the write command packet executes one or more write commands contained in the write command packet, i.e. write command 1, write command 2, …, write command N, and then returns a write status packet to the SPI interface module 200b, including:

[0190] When the execution result of each write command contained in the write command package is success, the function module 300 returns a write status package with success state information to the SPI interface module 200b;

[0191] When the execution result of at least one write command contained in the write command package is failure, the function module 300 returns a write status package with failure state information to the SPI interface module 200b.

[0192] At the first time, the SPI interface module 200b receives the write status package, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, the SPI interface module 200b drives the SPI_MISO signal line, and sends a write feedback package through the SPI_MISO signal line. The SPI master controller 100b samples the data on the SPI_MISO signal line on the rising edge of the clock on the SPI_CK signal line, reads the write feedback package, and the write feedback package starts with the second identifier. The write feedback package contains the state information contained in the write status package, which can be write success or write failure, or other state information. In an embodiment, the write feedback package can contain the success or failure information contained in each write status package received by the SPI interface module 200b. After receiving the write feedback package, the SPI master controller 100b can know the execution of the write command package by each function module 300 receiving the write command package according to the write feedback package, and then can perform subsequent processing according to the execution.

[0193] The write feedback package contains M bytes, each byte is 8-bit binary data, the first byte is the second identifier, and the 8-bit binary data of the first byte is represented as A 10 , A 11 ...A 17 The Mth byte of the write feedback package is the last byte of the write feedback package, and the 8-bit binary data of the Mth byte of the write feedback package is represented as A M0 , A M1 ...A M7 .

[0194] For easy understanding, in the embodiment shown in FIG. 15 and the description hereinafter, each byte is described as 8-bit binary data, but the present application does not limit the number of bits of each byte, and each byte can also be other number of bits.

[0195] In the embodiment shown in FIG. 15, the lengths of the first identifier and the second identifier are one byte, and the lengths of the write command packet and the write feedback packet are integral multiples of one byte. For ease of understanding, in the following description of the present application, the lengths of the first to fourth identifiers are one byte, and the lengths of the write command packet, the write feedback packet (including the write success feedback packet and the write failure feedback packet) are integral multiples of one byte. However, the present application does not limit the lengths of the first to fourth identifiers to one byte, nor does it limit the lengths of the first to fourth identifiers to integral multiples of one byte. Furthermore, the present application does not limit the lengths of the write command packet, the write feedback packet (including the write success feedback packet and the write failure feedback packet) to integral multiples of one byte.

[0196] In the interval identified as "no clock edge", the SPI master controller 100b does not generate a sampling clock edge on the SPI_CK signal line. In the description of the embodiment shown in FIG. 15 and the subsequent embodiments of the present application, the levels on the SPI_MOSI and SPI_MISO signal lines do not change in the interval of "no clock edge". The present application does not limit the levels on the SPI_MOSI and SPI_MISO signal lines in the interval of "no clock edge". The levels on the SPI_MOSI and SPI_MISO signal lines can also change in the interval of "no clock edge". However, because the sampling of the data on the SPI_MOSI and SPI_MISO signal lines is only performed at the sampling clock edge on the SPI_CK signal line (the sampling clock edge is the clock rising edge in the embodiment shown in FIG. 15), the change of the levels on the SPI_MOSI and SPI_MISO signal lines in the interval of "no clock edge" will not be sampled and received.

[0197] In the embodiment shown in FIG. 15, the SPI master controller 100b generates a clock edge on the SPI_CK signal line and drives the SPI_MOSI signal line at the same time. When the SPI interface module 200b does not have a write feedback packet to send while sending the write command packet through the SPI_MOSI signal line, the SPI interface module 200b drives the SPI_MISO signal line to the high level in this period. In this period, the SPI interface module 200b of the present application can also drive the SPI_MISO signal line to the low level or a changing level. However, the SPI interface module 200b should ensure that the level value or the changing level value driven on the SPI_MISO signal line will not be identified as the second identifier if it is sampled at the sampling clock edge on the SPI_CK signal line (the sampling clock edge is the clock rising edge in the embodiment shown in FIG. 15). Taking the embodiment shown in FIG. 15 as an example, because the SPI interface module 200b drives the SPI_MISO signal line to the high level (the sampling is continuous binary bit 1) in this period, in order not to be identified as the second identifier, the value of the second identifier should not be 0xFF.

[0198] In the embodiment shown in Fig. 15, the SPI master controller 100b generates the clock edge on the SPI_CK signal line, the SPI interface module 200b drives the SPI_MISO signal line, and sends the write feedback packet through the SPI_MISO signal line. At this time, the SPI master controller 100b has no write command packet to send, and the SPI master controller 100b drives the SPI_MOSI signal line to high level. During this period, the SPI master controller 100b can also drive the SPI_MOSI signal line to low level or a changing level, but the SPI master controller 100b should ensure that the level value or the changing level value driven by it on the SPI_MOSI signal line is not recognized as the first identifier if it is sampled by the sampling clock edge on the SPI_CK signal line (the sampling clock edge in the embodiment shown in Fig. 15 is the clock rising edge). Taking the embodiment shown in Fig. 15 as an example, because the SPI master controller 100b drives the SPI_MOSI signal line to high level (the sampling is continuous binary bit 1) during this period, in order not to be recognized as the first identifier, the value of the first identifier should not be 0xFF.

[0199] The SPI interface module 200b can be connected to the SPI master controller 100b through the SPI_CSN signal line in addition to the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line. The SPI master controller 100b drives the SPI_CSN signal line, the SPI_CK signal line and the SPI_MOSI signal line, and the SPI interface module 200b receives the SPI_CSN signal line, the SPI_CK signal line and the SPI_MOSI signal line. The SPI interface module 200b drives the SPI_MISO signal line, and the SPI master controller 100b receives the SPI_MISO signal line. The SPI_CSN signal line is a selection signal. In the SPI protocol, data transmission is performed only when the SPI_CSN signal line is low. One SPI master controller 100b can be connected to multiple SPI interface modules 200b. The SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line are shared by the SPI master controller 100b and the multiple SPI interface modules 200b. However, each SPI interface module 200b has an independent SPI_CSN signal line input. When the SPI_CSN signal line of one SPI interface module 200b is high, the SPI interface module 200b does not drive the SPI_MISO signal line (the driver output of the SPI_MISO signal line of the SPI interface module 200b is in the Hi-Z state). One SPI interface module 200b drives the SPI_MISO signal line only when its SPI_CSN signal line is low. When one SPI master controller 100b is connected to multiple SPI interface modules 200b, at any time, only the SPI_CSN signal line of one SPI interface module 200b is low, so that the conflict caused by the simultaneous driving of the SPI_MISO signal line by multiple SPI interface modules 200b can be avoided.

[0200] When one SPI master controller 100b is connected to one SPI interface module 200b, the SPI interface module 200b can drive the SPI_MISO signal line at any time without causing conflict. In this case, the SPI master controller 100b and the SPI interface module 200b can have no SPI_CSN signal line, i.e., the SPI master controller 100b and the SPI interface module 200b can be connected only through the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line. The above description of the embodiment shown in FIG. 15 is such a case.

[0201] In the description of the present application, only the case that there is no SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b is described, but according to the description of the present application, it is easy to extend to the case that there is an SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b, and the case that there is an SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b is not described again in the description of the present application. Whether there is an SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b or not, it is within the protection scope of the present application.

[0202] According to the embodiment of the present application, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, reads the write feedback packet through the SPI_MISO signal line,

[0203] When the SPI interface module 200b does not receive the write state packet, the SPI interface module 200b sends data that cannot be recognized as a write feedback packet to the SPI master controller 100b through the SPI_MISO signal line.

[0204] For example, as shown in FIG. 16, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, sends a write command package to the SPI interface module 200b through the SPI_MOSI signal line, the SPI interface module 200b receives the write command package from the SPI_MOSI signal line, sends the write command package to one or more functional modules 300, the functional module 300 receiving the write command package executes one or more write commands contained in the write command package, and then returns a write status package to the SPI interface module 200b. At the third moment, the SPI interface module 200b receives the write status package from each functional module 300 from which the write command package is sent. Before the third moment when the SPI interface module 200b receives the write status package from each functional module 300 from which the write command package is sent, between the first moment and the second moment, the SPI master controller 100b generates a clock edge on the SPI_CK signal line. In the embodiment shown in FIG. 16, the SPI interface module 200b drives the SPI_MISO signal line to high level during this period. During this period, the SPI interface module 200b can also drive the SPI_MISO signal line to low level or a changing level, but the SPI interface module 200b should ensure that the level value or the changing level value driven on the SPI_MISO signal line is not recognized as the second identifier if sampled by the sampling clock edge on the SPI_CK signal line (the clock rising edge in the embodiment shown in FIG. 16). That is, when the SPI master controller 100b generates a clock edge on the SPI_CK signal line, if the SPI interface module 200b does not receive the write status package from each functional module 300 from which the write command package is sent, the SPI interface module 200b sends data that cannot be recognized as a write feedback package to the SPI master controller 100b through the SPI_MISO signal line. After the third moment when the SPI interface module 200b receives the write status package from each functional module 300 from which the write command package is sent, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and reads the write feedback package from the SPI interface module 200b through the SPI_MISO signal line.

[0205] In the embodiment shown in FIG. 17, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, sends a write command package to the SPI interface module 200b through the SPI_MOSI signal line, the SPI interface module 200b receives the write command package from the SPI_MOSI signal line, sends the write command package to one or more functional modules 300, the functional module 300 receiving the write command package executes one or more write commands contained in the write command package, and then returns a write status package to the SPI interface module 200b. At the first time point, the SPI interface module 200b receives the write status package from each functional module 300 from which the write command package is sent, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and reads the write feedback package from the SPI interface module 200b through the SPI_MISO signal line. At the second time point, the SPI master controller 100b completes reading the write feedback package, the SPI interface module 200b completes sending the write feedback package, the SPI master controller 100b continues to generate a clock edge on the SPI_CK signal line, at this time, the SPI interface module 200b drives the SPI_MISO signal line to be high, during which, the SPI interface module 200b can also drive the SPI_MISO signal line to be low or a variable level, but the SPI interface module 200b should ensure that the level value or the variable level value driven by it on the SPI_MISO signal line is not recognized as the second identifier if it is sampled by the sampling clock edge on the SPI_CK signal line (the sampling clock edge is the clock rising edge in the embodiment shown in FIG. 17).

[0206] According to the embodiment of the application, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends a write command package to the SPI interface module 200b through the SPI_MOSI signal line.

[0207] Then the SPI master controller 100b generates a clock edge on the SPI_CK signal line, reads the write feedback package through the SPI_MISO signal line, and the SPI interface module 200b can continue to receive subsequent command packages (the subsequent command packages include write command packages and read command packages) after sending the write feedback package through the SPI_MISO signal line.

[0208] In the application, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, sends the write command package to the SPI interface module 200b through the SPI_MOSI signal line, the SPI interface module 200b sends the write command package to one or more functional modules 300 after receiving the write command package from the SPI_MOSI signal line, the functional module 300 receiving the write command package executes one or more write commands contained in the write command package, and then returns a write state package to the SPI interface module 200b, then the SPI master controller 100b generates a clock edge on the SPI_CK signal line, reads the write feedback package through the SPI_MISO signal line, if the SPI master controller 100b drives the SPI_MOSI signal line to send a command package (containing a write command package and a read command package) before the SPI master controller 100b reads the write feedback package, the SPI interface module 200b can choose not to receive the command package sent by the SPI master controller 100b before the SPI master controller 100b reads the write feedback package, and after the SPI master controller 100b reads the write feedback package, that is, after the SPI interface module 200b sends the write feedback package through the SPI_MISO signal line, the SPI interface module 200b can continue to receive a subsequent command package (the subsequent command package contains a write command package and a read command package).

[0209] According to the embodiment of the application, the write feedback package can be divided into a write success feedback package and a write failure feedback package.

[0210] The SPI master controller 100b generates a clock edge on the SPI_CK signal line, reads the write feedback package through the SPI_MISO signal line,

[0211] When the SPI interface module 200b receives a write state package from each functional module 300 from which the write command package is sent, and the state information contained in each write state package is success, the SPI interface module 200b sends a write success feedback package through the SPI_MISO signal line, and the write success feedback package starts with a third identifier.

[0212] When the SPI interface module 200b receives a write state package from each functional module 300 from which the write command package is sent, and the state information contained in at least one write state package is failure, the SPI interface module 200b sends a write failure feedback package through the SPI_MISO signal line, and the write failure feedback package starts with a fourth identifier.

[0213] As shown in FIG. 18, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, sends a write command package to the SPI interface module 200b through the SPI_MOSI signal line, the SPI interface module 200b sends the write command package to one or more functional modules 300 after receiving the write command package from the SPI_MOSI signal line, the functional module 300 receiving the write command package executes one or more write commands contained in the write command package, and then returns a write state package to the SPI interface module 200b, at the first time, the SPI interface module 200b receives the write state package from each functional module 300 sending the write command package, and the state information contained in each write state package is success, when the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads the write feedback package from the SPI interface module 200b through the SPI_MISO signal line, the SPI interface module 200b drives the SPI_MISO signal line to send a write success feedback package to the SPI master controller 100b through the SPI_MISO signal line, and the write success feedback package starts with a third identifier.

[0214] As shown in FIG. 19, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, sends a write command package to the SPI interface module 200b through the SPI_MOSI signal line, the SPI interface module 200b sends the write command package to one or more functional modules 300 after receiving the write command package from the SPI_MOSI signal line, the functional module 300 receiving the write command package executes one or more write commands contained in the write command package, and then returns a write state package to the SPI interface module 200b, at the first time, the SPI interface module 200b receives the write state package from each functional module 300 sending the write command package, and the state information contained in at least one write state package is failure, when the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads the write feedback package from the SPI interface module 200b through the SPI_MISO signal line, the SPI interface module 200b drives the SPI_MISO signal line to send a write failure feedback package to the SPI master controller 100b through the SPI_MISO signal line, and the write failure feedback package starts with a fourth identifier.

[0215] In the present application, the third identifier is different from the fourth identifier, and the SPI master controller 100b can judge whether the read write feedback package is a write success feedback package or a write failure feedback package by whether the write feedback package starts with the third identifier or the fourth identifier, therefore, the write success feedback package can only contain the third identifier, and the write failure feedback package can only contain the fourth identifier, so that the SPI master controller 100b can distinguish whether the read write feedback package is a write success feedback package or a write failure feedback package.

[0216] The master controller 100 in the present application can be an I2C master controller 100a, an SPI master controller 100b, or a master controller complying with other interface protocols (for example, a master controller complying with a serial port UART protocol, a CAN protocol, a LIN protocol, etc.). The interface module 200 in the present application can be an I2C interface module 200a, an SPI interface module 200b, or an interface module complying with other interface protocols (for example, an interface module complying with a serial port UART protocol, a CAN protocol, a LIN protocol, etc.). The use of a master controller complying with other interface protocols and an interface module complying with other interface protocols is also within the protection scope of the present application.

[0217] According to an embodiment of the present application, the master controller 100 (I2C master controller 100a or SPI master controller 100b or a master controller complying with other interface protocols) sends a write command package to the interface module 200 (I2C interface module 200a or SPI interface module 200b or an interface module complying with other interface protocols), and when the interface module 200 receives the write command package, sends the write command package to one or more functional modules 300. The write command package contains one or more write commands, as shown in FIG. 2 and FIG. 14.

[0218] As shown in FIG. 20, according to an embodiment of the present application, an interface system is provided, characterized in that the interface system comprises a master controller 100, an interface module 200, a plurality of functional modules 300, and a remote I2C slave device 400. The master controller 100 is connected to the interface module 200, the interface module 200 is connected to the plurality of functional modules 300, the serial numbers of the functional modules 300 are represented by 1 to N, and the functional modules 300 can or can not be connected to the remote I2C slave device 400.

[0219] As shown in FIG. 20, the functional modules 300 are all connected to the remote I2C slave device 400. The functional modules 300 can also not be connected to the plurality of remote I2C slave devices 400. The functional modules 300 can also be connected to the plurality of remote I2C slave devices 400.

[0220] In this example, the master controller 100 sends a write command package, the interface module 200 receives the write command package, and sends the write command package to one or more functional modules 300. The process is the same as that in the embodiment shown in FIG. 1 and described above, and will not be described again here.

[0221] In this example, the functional module 300 receiving the write command package is connected to the remote I2C slave device 400. After receiving the write command package from the interface module 200, the functional module 300 receiving the write command package executes one or more write commands contained in the write command package. The method for executing each write command is as follows:

[0222] The function module 300 sends an I2C START to the remote I2C slave device 400, then the function module 300 sends a remote I2C address byte to the remote I2C slave device 400, then the function module 300 sends a write command to the remote I2C slave device 400,

[0223] For each byte sent by the function module 300 to the remote I2C slave device 400, the function module 300 receives an I2C ACK sent by the remote I2C slave device 400, and determines the execution result of the write command.

[0224] After receiving the write command package, the function module 300 executes one or more write commands contained in the write command package, and returns a write status package to the interface module 200, including:

[0225] When the execution result of each write command contained in the write command package is successful, the function module 300 returns a write status package with successful status information to the interface module 200.

[0226] When the execution result of at least one write command contained in the write command package is failed, the function module 300 returns a write status package with failed status information to the interface module 200.

[0227] The interface module 200 receives the write status package from each function module 300 from which the write command package is sent, and returns the status information of the write status package to the host controller 100.

[0228] As shown in FIG. 21, for each write command (write command 1, write command 2, …, write command N) contained in the write command package, the function module 300 first sends an I2C START to the remote I2C slave device 400, then the function module 300 sends a remote I2C address byte to the remote I2C slave device 400, and then the function module 400 sends a write command to the remote I2C slave device 400. The remote I2C address byte is composed of an I2C address (ADDR) and a write operation indication bit (W).

[0229] For a write command, the I2C ACK received by the function module 300 after sending the remote I2C address byte is I2C ACK, and the I2C ACK received by the function module 300 after sending each byte of the write command is I2C ACK, and the function module 300 executes this write command successfully.

[0230] As shown in FIG. 21, when the execution result of each write command is successful, the function module 300 returns a write status package with successful status information to the interface module 200, and the interface module 200 returns the status information of the write status package to the host controller 100.

[0231] In other embodiments (not shown in FIG. 21), the functional module 300 can also agree with the remote I2C slave device 400 that, for one write command, the I2C ACK received by the functional module 300 after the functional module 300 sends the remote I2C address byte is I2C ACK, and the I2C ACK received by the functional module 300 after the functional module 300 sends each byte of the write command except the last byte is I2C ACK, and the I2C ACK received by the functional module 300 after the functional module 300 sends the last byte of the write command is I2C NAK, and the functional module 300 considers the result of executing this write command to be successful.

[0232] When the result of executing one write command is failure, the functional module 300 stops executing the subsequent write command, and the functional module 300 returns a write status package with the status information of failure to the interface module 200, and the interface module 200 returns the status information of the write status package to the host controller 100.

[0233] As shown in FIG. 22, when the functional module 300 sends the remote I2C address byte (write command 1 address byte) to the remote I2C slave device 400, the functional module 300 receives the I2C ACK sent by the remote I2C slave device 400, and the result of executing the write command 1 is failure. The functional module 300 stops executing the subsequent write command, and the functional module 300 returns a write status package with the status information of failure to the interface module 200, and the interface module 200 returns the status information of the write status package to the host controller 100.

[0234] As shown in FIG. 23, another embodiment of the execution of a write command is given, the I2C ACK received by the functional module 300 after the functional module 300 sends the remote I2C address byte, and the I2C ACK received by the functional module 300 after the functional module 300 sends each byte of the write command 1 is I2C ACK, and the result of executing the write command 1 is success, and then for the write command 2, the I2C ACK received by the functional module 300 after the functional module 300 sends the remote I2C address byte is I2C ACK, but after the functional module 300 sends the byte 1 of the write command 2, the functional module 300 receives the I2C ACK sent by the remote I2C slave device 400, and the result of executing the write command 2 is failure (in this embodiment, the byte 1 of the write command 2 is not the last byte of the write command 2, or the byte 1 of the write command 2 is the last byte of the write command 2 but the functional module 300 agrees with the remote I2C slave device 400 that the I2C ACK received after sending each byte of a write command is I2C ACK, and the functional module 300 considers the execution of this write command to be successful), so the result of executing at least one write command in the write command package is failure, and the functional module 300 returns a write status package with the status information of failure to the interface module 200, and the interface module 200 returns the status information of the write status package to the host controller 100.

[0235] When the execution result of at least one of the write commands contained in the write command package is failure, the function module 300 returns a write status package with the status information as failure to the interface module 200, and the interface module 200 returns the status information of the write status package to the host controller 100.

[0236] In the present application, the status information of the write status package can contain the success or failure information contained in each write status package received by the interface module 200, and the host controller 100 can learn the execution of the write command package by each function module 300 according to the status information after receiving the status information, and then can perform subsequent processing according to the execution.

[0237] In the embodiments shown in FIG. 22 and FIG. 23, when the execution result of one write command is failure, the function module 300 stops executing the subsequent write commands, and the function module 300 returns a write status package with the status information as failure to the interface module 200, and the interface module 200 returns the status information of the write status package to the host controller 100. In other embodiments, when the execution result of one write command is failure, the function module 300 can choose to continue executing the subsequent write commands contained in the write command package, but when the execution result of at least one of the write commands contained in the write command package is failure, the function module 300 returns a write status package with the status information as failure to the interface module 200, and the interface module 200 returns the status information of the write status package to the host controller 100.

[0238] In a preferred embodiment, the function module 300 contains a remote I2C address register, and the I2C address contained in the remote I2C address byte sent by the function module 300 to the remote I2C slave device 400 (such as ADDR shown in FIG. 21, FIG. 22, and FIG. 23) is the remote I2C address stored in the remote I2C address register.

[0239] In a preferred embodiment, the write command package contains a remote I2C address (such as the write command package containing a remote I2C address shown in FIG. 2 and FIG. 14), and the I2C address contained in the remote I2C address byte sent by the function module 300 to the remote I2C slave device 400 is the remote I2C address contained in the write command package.

[0240] Further, the function module 300 contains a remote I2C address register, and the function module 300 also contains a remote I2C address selection module, and the I2C address contained in the remote I2C address byte sent by the function module 300 to the remote I2C slave device 400 is derived from the remote I2C address stored in the remote I2C address register or from the remote I2C address contained in the write command package according to the indication of the remote I2C address selection module.

[0241] In a preferred embodiment, the plurality of write commands of the write command package each contains a remote I2C address, and the remote I2C address byte of the remote I2C address sent by the functional module 300 to the remote I2C slave device contains the remote I2C address contained in each write command.

[0242] As shown in FIG. 3, in another embodiment, the host controller 100 is an I2C host controller 100a, and the interface module 200 is an I2C interface module 200a. The I2C host controller 100a initiates an I2C write operation to send the write command package to the I2C interface module 200a, and then initiates a subsequent I2C read operation to read the status information,

[0243] In this example, after the I2C host controller 100a initiates an I2C write operation to send the write command package to the I2C interface module 200a, it must initiate a subsequent I2C read operation to read the status information,

[0244] After the I2C interface module 200a receives the address byte of the subsequent I2C read operation, it pulls down the I2C clock line, and sends the received write command package to one or more functional modules 300,

[0245] The functional module 300 receiving the write command package executes one or more write commands contained in the write command package, and returns a write status package to the I2C interface module 200a, including:

[0246] When the execution result of each write command contained in the write command package is success, the functional module 300 returns a write status package with success status information to the I2C interface module 200a,

[0247] When the execution result of at least one write command contained in the write command package is failure, the functional module 300 returns a write status package with failure status information to the I2C interface module 200a,

[0248] After the I2C interface module 200a receives the write status package from each functional module 300 from which it sends the write command package, the I2C interface module 200a stops pulling down the I2C clock line, and returns the status information of the write status package to the I2C host controller 100a.

[0249] Although the embodiments of the present application have been shown and described above, it should be understood by those skilled in the art that the above embodiments are exemplary and cannot be construed as limiting the present application, and that variations, modifications, replacements and variations of the above embodiments made by those skilled in the art within the scope of the present application all belong to the protection scope of the present application.

Claims

1. A multi-target data writing method based on an interface system, the interface system comprising a host controller, an interface module, and a plurality of function modules, the host controller being connected to the interface module, and the interface module being connected to the plurality of function modules, characterized in that, the host controller sends a write command package to the interface module, and the interface module sends the write command package to one or more function modules after receiving the write command package, the function module receiving the write command package executes one or more write commands contained in the write command package and returns a write status package to the interface module, including: when the execution result of each write command contained in the write command package is success, the function module returns a write status package with success status information to the interface module, when the execution result of at least one write command contained in the write command package is failure, the function module returns a write status package with failure status information to the interface module, the interface module receives the write status package from each function module from which the write command package is sent, and returns the status information of the write status package to the host controller.

2. The multi-target data writing method of claim 1, wherein, the host controller is an I2C host controller, and the interface module is an I2C interface module, the I2C host controller connects the I2C interface module through an I2C clock line and an I2C data line, the I2C host controller initiates an I2C write operation to send a write command package to the I2C interface module, the I2C interface module pulls down the I2C clock line after receiving the write command package, and sends the write command package to one or more function modules, the function module receiving the write command package returns the write status package to the I2C interface module, and the I2C interface module receives the write status package from each function module from which the write command package is sent, and returns the status information of the write status package to the I2C host controller.

3. The multi-target data writing method of claim 2, wherein, when the I2C interface module receives the write status package from each function module from which the write command package is sent and the status information of each write status package is success, the I2C interface module stops pulling down the I2C clock line and returns an I2C ACK to the I2C host controller, when the I2C interface module receives the write status package from each function module from which the write command package is sent and the status information of at least one write status package is failure, the I2C interface module stops pulling down the I2C clock line and returns an I2C NAK to the I2C host controller.

4. The multi-target data writing method of claim 2, wherein, when the I2C interface module receives the write status package from each function module from which the write command package is sent, the I2C interface module stops pulling down the I2C clock line and returns an I2C ACK or an I2C NAK to the I2C host controller, if the subsequent I2C operation initiated by the I2C host controller is an I2C read operation, the I2C interface module returns the status information of the write status package to the I2C host controller.

5. The multi-target data writing method of claim 1, wherein, the host controller is an I2C host controller, and the interface module is an I2C interface module, The I2C master controller connects the I2C interface module through I2C clock line and I2C data line, the I2C master controller initiates I2C write operation to send the write command package to the I2C interface module, the I2C interface module sends the write command package to one or more functional modules after receiving the write command package, The functional module receiving the write command package returns the write state package to the I2C interface module, After the I2C interface module receives the write command package, If the subsequent I2C operation initiated by the I2C master controller is I2C read operation, and the I2C interface module receives the write state package from each functional module sending the write command package, the I2C interface module returns the state information of the write state package to the I2C master controller.

6. The multi-target data writing method of claim 5, wherein, The subsequent I2C operation initiated by the I2C master controller is I2C write operation, If the I2C interface module receives the write state package from each functional module sending the write command package and the state information of each write state package is success, the I2C interface module receives the subsequent I2C write operation initiated by the I2C master controller, If the I2C interface module receives the write state package from each functional module sending the write command package and the state information of at least one write state package is failure, the I2C interface module returns I2C NAK to the I2C master controller.

7. The multi-target data writing method of claim 1, wherein, The master controller is SPI master controller, the interface module is SPI interface module, the SPI master controller connects the SPI interface module through SPI_CK signal line, SPI_MOSI signal line and SPI_MISO signal line, The SPI master controller generates clock edge on SPI_CK signal line, sends the write command package to the SPI interface module through SPI_MOSI signal line, the write command package starts with first identifier, the SPI interface module sends the write command package to one or more functional modules after receiving the write command package from SPI_MOSI, The functional module receiving the write command package returns the write state package to the SPI interface module, the SPI interface module receives the write state package from each functional module sending the write command package and returns the state information of the write state package to the SPI master controller, including: After the SPI interface module receives the write state package from each functional module sending the write command package, the SPI interface module sends the write feedback package to the SPI master controller through SPI_MISO signal line when the SPI master controller generates clock edge on SPI_CK, the write feedback package starts with second identifier, the write feedback package contains the state information contained in the write state package.

8. The multi-target data writing method of claim 7, wherein, The SPI master controller generates clock edge on SPI_CK signal line, reads the write feedback package through SPI_MISO signal line, When the SPI interface module does not receive the write status packet from each functional module from which the write command packet is sent, the SPI interface module sends data that cannot be identified as the write feedback packet to the SPI master controller through the SPI_MISO signal line.

9. The multi-target data writing method of claim 7, wherein, The SPI master controller generates a clock edge on the SPI_CK signal line and sends the write command packet to the SPI interface module through the SPI_MOSI signal line, Then the SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line, and after the SPI interface module sends the write feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets.

10. The multi-target data writing method of claim 7, wherein, The write feedback packet is divided into a write success feedback packet and a write failure feedback packet, The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line, When the SPI interface module receives the write status packet from each functional module from which the write command packet is sent, and the state information contained in each write status packet is success, the SPI interface module sends the write success feedback packet through the SPI_MISO signal line, and the write success feedback packet starts with a third identifier, When the SPI interface module receives the write status packet from each functional module from which the write command packet is sent, and the state information contained in at least one write status packet is failure, the SPI interface module sends the write failure feedback packet through the SPI_MISO signal line, and the write failure feedback packet starts with a fourth identifier.

11. The multi-target data writing method of claim 1, wherein, The functional module that receives the write command packet is connected to a remote I2C slave device, and after the functional module that receives the write command packet receives the write command packet from the interface module, it executes one or more write commands contained in the write command packet. The method for executing each write command is: The functional module sends I2C START to the remote I2C slave device, then the functional module sends the remote I2C address byte to the remote I2C slave device, and then the functional module sends the write command to the remote I2C slave device, For each byte sent by the functional module to the remote I2C slave device, the functional module receives the I2C response bit sent by the remote I2C slave device and determines the execution result of the write command.

12. The multi-target data writing method of claim 11, wherein, The functional module that receives the write command packet contains a remote I2C address register, and the I2C address contained in the remote I2C address byte sent by the functional module that receives the write command packet to the remote I2C slave device is the remote I2C address stored in the remote I2C address register.

13. The multi-target data writing method of claim 11, wherein, The write command packet contains a remote I2C address, and the I2C address contained in the remote I2C address byte sent by the functional module that receives the write command packet to the remote I2C slave device is the remote I2C address contained in the write command packet.

14. The multi-target data writing method of claim 13, wherein, The function module receiving the write command package comprises a remote I2C address register, and further comprises a remote I2C address selection module. The I2C address byte contained in the remote I2C address byte sent by the function module receiving the write command package to the remote I2C slave device is selected according to the indication of the remote I2C address selection module, and is derived from the remote I2C address stored in the remote I2C address register or from the remote I2C address contained in the write command package.

15. A multi-target data writing method based on an interface system, wherein the interface system comprises an I2C master controller, an I2C interface module and a plurality of function modules, the I2C master controller is connected to the I2C interface module, and the I2C interface module is connected to the plurality of function modules, characterized in that, the I2C master controller initiates an I2C write operation to send a write command package to the I2C interface module, and then initiates a subsequent I2C read operation to read state information, the I2C interface module pulls down the I2C clock line after receiving the address byte of the subsequent I2C read operation, and sends the received write command package to one or more function modules, the function module receiving the write command package executes one or more write commands contained in the write command package, and returns a write state package to the I2C interface module, comprising: when the execution result of each write command contained in the write command package is successful, the function module returns a write state package with successful state information to the I2C interface module, when the execution result of at least one write command contained in the write command package is failed, the function module returns a write state package with failed state information to the I2C interface module, after the I2C interface module receives the write state package from each function module sending the write command package, the I2C interface module stops pulling down the I2C clock line, and returns the state information of the write state package to the I2C master controller.

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