Communication method and related apparatus

Abstract

The present application relates to the technical field of wireless communications, and specifically relates to a communication method and a related apparatus. The method comprises: receiving a first synchronization signal on at least one time-domain symbol, wherein each of the at least one time-domain symbol comprises at least one high-level signal and / or at least one low-level signal; the at least one time-domain symbol comprises a first time-domain symbol; and the duration of a high-level signal and / or the duration of a low-level signal of the first time-domain symbol are / is used for determining the chip duration of the first synchronization signal, or, information carried by the first time-domain symbol is used for determining the chip duration of the first synchronization signal; and performing time-frequency synchronization on the basis of the first synchronization signal. By using the method, the chip duration of a synchronization signal can be indicated by means of the synchronization signal, thereby helping a receiving device to demodulate the synchronization signal after receiving the synchronization signal, and improving the effect of time-frequency synchronization.

Description

A communication method and related apparatus

[0001] This application claims priority to Chinese Patent Application No. 202411087491.8, filed on August 8, 2024, entitled "A Communication Method and Related Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a communication method and related apparatus. Background Technology

[0003] Synchronization signals play a crucial role in communication systems. They are typically used for time and frequency synchronization, ensuring that all synchronization signals in the communication network work together, thereby guaranteeing accurate data transmission and reception and improving the quality of information transmission.

[0004] Existing synchronization signals are typically designed using M-sequences, Gold sequences, etc., which are designed to reduce interference with the synchronization signal. However, synchronization signals designed based on these sequences are often difficult for receiving equipment to demodulate, thus affecting the effectiveness of time and frequency synchronization. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a communication method and related apparatus that can indicate the chip duration using a synchronization signal, thereby facilitating demodulation of the received synchronization signal by the receiving device and improving the time-frequency synchronization effect.

[0006] The following sections introduce this application from multiple perspectives. It is easy to understand that the implementation methods of these multiple aspects can be referenced from each other.

[0007] In a first aspect, embodiments of this application provide a communication method applicable to tag devices. The method includes: receiving a first synchronization signal on at least one time-domain symbol. Here, each of the at least one time-domain symbol includes at least one high-level signal and / or at least one low-level signal, and the at least one time-domain symbol includes a first time-domain symbol. The duration of the high-level signal and / or the duration of the low-level signal of the first time-domain symbol are used to determine the chip duration of the first synchronization signal, or, information carried by the first time-domain symbol is used to determine the chip duration of the first synchronization signal. Time-frequency synchronization is performed based on the first synchronization signal.

[0008] In this embodiment, the first synchronization signal includes at least one high-level signal and / or at least one low-level signal on the first time-domain symbol. The duration of the high-level signal and / or the duration of the low-level signal on the first time-domain symbol can be used to determine the chip duration of the first synchronization signal. Alternatively, the information carried by the first time-domain symbol can be directly used to determine the chip duration. Through this sequence design, the first synchronization signal can not only be used for time-frequency synchronization but also indicate the chip duration, enabling the tag device to determine the corresponding chip duration after receiving the first synchronization signal on the first time-domain symbol. Thus, when receiving the first synchronization signal on subsequent time-domain symbols, each chip can be identified based on the determined chip duration. This facilitates the demodulation of the information carried on each chip by the tag device, avoiding demodulation errors caused by mistaking multiple identical level signals for a single chip, and improving the time-frequency synchronization effect.

[0009] In conjunction with the first aspect, in one possible implementation, the first synchronization signal is obtained based on the first on / off key control formula, and the symbol length of each time-domain symbol corresponds to a chip duration.

[0010] In conjunction with the first aspect, in one possible implementation, the first synchronization signal includes a high-level signal in the (2i-1)th time domain symbol and a low-level signal in the 2ith time domain symbol. Alternatively, the first synchronization signal includes a low-level signal in the (2i-1)th time domain symbol and a high-level signal in the 2ith time domain symbol, where i is a positive integer greater than or equal to 1.

[0011] In the above implementation, since the first synchronization signal includes only one level signal per time-domain symbol, when the level signal at the end of a time-domain symbol is copied to the beginning of that symbol, the copied level signal at the beginning of the time-domain symbol has the same type as the level signal within the time-domain symbol; that is, the level signal does not change. Thus, the first synchronization signal does not introduce a new rising or falling edge due to CP, thereby avoiding the impact of a newly added rising or falling edge on time-frequency synchronization and improving the time-frequency synchronization effect of the first synchronization signal. Furthermore, this design of the first synchronization signal is simple and easy to implement.

[0012] In conjunction with the first aspect, in one possible implementation, the first synchronization signal is obtained based on the second on / off key control formula, and the symbol length of each time-domain symbol corresponds to two chip durations.

[0013] In conjunction with the first aspect, in one possible implementation, the first time-domain symbol sequentially includes a first low-level signal, a first high-level signal, a second high-level signal, and a second low-level signal in the time domain. Here, the sum of the durations of the first low-level signal and the second low-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the first high-level signal and the second high-level signal is half the symbol length of the first time-domain symbol.

[0014] In conjunction with the first aspect, in one possible implementation, the first low-level signal includes a cyclic prefix of the first synchronization signal.

[0015] In conjunction with the first aspect, in one possible implementation, the duration of the first high-level signal and the second high-level signal is used to determine the chip duration.

[0016] In conjunction with the first aspect, in one possible implementation, the first time-domain symbol sequentially includes a third high-level signal, a third low-level signal, a fourth low-level signal, and a fourth high-level signal in the time domain. Here, the sum of the durations of the third high-level signal and the fourth high-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the third low-level signal and the fourth low-level signal is half the symbol length of the first time-domain symbol.

[0017] In conjunction with the first aspect, in one possible implementation, the third high-level signal includes a cyclic prefix of the first synchronization signal.

[0018] In conjunction with the first aspect, in one possible implementation, the duration of the third low-level signal and the fourth low-level signal is used to determine the chip duration.

[0019] In the above implementation, since the start and stop level signals of the first synchronization signal on the first time domain symbol have the same level signal type (either high or low), when the level signal at the end of the first time domain symbol is copied to the beginning of that symbol, the level signal copied to the beginning of the first time domain symbol has the same level signal type as the start level signal within the first time domain symbol; that is, the level signal does not change. Thus, the first synchronization signal does not introduce a new rising or falling edge due to the CP (Clipping Edge), thereby avoiding the impact of a newly added rising or falling edge on time-frequency synchronization and improving the time-frequency synchronization effect of the first synchronization signal.

[0020] In conjunction with the first aspect, in one possible implementation, the first synchronization signal is obtained based on the third on / off key control formula, and the symbol length of each time-domain symbol corresponds to 2n chip durations, where n is a positive integer greater than or equal to 2.

[0021] In conjunction with the first aspect, in one possible implementation, the first time-domain symbol sequentially includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a low level signal, and the third level signal to the 2nth level signal is a repeated high level signal and a low level signal. The repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0022] In conjunction with the first aspect, in one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in sequence in the time domain. The first level signal to the second level signal of the second time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal, respectively. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0023] In conjunction with the first aspect, in one possible implementation, the first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0024] In conjunction with the first aspect, in one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the second time-domain symbol is a low level signal, and the third level signal to the 2nth level signal is a repeated high level signal, and the repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0025] In the above implementation, since the start and stop level signals of the first synchronization signal on a time-domain symbol have the same level signal type (either high or low), when the level signal at the end of a time-domain symbol is copied to the beginning of that symbol, the copied level signal at the beginning of the symbol has the same level signal type as the start level signal; that is, the level signal does not change. Thus, the first synchronization signal does not introduce a new rising or falling edge due to the CP (Clipping Probe), thereby avoiding the impact of a newly added rising or falling edge on time-frequency synchronization and improving the time-frequency synchronization effect of the first synchronization signal.

[0026] In conjunction with the first aspect, in one possible implementation, the method further includes: receiving a first signal. Here, when the first signal includes at least one low-level signal, the start-level signal of the first time-domain symbol of the first synchronization signal is a high-level signal. Or, when the end-level signal of the first signal is a low-level signal, the start-level signal of the first time-domain symbol of the first synchronization signal is a high-level signal.

[0027] In the above implementation, the termination level signal of the first signal and the start level signal of the first synchronization signal have different signal types. This allows the tag device to distinguish between the first signal and the first synchronization signal after receiving the first synchronization signal. It avoids misidentification of the first synchronization signal by the tag device when the termination level signal and the start level signal of the first synchronization signal have the same signal type, thereby improving the time-frequency synchronization effect. This design approach can also introduce a new rising or falling edge, which can increase the chance of synchronization identification.

[0028] In conjunction with the first aspect, in one possible implementation, at least one time-domain symbol includes a third time-domain symbol, which includes at least one high-level signal and / or at least one low-level signal for time-frequency synchronization.

[0029] In conjunction with the first aspect, in one possible implementation, the third time-domain symbol includes at least one high-level signal and / or at least one low-level signal obtained based on a fourth on / off switch control.

[0030] Secondly, embodiments of this application provide a communication method applicable to a reader. The method includes: generating a first synchronization signal. Here, the first synchronization signal includes at least one high-level signal and / or at least one low-level signal on each of at least one time-domain symbols, the at least one time-domain symbol including the first time-domain symbol, the duration of the high-level signal and / or the duration of the low-level signal of the first time-domain symbol being used to determine the chip duration of the first synchronization signal, or, information carried by the first time-domain symbol being used to determine the chip duration of the first synchronization signal. The first synchronization signal is then transmitted on at least one time-domain symbol.

[0031] In conjunction with the second aspect, in one possible implementation, the first synchronization signal is obtained based on the first on / off key control formula, and the symbol length of each time-domain symbol corresponds to a chip duration.

[0032] In conjunction with the second aspect, in one possible implementation, the first synchronization signal includes a high-level signal in the (2i-1)th time domain symbol and a low-level signal in the 2ith time domain symbol. Alternatively, the first synchronization signal includes a low-level signal in the (2i-1)th time domain symbol and a high-level signal in the 2ith time domain symbol, where i is a positive integer greater than or equal to 1.

[0033] In conjunction with the second aspect, in one possible implementation, the first synchronization signal is obtained based on the second on / off key control formula, and the symbol length of each time-domain symbol corresponds to two chip durations.

[0034] In conjunction with the second aspect, in one possible implementation, the first time-domain symbol sequentially includes a first low-level signal, a first high-level signal, a second high-level signal, and a second low-level signal in the time domain. Here, the sum of the durations of the first low-level signal and the second low-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the first high-level signal and the second high-level signal is half the symbol length of the first time-domain symbol.

[0035] In conjunction with the second aspect, in one possible implementation, the first low-level signal includes a cyclic prefix of the first synchronization signal.

[0036] In conjunction with the second aspect, in one possible implementation, the duration of the first high-level signal and the second high-level signal is used to determine the chip duration.

[0037] In conjunction with the second aspect, in one possible implementation, the first time-domain symbol sequentially includes a third high-level signal, a third low-level signal, a fourth low-level signal, and a fourth high-level signal in the time domain. Here, the sum of the durations of the third high-level signal and the fourth high-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the third low-level signal and the fourth low-level signal is half the symbol length of the first time-domain symbol.

[0038] In conjunction with the second aspect, in one possible implementation, the third high-level signal includes a cyclic prefix of the first synchronization signal.

[0039] In conjunction with the second aspect, in one possible implementation, the duration of the third low-level signal and the fourth low-level signal is used to determine the chip duration.

[0040] In conjunction with the second aspect, in one possible implementation, the first synchronization signal is obtained based on the third on / off key control formula, and the symbol length of each time domain symbol corresponds to 2n chip durations, where n is a positive integer greater than or equal to 2.

[0041] In conjunction with the second aspect, in one possible implementation, the first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a low level signal, and the third level signal to the 2nth level signal is a repeated high level signal and a low level signal. The repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0042] In conjunction with the second aspect, in one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in sequence in the time domain. The first level signal to the second level signal of the second time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal, respectively. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0043] In conjunction with the second aspect, in one possible implementation, the first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0044] In conjunction with the second aspect, in one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in sequence in the time domain. The first level signal to the second level signal of the second time-domain symbol is a low level signal, and the third level signal to the 2nth level signal is a repeated high level signal, and the repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0045] In conjunction with the second aspect, in one possible implementation, the method further includes: sending a first signal. Here, when the first signal includes at least one low-level signal, the start-level signal of the first time-domain symbol of the first synchronization signal is a high-level signal.

[0046] In conjunction with the second aspect, in one possible implementation, at least one time-domain symbol includes a third time-domain symbol, the third time-domain symbol including at least one high-level signal and / or at least one low-level signal for time-frequency synchronization.

[0047] In conjunction with the second aspect, in one possible implementation, the third time-domain symbol includes at least one high-level signal and / or at least one low-level signal, which is obtained based on a fourth on / off switch control.

[0048] It should be understood that the communication method provided in the second aspect above is used to cooperate with the communication method provided in the first aspect above, and thus can achieve the same beneficial effect. To avoid redundancy, it will not be explained again.

[0049] It should be understood that the communication method provided in the first aspect above is also applicable to functional components within the tag device, such as processors, chips, chip systems, circuits, etc., and this application does not specifically limit them. Similarly, the communication method provided in the second aspect above is also applicable to the corresponding functional components within the device, and to avoid redundancy, it will not be repeated here.

[0050] Thirdly, this application provides a communication device, which can be the tag device mentioned in the first aspect. The communication device includes modules, units, or means that implement the above-described methods. These modules, units, or means can be implemented in hardware, software, or by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the above-described functions.

[0051] In some possible designs, the communication device includes a transceiver unit (also called a transceiver module) and a processing unit (also called a processing module). The transceiver unit is used to receive a first synchronization signal on at least one time-domain symbol. Here, each of the at least one time-domain symbols includes at least one high-level signal and / or at least one low-level signal. The at least one time-domain symbol includes a first time-domain symbol. The duration of the high-level signal and / or the duration of the low-level signal of the first time-domain symbol are used to determine the chip duration of the first synchronization signal; alternatively, the information carried by the first time-domain symbol is used to determine the chip duration of the first synchronization signal. The processing unit is used to perform time-frequency synchronization based on the first synchronization signal.

[0052] In conjunction with the third aspect, in one possible implementation, the first synchronization signal is obtained based on the first on / off key control formula, and the symbol length of each time-domain symbol corresponds to a chip duration.

[0053] In conjunction with the third aspect, in one possible implementation, the first synchronization signal includes a high-level signal in the (2i-1)th time domain symbol and a low-level signal in the 2ith time domain symbol. Alternatively, the first synchronization signal includes a low-level signal in the (2i-1)th time domain symbol and a high-level signal in the 2ith time domain symbol, where i is a positive integer greater than or equal to 1.

[0054] In conjunction with the third aspect, in one possible implementation, the first synchronization signal is obtained based on the second on / off key control formula, and the symbol length of each time domain symbol corresponds to two chip durations.

[0055] In conjunction with the third aspect, in one possible implementation, the first time-domain symbol sequentially includes a first low-level signal, a first high-level signal, a second high-level signal, and a second low-level signal in the time domain. Here, the sum of the durations of the first low-level signal and the second low-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the first high-level signal and the second high-level signal is half the symbol length of the first time-domain symbol.

[0056] In conjunction with the third aspect, in one possible implementation, the first low-level signal includes a cyclic prefix of the first synchronization signal.

[0057] In conjunction with the third aspect, in one possible implementation, the duration of the first high-level signal and the second high-level signal is used to determine the chip duration.

[0058] In conjunction with the third aspect, in one possible implementation, the first time-domain symbol sequentially includes a third high-level signal, a third low-level signal, a fourth low-level signal, and a fourth high-level signal in the time domain. Here, the sum of the durations of the third high-level signal and the fourth high-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the third low-level signal and the fourth low-level signal is half the symbol length of the first time-domain symbol.

[0059] In conjunction with the third aspect, in one possible implementation, the third high-level signal includes a cyclic prefix of the first synchronization signal.

[0060] In conjunction with the third aspect, in one possible implementation, the duration of the third low-level signal and the fourth low-level signal is used to determine the chip duration.

[0061] In conjunction with the third aspect, in one possible implementation, the first synchronization signal is obtained based on the third on / off key control formula, and the symbol length of each time domain symbol corresponds to 2n chip durations, where n is a positive integer greater than or equal to 2.

[0062] In conjunction with the third aspect, in one possible implementation, the first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a low level signal, and the third level signal to the 2nth level signal is a repeated high level signal and a low level signal. The repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0063] In conjunction with the third aspect, in one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in sequence in the time domain. The first level signal to the second level signal of the second time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal, respectively. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0064] In conjunction with the third aspect, in one possible implementation, the first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0065] In conjunction with the third aspect, in one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the second time-domain symbol is a low level signal, and the third level signal to the 2n level signal is a repeated high level signal, and the repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0066] In conjunction with the third aspect, in one possible implementation, the transceiver unit is also used to receive the first signal. Here, when the first signal includes at least one low-level signal, the start-level signal of the first time-domain symbol of the first synchronization signal is a high-level signal.

[0067] In conjunction with the third aspect, in one possible implementation, at least one time-domain symbol includes a third time-domain symbol, which includes at least one high-level signal and / or at least one low-level signal for time-frequency synchronization.

[0068] In conjunction with the third aspect, in one possible implementation, the third time-domain symbol includes at least one high-level signal and / or at least one low-level signal obtained based on a fourth on / off switch control.

[0069] Fourthly, this application provides a communication device, which can be the reader mentioned in the second aspect above. The communication device includes modules, units, or means that implement the above-described methods. These modules, units, or means can be implemented in hardware, software, or by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the above-described functions.

[0070] In some possible designs, the communication device includes a transceiver unit (also called a transceiver module) and a processing unit (also called a processing module). The processing unit is used to generate a first synchronization signal. Here, the first synchronization signal includes at least one high-level signal and / or at least one low-level signal on each of at least one time-domain symbols, where at least one time-domain symbol includes a first time-domain symbol. The duration of the high-level signal and / or the duration of the low-level signal of the first time-domain symbol are used to determine the chip duration of the first synchronization signal; alternatively, the information carried by the first time-domain symbol is used to determine the chip duration of the first synchronization signal. The transceiver unit is used to transmit the first synchronization signal on at least one time-domain symbol.

[0071] In conjunction with the fourth aspect, in one possible implementation, the first synchronization signal is obtained based on the first on / off key control formula, and the symbol length of each time-domain symbol corresponds to a chip duration.

[0072] In conjunction with the fourth aspect, in one possible implementation, the first synchronization signal includes a high-level signal in the (2i-1)th time domain symbol and a low-level signal in the 2ith time domain symbol. Alternatively, the first synchronization signal includes a low-level signal in the (2i-1)th time domain symbol and a high-level signal in the 2ith time domain symbol, where i is a positive integer greater than or equal to 1.

[0073] In conjunction with the fourth aspect, in one possible implementation, the first synchronization signal is obtained based on the second on / off key control formula, and the symbol length of each time-domain symbol corresponds to two chip durations.

[0074] In conjunction with the fourth aspect, in one possible implementation, the first time-domain symbol sequentially includes a first low-level signal, a first high-level signal, a second high-level signal, and a second low-level signal in the time domain. Here, the sum of the durations of the first low-level signal and the second low-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the first high-level signal and the second high-level signal is half the symbol length of the first time-domain symbol.

[0075] In conjunction with the fourth aspect, in one possible implementation, the first low-level signal includes a cyclic prefix of the first synchronization signal.

[0076] In conjunction with the fourth aspect, in one possible implementation, the duration of the first high-level signal and the second high-level signal is used to determine the chip duration.

[0077] In conjunction with the fourth aspect, in one possible implementation, the first time-domain symbol sequentially includes a third high-level signal, a third low-level signal, a fourth low-level signal, and a fourth high-level signal in the time domain. Here, the sum of the durations of the third high-level signal and the fourth high-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the third low-level signal and the fourth low-level signal is half the symbol length of the first time-domain symbol.

[0078] In conjunction with the fourth aspect, in one possible implementation, the third high-level signal includes a cyclic prefix of the first synchronization signal.

[0079] In conjunction with the fourth aspect, in one possible implementation, the duration of the third low-level signal and the fourth low-level signal is used to determine the chip duration.

[0080] In conjunction with the fourth aspect, in one possible implementation, the first synchronization signal is obtained based on the third on / off key control formula, and the symbol length of each time-domain symbol corresponds to 2n chip durations, where n is a positive integer greater than or equal to 2.

[0081] In conjunction with the fourth aspect, in one possible implementation, the first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a low level signal, and the third level signal to the 2nth level signal is a repeated high level signal and a low level signal. The repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0082] In conjunction with the fourth aspect, in one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in sequence in the time domain. The first level signal to the second level signal of the second time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal, respectively. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0083] In conjunction with the fourth aspect, in one possible implementation, the first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0084] In conjunction with the fourth aspect, in one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in sequence in the time domain. The first level signal to the second level signal of the second time-domain symbol is a low level signal, and the third level signal to the 2n level signal is a repeated high level signal, and the repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0085] In conjunction with the fourth aspect, in one possible implementation, the transceiver unit is also used to transmit a first signal. Here, when the first signal includes at least one low-level signal, the start-level signal of the first time-domain symbol of the first synchronization signal is a high-level signal.

[0086] In conjunction with the fourth aspect, in one possible implementation, at least one time-domain symbol includes a third time-domain symbol, which includes at least one high-level signal and / or at least one low-level signal for time-frequency synchronization.

[0087] In conjunction with the fourth aspect, in one possible implementation, the third time-domain symbol includes at least one high-level signal and / or at least one low-level signal obtained based on the fourth on / off switch control.

[0088] Fifthly, this application provides a computer program product comprising instructions that, when executed on a computer, cause the computer to perform the method of any one of the first aspects or any possible implementations of the first aspect, or to perform the method of any one of the second aspects or any possible implementations of the second aspect.

[0089] Sixthly, this application provides a computer-readable storage medium storing a computer program that, when executed, performs the method described in any one of the first aspects or any possible implementations of the first aspect, or performs the method described in any one of the second aspects or any possible implementations of the second aspect.

[0090] In a seventh aspect, this application provides a communication device including at least one processor. The at least one processor is configured to execute the method described in any of the preceding aspects or any possible implementation thereof. The communication device may be a tag device as described in the first aspect, or a device including the aforementioned tag device, or a device included in the aforementioned tag device, such as a chip; or, the communication device may be a reader as described in the second aspect, or a device including the aforementioned reader, or a device included in the aforementioned reader, such as a chip.

[0091] In conjunction with the seventh aspect, in one possible implementation, the communication device further includes a memory for storing necessary program instructions and data (i.e., computer programs).

[0092] In conjunction with the seventh aspect, in one possible implementation, the memory can be coupled to the processor, or it can be independent of the processor.

[0093] Eighthly, this application provides a chip system that includes at least a processor. The processor is configured to execute computer execution instructions to cause a device mounted on the chip system to perform the method described in any one of the first aspects or any possible implementations of the first aspect, or to perform the method described in any one of the second aspects or any possible implementations of the second aspect.

[0094] In conjunction with aspect eight, in one possible implementation, the chip system may further include interface circuitry. This interface circuitry is used to receive computer execution instructions and transmit them to the processor.

[0095] Ninthly, this application provides a communication device comprising: a processor and an interface circuit. The interface circuit is configured to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device. The processor is configured to implement the method described in any of the preceding aspects through logic circuits or by executing computer programs or instructions. The communication device may be a tag device as described in the first aspect, or a device including the aforementioned tag device, or a device included in the aforementioned tag device, such as a chip system; or, the communication device may be a reader as described in the second aspect, or a device including the aforementioned reader, or a device included in the aforementioned reader.

[0096] In a tenth aspect, this application provides a communication system. The communication system includes at least a tag device and a reader. The tag device is used to execute the communication method provided by the first aspect or any possible implementation thereof, and the reader is used to execute the communication method provided by the second aspect or any possible implementation thereof.

[0097] In summary, the communication method provided in this application can use a synchronization signal to indicate its chip duration, which is beneficial for the receiving device to demodulate the synchronization signal after receiving it, thereby improving the effect of time and frequency synchronization. Attached Figure Description

[0098] Figure 1 is a schematic diagram of the architecture of a communication system provided in an embodiment of this application;

[0099] Figure 1a is a schematic diagram of a communication method provided in an embodiment of this application;

[0100] Figure 1b is a schematic diagram of another communication method provided in an embodiment of this application;

[0101] Figure 1c is a schematic diagram of another communication method provided in an embodiment of this application;

[0102] Figure 2 is a schematic diagram of a cyclic prefix of a synchronization signal provided in an embodiment of this application;

[0103] Figure 3 is a schematic diagram of a communication method provided in an embodiment of this application;

[0104] Figure 4 is a schematic diagram of a first synchronization signal provided in an embodiment of this application;

[0105] Figure 5 is a schematic diagram of yet another first synchronization signal provided in an embodiment of this application;

[0106] Figure 6 is a schematic diagram of yet another first synchronization signal provided in an embodiment of this application;

[0107] Figure 7 is a schematic diagram of yet another first synchronization signal provided in an embodiment of this application;

[0108] Figure 8 is a schematic diagram of a second synchronization signal provided in an embodiment of this application;

[0109] Figure 9 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0110] Figure 10 is a schematic diagram of another communication device provided in an embodiment of this application;

[0111] Figure 11 is a schematic diagram of the structure of another communication device provided in an embodiment of this application. Detailed Implementation

[0112] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0113] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. In the textual description of this application, the character " / " generally indicates an "or" relationship between the preceding and following related objects; in the formulas of this application, the character " / " indicates a "division" relationship between the preceding and following related objects. "Including at least one of A, B, and C" can mean: including A; including B; including C; including A and B; including A and C; including B and C; including A, B, and C.

[0114] The technical solutions provided in this application can be applied to various communication systems, such as Long Term Evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, 5th generation (5G) systems, or new radio (NR) systems. In addition, they can also be applied to subsequent evolution systems, such as 6th generation (6G) communication systems.

[0115] The system architecture used in the embodiments of this application is described below. It should be noted that the system architecture and business scenarios described in this application are for the purpose of more clearly illustrating the technical solutions of this application, and do not constitute a limitation on the technical solutions provided in this application. As those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in this application are also applicable to similar technical problems.

[0116] Please refer to Figure 1, which is a schematic diagram of the architecture of a communication system provided in an embodiment of this application. As shown in Figure 1, the communication system may include a reader and a tag device. The reader can interact with the tag device via radio frequency signals or wireless signals, and the two cooperate with each other to implement the communication method provided in this application.

[0117] A reader is a device capable of identifying and reading tags. A reader can retrieve information stored in a specified tag based on instructions from a server. For example, if the server instructs an inventory check (or inventory management), the reader can retrieve the tag's identification information. This identification information can be a unique tag identifier or a temporary tag identifier. Similarly, if the server instructs a read operation, the reader can read data from the tag's storage area.

[0118] In possible scenarios, the reader can also have a write function if it is necessary to rewrite the information stored in the tag. For example, if the server issues a write operation command, the reader can write data to the tag's storage area. Additionally, the reader can also perform an invalidation operation on the tag. After the reader performs the invalidation operation, the tag becomes invalid and cannot be subjected to inventory, read, or write operations. It should be understood that the reader can also be called a reader-writer, and may have other names; this application embodiment is not limited in this regard.

[0119] In the embodiments of this application, the reader can be a network device or a terminal device, and the embodiments of this application do not specifically limit the form of the reader.

[0120] The network device can be a base station, an access point, or an access network device, or it can refer to a device in the access network that communicates with a wireless terminal through one or more sectors on the air interface. The network device can be used to convert received air frames to and from Internet Protocol (IP) packets, and act as a router between the wireless terminal and the rest of the access network, which may include an IP network. The network device can also coordinate the attribute management of the air interface. For example, the network device can be an evolved node B (eNB or eNodeB) in an LTE system, a radio controller in a cloud radio access network (CRAN) or open radio access network (ORAN) scenario, or a relay station, access point, vehicle-mounted device, wearable device, access device in a 5G network, or a network device in a future evolved public land mobile network (PLMN), or an access point (AP) in a wireless local area network (WLAN), or a 5G radio base station (gNodeB or gNB) in an NR system. This application embodiment does not limit this.

[0121] In addition, in the embodiments of this application, the network device can be a device in the radio access network (RAN), or in other words, a RAN node that connects the terminal device to the wireless network. For example, by way of example and not limitation, network devices can include: gNB, TRP, evolved Node B (eNB), radio network controller (RNC), Node B (NB), base station controller (BSC), base transceiver station (BTS), home base station (e.g., home evolved Node B, or home Node B (HNB), base band unit (BBU), or wireless fidelity (WiFi) AP, etc.

[0122] Terminal equipment can be referred to as: user equipment (UE), mobile station (MS), mobile terminal (MT), access terminal, user unit, user station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device, etc.

[0123] Terminal devices can be devices that provide voice / data connectivity to users, such as handheld devices with wireless connectivity, in-vehicle devices, etc. Currently, some examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, and wireless terminals in transportation safety. Wireless terminals in smart cities, smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless demodulator, in-vehicle devices, wearable devices, terminal devices in 5G networks, or terminal devices in future PLMNs, etc., are not limited to these categories in this application.

[0124] As an example and not a limitation, in this application embodiment, wearable devices can also be called wearable smart devices. This is a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, and watches. Wearable devices are portable devices worn directly on the body or integrated into a user's clothing or accessories. Wearable devices are not merely hardware devices; they achieve powerful functions through software support, data interaction, and cloud interaction. Broadly defined, wearable devices include those with comprehensive functions, large size, and the ability to achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those focused on a specific application function that require interaction with other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0125] Furthermore, in this embodiment, the terminal device can also be a terminal device in an Internet of Things (IoT) system. IoT is an important component of future information technology development, and its main technical feature is connecting objects to networks through technology, thereby realizing an intelligent network for human-machine interconnection and object-to-object interconnection. In this embodiment, the terminal device can also include a relay. Alternatively, it can be understood that anything capable of data communication with a base station can be considered a terminal device.

[0126] It should be further noted that the aforementioned network devices and terminal devices can be fixed in location or mobile. Specifically, network devices and terminal devices can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted, on water, or in the air on airplanes, balloons, and satellites. This application does not impose specific limitations on the application scenarios of the network devices and terminal devices.

[0127] It should also be noted that the aforementioned network devices and terminal devices, as well as terminal devices communicating with each other, can communicate using licensed spectrum, unlicensed spectrum, or both simultaneously. Network devices and terminal devices, as well as terminal devices communicating with each other, can communicate using spectrum below 6 GHz, spectrum above 6 GHz, or both simultaneously. This application does not impose specific restrictions on the spectrum resources used between network devices and terminal devices.

[0128] The tag device can consist of coupling elements and chips. Each tag has an electronic code, and high-capacity electronic tags have user-writable storage space. Attached to an object, it identifies the target object. The tag can receive signals sent by a reader to drive internal circuitry for encoding, decoding, demodulation, and other processing operations. It also reflects signals sent by the reader, demodulating the information to be transmitted onto the reflected signal to send signaling to the reader. It should be understood that the tag device can also be called a tag, electronic tag, or electronic device, and other names are not limited to this application.

[0129] In this embodiment, the tag device can be an ambient internet of things (AIoT) tag, which can also be called an AIoT device. AIoT tags can operate without batteries or with low-power batteries, eliminating the need for manual battery replacement and instead collecting energy from the environment for service and communication.

[0130] There are generally two types of AIoT tags. Type 1 AIoT tags (hereinafter referred to as "first tags" for ease of distinction) typically have an output power consumption of about 1 microwatt (μW) and energy storage capabilities, but lack the ability to amplify uplink and downlink signals. First tags can only transmit information through backscattering of an externally provided carrier wave. Type 2 AIoT tags (hereinafter referred to as "second tags" for ease of distinction) typically have a peak power of no more than a few hundred microwatts and possess energy storage capabilities, as well as the ability to amplify uplink and / or downlink signals. Second tags can generate signals internally or transmit information through backscattering of an externally provided carrier wave.

[0131] In practice, there are two possible scenarios for communication between network devices and AIoT tags. The following will illustrate the communication process between network devices and the two types of AIoT tags in these two different scenarios with reference to Figures 1a, 1b, and 1c.

[0132] In Scenario 1, when the network device is operating in a limited-range mode, it can communicate directly with the AIoT tag. In this case, two different communication methods can be used for the first and second tags mentioned above.

[0133] Method 1: Please refer to Figure 1a, which is a schematic diagram of a communication method provided in an embodiment of this application. As shown in Figure 1a, for a first or second tag that supports reflection, the terminal device communicating with the network device can send a carrier wave, which can be reflected by the first or second tag to obtain a reflected signal. The first or second tag sends the reflected signal to the network device for uplink transmission. The network device can also send downlink signals to the first or second tag for downlink transmission.

[0134] Method 2: Please refer to Figure 1b, which is a schematic diagram of another communication method provided in this application embodiment. As shown in Figure 1b, for a second tag that supports internally generated signals, the signals generated internally by the second tag device can be used for uplink transmission with the network device. The network device can also send downlink signals to the second tag for downlink transmission.

[0135] In scenario two, when the network device is located outdoors, it can communicate with the AIoT tag through an additional intermediate node. It should be noted that communication between the AIoT tag and the intermediate node can be either from the intermediate node to the AIoT tag or vice versa.

[0136] Please refer to Figure 1c, which is a schematic diagram of another communication method provided in an embodiment of this application. As shown in Figure 1c, for a first tag or a second tag that supports reflection, the intermediate node can transmit a carrier wave for the first tag or the second tag to use for reflection. Optionally, in this embodiment of the application, the aforementioned intermediate node can be a terminal device, which can be fixed in position or mobile; this embodiment of the application does not limit this.

[0137] It should be noted that the network devices in Scenario 1 and the intermediate nodes in Scenario 2 can both be called readers, and the AIoT tags in Scenario 1 and Scenario 2 can be called tag devices, or simply devices.

[0138] It should be understood that the process of sending a message from the reader to the device can be called reader-to-device (R2D) transmission, and the process of sending a message from the device to the reader can be called device-to-reader (D2R) transmission. In Scenario 1 above, R2D transmission refers to the communication process from the network device to the AIoT tag, and D2R transmission refers to the communication process from the AIoT tag to the network device. In Scenario 2 above, R2D transmission refers to the communication process from the intermediate node (such as the UE) to the AIoT tag, and D2R transmission refers to the communication process from the AIoT tag to the intermediate node (such as the UE).

[0139] In the embodiments of this application, the method executed by the reader can also be implemented by functional components within the reader, such as chips, chip systems, processors, circuits, etc. Similarly, the method executed by the tag device can also be implemented by functional components within the tag device, such as chips, chip systems, processors, circuits, etc. The embodiments of this application do not limit this approach.

[0140] It should be understood that multiple tag devices can exist in a communication system. That is, a reader can establish communication connections with multiple tag devices. Similarly, multiple readers can exist in a communication system. That is, a tag device can establish communication connections with multiple readers simultaneously. In the embodiments of this application, no specific limitation is made on the number of readers and tag devices in the communication system. For ease of understanding, the following description uses one reader and one tag device as an example to illustrate the communication method provided in this application.

[0141] It should be noted that the R2D transmission process between the reader and the tag device is similar to the D2R transmission process. For ease of explanation, the following text will use the R2D transmission process between the reader and the tag device as an example to illustrate the communication method provided in this application.

[0142] To facilitate understanding of this application, some terms or concepts used in this application will be explained below.

[0143] 1. Symbol

[0144] The abbreviation for time-domain symbol can also be called OFDM symbol when using orthogonal frequency division multiplexing (OFDM) technology. It should be noted that time-domain symbols can also be combined with other multiple access methods in their naming, and this application does not limit this. The length of the time-domain symbol can vary for different subcarrier spacings.

[0145] 2. Cyclic prefix (CP)

[0146] A cyclic prefix is ​​a loop structure formed by copying the signal from the tail of an OFDM symbol to the head of that OFDM symbol. It should be understood that due to the presence of the cyclic prefix, an additional rising or falling edge is typically added to the signal.

[0147] For example, please refer to Figure 2, which is a schematic diagram of a cyclic prefix (CP) for a synchronization signal provided in an embodiment of this application. Here, we will explain the CP of a synchronization signal by taking an example where a time-domain symbol sequentially includes a high-level signal and a low-level signal in the time domain. As shown in Figure 2, the level signal at the end of the time-domain symbol is treated as CP and can be copied to the beginning of the time-domain symbol, thus introducing a new rising edge in the synchronization signal. It should be noted that this newly added rising edge will affect the synchronization effect of the synchronization signal.

[0148] The CP duration can be 160κ or 144κ. Here, κ is the duration specified in the standard, and in one possible implementation, κ = 1 / 30720 milliseconds (ms).

[0149] It should be noted that since multiple OFDM symbols can exist in a subframe, the CP duration can differ among different OFDM symbols. For example, suppose there are i OFDM symbols in a subframe, and these i OFDM symbols are numbered 1, 2, ..., i, where i is a positive integer greater than or equal to 1. For OFDM symbols whose number i is a multiple of 7, the corresponding CP duration can be 160kbps. For other OFDM symbols, the corresponding CP duration can be 144kbps.

[0150] 3. On-off keying (OOK) format, chip, and chip duration

[0151] OOK demodulation, also known as OOK signal demodulation, is a simple wireless signal demodulation method primarily used in digital communication systems. OOK demodulation is a special case of amplitude shift keying (ASK) demodulation, where changes in signal amplitude represent binary information. In OOK, the signal amplitude can take two discrete values: 0 (representing the off state) and a non-zero value, 1 (representing the on state). In this demodulation method, carrier transmission is controlled using binary 0s and 1s. A binary "1" corresponds to the on state of the carrier, and a binary "0" corresponds to the off state.

[0152] Signals obtained based on the OOK standard can carry at least one OOK level signal in a time-domain symbol, that is, at least one high-level signal and / or at least one low-level signal. A single OOK level signal can be called a chip, or in other words, a high-level signal or a low-level signal can be called a chip. It can be understood that a signal obtained based on the OOK standard can carry at least one chip in a time-domain symbol.

[0153] Chip duration refers to the duration of a chip within a time-domain symbol, or the symbol length occupied by a chip within a time-domain symbol, or the duration corresponding to a chip within a time-domain symbol.

[0154] It should be noted that the position of a level signal change can be used to measure and determine the duration of the level signal. In other words, the rising and falling edges of a level signal can be measured to obtain its duration. For example, a high-level signal lies between a rising edge and a falling edge; these rising and falling edges can be measured to determine the duration of the high-level signal. Similarly, a low-level signal lies between a falling edge and a rising edge; these falling and rising edges can be measured to determine the duration of the low-level signal.

[0155] Existing synchronization signals are typically designed using M-sequences or Gold sequences, which are intended to reduce interference. However, synchronization signals designed based on these sequences are often difficult for receiving equipment to demodulate, thus affecting the time-frequency synchronization effect. Therefore, the technical problem this application aims to solve is: how to avoid the impact of synchronization signal sequence design on time-frequency synchronization.

[0156] Based on the above, the communication method of this application embodiment will be described below by way of example.

[0157] Please refer to Figure 3, which is a schematic diagram of a communication method provided in an embodiment of this application. As shown in Figure 3, this method can be applied to the communication system shown in Figure 1. The communication method may include the following steps:

[0158] S301, the reader generates the first synchronization signal.

[0159] In some feasible implementations, the reader can generate a first synchronization signal before sending signaling to the tag device. Here, the first synchronization signal can be used for time-frequency synchronization between the reader and the tag device.

[0160] The first synchronization signal may include at least one high-level signal and / or at least one low-level signal in each of the at least one time-domain symbols. When the at least one time-domain symbol includes the first time-domain symbol, the duration of the high-level signal and / or the duration of the low-level signal of the first time-domain symbol can be used to determine the chip duration of the first synchronization signal; alternatively, the information carried by the first time-domain symbol can be used to determine the chip duration of the first synchronization signal. In other words, the first synchronization signal can be used to indicate its chip duration.

[0161] In practical implementation, there are two possible communication scenarios. One is where the reader sends a first synchronization signal to the tag device, allowing the tag device to simultaneously perform time-frequency synchronization and determine the chip duration based on the first synchronization signal (hereinafter referred to as Scenario 1). The other is where the reader sends a first synchronization signal to the tag device, where the first synchronization signal may include a first sub-synchronization signal and a second sub-synchronization signal. The tag device can perform time-frequency synchronization based on the first sub-synchronization signal and determine the chip duration based on the second sub-synchronization signal (hereinafter referred to as Scenario 2). For ease of understanding, the following will, in conjunction with Scenario 1 and Scenario 2, provide an exemplary description of at least one high-level signal and / or at least one low-level signal included in the first time domain symbol of the first synchronization signal, and the chip duration indicated by them.

[0162] In Scenario 1, the duration of the high-level signal and / or the duration of the low-level signal of the first synchronization signal on the first time domain symbol can be used to determine the chip duration of the first synchronization signal.

[0163] Optionally, the first synchronization signal can be obtained based on different on / off control methods. It should be noted that the number and position of high-level and / or low-level signals included in the first time-domain symbol may differ for first synchronization signals obtained based on different on / off control methods; in other words, the patterns corresponding to the first synchronization signals may be different. Correspondingly, the durations of the high-level and / or low-level signals in the first time-domain symbol will also be different, and consequently, the chip duration of the first synchronization signal determined based on the durations of the high-level and / or low-level signals in the first time-domain symbol will also be different.

[0164] The pattern of the first synchronization signal can be used to indicate the number of high-level signals and / or low-level signals corresponding to the first synchronization signal in each time domain symbol, as well as the position of the high-level signals and / or low-level signals.

[0165] The following section introduces three first synchronization signals obtained based on different on / off control methods, and the corresponding methods for indicating the chip duration of the first synchronization signal by the duration of the high-level signal and / or the duration of the low-level signal in the first time domain symbol.

[0166] In Method 1, when the first synchronization signal is obtained based on the first on / off key control, the symbol length of each time-domain symbol can correspond to a chip duration.

[0167] Optionally, the first synchronization signal obtained based on the first on / off key control can include either a high-level signal or a low-level signal on each time-domain symbol. That is, each time-domain symbol can carry one chip.

[0168] In a first optional implementation, the first synchronization signal may include a high-level signal on the (2i-1)th time domain symbol and a low-level signal on the 2ith time domain symbol. Here, i is a positive integer greater than or equal to 1.

[0169] In other words, the first synchronization signal is a high-level signal on the time domain symbols with odd-numbered labels and a low-level signal on the time domain symbols with even-numbered labels.

[0170] In a second alternative implementation, the first synchronization signal may include a low-level signal on the (2i-1)th time domain symbol and a high-level signal on the (2i)th time domain symbol.

[0171] In other words, the first synchronization signal is a low-level signal on the time domain symbols with odd-numbered labels and a high-level signal on the time domain symbols with even-numbered labels.

[0172] It can be understood that the high-level and low-level signals contained in the first synchronization signal in multiple time domain symbols can be interleaved sequentially.

[0173] Optionally, in the two optional embodiments described above, the duration of the high-level or low-level signal of the first synchronization signal within any time-domain symbol can be used to determine the chip duration. Since the duration of a high-level signal or a low-level signal is equal to the symbol length of a time-domain symbol, the chip duration of the first synchronization signal is equal to the symbol length of a time-domain symbol.

[0174] For example, please refer to Figure 4, which is a schematic diagram of a first synchronization signal provided in an embodiment of this application. As shown in Figure 4, the above two possible first synchronization signals are described here by taking the first synchronization signal as lasting for four consecutive time domain symbols (time domain symbol 1, time domain symbol 2, time domain symbol 3 and time domain symbol 4 shown in Figure 4) as an example.

[0175] As shown in Figure 4(a), the first synchronization signal includes high-level signals, low-level signals, high-level signals, and low-level signals in time domain symbols 1, 2, 3, and 4, respectively.

[0176] As shown in Figure 4(b), the first synchronization signal includes low-level signal, high-level signal, low-level signal, and high-level signal in time domain symbol 1, time domain symbol 2, time domain symbol 3, and time domain symbol 4, respectively.

[0177] It should be noted that since the first synchronization signal mentioned above includes only one level signal in each time domain symbol, if the first synchronization signal lasts only one time domain symbol, it does not include rising or falling edges. This reduces the chance of synchronization identification based on rising or falling edges, which is detrimental to time-frequency synchronization. Therefore, in order to increase the chance of synchronization identification, i.e., to increase the number of rising or falling edges included in the first synchronization signal, the first synchronization signal obtained based on the first on / off key control formula can usually last for multiple time domain symbols.

[0178] For example, the number of time-domain symbols in which the first synchronization signal lasts is an even number, such as 2, 4, 6, or 8. Since the high-level and low-level signals contained in the first synchronization signal across multiple time-domain symbols are interleaved, this ensures that the number of high-level and low-level signals included in the first synchronization signal is the same.

[0179] For example, the first synchronization signal may last for 7 or 14 time-domain symbols. That is, the first synchronization signal can last for half a time slot or the number of symbols in a full time slot. It should be noted that since the first time-domain symbol of every seven time-domain symbols contains a longer CP (Content Component) length than the other time-domain symbols, and the tag device may not be able to distinguish the CP length of each time-domain symbol after receiving the first synchronization signal, having the first synchronization signal last for multiple time-domain symbols avoids the problem that the level signal used to measure the chip duration of the first synchronization signal happens to be located in the first time-domain symbol, leading to a longer measured chip duration. In this case, the tag device can still measure the correct chip duration of the first synchronization signal based on the other time-domain symbols besides the first one.

[0180] Optionally, the first on / off switch control method described above can be called the OOK-1 system, or it can have other names. This application embodiment does not limit this.

[0181] In the above implementation, since the first synchronization signal includes only one level signal per time-domain symbol, when the level signal at the end of a time-domain symbol is copied to the beginning of that symbol, the copied level signal at the beginning of the time-domain symbol has the same type as the level signal within the time-domain symbol; that is, the level signal does not change. Thus, the first synchronization signal does not introduce a new rising or falling edge due to CP, thereby avoiding the impact of a newly added rising or falling edge on time-frequency synchronization and improving the time-frequency synchronization effect of the first synchronization signal. Furthermore, this design of the first synchronization signal is simple and easy to implement.

[0182] In the second method, when the first synchronization signal is obtained based on the second on / off key control, the symbol length of each time domain symbol can correspond to two chip durations.

[0183] Optionally, the first synchronization signal, based on the second on / off switch control, may include four level signals on each time domain symbol.

[0184] In a first optional implementation, the first time-domain symbol may sequentially include a first low-level signal, a first high-level signal, a second high-level signal, and a second low-level signal in the time domain.

[0185] Since the duration of each level signal can be the same, the sum of the durations of the first low-level signal and the second low-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the first high-level signal and the second high-level signal is half the symbol length of the first time-domain symbol.

[0186] It should be noted that, since the first low-level signal is the first level signal of the first time domain symbol, the first low-level signal may include the CP of the first synchronization signal.

[0187] Optionally, the durations of the first and second high-level signals can be used to determine the chip duration of the first synchronization signal. Since neither of these two high-level signals includes CP, the chip duration of the first synchronization signal is equal to the durations of the first and second high-level signals, which is half the symbol length of the first time-domain symbol.

[0188] Optionally, the durations of the first low-level signal and the second low-level signal can also be used to determine the chip duration of the first synchronization signal. Since the first low-level signal includes CP, the chip duration of the first synchronization signal is equal to the difference between the sum of the durations of the first low-level signal and the second low-level signal and the duration of CP, that is, the difference between half the symbol length of the first time-domain symbol and the duration of CP.

[0189] In a second alternative implementation, the first time-domain symbol may sequentially include a third high-level signal, a third low-level signal, a fourth low-level signal, and a fourth high-level signal in the time domain.

[0190] Since the duration of each level signal can be the same, the sum of the durations of the third high-level signal and the fourth high-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the third low-level signal and the fourth low-level signal is half the symbol length of the first time-domain symbol.

[0191] It should be noted that, since the aforementioned third high-level signal is the first level signal of the first time domain symbol, the third high-level signal may include the CP of the first synchronization signal.

[0192] Optionally, the durations of the third and fourth low-level signals can be used to determine the chip duration of the first synchronization signal. Since neither of these two low-level signals includes CP, the chip duration of the first synchronization signal is equal to half the symbol length of the first time-domain symbol.

[0193] Optionally, the durations of the third and fourth high-level signals can also be used to determine the chip duration of the first synchronization signal. Since the third high-level signal includes CP, the chip duration of the first synchronization signal is equal to the difference between the sum of the durations of the third and fourth high-level signals and the CP duration, that is, the difference between half the symbol length of the first time-domain symbol and the CP duration.

[0194] It should be noted that, since the first synchronization signal has two consecutive level signals in the first time domain symbol, and the tag device cannot identify the boundary between the two consecutive level signals, it will treat these two consecutive level signals as a single level signal. In other words, although the first synchronization signal includes four level signals in the first time domain symbol, the tag device, upon receiving the first synchronization signal, will assume that it carries two chips in the first time domain symbol. Therefore, in this implementation, the symbol length of each time domain symbol corresponds to the duration of two chips.

[0195] Optionally, when the first synchronization signal lasts for multiple time-domain symbols, each time-domain symbol includes the same four level signals in the time domain. For example, assume that the multiple time-domain symbols of the first synchronization signal include consecutive first and second time-domain symbols. In the first optional embodiment of the above-mentioned method two, the second time-domain symbol may sequentially include a low-level signal, a high-level signal, a high-level signal, and a low-level signal in the time domain. In the second optional embodiment of the above-mentioned method two, the second time-domain symbol may sequentially include a high-level signal, a low-level signal, a low-level signal, and a high-level signal in the time domain.

[0196] For example, please refer to Figure 5, which is a schematic diagram of another first synchronization signal provided in an embodiment of this application. As shown in Figure 5, the two possible first synchronization signals are described here using three consecutive time-domain symbols (time-domain symbol 1, time-domain symbol 2, and time-domain symbol 3 shown in Figure 5) as an example. It should be noted that the first level signal of each time-domain symbol may include the CP of the first synchronization signal.

[0197] As shown in Figure 5(a), time-domain symbol 1, time-domain symbol 2 and time-domain symbol 3 each include a low-level signal, a high-level signal, a high-level signal and a low-level signal in the time domain, respectively.

[0198] As shown in Figure 5(b), time-domain symbol 1, time-domain symbol 2 and time-domain symbol 3 each include a high-level signal, a low-level signal, a low-level signal and a high-level signal in the time domain, respectively.

[0199] Optionally, the first synchronization signal obtained based on the second on / off control formula described above can be sustained for multiple time-domain symbols. For example, the number of symbols sustained by the first synchronization signal can be 2, 3, 4, 5, etc.

[0200] For example, the number of time-domain symbols for which the first synchronization signal lasts can be 7 or 14, etc. That is, the number of time-domain symbols for which the first synchronization signal lasts can be the number of symbols in half a time slot, or it can be the number of symbols in one time slot. It should be noted that since the CP length of the first time-domain symbol in every seven time-domain symbols is longer than the CP lengths of the other time-domain symbols, and the tag device may not be able to distinguish the CP length of each time-domain symbol after receiving the first synchronization signal, having the first synchronization signal last for multiple time-domain symbols can avoid the problem that the level signal used to measure the chip duration of the first synchronization signal happens to be located in the first time-domain symbol, thus leading to a longer measured chip duration. In this case, after receiving the first synchronization signal, the tag device can still measure the correct chip duration of the first synchronization signal based on the other time-domain symbols besides the first one.

[0201] Optionally, the second switch control described above can be called the OOK-2 system, or it can have other names. This application embodiment does not limit this.

[0202] In the above implementation, since the start and stop level signals of the first synchronization signal on the first time domain symbol have the same level signal type (either high or low), when the level signal at the end of the first time domain symbol is copied to the beginning of that symbol, the level signal copied to the beginning of the first time domain symbol has the same level signal type as the start level signal within the first time domain symbol; that is, the level signal does not change. Thus, the first synchronization signal does not introduce a new rising or falling edge due to the CP (Clipping Edge), thereby avoiding the impact of a newly added rising or falling edge on time-frequency synchronization and improving the time-frequency synchronization effect of the first synchronization signal.

[0203] In method three, where the first synchronization signal is obtained based on the third on / off key control formula, the symbol length of each time-domain symbol can correspond to 2n chip durations. Here, n is a positive integer greater than or equal to 2.

[0204] Optionally, the first synchronization signal, based on the third on / off key control, may include 2n level signals in each time domain symbol.

[0205] In a first optional implementation, the first time-domain symbol may sequentially include 2n level signals in the time domain. Specifically, the first level signal to the second level signal of the first time-domain symbol may be a low level signal, a low level signal, and the third level signal to the 2nth level signal of the first time-domain symbol may be a repeated high level signal and a low level signal, respectively.

[0206] Since the duration of each level signal can be the same, the duration of each level signal in the repeated high-level and low-level signals of the first time-domain symbol is 1 / 2n of the symbol length of the first time-domain symbol, and the sum of the durations of the first two level signals of the first time-domain symbol is 1 / n of the symbol length of the first time-domain symbol.

[0207] It should be noted that the first level signal of the first time domain symbol may include the CP of the first synchronization signal.

[0208] Optionally, the aforementioned repeated high-level and low-level signals can be used to determine the chip duration. Since the repeated high-level and low-level signals do not include CP, the chip duration of the first synchronization signal is equal to the duration of any one of the repeated high-level and low-level signals, i.e., 1 / 2n of the symbol length of the first time-domain symbol.

[0209] Optionally, the first two level signals of the first time-domain symbol can also be used to roughly estimate the chip duration. Since the first level signal of the first time-domain symbol includes the CP, the chip duration of the first synchronization signal is equal to the difference between the sum of the durations of the first two level signals and the CP duration, that is, the difference between 1 / n of the symbol length of the first time-domain symbol and the CP duration.

[0210] In a second alternative implementation, the first time-domain symbol may sequentially include 2n level signals in the time domain. Specifically, the first to the second level signals of the first time-domain symbol are high-level signals, and the third to the 2nth level signals of the first time-domain symbol are repeating low-level signals and high-level signals, respectively.

[0211] Since the duration of each level signal can be the same, the duration of each level signal in the repeated low-level and high-level signals of the first time-domain symbol is 1 / 2n of the symbol length of the first time-domain symbol, and the sum of the durations of the first two level signals of the first time-domain symbol can be 1 / n of the symbol length of the first time-domain symbol.

[0212] It should be noted that the first level signal of the first time domain symbol may include the CP of the first synchronization signal.

[0213] Optionally, the repeated low-level and high-level signals mentioned above can be used to determine the chip duration. Since the repeated low-level and high-level signals do not include CP, the chip duration of the first synchronization signal is equal to the duration of either the repeated low-level or high-level signal, which is 1 / 2n of the symbol length of the first time-domain symbol.

[0214] Optionally, the first two level signals of the first time-domain symbol can also be used to roughly estimate the chip duration. Since the first level signal of the first time-domain symbol includes the CP, the chip duration of the first synchronization signal is equal to the difference between the sum of the durations of the first two level signals and the CP duration, that is, the difference between 1 / n of the symbol length of the first time-domain symbol and the CP duration.

[0215] It should be noted that in possible scenarios, the first synchronization signal can last for multiple time-domain symbols. To distinguish the level signals between two consecutive time-domain symbols, the level signal type of the last level signal of a time-domain symbol can be different from the level signal type of the first level signal of its adjacent next time-domain symbol. For example, assuming the last level signal of the first time-domain symbol is a low-level signal, to distinguish the level signals between the first and second time-domain symbols, the first level signal in the second time-domain symbol can be a high-level signal.

[0216] The following description uses the example of a second time-domain symbol adjacent to the first time-domain symbol, which is also included in at least one time-domain symbol of the first synchronization signal, to illustrate the level signal included in the second time-domain symbol.

[0217] In the first optional implementation of Method 3 described above, the second time-domain symbol may sequentially include 2n level signals in the time domain. Specifically, the first to the second level signals of the second time-domain symbol are high-level signals, and the third to the 2n level signals of the first time-domain symbol are repeating low-level signals and high-level signals, respectively.

[0218] The first level signal of the second time domain symbol may include the CP of the first synchronization signal.

[0219] Optionally, the aforementioned repeated low-level and high-level signals can be used to determine the chip duration of the first synchronization signal. Here, the process of determining the chip duration based on the level signals included in the second time-domain symbol is similar to the process of determining the chip duration based on the level signals included in the first time-domain symbol described above. For details, please refer to the relevant description above, which will not be repeated here.

[0220] In the second optional implementation of Method 3 described above, the second time-domain symbol may sequentially include 2n level signals in the time domain. Specifically, the first to the second level signals of the second time-domain symbol may be low-level signals, and the third to the 2n level signals of the first time-domain symbol may be repeated high-level signals and low-level signals.

[0221] The first level signal of the second time domain symbol may include the CP of the first synchronization signal.

[0222] Optionally, the aforementioned repeated high-level and low-level signals can be used to determine the chip duration of the first synchronization signal. Here, the process of determining the chip duration based on the level signals included in the second time-domain symbol is similar to the process of determining the chip duration based on the level signals included in the first time-domain symbol described above. For details, please refer to the relevant description above, which will not be repeated here.

[0223] Optionally, if the first synchronization signal can last for three or more time domain symbols, the level signal of the first synchronization signal on each time domain symbol can be an interleaving of the level signals of the first time domain symbol and the second time domain symbol.

[0224] For example, the level signal included in the time-domain symbol with an odd number can be the same as the level signal included in the first time-domain symbol, and the level signal included in the time-domain symbol with an even number can be the same as the level signal included in the second time-domain symbol. Again, for example, the level signal included in the time-domain symbol with an odd number can be the same as the level signal included in the second time-domain symbol, and the level signal included in the time-domain symbol with an even number can be the same as the level signal included in the first time-domain symbol.

[0225] For example, in the case where n=2, i.e., each time-domain symbol includes 4 level signals, please refer to Figure 6, which is a schematic diagram of another first synchronization signal provided by an embodiment of this application. As shown in Figure 6, the two possible first synchronization signals are described here using three consecutive time-domain symbols (time-domain symbol 1, time-domain symbol 2, and time-domain symbol 3 shown in Figure 6) as an example. It should be noted that the first level signal of each time-domain symbol may include the CP of the first synchronization signal.

[0226] As shown in Figure 6(a), time-domain symbols 1 and 3 each include a low-level signal, a low-level signal, a high-level signal, and a low-level signal in the time domain, respectively. Time-domain symbol 2 includes a high-level signal, a high-level signal, a low-level signal, and a high-level signal in the time domain, respectively.

[0227] As shown in Figure 6(b), time-domain symbols 1 and 3 each include a high-level signal, a high-level signal, a low-level signal, and a high-level signal in the time domain, respectively. Time-domain symbol 2 includes a low-level signal, a low-level signal, a high-level signal, and a low-level signal in the time domain, respectively.

[0228] For example, in the case where n=3, that is, each time domain symbol includes 6 level signals, please refer to Figure 7, which is a schematic diagram of another first synchronization signal provided by an embodiment of this application. As shown in Figure 7, here we take the first synchronization signal lasting for 2 consecutive time domain symbols (time domain symbol 1 and time domain symbol 2 shown in the figure) as an example to illustrate two possible first synchronization signals. It should be noted that the first level signal of each time domain symbol may include the CP of the first synchronization signal.

[0229] As shown in Figure 7(a), time-domain symbol 1 includes, in the time domain, a low-level signal, a high-level signal, a low-level signal, a high-level signal, and a low-level signal in sequence. Time-domain symbol 2 includes, in the time domain, a high-level signal, a high-level signal, a low-level signal, a high-level signal, a low-level signal, and a high-level signal in sequence.

[0230] As shown in Figure 7(b), time-domain symbol 1 consists of, in the time domain, a high-level signal, a high-level signal, a low-level signal, a high-level signal, a low-level signal, and a high-level signal, in sequence. Time-domain symbol 2 consists of, in the time domain, a low-level signal, a high-level signal, a low-level signal, a high-level signal, and a low-level signal, in sequence.

[0231] In the above implementation, since the start and stop level signals of the first synchronization signal on a time-domain symbol have the same level signal type (either high or low), when the level signal at the end of a time-domain symbol is copied to the beginning of that symbol, the copied level signal at the beginning of the symbol has the same level signal type as the start level signal; that is, the level signal does not change. Thus, the first synchronization signal does not introduce a new rising or falling edge due to the CP (Clipping Probe), thereby avoiding the impact of a newly added rising or falling edge on time-frequency synchronization and improving the time-frequency synchronization effect of the first synchronization signal.

[0232] It should be noted that in the two optional implementations of Method 3 above, the first synchronization signal, consisting of two consecutive low-level signals or two consecutive high-level signals, is located at the beginning of each time-domain symbol. In possible scenarios, the two consecutive low-level signals or two consecutive high-level signals may also be located at the end of each time-domain symbol. The following provides an exemplary description of two possible first synchronization signals in this scenario.

[0233] In a first optional implementation, the first time-domain symbol may sequentially include 2n level signals in the time domain. Specifically, the first level signal to the 2n-2 level signals of the first time-domain symbol are, in sequence, repeated low-level signals and high-level signals, and the last two level signals of the first time-domain symbol may be, in sequence, a low-level signal and a low-level signal.

[0234] Similarly, the second time-domain symbol adjacent to the first time-domain symbol can sequentially include 2n level signals in the time domain. Specifically, the first to 2n-2 level signals of the second time-domain symbol are repeating high-level and low-level signals, respectively, and the last two level signals of the first time-domain symbol can be high-level and high-level signals, respectively.

[0235] In a second alternative implementation, the first time-domain symbol may sequentially include 2n level signals in the time domain. Specifically, the first level signal to the 2n-2 level signals of the first time-domain symbol are sequentially repeated high-level signals and low-level signals, and the last two level signals of the first time-domain symbol can be sequentially high-level signals and high-level signals.

[0236] Similarly, the second time-domain symbol adjacent to the first time-domain symbol can sequentially include 2n level signals in the time domain. Specifically, the first to 2n-2 level signals of the second time-domain symbol are repeating low-level and high-level signals, respectively, and the last two level signals of the first time-domain symbol can be low-level and low-level signals, respectively.

[0237] It should be noted that the first synchronization signal obtained based on the third on / off key control formula may include n-1 high-level signals and n-1 low-level signals in each time domain symbol. Therefore, when n is large, there are more repeated high-level and low-level signals in each time domain symbol. In this case, there are more opportunities for synchronization identification based on the rising and falling edges within each time domain symbol. Thus, it is not necessary for the first synchronization signal to persist for multiple time domain symbols to increase the number of rising and falling edges. That is, a good time-frequency synchronization effect can be achieved even with a shorter duration of the first synchronization signal in fewer time domain symbols, thereby reducing overhead.

[0238] Optionally, the third on / off switch control method described above can be called the OOK-2n system, or it can have other names. This application embodiment does not limit this.

[0239] Optionally, the number of continuous time-domain symbols in the first synchronization signal obtained based on different on / off control methods may be different. For example, if the first synchronization signal obtained based on the OOK-1 standard has k continuous time-domain symbols, then the first synchronization signal obtained based on the OOK-2 standard can also have k continuous time-domain symbols. One or The first synchronization signal obtained based on the OOK-2n standard can have a duration of up to one time-domain symbol. indivual, One or One. Here, Represented as the floor function, it is used to map a real number a to the smallest integer not less than a.

[0240] For example, if the first synchronization signal obtained based on the OOK-1 standard has a duration of 7 time-domain symbols, then the first synchronization signal obtained based on the OOK-2 standard can have a duration of 7 time-domain symbols. The first synchronization signal, obtained based on the OOK-4 standard, has a duration of 4 time-domain symbols. One, that is, two. The first synchronization signal obtained based on the OOK-8 standard can have a duration of up to two time-domain symbols. One, that is, 1.

[0241] In Scenario 2, there are two possible ways to determine the chip duration based on the second sub-synchronization signal. One is that the duration of the high-level signal and / or the duration of the low-level signal included in at least one time domain symbol of the two sub-synchronization signals can be used to determine the chip duration (hereinafter referred to as Method 1). The other is that the information carried by the second sub-synchronization signal in the first time domain symbol can be used to determine the chip duration of the first synchronization signal (hereinafter referred to as Method 2).

[0242] In Method 1, the duration of the high-level signal and / or the duration of the low-level signal included in at least one time-domain symbol of the second sub-synchronization signal can be used to determine the chip duration.

[0243] Optionally, the second sub-synchronization signal can also be obtained based on the three different on / off control methods described in Scenario 1. That is to say, the second sub-synchronization signal is similar to the first synchronization signal described in Scenario 1, as detailed in the previous text, and will not be repeated here.

[0244] Here, the way in which the duration of the high-level signal and / or the duration of the low-level signal included in at least one time domain symbol of the second sub-synchronization signal indicates the chip duration is similar to the way in which the duration of the high-level signal and / or the duration of the low-level signal of the first synchronization signal in the first time domain symbol described in Scenario 1 above indicates the chip duration of the first synchronization signal. For details, please refer to the relevant description above, which will not be repeated here.

[0245] It should be noted that since the second sub-synchronization signal is only used to determine the chip duration and does not need to perform time-frequency synchronization, the second sub-synchronization signal does not need to last for a long time domain symbol to increase the chance of synchronization recognition. For example, when the second sub-synchronization signal is obtained based on the second on / off key control formula in scenario one, the second sub-synchronization signal may last for only one time domain symbol, or it may last for two time domain symbols. This application embodiment does not limit this.

[0246] Method 2: The information carried by the second sub-synchronization signal on the first time domain symbol can be used to determine the chip duration of the first synchronization signal.

[0247] Optionally, the information carried by the first time-domain symbol can be used to indicate the target on / off key control mode, and the target on / off key control mode can be used to indicate the chip duration of the first synchronization signal.

[0248] The information carried by the first time-domain symbol can be determined by the high-level and / or low-level signals it includes. For example, if the first time-domain symbol includes low-level signals and low-level signals sequentially in the time domain, then the information it carries can be represented as 00. As another example, if the first time-domain symbol includes low-level signals and high-level signals sequentially in the time domain, then the information it carries can be represented as 01.

[0249] It should be noted that the target on / off key control mode can be the first on / off key control mode, the second on / off key control mode, or the third on / off key control mode described above. The chip duration indicated by these three on / off key control modes is the symbol length of the first time domain symbol, half of the symbol length of the first time domain symbol, and half of the symbol length of the first time domain symbol, respectively.

[0250] For example, when the information carried by the first time-domain symbol is 00, the target on / off key control mode indicated by it can be the first on / off key control mode, which can then indicate that the chip duration of the first synchronization signal is the symbol length of the first time-domain symbol. As another example, when the information carried by the first time-domain symbol is 01, the target on / off key control mode indicated by it can be the second on / off key control mode, which can then indicate that the chip duration of the first synchronization signal is 1 / 2 of the symbol length of the first time-domain symbol.

[0251] Optionally, the chip duration corresponding to different on / off control modes can be indicated to the tag device by the reader sending instruction information, or it can be agreed upon by the protocol. This application embodiment does not limit this.

[0252] Optionally, in scenario two, the at least one time-domain symbol mentioned above may also include a third time-domain symbol, and the first sub-synchronization signal included in the third time-domain symbol may be used for time-frequency synchronization.

[0253] It should be noted that the at least one high-level signal and / or at least one low-level signal included in the third time-domain symbol can be obtained based on the fourth on-key control formula. The fourth on-key control formula can be the first, second, or third on-key control formula described above, and this application embodiment is not limited to this.

[0254] In other words, the number and position of at least one high-level signal and / or at least one low-level signal included in the third time domain symbol of the first sub-synchronization signal are similar to those of at least one high-level signal and / or at least one low-level signal included in the first time domain symbol of the first synchronization signal described above. For details, please refer to the first synchronization signal described in Scenario 1 above, which will not be repeated here.

[0255] S302, the reader sends a first synchronization signal to the tag device on at least one time domain symbol. Accordingly, the tag device receives the first synchronization signal on at least one time domain symbol.

[0256] In some feasible implementations, after generating the first synchronization signal, the reader can send the first synchronization signal to the tag device on at least one time-domain symbol. Accordingly, the tag device can receive the first synchronization signal on at least one time-domain symbol.

[0257] Optionally, after receiving the first synchronization signal, the tag device can determine the corresponding chip duration based on the duration of the high-level signal and / or the duration of the low-level signal included in the first time domain symbol, or determine the corresponding chip duration based on the information carried by the first synchronization signal in the first time domain symbol. In this way, after determining the chip duration of a first synchronization signal based on the first time domain symbol, the tag device can know the corresponding chip duration in subsequent time domain symbols, and thus correctly identify each chip based on the chip duration, facilitating the demodulation of the information carried by a chip in subsequent time domain symbols.

[0258] The following will describe the process by which the tag device determines the chip duration based on the received first synchronization signal, specifically for scenarios one and two in step S301.

[0259] In the case of Method 1 in Scenario 1 described above, the tag device can determine its chip duration as the symbol length of the first time domain symbol based on the duration of the high-level signal and / or the duration of the low-level signal included in the first time domain symbol by the first synchronization signal.

[0260] In the case of Method 2 in Scenario 1 described above, the tag device can determine its chip duration as 1 / 2 of the symbol length of the first time domain symbol based on the duration of the high-level signal and / or the duration of the low-level signal included in the first time domain symbol by the first synchronization signal, and / or the chip duration is the difference between 1 / 2 of the symbol length of the first time domain symbol and the CP duration.

[0261] In the case of Method 2 in Scenario 1 described above, the tag device can determine its chip duration as 1 / 2n of the symbol length of the first time domain symbol based on the duration of the high-level signal and / or the duration of the low-level signal included in the first time domain symbol by the first synchronization signal, and / or the chip duration is the difference between 1 / n of the symbol length of the first time domain symbol and the CP duration.

[0262] It should be understood that, in the case of Method 1 in Scenario 2 described above, the process by which the tag device determines the chip duration based on the first synchronization signal is similar to the process of determining the chip duration in Scenario 1. For details, please refer to the relevant content above, which will not be repeated here.

[0263] In the scenario 2 described above, under mode 2, the tag device can first determine the target on / off key control formula based on the information carried on the first time domain symbol by the first synchronization signal, and further determine the corresponding chip duration based on the target on / off key control formula. Here, the target on / off key control formula can be used to indicate the chip duration of the first synchronization signal.

[0264] S303, the tag device performs time and frequency synchronization based on the first synchronization signal.

[0265] In some feasible implementations, after receiving the first synchronization signal, the tag device can perform time-frequency synchronization based on the first synchronization signal.

[0266] In this embodiment, the first synchronization signal includes at least one high-level signal and / or at least one low-level signal on the first time-domain symbol. The duration of the high-level signal and / or the duration of the low-level signal on the first time-domain symbol can be used to determine the chip duration of the first synchronization signal. Alternatively, the information carried by the first time-domain symbol can be directly used to determine the chip duration. Through this sequence design, the first synchronization signal can not only be used for time-frequency synchronization but also indicate the chip duration, allowing the tag device to determine the corresponding chip duration after receiving the synchronization signal on the first time-domain symbol. Thus, when receiving the first synchronization signal on subsequent time-domain symbols, each chip can be identified based on the determined chip duration. This facilitates the demodulation of the information carried on each chip by the tag device, avoiding demodulation errors caused by mistaking multiple identical level signals for a single chip, and improving the time-frequency synchronization effect.

[0267] Optionally, the communication method shown in Figure 3 may further include step S304. Optionally, step S304 may be executed before step S301 or step S302, and this embodiment of the application is not limited in this respect. For ease of explanation, the following description assumes that step S304 is executed before step S301.

[0268] S304, the reader sends a first signal to the tag device. Correspondingly, the tag device receives the first signal.

[0269] In some feasible implementations, the reader may generate a first signal and send the first signal to the tag device before sending the first synchronization signal, in order to indicate to the tag device that there is subsequent signaling transmission.

[0270] Wherein, if the first signal may include at least one low-level signal, the start level signal of the first time-domain symbol of the first synchronization signal is a high-level signal.

[0271] Optionally, the first signal includes two possible design methods for the level signals. The first design method is to use only low-level signals, that is, the first signal may include at least one low-level signal. The second design method is to use an interleaved combination of high-level and low-level signals, that is, the first signal includes interleaved high-level and low-level signals.

[0272] Optionally, when the first signal adopts the first design method described above, since the level signals included in the first signal are all low-level signals, the starting level signal of the first synchronization signal in the first time domain symbol can be a high-level signal.

[0273] Optionally, if the first signal adopts the second design method described above, and the termination level signal of the first signal is a high-level signal, then the start level signal of the first synchronization signal in the first time domain symbol can be a low-level signal. If the termination level signal of the first signal is a low-level signal, then the start level signal of the first synchronization signal in the first time domain symbol can be a high-level signal.

[0274] In the above implementation, the termination level signal of the first signal and the start level signal of the first synchronization signal have different signal types. This allows the tag device to distinguish between the first signal and the first synchronization signal after receiving the first synchronization signal. It avoids misidentification of the first synchronization signal by the tag device when the termination level signal and the start level signal of the first synchronization signal have the same signal type, thereby improving the time-frequency synchronization effect. This design approach can also introduce a new rising or falling edge, which can increase the chance of synchronization identification.

[0275] In a possible implementation, when the first synchronization signal is obtained based on the second on / off control method described above, since the duration of the start level signal of the first synchronization signal in the first time domain symbol is the sum of 1 / 4 of the symbol length of the first time domain symbol and the CP duration, in order to avoid the tag device erroneously identifying its chip duration after receiving the first synchronization signal, the level signal types of the start level signal of the first synchronization signal in the first time domain symbol and the end level signal of the first signal can also be the same.

[0276] Optionally, when the first signal adopts the first design method described above, since the level signals included in the first signal are all low-level signals, the starting level signal of the first synchronization signal in the first time domain symbol can also be a low-level signal.

[0277] Optionally, if the first signal adopts the second design method described above, and the termination level signal of the first signal is a high-level signal, then the start level signal of the first synchronization signal in the first time domain symbol can be a high-level signal. If the termination level signal of the first signal is a low-level signal, then the start level signal of the first synchronization signal in the first time domain symbol can be a low-level signal.

[0278] In the above implementation, since the termination level signal of the first signal and the start level signal of the first synchronization signal have the same level signal type, the tag device cannot distinguish between these two level signals. Therefore, a chip duration can be determined based on the duration of these two level signals. This avoids the problem of the tag device misidentifying the chip duration based on the start level signal of the first synchronization signal because the termination level signal of the first signal and the start level signal of the first synchronization signal have different level signal types.

[0279] In the embodiments of this application, the first signal may be called a start-indicator signal, but it may also have other names, which are not limited in the embodiments of this application.

[0280] It should be noted that the preceding description refers to the first synchronization signal used in the R2D transmission process. It should be understood that the second synchronization signal used in the D2R transmission process can also be obtained based on the on / off control method described above. Optionally, the level signals included in the second synchronization signal may be the same as or different from the level signals included in the first synchronization signal.

[0281] The on / off control method used for the second synchronization signal can be either pre-defined by the protocol or indicated by signaling sent by the reader. This application embodiment does not limit this.

[0282] It should be noted that during D2R transmission, since there is no CP (Concurrent Probe) for the second synchronization signal, the level signals included in the second synchronization signal may be different from those included in the first synchronization signal. In possible implementations, the level signals included in the second synchronization signal over at least one time-domain symbol may be interleaved high-level and low-level signals.

[0283] For example, when the second synchronization signal is obtained based on the third on / off key control formula described above, the first time-domain symbol may sequentially include 2n level signals in the time domain. Specifically, the first to the 2nth level signals of the first time-domain symbol are sequentially repeated high-level signals and low-level signals, or the first to the 2nth level signals of the first time-domain symbol are sequentially repeated low-level signals and high-level signals.

[0284] For example, if the first time domain symbol includes four level signals in sequence, please refer to Figure 8, which is a schematic diagram of a second synchronization signal provided in an embodiment of this application. Here, we will explain two possible first synchronization signals by taking the first synchronization signal as lasting for two consecutive time domain symbols (time domain symbol 1 and time domain symbol 2 shown in Figure 8) as an example.

[0285] As shown in Figure 8(a), time-domain symbol 1 includes, in the time domain, a high-level signal, a low-level signal, a high-level signal, and a low-level signal in sequence. Time-domain symbol 2 includes, in the time domain, a high-level signal, a low-level signal, a high-level signal, and a low-level signal in sequence.

[0286] As shown in Figure 8(b), time-domain symbol 1 includes, in the time domain, a low-level signal, a high-level signal, a low-level signal, and a high-level signal in sequence. Time-domain symbol 2 includes, in the time domain, a low-level signal, a high-level signal, a low-level signal, and a high-level signal in sequence.

[0287] The communication method provided by the embodiments of this application has been described in detail above with reference to Figures 3 to 8. The communication device provided by the embodiments of this application will now be described in detail with reference to Figures 9 and 10. It should be understood that the description of the embodiments of the communication device corresponds to the description of the embodiments of the communication method; therefore, any parts not described in detail can be referred to the method embodiments above.

[0288] Please refer to Figure 9, which is a schematic diagram of the structure of a communication device provided in an embodiment of this application. As shown in Figure 9, the communication device 900 may include a transceiver unit 901 and a processing unit 902.

[0289] In some feasible implementations, the communication device 900 may correspond to the tag device mentioned above, or a component (such as a circuit, chip, or chip system) configured in the tag device.

[0290] In a specific implementation, the transceiver unit 901 is used to receive a first synchronization signal on at least one time-domain symbol. Here, each time-domain symbol in the at least one time-domain symbol includes at least one high-level signal and / or at least one low-level signal, and the at least one time-domain symbol includes a first time-domain symbol. The duration of the high-level signal and / or the duration of the low-level signal of the first time-domain symbol are used to determine the chip duration of the first synchronization signal, or the information carried by the first time-domain symbol is used to determine the chip duration of the first synchronization signal. The processing unit 902 is used to perform time-frequency synchronization based on the first synchronization signal.

[0291] In one possible implementation, the first synchronization signal is obtained based on the first on / off key control, and the symbol length of each time-domain symbol corresponds to a chip duration.

[0292] In one possible implementation, the first synchronization signal includes a high-level signal in the (2i-1)th time domain symbol and a low-level signal in the 2ith time domain symbol. Alternatively, the first synchronization signal includes a low-level signal in the (2i-1)th time domain symbol and a high-level signal in the 2ith time domain symbol, where i is a positive integer greater than or equal to 1.

[0293] In one possible implementation, the first synchronization signal is obtained based on the second on / off switch control, and the symbol length of each time-domain symbol corresponds to two chip durations.

[0294] In one possible implementation, the first time-domain symbol sequentially includes a first low-level signal, a first high-level signal, a second high-level signal, and a second low-level signal in the time domain. Here, the sum of the durations of the first low-level signal and the second low-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the first high-level signal and the second high-level signal is half the symbol length of the first time-domain symbol.

[0295] In one possible implementation, the first low-level signal includes a cyclic prefix of the first synchronization signal.

[0296] In one possible implementation, the duration of the first high-level signal and the second high-level signal is used to determine the chip duration.

[0297] In one possible implementation, the first time-domain symbol sequentially includes a third high-level signal, a third low-level signal, a fourth low-level signal, and a fourth high-level signal in the time domain. Here, the sum of the durations of the third high-level signal and the fourth high-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the third low-level signal and the fourth low-level signal is half the symbol length of the first time-domain symbol.

[0298] In one possible implementation, the third high-level signal includes a cyclic prefix of the first synchronization signal.

[0299] In one possible implementation, the duration of the third low-level signal and the fourth low-level signal is used to determine the chip duration.

[0300] In one possible implementation, the first synchronization signal is obtained based on the third on / off key control formula, and the symbol length of each time-domain symbol corresponds to 2n chip durations, where n is a positive integer greater than or equal to 2.

[0301] In one possible implementation, the first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a low level signal, and the third level signal to the 2nth level signal is a repeated high level signal and a low level signal. The repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0302] In one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in sequence in the time domain. The first level signal to the second level signal of the second time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal, respectively. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0303] In one possible implementation, the first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0304] In one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the second time-domain symbol is a low level signal, and the third level signal to the 2n level signal is a repeated high level signal, and the repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0305] In one possible implementation, the transceiver unit 901 is also configured to receive a first signal. Here, if the first signal includes at least one low-level signal, the start-level signal of the first time-domain symbol of the first synchronization signal is a high-level signal.

[0306] In one possible implementation, at least one time-domain symbol includes a third time-domain symbol, which includes at least one high-level signal and / or at least one low-level signal for time-frequency synchronization.

[0307] In one possible implementation, the third time-domain symbol includes at least one high-level signal and / or at least one low-level signal, which is obtained based on a fourth on / off switch control.

[0308] In some feasible implementations, the communication device 900 may correspond to the reader mentioned above, or to a component (such as a circuit, chip, or chip system) configured in the reader.

[0309] In a specific implementation, processing unit 902 is used to generate a first synchronization signal. Here, the first synchronization signal includes at least one high-level signal and / or at least one low-level signal on each of the at least one time-domain symbols. The at least one time-domain symbol includes a first time-domain symbol. The duration of the high-level signal and / or the duration of the low-level signal of the first time-domain symbol are used to determine the chip duration of the first synchronization signal, or the information carried by the first time-domain symbol is used to determine the chip duration of the first synchronization signal. Transceiver unit 901 is used to transmit the first synchronization signal on at least one time-domain symbol.

[0310] In one possible implementation, the first synchronization signal is obtained based on the first on / off key control, and the symbol length of each time-domain symbol corresponds to a chip duration.

[0311] In one possible implementation, the first synchronization signal includes a high-level signal in the (2i-1)th time domain symbol and a low-level signal in the 2ith time domain symbol. Alternatively, the first synchronization signal includes a low-level signal in the (2i-1)th time domain symbol and a high-level signal in the 2ith time domain symbol, where i is a positive integer greater than or equal to 1.

[0312] In one possible implementation, the first synchronization signal is obtained based on the second on / off switch control, and the symbol length of each time-domain symbol corresponds to two chip durations.

[0313] In one possible implementation, the first time-domain symbol sequentially includes a first low-level signal, a first high-level signal, a second high-level signal, and a second low-level signal in the time domain. Here, the sum of the durations of the first low-level signal and the second low-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the first high-level signal and the second high-level signal is half the symbol length of the first time-domain symbol.

[0314] In one possible implementation, the first low-level signal includes a cyclic prefix of the first synchronization signal.

[0315] In one possible implementation, the duration of the first high-level signal and the second high-level signal is used to determine the chip duration.

[0316] In one possible implementation, the first time-domain symbol sequentially includes a third high-level signal, a third low-level signal, a fourth low-level signal, and a fourth high-level signal in the time domain. Here, the sum of the durations of the third high-level signal and the fourth high-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the third low-level signal and the fourth low-level signal is half the symbol length of the first time-domain symbol.

[0317] In one possible implementation, the third high-level signal includes a cyclic prefix of the first synchronization signal.

[0318] In one possible implementation, the duration of the third low-level signal and the fourth low-level signal is used to determine the chip duration.

[0319] In one possible implementation, the first synchronization signal is obtained based on the third on / off key control formula, and the symbol length of each time-domain symbol corresponds to 2n chip durations, where n is a positive integer greater than or equal to 2.

[0320] In one possible implementation, the first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a low level signal, and the third level signal to the 2nth level signal is a repeated high level signal and a low level signal. The repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0321] In one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in sequence in the time domain. The first level signal to the second level signal of the second time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal, respectively. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0322] In one possible implementation, the first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0323] In one possible implementation, at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the second time-domain symbol is a low level signal, and the third level signal to the 2n level signal is a repeated high level signal, and the repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes a cyclic prefix of the first synchronization signal.

[0324] In one possible implementation, the transceiver unit 901 is also used to transmit a first signal. Here, if the first signal includes at least one low-level signal, the start-level signal of the first time-domain symbol of the first synchronization signal is a high-level signal.

[0325] In one possible implementation, at least one time-domain symbol includes a third time-domain symbol, which includes at least one high-level signal and / or at least one low-level signal for time-frequency synchronization.

[0326] In one possible implementation, the third time-domain symbol includes at least one high-level signal and / or at least one low-level signal, which is obtained based on a fourth on / off switch control.

[0327] Please refer to Figure 10, which is a schematic diagram of another communication device provided in this application. This communication device 1000 can be used to implement the operations performed by the first device, the second device, or the sensing device in the above embodiments; alternatively, the communication device 1000 can be the first device, the second device, or the sensing device described above. The communication device 1000 includes: a processor 1001, a memory 1002, and a bus system 1003.

[0328] The memory 1002 includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM). The memory 1002 is used to store related instructions and data. The memory 1002 stores executable modules or data structures, or subsets thereof, or extended sets thereof:

[0329] Operation instructions: This includes various operation instructions used to perform various operations.

[0330] Operating system: includes various system programs used to implement various basic business functions and handle hardware-based tasks.

[0331] Figure 10 shows only one memory, but of course, multiple memories can be set as needed.

[0332] In one possible implementation, the communication device 1000 may include only the processor 1001 and the bus system 1003, that is, it may exclude the memory 1002.

[0333] The communication device 1000 may further include a transceiver 1004. The transceiver 1004 may be a communication module or a transceiver circuit. In the embodiments of this application, the transceiver 1004 is used to perform the message sending and receiving operations described in the above embodiments.

[0334] Processor 1001 may be configured with at least one, specifically it may be a controller, central processing unit (CPU), general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, transistor logic device, hardware component, or any combination thereof. Processor 1001 may also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of DSP and microprocessor, etc.

[0335] In specific applications, the various components of the communication device 1000 are coupled together through a bus system 1003. The bus system 1003 includes not only a data bus but may also include a power bus, a control bus, and a status signal bus. However, for clarity, all buses are labeled as bus system 1003 in Figure 10. For ease of illustration, Figure 10 is only schematically shown.

[0336] In specific implementation, the communication device 1000 can execute the steps of the method performed by the first device, the second device, or the sensing device in the above embodiments. Specifically, when the communication device 1000 is used to implement the various steps performed by the first device, the second device, or the sensing device in the communication method provided in the embodiments, the processor 1001 can implement the function of the processing unit 902, and the transceiver 1004 can implement the function of the transceiver unit 901.

[0337] It should be noted that in practical applications, the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0338] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be ROM, programmable read-only memory (PROM), EPROM, electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be RAM, which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory described in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0339] This application also provides a computer-readable medium having a computer program stored thereon, which, when executed by a computer, implements the method steps performed by the tag device or reader in the above embodiments.

[0340] This application also provides a computer program product that, when executed by a computer, implements the method steps performed by the tag device or reader in the above embodiments.

[0341] This application also provides a chip including at least one processor. The at least one processor is configured to execute computer execution instructions to cause a device on which the chip is mounted to perform the method steps performed by the tag device or reader in the above embodiments.

[0342] Optionally, the chip may also include interface circuitry. This interface circuitry is used to receive computer execution instructions and transmit them to the processor.

[0343] This application also provides a chip system including a processor for supporting the device on which the chip system is installed to implement the method steps performed by the tag device or reader in the above embodiments, such as generating or processing the data and / or information involved in the above methods. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for the data transmitting device. The chip system may be composed of chips or may include chips and other discrete devices.

[0344] Optionally, the chip system may also include interface circuitry. This interface circuitry can be used to receive computer-executed instructions and transmit them to the processor.

[0345] Please refer to Figure 11, which is a schematic diagram of another communication device provided in an embodiment of this application. The communication device 1100 may include a processor 1101 and an interface circuit 1102. The interface circuit 1102 can be used to receive signals from other communication devices besides the communication device 1100 and transmit them to the processor 1101, or to send signals from the processor 1101 to other communication devices besides the communication device 1100. The processor 1101 can be used to execute computer programs or instructions through logic circuits to implement the communication methods described in the preceding embodiments.

[0346] In some possible designs, the communication device 1100 may be the tag device described above, or a device including the tag device described above, or a device contained in the tag device described above, such as a chip system. The communication device 1100 may also be the reader described above, or a device of the reader described above, or a device contained in the reader described above.

[0347] This application also provides a communication system, which includes at least the tag device and reader described above. The tag device and reader work together to implement the communication method described in the preceding embodiments.

[0348] In the above method embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0349] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0350] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

[0351] The above description is merely a preferred embodiment of the technical solution of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A communication method, characterized in that, The method includes: A first synchronization signal is received on at least one time-domain symbol, wherein each of the at least one time-domain symbols includes at least one high-level signal and / or at least one low-level signal, the at least one time-domain symbol includes a first time-domain symbol, the duration of the high-level signal and / or the duration of the low-level signal of the first time-domain symbol is used to determine the chip duration of the first synchronization signal, or the information carried by the first time-domain symbol is used to determine the chip duration of the first synchronization signal; Time and frequency synchronization is performed based on the first synchronization signal.

2. The method according to claim 1, characterized in that, The first synchronization signal is obtained based on the first on / off key control formula, and the symbol length of each time domain symbol corresponds to one chip duration.

3. The method according to claim 2, characterized in that, The first synchronization signal includes a high-level signal in the (2i-1)th time domain symbol and a low-level signal in the 2ith time domain symbol; Alternatively, the first synchronization signal may include a low-level signal in the (2i-1)th time domain symbol and a high-level signal in the 2ith time domain symbol, where i is a positive integer greater than or equal to 1.

4. The method according to claim 1, characterized in that, The first synchronization signal is obtained based on the second on / off key control formula, and the symbol length of each time domain symbol corresponds to the duration of two chips.

5. The method according to claim 4, characterized in that, The first time-domain symbol includes, in the time domain, a first low-level signal, a first high-level signal, a second high-level signal, and a second low-level signal, wherein the sum of the durations of the first low-level signal and the second low-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the first high-level signal and the second high-level signal is half the symbol length of the first time-domain symbol.

6. The method according to claim 5, characterized in that, The first low-level signal includes a cyclic prefix of the first synchronization signal.

7. The method according to claim 5 or 6, characterized in that, The duration of the first high-level signal and the second high-level signal is used to determine the chip duration.

8. The method according to claim 4, characterized in that, The first time-domain symbol includes, in the time domain, a third high-level signal, a third low-level signal, a fourth low-level signal, and a fourth high-level signal, wherein the sum of the durations of the third high-level signal and the fourth high-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the third low-level signal and the fourth low-level signal is half the symbol length of the first time-domain symbol.

9. The method according to claim 8, characterized in that, The third high-level signal includes a cyclic prefix of the first synchronization signal.

10. The method according to claim 8 or 9, characterized in that, The duration of the third low-level signal and the fourth low-level signal is used to determine the chip duration.

11. The method according to claim 1, characterized in that, The first synchronization signal is obtained based on the third on / off key control formula, and the symbol length of each time domain symbol corresponds to the duration of 2n chips, where n is a positive integer greater than or equal to 2.

12. The method according to claim 11, characterized in that, The first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a low level signal, and the third level signal to the 2nth level signal is a repeated high level signal and a low level signal. The repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes the cyclic prefix of the first synchronization signal.

13. The method according to claim 12, characterized in that, The at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the second time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes the cyclic prefix of the first synchronization signal.

14. The method according to claim 11, characterized in that, The first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes the cyclic prefix of the first synchronization signal.

15. The method according to claim 14, characterized in that, The at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the second time-domain symbol is a low level signal, and the third level signal to the 2n level signal is a repeated high level signal, and the repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes the cyclic prefix of the first synchronization signal.

16. The method according to any one of claims 1-15, characterized in that, The method further includes: The first signal is received, the first signal including at least one low-level signal, and the start level signal of the first time domain symbol of the first synchronization signal is a high-level signal.

17. The method according to claim 1, characterized in that, The at least one time-domain symbol includes a third time-domain symbol, which includes at least one high-level signal and / or at least one low-level signal for time-frequency synchronization.

18. The method according to claim 17, characterized in that, The third time-domain symbol includes at least one high-level signal and / or at least one low-level signal, which are obtained based on the fourth on / off switch control formula.

19. A communication method, characterized in that, The method includes: A first synchronization signal is generated, wherein the first synchronization signal includes at least one high-level signal and / or at least one low-level signal in each time domain symbol of at least one time domain symbol, the at least one time domain symbol including a first time domain symbol, the duration of the high-level signal and / or the duration of the low-level signal of the first time domain symbol is used to determine the chip duration of the first synchronization signal, or the information carried by the first time domain symbol is used to determine the chip duration of the first synchronization signal. The first synchronization signal is transmitted on at least one time domain symbol.

20. The method according to claim 19, characterized in that, The first synchronization signal is obtained based on the first on / off key control formula, and the symbol length of each time domain symbol corresponds to one chip duration.

21. The method according to claim 20, characterized in that, The first synchronization signal includes a high-level signal in the (2i-1)th time domain symbol and a low-level signal in the 2ith time domain symbol; Alternatively, the first synchronization signal may include a low-level signal in the (2i-1)th time domain symbol and a high-level signal in the 2ith time domain symbol, where i is a positive integer greater than or equal to 1.

22. The method according to claim 19, characterized in that, The first synchronization signal is obtained based on the second on / off key control formula, and the symbol length of each time domain symbol corresponds to the duration of two chips.

23. The method according to claim 22, characterized in that, The first time-domain symbol includes, in the time domain, a first low-level signal, a first high-level signal, a second high-level signal, and a second low-level signal, wherein the sum of the durations of the first low-level signal and the second low-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the first high-level signal and the second high-level signal is half the symbol length of the first time-domain symbol.

24. The method according to claim 23, characterized in that, The first low-level signal includes a cyclic prefix of the first synchronization signal.

25. The method according to claim 23 or 24, characterized in that, The duration of the first high-level signal and the second high-level signal is used to determine the chip duration.

26. The method according to claim 22, characterized in that, The first time-domain symbol includes, in the time domain, a third high-level signal, a third low-level signal, a fourth low-level signal, and a fourth high-level signal, wherein the sum of the durations of the third high-level signal and the fourth high-level signal is half the symbol length of the first time-domain symbol, and the sum of the durations of the third low-level signal and the fourth low-level signal is half the symbol length of the first time-domain symbol.

27. The method according to claim 26, characterized in that, The third high-level signal includes a cyclic prefix of the first synchronization signal.

28. The method according to claim 26 or 27, characterized in that, The duration of the third low-level signal and the fourth low-level signal is used to determine the chip duration.

29. The method according to claim 19, characterized in that, The first synchronization signal is obtained based on the third on / off key control formula, and the symbol length of each time domain symbol corresponds to the duration of 2n chips, where n is a positive integer greater than or equal to 2.

30. The method according to claim 29, characterized in that, The first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a low level signal, and the third level signal to the 2nth level signal is a repeated high level signal and a low level signal. The repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes the cyclic prefix of the first synchronization signal.

31. The method according to claim 30, characterized in that, The at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the second time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes the cyclic prefix of the first synchronization signal.

32. The method according to claim 29, characterized in that, The first time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the first time-domain symbol is a high level signal, and the third level signal to the 2nth level signal is a repeating low level signal and a high level signal. The repeating low level signal and high level signal are used to determine the chip duration. The first level signal of the first time-domain symbol includes the cyclic prefix of the first synchronization signal.

33. The method according to claim 32, characterized in that, The at least one time-domain symbol further includes a second time-domain symbol adjacent to the first time-domain symbol. The second time-domain symbol includes 2n level signals in the time domain. The first level signal to the second level signal of the second time-domain symbol is a low level signal, and the third level signal to the 2n level signal is a repeated high level signal, and the repeated high level signal and low level signal are used to determine the chip duration. The first level signal of the second time-domain symbol includes the cyclic prefix of the first synchronization signal.

34. The method according to claims 19-33, characterized in that, The method further includes: A first signal is sent, the first signal including at least one low-level signal, and the start level signal of the first time domain symbol of the first synchronization signal is a high-level signal.

35. The method according to claim 19, characterized in that, The at least one time-domain symbol includes a third time-domain symbol, which includes at least one high-level signal and / or at least one low-level signal for time-frequency synchronization.

36. The method according to claim 35, characterized in that, The third time-domain symbol includes at least one high-level signal and / or at least one low-level signal, which are obtained based on the fourth on / off switch control formula.

37. A communication device, characterized in that, The communication device is used to implement the communication method according to any one of claims 1-18, or the communication method according to any one of claims 19-36.

38. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, implements the communication method according to any one of claims 1-18, or the communication method according to any one of claims 19-36.

39. A chip system, characterized in that, Including the processor; The processor is configured to execute computer execution instructions to cause a device equipped with the chip system to perform the communication method of any one of claims 1-18, or the communication method of any one of claims 19-36.

40. The chip system according to claim 39, characterized in that, The chip system also includes an interface circuit, which is used to receive computer execution instructions and transmit them to the processor.

41. A computer program product, characterized in that, The computer program product is executed by a computer using the communication method according to any one of claims 1-18, or the communication method according to any one of claims 19-36.

42. A communication device, characterized in that, It includes at least one processor for executing a computer program stored in a memory, such that the communication device performs the communication method of any one of claims 1-18, or the communication method of any one of claims 19-36.

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