Embedded controller, debugger, interface controller, chip, and electronic device

Abstract

Embodiments of the present application provide an embedded controller, a debugger, an interface controller, a chip, and an electronic device. The embedded controller comprises: a bus interface circuit; a processor which communicates with a host processor by means of the bus interface circuit; and a debugging circuit which communicates with a debugger by means of the bus interface circuit, and is used for debugging the embedded controller on the basis of a debugging instruction of the debugger.

Description

Embedded controller, debugger, interface controller, chip and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411086483.1, filed on August 8, 2024, and entitled "Embedded controller, debugger, interface controller, chip and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of electronic circuits, in particular to an embedded controller, a debugger, an interface controller, a chip and an electronic device. BACKGROUND

[0003] An embedded controller (EC) is an embedded master control chip hung on the bus of a host CPU. The EC can be applied to electronic devices such as notebook computers, which can help the electronic devices manage low-speed peripherals such as touchpads and matrix keyboards. In addition, the electronic devices can perform power management through the EC, for example, in a notebook computer, the power supply for turning on and off can be controlled, and the notebook computer can be controlled to hibernate and then wake up.

[0004] It is necessary to debug the EC. In the related art, when debugging the EC, the electronic device needs to be disassembled, and then a debugging interface of the EC chip is soldered out, and then a debugger dedicated to the EC is connected through an Inter-Integrated Circuit (I2C), a Serial Wire Debug (SWD) or a Joint Test Action Group (JTAG) protocol to enter a debugging mode to analyze code problems. The disassembly is not convenient for EC debugging, and the debugging interfaces of various ECs are not unified, which increases the debugging cost. TECHNICAL PROBLEM

[0005] The embodiments of the present application provide an embedded controller, a debugger, an interface controller, a chip and an electronic device to solve the problem of non-uniform interface of the embedded controller and the need to disassemble and solder a debugging interface. TECHNICAL SOLUTION

[0006] The technical solution of the present application is as follows:

[0007] In a first aspect, the embodiments of the present application provide an embedded controller, comprising: a bus interface circuit; a processor communicating with a host processor through the bus interface circuit; a debugging circuit communicating with a debugger through the bus interface circuit, configured to debug the embedded controller according to a debugging instruction of the debugger.

[0008] In a second aspect, the embodiments of the present application provide an interface controller, comprising: an identification module, configured to identify a device type of a device connected to an interface; and a control module, configured to control a multiplexer to connect the interface to a bus in a case that the device type is a debugger used to debug an embedded controller, the bus being a bus between the embedded controller and a host processor.

[0009] In a third aspect, the embodiments of the present application provide a chip, comprising the above-mentioned embedded controller or the above-mentioned interface controller.

[0010] In a fourth aspect, the embodiments of the present application provide an electronic device, comprising a device body and a host processor, an embedded controller connected to the host processor through a bus, an interface, a multiplexer having one end connected to the bus, and an interface controller.

[0011] In a fifth aspect, the embodiments of the present application provide a debugger, comprising: a first interface, configured to be connected to a second interface of an electronic device, wherein the second interface is connectable to a bus between an embedded controller and a host processor; and a control circuit, connected to the first interface, configured to listen to bus packets on the bus between the embedded controller and the host processor, and / or communicate with the embedded controller through the bus to debug the embedded controller.

[0012] These and other aspects of the present application will become more apparent from the following description. Advantageous Effects

[0013] The embedded controller provided by the embodiments of the present application can avoid non-uniform interfaces of the embedded controller by using the bus interface circuit of the embedded controller as a debugging interface, and can reduce debugging costs without disassembling and welding a debugging interface.

[0014] The interface controller provided by the embodiments of the present application can connect the interface and the bus between the embedded controller and the host processor through the interface controller, so that the debugger connected to the interface can communicate with the embedded controller and listen to bus packets on the bus, without disassembling and welding a debugging interface, and can reduce debugging costs.

[0015] The electronic device provided by the embodiments of the present application can communicate between the debugger and the embedded controller through the bus interface circuit of the embedded controller as a debugging interface, and can connect the interface and the bus between the embedded controller and the host processor through the interface controller, so that the debugger connected to the interface can communicate with the embedded controller and listen to bus packets on the bus, without disassembling and welding a debugging interface, and can reduce debugging costs.

[0016] The embedded controller, the debugger, the interface controller, the chip and the electronic device provided by the embodiments of the present application can reduce the debugging cost by using the bus interface circuit of the embedded controller as the debugging interface without disassembling and welding the debugging interface. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description only represent some embodiments of the present application, and all other drawings obtained by those skilled in the art without creative effort based on these drawings also belong to the protection scope of the present application.

[0018] FIG. 1 shows a schematic diagram of an embedded controller according to an embodiment of the present application.

[0019] FIG. 2 shows a schematic diagram of another embedded controller according to an embodiment of the present application.

[0020] FIG. 3 shows a schematic diagram of an interface controller according to an embodiment of the present application.

[0021] FIG. 4 shows a schematic diagram of an electronic device according to an embodiment of the present application.

[0022] FIG. 5 shows a schematic diagram of a debugger according to an embodiment of the present application.

[0023] Embodiments of the present application

[0024] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the drawings, in which the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0025] In order to enable those skilled in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application.

[0026] In the embodiments of the present application, it should be noted that in this document, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations.

[0027] Also, the use of "or" means "and / or" in all possible senses, unless the context clearly indicates otherwise; the use of "comprise", "comprises" or "comprising" means "includes", "including" or "include" in all possible senses, unless the context clearly indicates otherwise; and the use of "a" or "an" means "one or more" in all possible senses, unless the context clearly indicates otherwise.

[0028] In the description of the embodiments of the present application, the words "example" or "for example" or similar words do not mean that a specific example or design scheme is preferred over another specific example or design scheme. The use of the words "example" or "for example" or similar words is intended to present one or more relative concepts in a clear manner.

[0029] In addition, "multiple" in the embodiments of the present application means two or more, and therefore "multiple" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C means that A, B, C, A and B, A and C, B and C, or A and B and C can be included.

[0030] It should be noted that in the embodiments of the present application, the association relationship of the associated objects described by "and / or" means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents a "or" relationship between the associated objects before and after it.

[0031] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.

[0032] Figure 1 shows a schematic diagram of an embedded controller according to an embodiment of the present application. As shown in Figure 1, the embedded controller 100 according to an embodiment of the present application can include a bus interface circuit 101, a processor 102, and a debugging circuit 103. The processor 102 communicates with a host processor 200 through the bus interface circuit 101, and the debugging circuit 103 communicates with a debugger 300 through the bus interface circuit 101. The debugging circuit 103 is configured to debug the embedded controller 100 according to a debugging instruction of the debugger 300.

[0033] In an embodiment of the present application, the processor 102 and the host processor 200 are connected through a bus. The bus can include, but is not limited to, an LPC (Low Pin Count) bus, an SPI (Serial Peripheral Interface) bus, an eSPI (Enhanced Serial Peripheral Interface) bus, etc. Correspondingly, the bus interface circuit 101 can include an LPC slave circuit, an SPI slave circuit, or an eSPI slave circuit; and the host processor 200 can include an LPC master circuit, an SPI master circuit, or an eSPI master circuit. When the processor 102 communicates with the host processor 200, bus data packets (e.g., LPC data packets, SPI data packets, eSPI data packets, etc.) are transmitted through the bus. When the debugging circuit 103 communicates with the debugger 300 through the bus interface circuit 101, bus data packets (e.g., LPC data packets, SPI data packets, eSPI data packets, etc.) are transmitted through the bus.

[0034] In an embodiment of the present application, the debugging circuit 103 is connected to the bus interface circuit 101. The debugging circuit 103 communicates with the debugger 300 through the bus interface circuit 101, so that the debugger 300 can listen to the bus data packets on the bus between the processor 102 and the host processor 200, and thus record the bus data packets between the processor 102 and the host processor 200. For example, the debugger 300 can obtain a BIOS (Basic Input Output System) debug code from the bus data packets between the processor 102 and the host processor 200, and determine a BIOS startup condition according to the BIOS debug code.

[0035] In some embodiments, the debugger 300 can send a debugging instruction to the bus interface circuit 101, so that the debugging circuit 103 debugs the embedded controller 100 according to the debugging instruction of the debugger 300.

[0036] As an implementation, the bus interface circuit 101 can identify the received instruction, and in the case that the instruction is a debugging instruction, forward the received instruction to the debugging circuit 103. The debugging circuit 103 debugs the embedded controller 100 according to the debugging instruction forwarded by the bus interface circuit 101. If the instruction received by the bus interface circuit 101 is not a debugging instruction, the received instruction is not forwarded to the debugging circuit 103.

[0037] As another implementation, the bus interface circuit 101 forwards the received instruction to the debugging circuit 103, and the debugging circuit 103 identifies the received instruction, and in the case that the received instruction is a debugging instruction, debugs the embedded controller 100 according to the debugging instruction.

[0038] As an example, the debugger 300 can burn firmware to the embedded controller 100, the debugger 300 can send a second debugging instruction for burning firmware, and the debugging circuit 103 can burn firmware to the embedded controller 100 according to the second debugging instruction. With this technical solution, firmware update and other operations can be realized without disassembling. For example, referring to FIG. 2, a flash memory 106 is arranged in the embedded controller 100, the flash memory 106 can be used to store firmware, and the debugging circuit 103 can burn firmware to the flash memory 106 according to the second debugging instruction.

[0039] Optionally, the bus interface circuit 101 identifies the received instruction, and in the case that the instruction is a second debugging instruction for burning firmware, forwards the received second debugging instruction to the debugging circuit 103, and the debugging circuit 103 burns firmware to the embedded controller 100 according to the second debugging instruction.

[0040] Optionally, the bus interface circuit 101 forwards the received instruction to the debugging circuit 103, and the debugging circuit 103 identifies the received instruction, and in the case that the instruction is a second debugging instruction for burning firmware, burns firmware to the embedded controller 100 according to the second debugging instruction.

[0041] As an example, referring to FIG. 2, the embedded controller 100 can include one or more peripheral modules 104. Taking a notebook computer as an example, the peripheral modules 104 can include a fingerprint control module, a power supply monitoring module, a keyboard control module, an atmosphere lamp control module, a fan control module, a breathing lamp control module, etc. The debugger 300 can access one or more peripheral modules 104 of the embedded controller 100, the debugger 300 can send a first debugging instruction for accessing one or more peripheral modules 104, and the debugging circuit 103 can access the corresponding peripheral module 104 according to the first debugging instruction, for example, perform a read operation on a peripheral register of the peripheral module 104. With this technical solution, the debugging circuit 103 can access the corresponding peripheral module 104 according to the first debugging instruction.

[0042] Optionally, the bus interface circuit 101 identifies the received instruction, and forwards the received first debug instruction to the debug circuit 103 in the case that the instruction is a first debug instruction for accessing one or more peripheral modules 104, and the debug circuit 103 accesses the corresponding peripheral module 104 according to the first debug instruction.

[0043] Optionally, the bus interface circuit 101 forwards the received instruction to the debug circuit 103, and the debug circuit 103 identifies the received instruction, and accesses the corresponding peripheral module 104 according to the first debug instruction in the case that the instruction is a first debug instruction for accessing one or more peripheral modules 104.

[0044] As an example, referring to FIG. 2, the embedded controller 100 can include a memory 105, the debugger 300 can access the memory 105 of the embedded controller 100, the debugger 300 can send a third debug instruction for accessing the memory 105, and the debug circuit 103 can access the memory 105 according to the third debug instruction, for example, perform a read operation on the memory 105.

[0045] Optionally, the bus interface circuit 101 identifies the received instruction, and forwards the received third debug instruction to the debug circuit 103 in the case that the received instruction is a third debug instruction for accessing the memory 105, and the debug circuit 103 accesses the memory 105 according to the third debug instruction.

[0046] Optionally, the bus interface circuit 101 forwards the received instruction to the debug circuit 103, and the debug circuit 103 identifies the received instruction, and accesses the memory 105 according to the third debug instruction in the case that the instruction is the third debug instruction.

[0047] In some embodiments, the bus interface circuit 101 can directly access one or more peripheral modules 104, etc. according to the instructions of the host processor 200. The debugger 300 can use the same instructions to access one or more peripheral modules 104, etc., and the access process can not pass through the debug circuit 103. For example, taking an eSPI bus as an example, the host processor 200 and the debugger 300 can act as eSPI masters, and the bus interface circuit 101 can act as an eSPI slave. The host processor 200 and the debugger 300 can send instructions to access peripheral registers of the peripheral module 104, etc., and the bus interface circuit 101 can access the peripheral registers of the peripheral module 104, etc. based on the instructions.

[0048] In some embodiments, referring to FIG. 2, the embedded controller 100 can further include a control module 107. The control module 107 is configured to acquire the device type of the device connected to the interface, and control the multiplexer to connect the interface and the bus between the embedded controller 100 and the host processor 200 in the case that the device type is a debugger used for debugging the embedded controller 100. The control module 107 can be a circuit or program code executed by the processor 102, and the embodiments are not limited in this regard. As an embodiment, the control module 107 can be an interface controller. For example, the interface controller can be a PD (Power delivery) controller.

[0049] As an embodiment, the control module 107 can acquire the device type of the device connected to the interface from the host processor 200. The host processor 200 can send the device type to the embedded controller 100 in the case that the host processor 200 identifies that the device type of the device connected to the interface is a debugger. The control module 107 can control the multiplexer to connect the interface and the bus between the embedded controller 100 and the host processor 200 in the case that the control module 107 receives the device type of the debugger. In this way, the debugger 300 can be connected to the bus, can monitor the bus packets on the bus, and can communicate with the bus interface circuit 101.

[0050] In some embodiments, the device type of the device connected to the interface can be identified by the interface controller. The multiplexer can be controlled to connect the interface and the bus between the embedded controller 100 and the host processor 200 in the case that the device type is a debugger used for debugging the embedded controller.

[0051] In some embodiments, the interface controller is integrated in the embedded controller 100, and the control module 107 can be the interface controller. For example, the interface can be a USB Type C interface, the interface controller can be a PD (Power delivery) controller, and the PD controller can be integrated in the embedded controller 100.

[0052] FIG. 3 shows a schematic block diagram of an interface controller according to an embodiment of the present application. As shown in FIG. 3, the interface controller 400 can include an identification module 401 and a control module 402. The identification module 401 is configured to identify the device type of the device connected to the interface 500. The control module 402 is connected to the identification module 401 and is configured to control the multiplexer 600 to connect the interface and the bus in the case that the device type is a debugger used for debugging the embedded controller, the bus being a bus between the embedded controller and the host processor.

[0053] In some embodiments, the interface 500 is a USB Type C interface. The multiplexer 600 can include a plurality of channels, one of which is a channel between the interface 500 and the bus described above, and can further include other channels, for example, a channel between the interface 500 and a USB controller, a channel between the interface 500 and a DP (Display Port) controller, which are not limited in the embodiments of the present application. For example, when the device type of the device connected to the interface 500 is a USB device, the multiplexer 600 connects the interface 500 to the USB controller for USB communication; when the device type of the device connected to the interface 500 is a DP device, the multiplexer 600 connects the interface 500 to the DP controller for DP communication.

[0054] In the embodiments of the present application, the pins of the interface are multiplexed as the pins of the bus. Taking the eSPI bus and the USB Type C interface as an example, the pins of the eSPI bus can include: a clock signal pin, a chip select signal pin, a reset signal pin, a warning signal pin, and four data pins. The pins of the USB Type C interface can include 24 pins. In the embodiments of the present application, part of the 24 pins are used as the pins of the bus, and the bus signals are transmitted through these pins.

[0055] In some embodiments, the interface controller 400 is a PD (Power delivery) controller. The PD controller can perform CC pin (configuration channel pin) detection to obtain the device type of the device connected to the USB Type C interface, and in the case where the device type is a debugger, control the multiplexer 600 to connect the USB Type C interface and the bus between the embedded controller and the host processor.

[0056] In some embodiments, the interface controller 400 as shown in FIG. 3 can be integrated into the embedded controller 100 as shown in FIG. 1 and FIG. 2, and the interface controller 400 can implement the functions of the control module 107 as shown in FIG. 2.

[0057] The embodiments of the present application provide an electronic device, as shown in FIG. 4, the electronic device 700 can include: an embedded controller 710, a host processor 720, a multiplexer 730, an interface controller 740, and an interface 750. Although separate circuit modules are shown by wireframes in FIG. 4, in the embodiments of the present application, one or more modules can be integrated, which are not limited in the embodiments of the present application. For example, the embedded controller 710 and the interface controller 740 can be integrated.

[0058] Referring to FIG. 4, the embedded controller 710 is connected with the host processor 720 through a bus. The multiplexer 730 is connected with the interface 750, one channel of the multiplexer 730 is connected with the bus between the embedded controller 710 and the host processor 720, and when the multiplexer 730 switches to the channel, a path is formed between the interface 750 and the bus, and bus communication can be performed.

[0059] Referring to FIG. 4, the interface controller 740 can identify the device type of the device connected with the interface 750, and in the case that the device type is the debugger 300 used for debugging the embedded controller, the multiplexer 730 is controlled to connect the interface 750 and the bus between the embedded controller 710 and the host processor 720. The debugger 300 can perform bus communication with the embedded controller 710 through the interface 750 and the bus. In the embodiment of the present application, the debugger 300 debugs the embedded controller 710 through bus communication.

[0060] In some embodiments, as shown in FIG. 4, the embedded controller 710 can include a bus interface circuit 711, a processor 712 and a debugging circuit 713. The processor 712 communicates with the host processor 720 through the bus interface circuit 711, and the debugging circuit 713 communicates with the debugger 300 through the bus interface circuit 711. The debugger 300 can send a bus data packet carrying a debugging instruction. The debugging circuit 713 can debug the embedded controller 710 according to the debugging instruction of the debugger 300.

[0061] In the embodiment of the present application, the processor 712 is connected with the host processor 720 through a bus, and the bus can include but is not limited to an LPC (Low Pin Count, referred to as LPC for short) bus, an SPI (Serial Peripheral Interface, referred to as SPI for short) bus, an eSPI (Enhanced Serial Peripheral Interface, referred to as eSPI for short) bus, etc. Correspondingly, the bus interface circuit 711 can include an LPC slave circuit, an SPI slave circuit or an eSPI slave circuit; the host processor 720 can include an LPC master circuit, an SPI master circuit or an eSPI master circuit. When the processor communicates with the host processor 720, a bus data packet (for example, an LPC data packet, an SPI data packet, an eSPI data packet, etc.) is transmitted through the bus. When the debugging circuit 713 communicates with the debugger 300 through the bus interface circuit 711, a bus data packet (for example, an LPC data packet, an SPI data packet, an eSPI data packet, etc.) is transmitted through the bus.

[0062] In some embodiments, the interface 750 can be a USB Type-C interface. The multiplexer 730 can include a plurality of channels, one of which is a channel between the interface 750 and the bus described above, and can further include other channels, such as a channel between the interface 750 and a USB controller, a channel between the interface 750 and a DP controller, without limitation. For example, when the device type of the device connected to the interface 750 is a USB device, the multiplexer 730 connects the interface 750 to the USB controller to perform USB communication; when the device type of the device connected to the interface 750 is a DP device, the multiplexer 730 connects the interface 750 to the DP controller to perform DP communication.

[0063] In some embodiments, the interface controller 740 is a PD controller. The PD controller can perform CC pin (configuration channel pin) detection to obtain the device type of the device connected to the USB Type-C interface, and in the case where the device type is a debugger, control the multiplexer 730 to connect the USB Type-C interface and the embedded controller 710 to the bus between the host processor 720.

[0064] In some embodiments, the debugger 300 can send a debugging instruction to the bus interface circuit 711 to cause the debugging circuit 713 to debug the embedded controller 710 according to the debugging instruction of the debugger 300. As an embodiment, the bus interface circuit 711 can identify the received instruction, and in the case where the instruction is a debugging instruction, forward the received instruction to the debugging circuit 713. The debugging circuit 713 debugs the embedded controller 710 according to the debugging instruction forwarded by the bus interface circuit 711. If the received instruction is not a debugging instruction, the received instruction is not forwarded to the debugging circuit 713.

[0065] As an example, the debugger 300 can burn firmware to the embedded controller 710, and the debugger 300 can send a second debugging instruction for burning the firmware, and the debugging circuit 713 can burn the firmware to the embedded controller 710 according to the second debugging instruction. Alternatively, the bus interface circuit 711 identifies the received instruction, and in the case where the instruction is the second debugging instruction for burning the firmware, forwards the received instruction to the debugging circuit 713. For example, referring to FIG. 4, a flash memory (Flash) 716 is provided in the embedded controller 710, which can be used to store firmware, and the debugging circuit 713 can burn the firmware to the flash memory 716 according to the second debugging instruction. With this technical solution, firmware update and other operations can be performed without disassembling the device.

[0066] As an example, referring to FIG. 4, the embedded controller 710 can include one or more peripheral modules 714, for example, the peripheral modules 714 can include a fingerprint control module, a power monitoring module, a keyboard control module, an atmosphere light control module, a fan control module, a breathing light control module, etc. The debugger 300 can access one or more peripheral modules 714 of the embedded controller 710, the debugger 300 can send a first debugging instruction for accessing the one or more peripheral modules 714, the debugging circuit 713 can access the corresponding peripheral module 714 according to the first debugging instruction, for example, perform a read operation on a peripheral register of the peripheral module 714. Optionally, the bus interface circuit 711 identifies the received instruction, in a case where the instruction is the first debugging instruction for accessing the one or more peripheral modules 714, forwards the received instruction to the debugging circuit 713. With this technical solution, the debugging circuit 103 can access the corresponding peripheral module 714 according to the first debugging instruction.

[0067] As an example, referring to FIG. 4, the embedded controller 100 can include a memory 715, the debugger 300 can access the memory 715 of the embedded controller 710, the debugger 300 can send a third debugging instruction for accessing the memory 715, the debugging circuit 713 can access the memory 715 according to the third debugging instruction, for example, perform a read operation on the memory 715. Optionally, the bus interface circuit 711 identifies the received instruction, in a case where the instruction is the third debugging instruction for accessing the memory 715, forwards the received instruction to the debugging circuit 713.

[0068] In some embodiments, the bus interface circuit 711 can directly access one or more peripheral modules 714, etc. according to an instruction of the host processor 720. The debugger 300 can use the same instruction to access the one or more peripheral modules 714, etc., and the access process can not pass through the debugging circuit 713. As an example, taking an eSPI bus as an example, the host processor 720 and the debugger 300 can act as an eSPI master, the bus interface circuit 711 can act as an eSPI slave, the host processor 720 and the debugger 300 can send an instruction to access a peripheral register of the peripheral module 714, etc., and the bus interface circuit 711 can access the peripheral register of the peripheral module 714, etc. based on the instruction.

[0069] The embodiment of the present application provides a kind of debugger, as shown in Figure 5, debugger 300 can include: first interface 301 and control circuit 302.First interface 301 is used to connect with the second interface of electronic equipment, wherein, referring to Figure 4, the second interface (interface 750) can be connected with the bus between embedded controller 710 and host processor 720.Control circuit 302 is connected with first interface 301.In some embodiments, referring to Figure 5, control circuit 302 can listen to the bus data packet between embedded controller 710 and host processor 720.In some embodiments, referring to Figure 5, control circuit 302 can communicate with embedded controller 710 by bus, to debug embedded controller 710.First interface 301 can be USB type C interface.

[0070] In some embodiments, control circuit 302 can send bus data packet carrying debugging instruction to embedded controller by bus, and receive bus data packet sent by embedded controller.

[0071] As an example, referring to Figure 5 and Figure 4, debugger 300 can burn firmware to embedded controller 710, control circuit 302 can send second debugging instruction for burning firmware, and debugging circuit 713 can burn firmware in embedded controller 710 according to the second debugging instruction.Using this technical solution, firmware update and other operations can be realized without disassembling.

[0072] As an example, referring to Figure 5 and Figure 4, debugger 300 can access one or more peripheral modules 714 of embedded controller 710, control circuit 302 can send first debugging instruction for accessing one or more peripheral modules 714, and debugging circuit 713 can access corresponding peripheral module 714 according to the first debugging instruction, for example, read operation is carried out to peripheral register of peripheral module 714.Using this technical solution, debugger 300 can access peripheral module, and debugging circuit 103 can access corresponding peripheral module 714 according to the first debugging instruction.

[0073] As an example, referring to Figure 5 and Figure 4, debugger 300 can access memory 715 of embedded controller 710, control circuit 302 can send third debugging instruction for accessing memory 715, and debugging circuit 713 can access memory 715 according to the third debugging instruction, for example, read operation is carried out to memory 715.

[0074] In some embodiments, the bus interface circuit 711 can directly access one or more peripheral modules 714 and the like according to instructions of the host processor 720. The control circuit 302 of the debugger 300 can use the same instructions to access one or more peripheral modules 714 and the like, which can not pass through the debugging circuit 713. For example, the host processor 720 and the debugger 300 can act as an eSPI master, the bus interface circuit 711 can act as an eSPI slave, the host processor 720 and the control circuit 302 can send instructions to access peripheral registers of the peripheral module 714 and the like, and the bus interface circuit 711 can access the peripheral registers of the peripheral module 714 and the like based on the instructions.

[0075] In some embodiments, the debugger 300 can listen to bus packets between the embedded controller 710 and the host processor 720. For example, the control circuit 302 can obtain BIOS debugging codes from the bus packets between the embedded controller 710 and the host processor 720, and determine the BIOS startup condition according to the BIOS debugging codes. For example, when listening to the bus packets between the embedded controller 710 and the host processor 720, the debugger 300 can act as an eSPI slave.

[0076] In some embodiments, as shown in FIG. 5, the control circuit 302 can include a bus interface circuit 303 and a microcontroller 304. The bus interface circuit 303 receives and sends bus packets. The microcontroller 304 executes a debugging program, and when a debugging instruction is generated, carries the debugging instruction in a bus packet through the bus interface circuit 303 and sends it.

[0077] Embodiments of the present application also provide a chip, which includes the above-mentioned embedded controller and interface control circuit. The chip is also called an integrated circuit (IC), which can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. The chip uses the bus interface circuit through which the embedded controller communicates with the host processor as a debugging interface, without the need to disassemble and solder the debugging interface, which can reduce the debugging cost.

[0078] The application further provides an electronic device, which comprises a device main body and a chip as described above arranged in the device main body. The electronic device can be, but is not limited to, a car central control screen, a car, a smart wearable device, a mobile terminal and a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, a cervical vertebra massage instrument. The mobile terminal includes, but is not limited to, a smart phone, a notebook computer, a tablet computer and a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper and a smart lamp. The electronic device uses a bus interface circuit of an embedded controller and a host processor as a debugging interface, does not need to disassemble and weld the debugging interface, and can reduce the debugging cost.

[0079] The above is only a preferred embodiment of the application, and does not limit the application in any form. Although the application has been disclosed as the above preferred embodiment, it is not intended to limit the application. Any person skilled in the art can make some changes or modifications to the equivalent embodiments with the above disclosed technical content without departing from the scope of the application. Any modification, change and modification of the above embodiments according to the technical essence of the application are still within the scope of the application.

Claims

1. An embedded controller, characterized by The embedded controller comprises: a bus interface circuit; a processor in communication with a host processor through the bus interface circuit; a debugging circuit in communication with a debugger through the bus interface circuit, configured to debug the embedded controller according to a debugging instruction of the debugger.

2. The embedded controller of claim 1, wherein, The bus interface circuit is configured to identify a received instruction, and forward the instruction to the debugging circuit in a case where the instruction is a debugging instruction.

3. The embedded controller of claim 1 or 2, wherein, Further comprising: one or more peripheral modules; the debugging instruction comprises a first debugging instruction for accessing the one or more peripheral modules; the debugging circuit is further configured to access a corresponding peripheral module according to the first debugging instruction.

4. The embedded controller of claim 1 or 2, wherein, the debugging instruction comprises a second debugging instruction for burning firmware; and the debugging circuit is further configured to burn firmware in the embedded controller according to the second debugging instruction.

5. The embedded controller of claim 1 or 2, wherein, Further comprising: a memory; the debugging instruction comprises a third debugging instruction for accessing the memory; the debugging circuit is further configured to access the memory according to the third debugging instruction.

6. The embedded controller of claim 1, wherein, Further comprising: one or more peripheral modules; the bus interface circuit is further configured to access the one or more peripheral modules according to an instruction of the debugger.

7. The embedded controller of claim 1, wherein, Further comprising: a control module configured to acquire a device type of a device connected to an interface, and control a multiplexer to connect the interface to a bus in a case where the device type is a debugger for debugging an embedded controller, the bus being a bus between the embedded controller and a host processor.

8. An interface controller, comprising: Comprising: an identification module configured to identify a device type of a device connected to an interface; a control module configured to control a multiplexer to connect the interface to a bus in a case where the device type is a debugger for debugging an embedded controller, the bus being a bus between the embedded controller and a host processor.

9. The interface controller of claim 8, wherein, The interface is a USB Type-C interface.

10. An interface controller as claimed in claim 8 or 9, characterized in that The interface controller is a PD controller.

11. A chip, characterized by The embedded controller comprises any one of the above claims 1-7, and / or the interface controller of the above claims 8, 9 or 10.

12. An electronic device, comprising: The device comprises a device body and the following components arranged on the device body: a host processor; the embedded controller of any one of the above claims 1-7, the embedded controller being connected to the host processor through a bus; an interface; a multiplexer, one end of the multiplexer being connected to the bus; the interface controller of the above claims 8, 9 or 10.

13. A debugger, characterized in that, Comprising: a first interface configured to be connected to a second interface of an electronic device, wherein the second interface can be connected to a bus between an embedded controller and a host processor; a control circuit connected to the first interface, configured to listen to a bus packet between the embedded controller and the host processor, and / or communicate with the embedded controller through the bus to debug the embedded controller.

14. The debugger of claim 13, wherein, The control circuit is configured to send a bus packet carrying a debugging instruction to the embedded controller through the bus, and receive a bus packet sent by the embedded controller.

15. The debugger of claim 13, wherein, The control circuit is configured to acquire the BIOS debugging code from a bus data packet between the embedded controller and the host processor, and determine the BIOS startup condition according to the BIOS debugging code.

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