Semiconductor device

Abstract

Provided is a semiconductor device capable of reading data from a ferroelectric capacitor having a small amount of polarization. The semiconductor device includes first to fourth transistors, first and second capacitive elements, and first and second inverters. A first terminal of the first capacitive element is connected to a first terminal of each of the first and second transistors and to an input terminal of the first inverter. A first terminal of the second capacitive element is connected to a first terminal of each of the second and third transistors and to an input terminal of the second inverter. An output terminal of the first inverter is connected to a second terminal of each of the first and second transistors. An output terminal of the second inverter is connected to a second terminal of each of the third and fourth transistors. A gate of each of the first and third transistors is connected to first wiring. A gate of each of the second and fourth transistors is connected to second wiring.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] In recent years, development of FeRAM (Ferroelectric Random Access Memory) including a ferroelectric capacitor has been progressing. A ferroelectric capacitor is a capacitor in which a ferroelectric dielectric is sandwiched between a pair of electrodes. The direction of the dielectric polarization moment can be determined by applying an external voltage, and the direction of the dielectric polarization moment in the dielectric is maintained even when the external voltage is 0 V (the characteristic of generating remanent polarization). By applying this characteristic, it is possible to fabricate a memory (non-volatile memory) that can retain data even without applying a voltage. Furthermore, Patent Document 1 discloses a read circuit for reading data from a ferroelectric memory cell (a memory element including a ferroelectric capacitor) and a read method thereof.

[0004] JP 2003-132671 A

[0005] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0006] Patent Document 1 describes that the amount of polarization held by a ferroelectric capacitor actually decreases during memory retention, and also mentions that when the amount of polarization decreases, the memory window in the ferroelectric capacitor becomes smaller, making accurate reading difficult.

[0007] Furthermore, as the number of rewrites increases, a ferroelectric capacitor experiences a wake-up phenomenon in which the amount of polarization increases, or a fatigue phenomenon in which the amount of polarization decreases. In particular, the decrease in the amount of polarization due to the fatigue phenomenon reduces the memory window of the ferroelectric capacitor, and ultimately makes it difficult to read data from the ferroelectric capacitor. In other words, the fatigue phenomenon places a limit on the number of times data can be written to or read from the ferroelectric capacitor.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device capable of reading data from a ferroelectric capacitor having a small amount of polarization.An object of one embodiment of the present invention is to provide a semiconductor device having a high driving speed.An object of one embodiment of the present invention is to provide a semiconductor device having a reduced circuit area.An object of one embodiment of the present invention is to provide a memory device including the above-described semiconductor device.An object of one embodiment of the present invention is to provide a memory device having a large number of writable and readable times in a ferroelectric capacitor.An object of one embodiment of the present invention is to provide a novel semiconductor device or a novel memory device.

[0009] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0010] As described above, the polarization amount of a ferroelectric capacitor increases or decreases as the number of rewrites increases. For example, the polarization amount when logic "1" data is stored in the ferroelectric capacitor and the polarization amount when logic "0" data is stored in the ferroelectric capacitor each decrease as the number of rewrites increases. When data is read from the ferroelectric capacitor, the potential applied to the write and read wiring is determined by one of the two polarization amounts described above.

[0011] In conventional circuits, this potential is compared with a reference potential for reading to determine whether the logic of the read data is "1" or "0." However, as the polarization amount of the data held by the ferroelectric capacitor decreases, the memory window also becomes smaller. For example, the potential, which is originally higher than the reference potential for reading, may become lower than the reference potential for reading as the number of rewrites increases. Conversely, the potential, which is lower than the reference potential for reading, may become higher than the reference potential for reading as the number of rewrites increases. In this way, the relationship between the potential and the reference potential for reading may change as the number of rewrites increases.

[0012] Therefore, a circuit configuration is proposed that enables generation of a reference potential for reading according to the number of times of rewriting, and amplification of the read potential to a high level potential or a low level potential by comparing the reference potential with the read potential.

[0013] (1) One aspect of the present invention is a semiconductor device including a first cell, a second cell, a third cell, a circuit, and a first transistor. Each of the first cell to the third cell includes a ferroelectric capacitor. The first cell stores first data, the second cell stores second data, and the third cell stores third data. The second data and the third data have mutually inverted logic. The circuit also includes a first terminal and a second terminal.

[0014] The first cell has a function of applying a first potential corresponding to first data to the first wiring by a read operation, the second cell has a function of applying a second potential corresponding to second data to the second wiring by a read operation, and the third cell has a function of applying a third potential corresponding to third data to the third wiring by a read operation.

[0015] When the first transistor is turned on, the first transistor has the function of redistributing charge between the second wiring and the third wiring and generating a fourth potential based on the second potential and the third potential.

[0016] The circuit has a function of establishing a conductive state between the first wiring and the first terminal to obtain a first potential from the first terminal and establishing a conductive state between the second wiring and the second terminal to obtain a fourth potential from the second terminal. The circuit also has a function of establishing a conductive state between the second wiring and the first terminal to redistribute charge between the second wiring and the first terminal to change the first potential to a fifth potential and establishing a conductive state between the first wiring and the second terminal to redistribute charge between the first wiring and the second terminal to change the fourth potential to a sixth potential. The circuit also has a function of amplifying the fifth potential of the first terminal to one of a high-level potential and a low-level potential and amplifying the sixth potential of the second terminal to the other of a high-level potential and a low-level potential, depending on the magnitude relationship between the amount of change from the first potential to the fifth potential at the first terminal and the amount of change from the fourth potential to the sixth potential at the second terminal.

[0017] (2) Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, a first inverter, and a second inverter.

[0018] One of a pair of electrodes of the first capacitor, one of the source or drain of the first transistor, one of the source or drain of the fourth transistor, and the input terminal of the first inverter are electrically connected to each other. One of a pair of electrodes of the second capacitor, one of the source or drain of the second transistor, one of the source or drain of the third transistor, and the input terminal of the second inverter are electrically connected to each other. The other of the source or drain of the first transistor, the other of the source or drain of the second transistor, and the output terminal of the first inverter are electrically connected to each other. The other of the source or drain of the third transistor, the other of the source or drain of the fourth transistor, and the output terminal of the second inverter are electrically connected to each other. The gates of the first transistor and the third transistor are each electrically connected to a first wiring, and the gates of the second transistor and the fourth transistor are each electrically connected to a second wiring.

[0019] (3) Alternatively, in one aspect of the present invention, in the above (2), a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor may be included.

[0020] In particular, it is preferable that the other of the pair of electrodes of the first capacitor, one of the source or drain of the fifth transistor, and one of the source or drain of the sixth transistor are electrically connected to each other. It is also preferable that the other of the pair of electrodes of the second capacitor, one of the source or drain of the seventh transistor, and one of the source or drain of the eighth transistor are electrically connected to each other. It is also preferable that the other of the source or drain of the fifth transistor and the other of the source or drain of the seventh transistor are electrically connected to a third wiring. It is also preferable that the other of the source or drain of the sixth transistor and the other of the source or drain of the eighth transistor are electrically connected to a fourth wiring. It is also preferable that the gate of the fifth transistor and the gate of the eighth transistor are electrically connected to a fifth wiring. It is also preferable that the gate of the sixth transistor and the gate of the seventh transistor are electrically connected to a sixth wiring.

[0021] (4) Alternatively, according to one aspect of the present invention, in the above-described (3), the first cell, the second cell, the third cell, and a ninth transistor may be included. In particular, each of the first cell to the third cell preferably includes a third capacitor and a tenth transistor.

[0022] In each of the first to third cells, one of the source or drain of the tenth transistor is preferably electrically connected to one of the first terminals of the third capacitance element. Furthermore, in the first cell, the other of the source or drain of the tenth transistor is preferably electrically connected to the third wiring. Furthermore, in the second cell, the other of the source or drain of the tenth transistor is preferably electrically connected to the fourth wiring. Furthermore, in the third cell, the other of the source or drain of the tenth transistor is preferably electrically connected to the seventh wiring. Furthermore, it is preferable that one of the source or drain of the ninth transistor is electrically connected to the fourth wiring, and that the other of the source or drain of the ninth transistor is electrically connected to the seventh wiring.

[0023] (5) Alternatively, in one aspect of the present invention, in the above-mentioned (4), the third capacitance element may be a ferroelectric capacitor. In particular, it is preferable that the material that can have ferroelectricity and is sandwiched between the pair of electrodes of the third capacitance element has an oxide containing one or both of hafnium and zirconium.

[0024] (6) In one embodiment of the present invention, in the above-described (4), each of the first to tenth transistors may be an n-channel transistor. In particular, each of the first to tenth transistors preferably includes an oxide containing indium in a channel formation region.

[0025] (7) Alternatively, according to one aspect of the present invention, in the above (2), the first inverter may include an eleventh transistor and a twelfth transistor, and the second inverter may include a thirteenth transistor and a fourteenth transistor. In particular, it is preferable that the eleventh transistor and the thirteenth transistor are p-channel transistors, and it is preferable that the twelfth transistor and the fourteenth transistor are n-channel transistors.

[0026] The gates of the 11th transistor and the 12th transistor function as input terminals of the first inverter, and one of the source or drain of the 11th transistor and one of the source or drain of the 12th transistor function as output terminals of the first inverter. The gates of the 13th transistor and the 14th transistor function as input terminals of the second inverter, and one of the source or drain of the 13th transistor and one of the source or drain of the 14th transistor function as output terminals of the second inverter.

[0027] (8) Alternatively, according to one embodiment of the present invention, in the above (7), the 11th transistor and the 13th transistor may each include silicon in a channel formation region, and the 12th transistor and the 14th transistor may each include an oxide containing indium in a channel formation region.

[0028] (9) Alternatively, in one embodiment of the present invention, in the above-described (7), each of the eleventh to fourteenth transistors may include silicon in a channel formation region.

[0029] (10) Alternatively, according to one aspect of the present invention, in any one of the above (2) to (9), a fourth capacitor and a fifth capacitor may be provided.

[0030] In particular, it is preferable that the first terminal of the fifth capacitive element is electrically connected to the first terminal of the first capacitive element, one of the source or drain of the first transistor, one of the source or drain of the fourth transistor, and the input terminal of the first inverter. It is also preferable that the first terminal of the fourth capacitive element is electrically connected to the first terminal of the second capacitive element, one of the source or drain of the second transistor, one of the source or drain of the third transistor, and the input terminal of the second inverter. It is also preferable that the second terminal of the fourth capacitive element is electrically connected to the other of the source or drain of the first transistor, the other of the source or drain of the second transistor, and the output terminal of the first inverter. It is also preferable that the second terminal of the fifth capacitive element is electrically connected to the other of the source or drain of the third transistor, the other of the source or drain of the fourth transistor, and the output terminal of the second inverter.

[0031] In the configuration (1) above, the first cell is a memory cell for writing or reading, and the second cell and the third cell are memory cells for generating a reference potential for reading. Since the data stored in the second cell and the third cell are logically inverted, a second potential is applied to the second wiring as a read potential for the second data of the second cell, and a third potential is applied to the third wiring as a read potential for the third data of the third cell, thereby turning on the first transistor, thereby generating a fourth potential as a potential intermediate between the second potential and the third potential. The fourth potential is treated as the reference potential for reading.

[0032] Furthermore, in the circuit (1) described above, when the change from the first potential to the fifth potential is either an increase or a decrease, the change from the fourth potential to the sixth potential is either an increase or a decrease. In other words, when the change from the first potential to the fifth potential is either a positive voltage or a negative voltage, the change from the fourth potential to the sixth potential is either a positive voltage or a negative voltage. Here, the difference between the change from the first potential to the fifth potential and the change from the fourth potential to the sixth potential is greater than the difference between the first potential and the fourth potential. Therefore, it is easier to compare the change from the first potential to the fifth potential with the change from the fourth potential to the sixth potential than to the first potential and the fourth potential. This makes it easier to determine whether the logic of the first data stored in the first cell is "0" or "1."

[0033] As described above, even if the number of rewrites is large, for example, even if the amount of polarization of the ferroelectric capacitor in the first cell is small, the first data held in the first cell can be read.

[0034] According to one embodiment of the present invention, a semiconductor device capable of reading data from a ferroelectric capacitor having a small amount of polarization can be provided. According to another embodiment of the present invention, a semiconductor device having a high driving speed can be provided. According to another embodiment of the present invention, a semiconductor device having a reduced circuit area can be provided. According to another embodiment of the present invention, a memory device including the semiconductor device described above can be provided. According to another embodiment of the present invention, a memory device having a large number of writable and readable times in a ferroelectric capacitor can be provided. According to another embodiment of the present invention, a novel semiconductor device or a novel memory device can be provided.

[0035] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0036] FIG. 1 is a circuit diagram showing an example of a driving circuit. FIG. 2 is a block diagram showing an example of a memory device. FIGS. 3A and 3B are circuit diagrams showing an example of a circuit included in a memory device. FIG. 4 is a timing chart showing an example of an operation of a memory device. FIG. 5 is a timing chart showing an example of an operation of a memory device. FIG. 6 is a timing chart showing an example of an operation of a memory device. FIG. 7 is a circuit diagram showing an example of a driving circuit. FIG. 8 is a circuit diagram showing an example of a driving circuit. FIGS. 9A and 9B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 9C is a cross-sectional view illustrating an indium oxide film. FIG. 10 is a schematic perspective view showing an example of a configuration of a memory device. FIGS. 11A and 11B are schematic plan views showing an example of a configuration of a circuit included in a memory device. FIG. 12 is a schematic plan view showing an example of a configuration of a circuit included in a memory device. FIGS. 13A and 13B are schematic plan views showing an example of a configuration of a circuit included in a memory device. FIG. 14 is a schematic cross-sectional view showing an example of a configuration of a semiconductor device. FIG. 15 is a schematic cross-sectional view showing an example of a configuration of a transistor included in a semiconductor device. 16A and 16B are cross-sectional schematic views showing an example of the configuration of a transistor included in a semiconductor device. FIGS. 17A, 17B, and 17C are cross-sectional schematic views showing an example of the configuration of a transistor included in a semiconductor device. FIG. 18 is a perspective schematic view showing an example of the configuration of a transistor included in a semiconductor device. FIGS. 19A and 19B are cross-sectional schematic views showing an example of the configuration of a capacitive element included in a semiconductor device. FIGS. 20A, 20B, 20C, and 20D are diagrams showing an example of electronic components. FIGS. 21A and 21B are diagrams showing an example of electronic equipment, and FIG. 21C is a diagram showing an example of a mainframe computer. FIG. 22 is a diagram showing an example of space equipment. FIG. 23 is a diagram showing an example of a storage system applicable to a data center. 24A1, 24A2, 24A3, 24A4, 24A5, 24A6, 24A7 and 24B1, 24B2, 24B3, 24B4, 24B5, and 24B6 are circuit diagrams for explaining electrical connections.

[0037] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component that houses a chip in a package. For example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0038] In this specification, "connection" includes, for example, "electrical connection."

[0039] When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, for example, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0040] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0041] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 24A1 and 24A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 24A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0042] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 24A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 24A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0043] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 24A6 and 24A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 24A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 24A6 and 24A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0044] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0045] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 24B1, 24B2, and 24B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 24B4 and 24B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," even when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 24B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0046] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0047] Even when independent components are shown connected to each other in a circuit diagram, a single component may have the functions of multiple components. For example, if a portion of a "wiring" also functions as an "electrode," a single conductive film has both the functions of a "wiring" and an "electrode." Furthermore, if a portion of a "wiring" also functions as a "terminal," a single conductive film has both the functions of a "wiring" and a "terminal." Therefore, two or more selected from "electrode," "wiring," and "terminal" may be said to be integrally formed with each other. Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases. Therefore, the term "connection" in this specification also includes cases in which a single conductive film has the functions of multiple components.

[0048] The switches described in this specification are described as having the function of being turned on or off and controlling whether or not a current flows, or as having the function of selecting and switching the path through which a current flows.

[0049] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0050] In addition, in this specification, the terms "conductive" or "conductive state" used when conductive layers are in direct contact with each other refer to a state in which a current can flow between the conductive layers, for example.

[0051] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0052] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits that combine these. An example of a mechanical switch is a switch that uses MEMS (Micro Electro Mechanical Systems) technology. Such a switch has a mechanically movable electrode, and operates by controlling the on state and off state by the movement of the electrode.

[0053] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" are sometimes interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain is sometimes referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain is sometimes referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, in this specification, when a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0054] For example, an example of a transistor described herein may include a multi-gate transistor with two or more gate electrodes. The multi-gate structure connects the channel formation regions in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the transistor's breakdown voltage (reliability). Alternatively, the multi-gate structure can provide a flat Id-Vds characteristic when operating in the saturation region of the Id (source-drain current)-Vds (drain-source voltage) characteristic, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing the flat Id-Vds characteristic, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0055] In this specification, the term "capacitive element" refers to a circuit element including a dielectric and a pair of conductors sandwiching the dielectric. The term "pair of conductors" in "capacitive element" can be replaced with "pair of electrodes," "pair of conductive layers," "pair of conductive regions," "pair of regions," "pair of terminals," etc. The terms "one of the pair of electrodes" and "the other of the pair of electrodes" may be referred to as a first terminal and a second terminal, respectively.

[0056] Generally, the threshold voltage of a transistor is a voltage between the subthreshold region (weak inversion region) and the strong inversion region, and can also be said to be the voltage at which switching between the subthreshold region and the strong inversion region occurs. In addition, as an example of a method for measuring the threshold voltage, Id is calculated based on the Id-Vgs (gate-source voltage) characteristic. １／２ -Vgs characteristics are plotted, and Id １／２ Id on the tangent line where the slope of the -Vgs characteristic is maximum １／２ As another example, in the Id-Vgs characteristic where the drain potential is 1.2 V, Id=1.0×10 −１２ A is set as the threshold voltage.

[0057] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected in series. For example, when a circuit diagram shows one capacitance element, this includes two or more capacitance elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0058] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. A terminal, a wiring, etc. can also be referred to as a node.

[0059] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the counter may be omitted in the claims. For example, a component with an ordinal number "first" in one embodiment of this specification may be a component with a different ordinal number such as "second" or "third" in other embodiments or claims. Furthermore, for example, a component with an ordinal number "first" in one embodiment of this specification may be omitted in other embodiments or claims.

[0060] In addition, timing charts may be used in this specification to explain an operation method of a semiconductor device. The timing charts used in this specification illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. For example, to clearly illustrate the timing charts, two or more overlapping signals may be intentionally shifted.

[0061] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0062] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0063] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0064] Embodiment 1 In this embodiment, a memory device of one embodiment of the present invention and a reading circuit that can be included in the memory device will be described.

[0065] 2 is a block diagram illustrating a configuration example of a memory device MDV according to one embodiment of the present invention. The memory device MDV includes, for example, a cell array MCA, a cell array MCAr, a control circuit CTLD, a driver circuit WRBD, a driver circuit RFWD, a driver circuit RQD, a driver circuit RFPD, a driver circuit SAS, a driver circuit WRWD, and a driver circuit PD.

[0066] As an example, the cell array MCA has a plurality of memory cells MC. Specifically, the memory cells MC are arranged in a matrix of m rows and n columns (m and n are each an integer of 1 or greater) in the cell array MCA. Note that the cell array MCA in FIG. 2 only shows the memory cell MC[1,1] located in the first row and first column, the memory cell MC[m,1] located in the mth row and first column, the memory cell MC[1,n] located in the first row and nth column, and the memory cell MC[m,n] located in the mth row and nth column, and does not show memory cells MC other than those mentioned above.

[0067] In addition, in the cell array MCA, each of the wirings WL[1] to WL[m] extends in the row direction, each of the wirings PL[1] to PL[m] extends in the row direction, and each of the wirings BL[1] to BL[n] extends in the column direction.

[0068] In this specification, for the sake of simplicity, the memory cell MC located in the i-th row and j-th column will be referred to as memory cell MC[i,j] using variables i and j. Note that i is an integer between 1 and m, and j is an integer between 1 and n. Similarly, the wiring WL and wiring PL extending in the i-th row will be referred to as wiring WL[i] and wiring PL[i], respectively, using variable i. Furthermore, the wiring BL extending in the j-th column will be referred to as wiring BL[j] using variable j. Note that the respective symbols for memory cell MC[i,j], wiring WL[i], wiring PL[i], and wiring BL[j] are not shown in FIG. 2. Furthermore, symbols other than those mentioned above that use variables i and j may not be shown in FIG. 2.

[0069] In FIG. 2, the memory cell MC[i,j] is connected to, for example, a wiring WL[i], a wiring PL[i], and a wiring BL[j].

[0070] 2, each of the wirings WL[1] to WL[m] is connected to the driver circuit WRWD, and each of the wirings PL[1] to PL[m] is connected to the driver circuit PD. The wiring BL[j] is connected to a circuit SA[j] included in the driver circuit SAS. The circuit SA[j] will be described later.

[0071] As an example, the cell array MCAr has a plurality of memory cells MCr0 and a plurality of memory cells MCr1. Specifically, in the cell array MCAr of FIG. 2, n memory cells MCr0 and n memory cells MCr1 are arranged alternately in the row direction. That is, in the cell array MCAr, the memory cells MCr0 and MCr1 are arranged in a matrix of 1 row and 2n columns. That is, when k is an integer between 1 and 2n, and k is an odd number, the memory cell MCr0[(k+1) / 2] is arranged in the k-th column of the cell array MCAr, and when k is an even number, the memory cell MCr1[k / 2] is arranged in the k-th column of the cell array MCAr. In addition, the cell array MCAr in Figure 2 shows only the memory cell MCr0[1] located in the first column, the memory cell MCr1[1] located in the second column, the memory cell MCr0[n] located in the 2n-1th column, and the memory cell MCr1[n] located in the 2nth column, and does not show memory cells MCr0 and MCr1 other than those mentioned above.

[0072] In the cell array MCAr, the wiring WLr extends in the row direction, the wiring PLr extends in the row direction, the wiring REQ extends in the row direction, and the wirings RFL[1] to RFL[n] and the wirings RFLB[1] to RFLB[n] extend in the column direction.

[0073] For example, memory cell MCr0[j] is connected to wiring WLr, wiring PLr, and wiring RFL[j], and memory cell MCr1[j] is connected to wiring WLr, wiring PLr, and wiring RFLB[j].

[0074] Furthermore, the cell array MCAr includes n transistors M21, and FIG. 2 shows transistor M21[1] and transistor M21[n].

[0075] A first terminal of the transistor M21[j] is connected to the wiring RFL[j], a second terminal of the transistor M21[j] is connected to the wiring RFLB[j], and gates of the transistors M21[1] to M21[n] are connected to the wiring REQ.

[0076] The transistor M21[j] functions as a switching transistor. Specifically, the transistor M21[j] has a function of bringing the wiring RFL[j] and the wiring RFLB[j] into a conductive state or a non-conductive state.

[0077] 2 illustrates the transistor M21[j] as an n-channel transistor. Note that in the semiconductor device of one embodiment of the present invention, the transistor M21[j] may be a p-channel transistor instead of an n-channel transistor. Furthermore, the transistor M21[j] may be an analog switch including an n-channel transistor and a p-channel transistor instead of a single transistor.

[0078] Furthermore, in order to reduce the influence of the off-state current flowing between the wiring RFL[j] and the wiring RFLB[j], it is preferable to use a transistor with a very low off-state current as the transistor M21[j]. For example, a transistor including an oxide semiconductor in a channel formation region (hereinafter referred to as an OS transistor) is an example of a transistor with a very low off-state current. Examples of oxide semiconductors include indium oxide and indium gallium zinc oxide. In particular, a transistor including indium oxide in a channel formation region (hereinafter referred to as an IO transistor) can have characteristics of a very low off-state current and a high on-state current. Therefore, by using an IO transistor as the transistor M21[j], malfunctions due to leakage current or the like can be prevented and high-speed operation due to a large on-state current can be achieved. Note that indium oxide will be described later in Embodiment 2.

[0079] As the transistor M21[j], a transistor including silicon in a channel formation region (referred to as a Si transistor) can be used other than an OS transistor.

[0080] 2, each of the wirings RFL[1] to RFL[n] and each of the wirings RFLB[1] to RFLB[n] are connected to the driver circuit WRBD. The wiring WLr is connected to the driver circuit RFWD, and the wiring PLr is connected to the driver circuit RFPD. The wiring REQ is connected to the driver circuit RQD.

[0081] The driver circuit SAS includes, for example, circuits SA[1] to SA[n]. Specifically, in the driver circuit SAS shown in FIG. 2, n circuits SA are arranged side by side in the row direction.

[0082] Each of the circuits SA[1] to SA[n] included in the driver circuit SAS is connected to a wiring STLx, a wiring STLy, a wiring RSTL, and a wiring DRVL. Each of the wirings STLx, STLy, RSTL, and DRVL is connected to the control circuit CTLD.

[0083] As an example, each of the memory cell MC[i,j], memory cell MCr0[j], and memory cell MCr1[j] can be a memory cell having one transistor and one capacitive element. In particular, by using a ferroelectric capacitor as the capacitive element, the memory device MDV including each of the memory cell MC[i,j], memory cell MCr0[j], and memory cell MCr1[j] may be referred to as a ferroelectric memory, FeRAM (Ferroelectric Random Access Memory), or the like. Note that in this specification, each of the memory cell MC[i,j], memory cell MCr0[j], and memory cell MCr1[j] will be described as a memory cell having a ferroelectric capacitor.

[0084] The memory cell MC[i,j] functions as a memory cell for writing or reading in the memory device MDV. The memory cell MCr0[j] and the memory cell MCr1[j] are memory cells for generating a reference potential for reading data to determine its logic based on a potential corresponding to the data read from the memory cell MC[i,j].

[0085] It is assumed that first data is held in memory cell MC[i,j]. It is also assumed that second data is held in memory cell MCr0[j], and third data is held in memory cell MCr1[j]. It is also assumed that each of the first data to third data is digital data whose logic is "0" or "1", as an example. In particular, it is assumed that the second data and the third data have mutually inverted logic. For example, when the logic of the second data is either "0" or "1", the logic of the third data is the other of "0" or "1".

[0086] From the above, it is assumed that memory cell MC[i,j] has a function of applying a first potential corresponding to first data to line BL[j] during a read operation. Similarly, memory cell MCr0[j] has a function of applying a second potential corresponding to second data to line RFL[j] during a read operation. Furthermore, memory cell MCr1[j] has a function of applying a third potential corresponding to third data to line RFLB[j] during a read operation.

[0087] Furthermore, when the transistor M21[j] itself is turned on, the transistor M21[j] redistributes charge between the wiring RFL[j] and the wiring RFLB[j]. In other words, the transistor M21[j] has a function of generating a fourth potential as the potential of the wiring RFL[j] and the wiring RFLB[j] based on the second potential of the wiring RFL[j] and the third potential of the wiring RFLB[j]. Note that the fourth potential serves as the reference potential for reading described above.

[0088] The circuit SA[j] has, for example, a first terminal and a second terminal, and has a function of bringing the wiring BL[j] and the first terminal into electrical continuity to acquire a first potential of the wiring BL[j] from the first terminal and bringing the wiring RFL[j] and the second terminal into electrical continuity to acquire a fourth potential of the wiring RFL[j] from the second terminal.

[0089] As an example, the circuit SA[j] has the function of bringing the wiring RFL[j] and the first terminal into electrical continuity, redistributing charge between the wiring RFL[j] and the first terminal, and changing the first potential of the first terminal to a fifth potential, and bringing the wiring BL[j] and the second terminal into electrical continuity, redistributing charge between the wiring BL[j] and the second terminal, and changing the fourth potential of the second terminal to a sixth potential.

[0090] In addition, the circuit SA[j] has the function of amplifying the fifth potential of the first terminal to either a high-level potential or a low-level potential, and amplifying the sixth potential of the second terminal to either a high-level potential or a low-level potential, depending on the magnitude relationship between the amount of change from the first potential to the fifth potential at the first terminal and the amount of change from the fourth potential to the sixth potential at the second terminal.

[0091] Furthermore, in the circuit SA[j], when the change from the first potential to the fifth potential is either an increase or a decrease, the change from the fourth potential to the sixth potential is either an increase or a decrease. In other words, when the change from the first potential to the fifth potential is either a positive voltage or a negative voltage, the change from the fourth potential to the sixth potential is either a positive voltage or a negative voltage. Here, the difference between the change from the first potential to the fifth potential and the change from the fourth potential to the sixth potential is greater than the difference between the first potential and the fourth potential. Therefore, it is easier to compare the change from the first potential to the fifth potential and the change from the fourth potential to the sixth potential than to the first potential and the fourth potential. This makes it easier to amplify the fifth potential of the first terminal to either a high-level potential or a low-level potential, and to amplify the sixth potential of the second terminal to the other of a high-level potential or a low-level potential.

[0092] As a result, it is possible to easily compare the first potential corresponding to the first data stored in the first cell with the fourth potential serving as reference data for reading, and to read the first data stored in the first cell. In particular, even when the number of rewrites increases in each memory cell of the memory device MDV and the polarization amount of the ferroelectric capacitor provided in each memory cell decreases, the memory cells MCr0[j], MCr1[j], and the transistor M21[j] can generate a reference potential for reading (fourth potential) that is intermediate between the second potential and the third potential, which have a low potential difference, and it is possible to easily compare the first potential and the fourth potential, which have a low potential difference. Therefore, it is possible to read data from the ferroelectric capacitor in the first cell, whose polarization amount has decreased due to a fatigue phenomenon or the like.

[0093] The memory device MDV may be configured such that the ferroelectric capacitors of the memory cells MC, MCr0, and MCr1 are replaced with capacitance elements each having a paraelectric material sandwiched between a pair of electrodes. In other words, the memory device MDV may be a DRAM (Dynamic Random Access Memory).

[0094] Furthermore, unless otherwise specified, the category of "capacitive element" described in this specification includes "ferroelectric capacitor" and "capacitive element having a paraelectric material sandwiched between a pair of electrodes." Therefore, "capacitive element" described in this specification refers to one or both of "ferroelectric capacitor" and "capacitive element having a paraelectric material sandwiched between a pair of electrodes."

[0095] <<Circuit SA>> Next, an example of a circuit configuration that can be applied to each of the circuits SA[1] to SA[n] included in the driver circuit SAS will be described.

[0096] 1 is a configuration example of each of the circuits SA[1] to SA[n] shown in FIG. 2, and includes, as an example, transistors MN2a, MN2b, MN3a, MN3b, MN4a, MN4b, MN5a, MN5b, capacitors C1a, C1b, C3a, C3b, inverters IVa, and IVb. Note that each of the capacitors C1a, C1b, C3a, and C3b can be a capacitor formed by sandwiching a paraelectric material between a pair of electrodes.

[0097] The first terminal of the transistor MN5a and the first terminal of the transistor MN5b are connected to the wiring RFL. The second terminal of the transistor MN5a is connected to the first terminal of the transistor MN4a and the first terminal of the capacitance element C1a. The second terminal of the transistor MN5b is connected to the first terminal of the transistor MN4b and the first terminal of the capacitance element C1b. The second terminal of the transistor MN4a and the second terminal of the transistor MN4b are connected to the wiring BL. The gates of the transistors MN5a and MN4b are connected to the wiring STLx, and the gates of the transistors MN5b and MN4a are connected to the wiring STLy.

[0098] The second terminal of the capacitance element C1a is connected to the first terminal of the transistor MN2a, the input terminal of the inverter IVa, the first terminal of the capacitance element C3b, and the first terminal of the transistor MN3b. The second terminal of the capacitance element C1b is connected to the first terminal of the transistor MN2b, the input terminal of the inverter IVb, the first terminal of the capacitance element C3a, and the first terminal of the transistor MN3a. The second terminal of the capacitance element C3a is connected to the output terminal of the inverter IVa, the second terminal of the transistor MN2a, and the second terminal of the transistor MN3a. The second terminal of the capacitance element C3b is connected to the output terminal of the inverter IVb, the second terminal of the transistor MN2b, and the second terminal of the transistor MN3b.

[0099] In this specification, the first terminal of the capacitance element C1a will be referred to as the terminal IOT. The connection point between the first terminal of the capacitance element C1a, the second terminal of the transistor MN5a, and the first terminal of the transistor MN4a may also be referred to as the terminal IOT. Similarly, the first terminal of the capacitance element C1b will be referred to as the terminal IOTB. The connection point between the first terminal of the capacitance element C1b, the second terminal of the transistor MN5b, and the first terminal of the transistor MN4b may also be referred to as the terminal IOTB. In particular, the terminal IOT may be the first terminal of the circuit SA[j] described above, and the terminal IOTB may be the second terminal of the circuit SA[j] described above.

[0100] In this specification, the connection points among the second terminal of the capacitance element C1a, the first terminal of the transistor MN2a, the input terminal of the inverter IVa, the first terminal of the capacitance element C3b, and the first terminal of the transistor MN3b are referred to as nodes SN. The connection points among the second terminal of the capacitance element C1b, the first terminal of the transistor MN2b, the input terminal of the inverter IVb, the first terminal of the capacitance element C3a, and the first terminal of the transistor MN3a are referred to as nodes SNB.

[0101] The gates of the transistors MN2a and MN2b are connected to the wiring RSTL, and the gates of the transistors MN3a and MN3b are connected to the wiring DRVL.

[0102] Each of the transistors MN2a, MN2b, MN3a, MN3b, MN4a, MN4b, MN5a, and MN5b functions as a switching transistor. The transistors listed above may be the same as those applicable to the transistor M21[j].

[0103] 1, each of the listed transistors is illustrated as an n-channel transistor. Note that in a semiconductor device of one embodiment of the present invention, each of the listed transistors may be a p-channel transistor instead of an n-channel transistor. Furthermore, each of the listed transistors may be an analog switch including an n-channel transistor and a p-channel transistor instead of a single transistor.

[0104] <<Control Circuit CTLD>> The control circuit CTLD has, for example, a function to amplify and latch data read from the memory cell MC in the circuit SA of Fig. 1, and a function to reset the data latched in the circuit SA of Fig. 1. In addition, the control circuit CTLD has, for example, a function to activate or deactivate the circuit SA.

[0105] In addition, the control circuit CTLD has the function of controlling the switching between a conductive state and a non-conductive state between the first terminal of the capacitance element C1a and the wiring RFL, the switching between a conductive state and a non-conductive state between the first terminal of the capacitance element C1a and the wiring BL, the switching between a conductive state and a non-conductive state between the first terminal of the capacitance element C1b and the wiring RFL, and the switching between a conductive state and a non-conductive state between the first terminal of the capacitance element C1b and the wiring BL.

[0106] Therefore, the control circuit CTLD transmits control signals to each of the wiring STLx, the wiring STLy, the wiring RSTL, and the wiring DRVL in order to drive the circuit SA.

[0107] Specifically, for example, the control circuit CTLD can apply a high-level potential to the wiring STLx to bring the first terminal of the capacitance element C1a and the wiring RFL into a conductive state and bring the first terminal of the capacitance element C1b and the wiring BL into a conductive state, and can apply a low-level potential to the wiring STLx to bring the first terminal of the capacitance element C1a and the wiring RFL into a non-conductive state and bring the first terminal of the capacitance element C1b and the wiring BL into a non-conductive state.

[0108] For example, the control circuit CTLD can apply a high-level potential to the wiring STLy to bring the first terminal of the capacitance element C1a and the wiring BL into a conductive state and bring the first terminal of the capacitance element C1b and the wiring RFL into a conductive state. For example, the control circuit CTLD can apply a low-level potential to the wiring STLy to bring the first terminal of the capacitance element C1a and the wiring BL into a non-conductive state and bring the first terminal of the capacitance element C1b and the wiring RFL into a non-conductive state.

[0109] Further, for example, by applying a high-level potential to the wiring DRVL, the control circuit CTLD can bring the input terminal of the inverter IVa and the output terminal of the inverter IVb into a conductive state and bring the input terminal of the inverter IVb into a conductive state and the output terminal of the inverter IVa into a conductive state. Furthermore, by applying a low-level potential to the wiring RSTL, the control circuit CTLD can bring the input terminal of the inverter IVa into a non-conductive state and bring the input terminal of the inverter IVb into a non-conductive state and the output terminal of the inverter IVb into a non-conductive state. This activates the inverter loop formed by the inverters IVa and IVb, amplifying the potential of the node SN to one of the high power supply potential and the low power supply potential, and amplifying the potential of the node SNB to the other of the high power supply potential and the low power supply potential. This allows the circuit SA to latch data corresponding to the potentials of the nodes SN and SNB.

[0110] Furthermore, for example, the control circuit CTLD can apply a low-level potential to the wiring DRVL to bring the input terminal of the inverter IVa and the output terminal of the inverter IVb into a non-conductive state and bring the input terminal of the inverter IVb into a non-conductive state and the output terminal of the inverter IVa into a non-conductive state, thereby inactivating the inverter loop formed by the inverters IVa and IVb.

[0111] Furthermore, for example, the control circuit CTLD can apply a high-level potential to the wiring RSTL to bring the input terminal of the inverter IVa and the output terminal of the inverter IVa into a conductive state and bring the input terminal of the inverter IVb into a conductive state and the output terminal of the inverter IVb into a conductive state. Furthermore, as described above, the control circuit CTLD applies a low-level potential to the wiring DRVL to bring the input terminal of the inverter IVa into a non-conductive state and bring the input terminal of the inverter IVb into a non-conductive state and bring the input terminal of the inverter IVb into a non-conductive state. This allows the potentials of the nodes SN and SNB in ​​the circuit SA to converge to a high power supply potential or higher, which is equal to or higher than the low power supply potential. This allows the data latched in the circuit SA to be reset.

[0112] <<Memory Cell MC>> Next, the memory cell MC[i, j] included in the cell array MCA will be described.

[0113] As described above, the memory cell MC[i,j] may include one transistor and one capacitance element. The capacitance element may be a ferroelectric capacitor. In this case, the memory device MDV including the memory cell MC[i,j] may be called an FeRAM.

[0114] For example, each of the memory cells MC[1,1] to MC[m,n] shown in Fig. 2 can have the circuit configuration shown in Fig. 3A. In Fig. 3A, the memory cell MC includes, as an example, a transistor M1 and a ferroelectric capacitor CF1.

[0115] A first terminal of the transistor M1 is connected to a first terminal of the ferroelectric capacitor CF1, a second terminal of the transistor M1 is connected to the wiring BL, a gate of the transistor M1 is connected to the wiring WL, and a second terminal of the ferroelectric capacitor CF1 is connected to the wiring PL.

[0116] The wiring WL shown in Fig. 3A can be any one of the wirings WL[1] to WL[m] shown in Fig. 2. The wiring PL shown in Fig. 3A can be any one of the wirings PL[1] to PL[m] shown in Fig. 2. The wiring BL shown in Fig. 3A can be any one of the wirings BL[1] to BL[n] shown in Fig. 2.

[0117] The wiring WL functions as a word line for the memory cell MC. Specifically, the wiring WL functions as a wiring that transmits a selection signal to the memory cell MC when writing data to the memory cell MC or reading data held in the memory cell MC. The wiring WL may also be called a selection signal line or the like in addition to being called a word line.

[0118] The wiring BL functions as a bit line for the memory cell MC. Specifically, the wiring BL functions as a wiring that transmits data to be written to the memory cell MC or data read from the memory cell MC. The wiring BL may also be called a data line, a data signal line, or the like, in addition to being a bit line.

[0119] The wiring PL functions as a plate line for the memory cell MC. Specifically, when a write operation or a read operation is performed in the memory cell, the wiring PL functions as a wiring for applying a potential to the memory cell MC according to each operation.

[0120] <<Memory Cells MCr0 and MCr1>> Next, the memory cells MCr0[j] and MCr1[j] included in the cell array MCAr will be described.

[0121] Each of the memory cells MCr0[j] and MCr1[j] has one transistor and one capacitance element, similar to the memory cell MC in Fig. 3A. The capacitance element may be a ferroelectric capacitor.

[0122] For example, each of memory cells MCr0[1] to MCr0[n] and memory cells MCr1[1] to MCr1[n] shown in Fig. 2 can have the circuit configuration shown in Fig. 3B. In Fig. 3B, memory cell MCr0 has, as an example, a transistor M10 and a ferroelectric capacitor CF10, and memory cell MCr1 has, as an example, a transistor M11 and a ferroelectric capacitor CF11. Fig. 3B also shows transistor M21, which is arranged in the same column as memory cells MCr0 and MCr1.

[0123] A first terminal of the transistor M10 is connected to a first terminal of the ferroelectric capacitor CF10, a second terminal of the transistor M10 is connected to the wiring RFL, and a gate of the transistor M10 is connected to the wiring WLr. A second terminal of the ferroelectric capacitor CF10 is connected to the wiring PLr. A first terminal of the transistor M11 is connected to a first terminal of the ferroelectric capacitor CF11, a second terminal of the transistor M11 is connected to the wiring RFLB, and a gate of the transistor M11 is connected to the wiring WLr. A second terminal of the ferroelectric capacitor CF11 is connected to the wiring PLr.

[0124] It is assumed that each of memory cells MCr0[j] and MCr1[j] holds reference data, which is data used when data held in memory cells MC included in cell array MCA is read by circuit SA.

[0125] Specifically, for example, each memory cell MCr0[j] holds reference data whose logic is "0," and each memory cell MCr1[j] holds reference data whose logic is "1." In other words, it can be said that memory cell MCr0[j] and memory cell MCr1[j] hold complementary digital data.

[0126] As described above, the first terminal of the transistor M21 is connected to the wiring RFL, the second terminal of the transistor M21 is connected to the wiring RFLB, and the gate of the transistor M21 is connected to the wiring REQ.

[0127] The wiring WLr shown in FIG. 3B can be the wiring WLr shown in FIG. 2. The wiring PLr shown in FIG. 3B can be the wiring PLr shown in FIG. 2. The wiring RFL shown in FIG. 3B can be any one of the wirings RFL[1] to RFL[n] shown in FIG. 2, and the wiring RFLB shown in FIG. 3B can be any one of the wirings RFLB[1] to RFLB[j] shown in FIG. 2. The wiring REQ shown in FIG. 3B can be the wiring REQ shown in FIG. 2.

[0128] The wiring WLr functions as a word line for the memory cells MCr0 and MCr1, similarly to the wiring WL.

[0129] The wiring RFL functions as a bit line for the memory cell MCr0, similar to the wiring BL, and the wiring RFLB functions as a bit line for the memory cell MCr1.

[0130] The wiring PLr functions as a plate line for the memory cells MCr0 and MCr1, similar to the wiring PL.

[0131] Next, a drive circuit for operating the memory device MDV shown in FIG. 2 will be described.

[0132] <<Driver Circuit WRBD>> The driver circuit WRBD shown in FIG. 2 has a function of transmitting reference data with a logic "0" to the wiring RFL[j] in order to write the reference data to the memory cell MCr0[j]. The driver circuit WRBD has a function of transmitting reference data with a logic "1" to the wiring RFLB[j] in order to write the reference data to the memory cell MCr1[j]. The driver circuit WRBD has a function of transmitting data with a logic "0" or "1" to the wiring BL[j] via the wiring RFL[j] and the circuit SA[j] in order to write the data to any one of the memory cells MC[1,j] to MC[m,j].

[0133] In other words, the driver circuit WRBD may be called a write bit line driver circuit for memory cells MCr0[1] to MCr0[n], memory cells MCr1[1] to MCr1[n], and memory cells MC[1,1] to MC[m,n].

[0134] The driver circuit WRBD also has a function of applying a predetermined potential to the wiring RFL in order to read reference data from the memory cell MCr0. Similarly, the driver circuit WRBD also has a function of applying a predetermined potential to the wiring RFLB in order to read reference data from the memory cell MCr1. Similarly, the driver circuit WRBD also has a function of applying a predetermined potential to the wiring BL via the wiring RFL and the circuit SA in order to read data from the memory cell MC. After applying a predetermined potential to the wiring RFL or the wiring RFLB, the driver circuit WRBD may also have a function of bringing the output terminal of the driver circuit WRBD and the wiring RFL into a non-conductive state, or bringing the output terminal of the driver circuit WRBD and the wiring RFLB into a non-conductive state, in order to put the wiring to which the potential has been applied into a floating state.

[0135] Note that in order to hold a predetermined potential after the wiring RFL, the wiring RFLB, or the wiring BL is set in a floating state, a capacitor may be provided for each of the wiring RFL, the wiring RFLB, and the wiring BL.

[0136] 2 has a function of transmitting a selection signal to the wiring WLr to be applied to each of the memory cells MCr0 and MCr1 listed above when writing reference data to each of the memory cells MCr0[j] and MCr1[j]. For this reason, the drive circuit RFWD is sometimes called a word line driver circuit.

[0137] 2 has a function of transmitting a predetermined signal to the wiring PLr in order to write reference data to each of the memory cells MCr0[j] and MCr1[j], or to read reference data from each of the memory cells MCr0[j] and MCr1[j]. For this reason, the drive circuit RFPD is sometimes called a plate line driver circuit.

[0138] 2 has a function of transmitting a signal to the wiring REQ for controlling switching between the on state and the off state of the transistor M21[j] included in the cell array MCAr, for example. Specifically, by applying a high-level potential as the signal to the wiring REQ, the transistor M21[j] can be turned on. On the other hand, by applying a low-level potential as the signal to the wiring REQ, the transistor M21[j] can be turned off.

[0139] Note that by turning on the transistor M21[j] using the driver circuit RQD, electrical continuity can be established between the wiring RFL[j] and the wiring RFLB[j]. Furthermore, when the wiring RFL[j] and the wiring RFLB[j] are both floating, electrical continuity can be established between the wiring RFL[j] and the wiring RFLB[j], thereby redistributing the electric charges accumulated in the wiring RFL[j] and the wiring RFLB[j] to each other. This allows the wiring RFL[j] and the wiring RFLB[j] to have the same potential.

[0140] 2 has a function of transmitting a selection signal to the wiring WL[i] to be applied to each of the memory cells MC[i,1] to MC[i,n] arranged in the i-th row of the cell array MCA when writing data to each of the memory cells MC[i,1] to MC[i,n] arranged in the i-th row of the cell array MCA. For this reason, the drive circuit WRWD, like the drive circuit RFWD, may be called a word line driver circuit.

[0141] 2 has a function of transmitting a predetermined signal to a wiring PL[i] in order to write data to or read data from each of the memory cells MC[i,1] to MC[i,n] arranged in the i-th row of the cell array MCA. For this reason, the drive circuit PD, like the drive circuit RFPD, is sometimes called a plate line driver circuit.

[0142] <Operation Example 1 of Storage Device> Here, an example of a read operation of the storage device MDV shown in FIG. 2 will be described.

[0143] As described above, the memory device MDV, which is a semiconductor device according to one embodiment of the present invention, includes a memory cell MC for writing and reading data, and memory cells MCr0 and MCr1 for holding reference data. Furthermore, the memory device MDV can operate, using a control circuit (sometimes referred to as a memory controller) or the like provided in the memory device itself, so that the number of write and read operations in each of the memory cells MC, MCr0, and MCr1 is approximately equal. In other words, the reduction in polarization due to fatigue or the like in the ferroelectric capacitors provided in each of the memory cells MC, MCr0, and MCr1 may be approximately equal.

[0144] Even if the polarization amount of the data held in the memory cell MC decreases due to a fatigue phenomenon or the like, the memory device MDV can accurately read the data with reduced polarization amount held in the memory cell MC by using reference data with reduced polarization amount read from the memory cells MCr0 and MCr1, similarly due to a fatigue phenomenon or the like.

[0145] In this operation example, the circuits SA[1] to SA[n] in the memory device MDV in Fig. 2 refer to the circuit SA in Fig. 1. Furthermore, the memory cells MC[1,1] to MC[m,n] in the memory device MDV in Fig. 2 refer to the memory cell MC in Fig. 3A. Furthermore, the memory cells MCr0[1] to MCr0[n] in the memory device MDV in Fig. 2 refer to the memory cell MCr0 in Fig. 3B, and the memory cells MCr1[1] to MCr1[n] refer to the memory cell MCr1 in Fig. 3B.

[0146] 4 is a timing chart showing an example of the operation of the memory device MDV. In FIG. 4, potential changes of the wirings WLr, PLr, REQ, RFL, RFLB, WL, PL, BL, STLx, STLy, RSTL, DRVL, the node SN, and the node SNB are shown during the period T00 to T06 as a read operation of data held in the memory cell MC. In FIG. 4, a high-level potential is indicated as "High" and a low-level potential is indicated as "Low."

[0147] As described above, it is assumed that reference data is held in advance in each of memory cells MCr0[1] to MCr0[n] and memory cells MCr1[1] to MCr1[n]. Specifically, for example, it is assumed that reference data with a logic value of "0" is held in each of memory cells MCr0[1] to MCr0[n], and that reference data with a logic value of "1" is held in each of memory cells MCr1[1] to MCr1[n].

[0148] In particular, in this specification, when a high-level potential is applied to the first terminal and a low-level potential is applied to the second terminal of each of the ferroelectric capacitors CF10 and CF11, the dielectric polarization moment in each ferroelectric capacitor is oriented in the direction from the first terminal to the second terminal, and this direction is defined as the positive direction in this specification. Also, when a low-level potential is applied to the first terminal and a high-level potential is applied to the second terminal, the dielectric polarization moment in each ferroelectric capacitor is oriented in the direction from the second terminal to the first terminal, and this direction is defined as the negative direction in this specification.

[0149] In addition, the ferroelectric capacitor CF10 has a dielectric polarization moment that faces in the negative direction as logic data "0", and the ferroelectric capacitor CF11 has a dielectric polarization moment that faces in the positive direction as logic data "1".

[0150] Furthermore, it is assumed that VDD is applied as a high power supply potential to each of the inverters IVa and IVb included in the circuit SA, and VSS is applied as a low power supply potential. Therefore, each of the inverters IVa and IVb outputs VDD or VSS from the output terminal depending on the potential input to the input terminal. Note that when there is conduction between the input terminal and the output terminal in each of the inverters IVa and IVb, the potentials output from the output terminals of the inverters IVa and IVb converge to a potential equal to or higher than VSS and equal to or lower than VDD. Note that, as an example, this potential is referred to as V Ｑ Let's say.

[0151] [Period T00] During period T00, the memory device MDV performs an initial operation to read reference data from each of memory cells MCr0 and MCr1. Specifically, the control circuit CTLD applies a high-level potential to each of the wirings STLx and STLy. As a result, the high-level potential is applied to the gates of transistors MN4a, MN4b, MN5a, and MN5b, turning these transistors on.

[0152] Furthermore, in the period T00, while the transistors MN4a, MN4b, MN5a, and MN5b are in the on state, the driver circuit WRBD precharges the wirings BL, RFL, and RFLB to a low-level potential. Specifically, the driver circuit WRBD applies a low-level potential to the wirings RFL and RFLB. Furthermore, since the transistors MN4a, MN4b, MN5a, and MN5b are in the on state, a low-level potential is applied to the wirings RFL and RFLB, and the potential of the wiring BL also becomes a low-level potential. In particular, here, the low-level potential applied to the wirings RFL, RFLB, and BL is V Ｌ Let's say.

[0153] In addition, the potentials of the wirings BL, RFL, and RFLB are set to VＬ After this, the control circuit CTLD applies a low-level potential to each of the wirings STLx and STLy. As a result, a low-level potential is applied to the gates of the transistors MN4a, MN4b, MN5a, and MN5b, turning these transistors off. As a result, the wiring BL is brought into a floating state.

[0154] In addition, the potentials of the wirings RFL and RFLB are set to V Ｌ After this, the driver circuit WRBD operates to bring the circuit WRBD itself and the wiring RFL into a non-conductive state, and also to bring the circuit WRBD itself and the wiring RFLB into a non-conductive state.

[0155] During the period T00, the driver circuit RQD applies a low-level potential to the wiring REQ. Therefore, a low-level potential is applied to the gate of the transistor M21, turning the transistor M21 off. Note that in this operation example, during the period T00, while the wirings RFL, RFLB, and BL are precharged with low-level potentials, the driver circuit RQD may apply a high-level potential to the wiring REQ to turn the transistor M21 on.

[0156] The above operations complete the initial operation for reading reference data from each of memory cells MCr0 and MCr1.

[0157] During the period T00, the control circuit CTLD applies a low-level potential to each of the wirings RSTL and DRVL. As a result, a low-level potential is applied to the gates of the transistors MN2a, MN2b, MN3a, and MN3b, turning these transistors off. As a result, the inverter loop included in the circuit SA is in an inactive state.

[0158] Note that the potentials of the nodes SN and SNB are not particularly limited during the period T00. Therefore, the potentials of the nodes SN and SNB during the period T00 in the timing chart of FIG. 4 are indefinite, as indicated by diagonal hatching.

[0159] During the period T00, no write or read operation is performed on the memory cells MCr0, MCr1, and MC. Therefore, a low-level potential is applied from the drive circuit RFWD to the wiring WLr, and a low-level potential is applied from the drive circuit WRWD to the wiring WL. As a result, a low-level potential is applied to the gates of the transistors M10, M11, and M1, and these transistors are turned off.

[0160] In addition, in the period T00, the driver circuit RFPD applies a potential V ＨＬ is applied to the wiring PL from the driving circuit PD. ＨＬ Therefore, the second terminals of the ferroelectric capacitors CF10, CF11, and CF1 are supplied with V ＨＬ The potential V ＨＬ is set to a potential that does not affect the direction of the remanent polarization of each of the ferroelectric capacitors CF10, CF11, and CF1.

[0161] [Period T01] During period T01, the control circuit CTLD applies a high-level potential to the wiring STLx. This applies the high-level potential to the gates of the transistors MN5a and MN4b included in the circuit SA, turning these transistors on. That is, electrical continuity is established between the wiring RFL and the first terminal of the capacitor C1a, and between the wiring BL and the first terminal of the capacitor C1b.

[0162] During the period T01, the driving circuit RFWD applies a high-level potential to the wiring WLr. This applies the high-level potential to the gate of the transistor M10 included in the memory cell MCr0 and the gate of the transistor M11 included in the memory cell MCr1. As a result, these transistors are turned on.

[0163] After a high-level potential is applied to the wiring WLr, the driver circuit RFPD applies a potential VＲＤ is given. V ＲＤ is V ＨＬ The potential is set to be higher than the potential at which the direction of the remanent polarization can be reversed from the positive direction to the negative direction in each of the ferroelectric capacitors CF10 and CF11.

[0164] From the above, the second terminal of the ferroelectric capacitor CF10 included in the memory cell MCr0 and the second terminal of the ferroelectric capacitor CF11 included in the memory cell MCr1 are respectively connected to V ＲＤ In particular, since the dielectric polarization moment of the ferroelectric capacitor CF10 is oriented in the negative direction, V ＲＤ is applied, the direction of the dielectric polarization moment of the ferroelectric capacitor CF10 does not change. Ｌ On the other hand, since the dielectric polarization moment of the ferroelectric capacitor CF11 is oriented in the positive direction, V ＲＤ When the voltage Vcc is applied, the direction of the dielectric polarization moment of the ferroelectric capacitor CF11 changes from the positive direction to the negative direction. At this time, the potential of the first terminal of the ferroelectric capacitor CF11 decreases, and the potential of the wiring RFLB increases.

[0165] In the period T01, the driver circuit WRWD applies a high-level potential to the wiring WL, which in turn applies the high-level potential to the gate of the transistor M1 included in the memory cell MC. As a result, the transistor M1 is turned on.

[0166] After a high-level potential is applied to the wiring WL, V ＲＤ As a result, V is applied to the second terminal of the ferroelectric capacitor CF1 included in the memory cell MC. ＲＤ is given.

[0167] When the direction of the dielectric polarization moment of the ferroelectric capacitor CF1 is in the negative direction, V ＲＤis applied, the direction of the dielectric polarization moment of the ferroelectric capacitor CF1 does not change. At this time, the potential of the wiring BL does not change substantially, and V Ｌ 4, the potential at the wiring BL in this case (when logic "0" data is held in the ferroelectric capacitor CF1) is indicated by a thick dashed line.

[0168] On the other hand, when the direction of the dielectric polarization moment of the ferroelectric capacitor CF1 is in the positive direction, V ＲＤ is applied, the direction of the dielectric polarization moment of the ferroelectric capacitor CF1 changes from the positive direction to the negative direction. At this time, the potential of the first terminal of the ferroelectric capacitor CF1 drops, and the potential of the wiring BL rises. In the timing chart of FIG. 4, the potential of the wiring BL in this case (when data with a logic value of "1" is held in the ferroelectric capacitor CF1) is shown by a solid line, and the potential of the wiring BL is V Ｐ It is assumed that V Ｐ is V Ｌ The potential is set to be higher than

[0169] In addition, in the period T01, a high-level potential is applied from the control circuit CTLD to the wiring RSTL. As a result, a high-level potential is applied to the gates of the transistors MN2a and MN2b, turning these transistors on. As a result, the input terminal and the output terminal of the inverter IVa are brought into a mutually conductive state, and the potentials of the input terminal and the output terminal of the inverter IVa are set to an intermediate potential V between the high power supply potential and the low power supply potential applied to the inverter IVa. Ｑ That is, the potential of the second terminal (node ​​SN) of the capacitance element C1a becomes V Ｑ Similarly, the potentials of the input terminal and output terminal of the inverter IVb are set to an intermediate potential V between the high power supply potential and the low power supply potential applied to the inverter IVb. Ｑ That is, the potential of the second terminal (node ​​SNB) of the capacitance element C1b is also V Ｑ This becomes:

[0170] [Period T02] During period T02, a high-level potential is applied from the drive circuit RQD to the wiring REQ. As a result, a high-level potential is applied to the gate of the transistor M21 included in the cell array MCAr, and the transistor M21 is turned on. With the transistor M21 turned on, the wiring RFL and the wiring RFLB are brought into a conductive state, and charge is redistributed between the wiring RFL and the wiring RFLB. Due to the charge redistribution, the respective potentials of the wiring RFL and the wiring RFLB ideally become equal to each other. Note that in the timing chart of FIG. 4, the respective potentials of the wiring RFL and the wiring RFLB are set to V ＭＤ It is shown as V ＭＤ is V Ｌ Higher than V Ｐ The potential is set to be lower than

[0171] <<Period T03>> During period T03, a low-level potential is applied from the drive circuit RFPD to the line PLr. As a result, a low-level potential is applied to the second terminal of the ferroelectric capacitor CF10 included in the memory cell MCr0 and the second terminal of the ferroelectric capacitor CF11 included in the memory cell MCr1. Note that this operation does not cause a change in the direction of the dielectric polarization moment in the ferroelectrics of the ferroelectric capacitors CF10 and CF11.

[0172] After a low-level potential is applied to the wiring PLr, the driving circuit RFWD applies a low-level potential to the wiring WLr, which applies the low-level potential to the gate of the transistor M10 included in the memory cell MCr0 and the gate of the transistor M11 included in the memory cell MCr1, turning these transistors off.

[0173] During a period T03, a low-level potential is applied from the drive circuit PD to the wiring PL. This applies a low-level potential to the second terminal of the ferroelectric capacitor CF1 included in the memory cell MC. Note that this operation does not cause a change in the direction of the dielectric polarization moment within the ferroelectric of the ferroelectric capacitor CF1.

[0174] After the low-level potential is applied to the wiring PL, the driver circuit WRWD applies the low-level potential to the wiring WL, which in turn applies the low-level potential to the gate of the transistor M1 included in the memory cell MC, turning the transistor M1 off.

[0175] <<Period T04>> During the period T04, the control circuit CTLD applies a low-level potential to the wiring STLx. As a result, a low-level potential is applied to the gates of the transistors MN5a and MN4b, turning these transistors off. At this time, the first terminal of the capacitor C1a is in a floating state, and the first terminal of the capacitor C1a is supplied with a potential V ＭＤ Similarly, the first terminal of the capacitance element C1b is also in a floating state, and the first terminal of the capacitance element C1b is held at the potential V Ｐ or V Ｌ is maintained.

[0176] In addition, in a period T04, a low-level potential is applied from the control circuit CTLD to the wiring RSTL. As a result, a low-level potential is applied to the gates of the transistors MN2a and MN2b, turning these transistors off. With the transistor MN2a turned off, the second terminal of the capacitance element C1a is brought into a floating state, and the second terminal (node ​​SN) of the capacitance element C1a is supplied with an intermediate potential V Ｑ Similarly, the second terminal of the capacitance element C1b is also in a floating state, and the second terminal (node ​​SNB) of the capacitance element C1b is held at the intermediate potential V Ｑ is maintained.

[0177] That is, in the period T04, V ＭＤ -V Ｑ The voltage of V is held in the capacitance element C1b. Ｐ -V Ｑ or V Ｌ -V Ｑ The voltage is maintained at .

[0178] <<Period T05>> During period T05, the control circuit CTLD applies a high-level potential to the wiring STLy. This applies a high-level potential to the gates of the transistors MN4a and MN5b, turning these transistors on. This means that electrical continuity is established between the wiring RFL and the first terminal of the capacitance element C1b, and between the wiring BL and the first terminal of the capacitance element C1a.

[0179] Immediately before the transistor MN5b is turned on, the potentials of the wirings RFL and RFLB are V ＭＤ and the potential of the first terminal of the capacitance element C1b is V Ｐ or V Ｌ When the transistor MN5b is turned on, charge redistribution occurs between the wiring RFL and the wiring RFLB and the capacitor C1b, and the potential of the first terminal of the capacitor C1b and the potentials of the wiring RFL and the wiring RFLB change. For example, when the potential of the wiring BL in the period T04 is V Ｐ (during the period T00, when the ferroelectric capacitor CF1 holds data with a logic value of "1"), the potential of the first terminal of the capacitive element C1b is V Ｐ From V Ｐ −ΔV ＭＤＰ At this time, the potential of the wiring RFL and the wiring RFLB is V ＭＤ From V Ｐ −ΔV ＭＤＰ (In the timing chart in FIG. 4, this is indicated by a solid line from the period T05 onward.) Ｌ (during the period T00, when the ferroelectric capacitor CF1 holds data with a logic value of "0"), the potential of the first terminal of the capacitive element C1b is V Ｌ From V Ｌ +ΔV ＭＤＬ At this time, the potential of the wiring RFL and the wiring RFLB rises to V ＭＤ From V Ｌ +ΔV ＭＤＬ (In the timing chart of FIG. 4, this is shown by a thick dashed line from period T05 onwards).

[0180] In addition, VＰ −ΔV ＭＤＰ is V Ｐ and V Ｌ +ΔV ＭＤＬ is V Ｌ It will have a higher potential than

[0181] Furthermore, since the second terminal (node ​​SNB) of the capacitance element C1b is in a floating state, when the potential of the first terminal of the capacitance element C1b fluctuates, the potential of the second terminal (node ​​SNB) of the capacitance element C1b also fluctuates due to capacitive coupling. Here, the capacitive coupling coefficient is k ｂ In addition, the potential of the wiring BL in the period T04 is V Ｐ (during the period T00, when the ferroelectric capacitor CF1 holds data with a logic value of "1"), the potential of the second terminal (node ​​SNB) of the capacitive element C1b becomes V Ｑ From V Ｑ -k ｂ ΔV ＭＤＰ In addition, the potential of the wiring BL in the period T04 is reduced to V Ｌ (during the period T00, when the ferroelectric capacitor CF1 holds data with a logic value of "0"), the potential of the second terminal (node ​​SNB) of the capacitive element C1b becomes V Ｑ From V Ｑ +k ｂ ΔV ＭＤＰ shall rise to

[0182] Immediately before the transistor MN4a is turned on, the potential of the wiring BL is V Ｐ or V Ｌ and the potential of the first terminal of the capacitance element C1a is V ＭＤ When the transistor MN4a is turned on, charge redistribution occurs between the wiring BL and the capacitor C1a, and the potential of the first terminal of the capacitor C1a and the potential of the wiring BL change. For example, when the potential of the wiring BL in the period T04 is V Ｐ (during the period T00, when the ferroelectric capacitor CF1 holds data with a logic value of "1"), the potential of the first terminal of the capacitance element C1a is V ＭＤ From V ＭＤ +ΔVＰ At this time, the potential of the wiring BL rises to V Ｐ From V ＭＤ +ΔV Ｐ (In the timing chart in FIG. 4, this is indicated by a solid line from the period T05 onward.) Ｌ (during the period T00, when the ferroelectric capacitor CF1 holds data with a logic value of "0"), the potential of the first terminal of the capacitance element C1a is V ＭＤ From V ＭＤ −ΔV Ｌ At this time, the potential of the wiring BL is V Ｌ From V ＭＤ −ΔV Ｌ (In the timing chart of FIG. 4, this is indicated by a thick dashed line from period T05 onwards).

[0183] In addition, V ＭＤ +ΔV Ｐ is V ＭＤ and V ＭＤ −ΔV Ｌ is V ＭＤ The potential is lower than

[0184] Furthermore, since the second terminal (node ​​SN) of the capacitance element C1a is in a floating state, when the potential of the first terminal of the capacitance element C1a fluctuates, the potential of the second terminal (node ​​SN) of the capacitance element C1a also fluctuates due to capacitive coupling. Here, the capacitive coupling coefficient is k ａ In addition, the potential of the wiring BL in the period T04 is V Ｐ (during the period T00, when the ferroelectric capacitor CF1 holds data with a logic value of "1"), the potential of the second terminal (node ​​SN) of the capacitive element C1a becomes V Ｑ From V Ｑ +k ａ ΔV Ｐ In addition, the potential of the wiring BL in the period T04 is increased to V Ｌ (during the period T00, when the ferroelectric capacitor CF1 holds data with a logic value of "0"), the potential of the second terminal (node ​​SN) of the capacitance element C1a becomes V Ｑ From VＱ -k ａ ΔV Ｌ shall be reduced to

[0185] <<Period T06>> During period T06, the control circuit CTLD applies a high-level potential to the wiring DRVL. As a result, a high-level potential is applied to the gates of the transistors MN3a and MN3b, turning these transistors on. That is, the output terminal of the inverter IVa and the input terminal of the inverter IVb are electrically connected, and the output terminal of the inverter IVb and the input terminal of the inverter IVa are electrically connected, turning the inverter loop formed by the inverters IVa and IVb into an active state.

[0186] When the inverter loop is activated, the potentials of the nodes SN and SNB are amplified. Ｑ +k ａ ΔV Ｐ and the potential of the node SNB is V Ｑ -k ｂ ΔV ＭＤＰ (during the period T00, when the ferroelectric capacitor CF1 holds data with a logic value of "1"), the inverter loop is activated, and the potential of the node SN becomes V Ｑ +k ａ ΔV Ｐ VDD, and the potential of the node SNB rises to V Ｑ -k ｂ ΔV ＭＤＰ The potential of the wiring BL changes due to capacitive coupling by the capacitor C1a when the potential of the node SN changes, and the potential of the wiring RFL and the wiring RFLB changes due to capacitive coupling by the capacitor C1b when the potential of the node SNB changes. ＭＤ +ΔV Ｐ From V ＰＰ The potential of the wiring RFL and the wiring RFLB is V Ｐ −ΔV ＭＤＰ From V ＬＭ It is assumed that the value has decreased to

[0187] In addition, V ＰＰ For example, V Ｐ In addition, V ＬＭ For example, V ＭＤ In the timing chart of FIG. ＬＭ is V Ｌ Depending on the power supply voltage applied to the inverter IVa and the inverter IVb, V ＬＭ is V Ｌ The potential can be lower than

[0188] Furthermore, for example, when the potential of the node SN is V Ｑ -k ａ ΔV Ｌ and the potential of the node SNB is V Ｑ +k ｂ ΔV ＭＤＬ (during the period T00, when the ferroelectric capacitor CF1 holds data with a logic value of "0"), the inverter loop is activated, and the potential of the node SN becomes V Ｑ -k ａ ΔV Ｌ The potential of the node SNB drops from V Ｑ +k ｂ ΔV ＭＤＬ The potential of the wiring BL changes due to capacitive coupling by the capacitor C1a when the potential of the node SN changes, and the potential of the wiring RFL and the wiring RFLB changes due to capacitive coupling by the capacitor C1b when the potential of the node SNB changes. ＭＤ −ΔV Ｌ From V ＬＬ The potential of the wiring RFL and the wiring RFLB is V Ｌ +ΔV ＭＤＬ From V ＰＭ It is assumed that the value has risen to

[0189] In addition, V ＬＬ For example, V Ｌ In addition, the potential can be set to be lower than V ＰＭ For example, VＭＤ In the timing chart of FIG. ＰＭ is V Ｐ Depending on the power supply voltage applied to the inverter IVa and the inverter IVb, ＰＭ is V Ｐ The potential can be higher than

[0190] By performing the operation method of the period T00 to the period T06 of the timing chart shown in FIG. 4, the data written in the ferroelectric capacitor CF1 of the memory cell MC is converted to the potential V ＰＰ or potential V ＬＬ By carrying out the above-described operation method, data can be read from a ferroelectric capacitor whose remanent polarization (polarization amount) has decreased due to a fatigue phenomenon or the like.

[0191] Next, the functions of the capacitive elements C3a and C3b will be described.

[0192] When the ferroelectric capacitor CF1 holds data with a logic value of "1" during the period T00, the input terminal of the inverter IVa receives V Ｑ +k ａ ΔV Ｐ The input terminal of the inverter IVb is supplied with a potential of V Ｑ -k ｂ ΔV ＭＤＰ At this time, VSS may be output from the output terminal of the inverter IVa as a low power supply potential, and VDD may be output from the output terminal of the inverter IVb as a high power supply potential. In this case, the potential of the output terminal of the inverter IVa drops to VSS due to capacitive coupling by the capacitive element C3a, and the potential V Ｑ -k ｂ ΔV ＭＤＰ Furthermore, the potential of the output terminal of the inverter IVb rises to VDD due to capacitive coupling by the capacitive element C3b, and the potential V Ｑ +k ａ ΔV Ｐcan be further increased from

[0193] In the operation of the period T05, the potential of the node SN is V Ｑ +k ａ ΔV Ｐ By further increasing the potential of the node SN from V Ｑ -k ｂ ΔV ＭＤＰ By further decreasing the potential at the node SNB from VDD, the potential at the node SNB approaches VSS. Therefore, by activating the inverter loop in the period T06, it is possible to speed up the change in potential at the node SN to VDD and the change in potential at the node SNB to VSS.

[0194] Similarly, when the ferroelectric capacitor CF1 holds data with a logic value of "0" during the period T00, the input terminal of the inverter IVa receives V Ｑ -k ａ ΔV Ｐ The input terminal of the inverter IVb is supplied with a potential of V Ｑ +k ｂ ΔV ＭＤＰ At this time, VDD may be output from the output terminal of the inverter IVa as a high power supply potential, and VSS may be output from the output terminal of the inverter IVb as a low power supply potential. In this case, the potential of the output terminal of the inverter IVa rises to VDD due to capacitive coupling by the capacitive element C3a, and the potential V Ｑ +k ｂ ΔV ＭＤＰ Furthermore, the potential of the output terminal of the inverter IVb is reduced to VSS due to capacitive coupling by the capacitive element C3b, and the potential of the node SN is reduced to VSS. Ｑ -k ａ ΔV Ｐ can be further reduced from

[0195] In the operation of the period T05, the potential of the node SN is V Ｑ -k ａ ΔV Ｐ By further decreasing the potential of the node SN from VSS, the potential of the node SNB approaches VSS.Ｑ +k ｂ ΔV ＭＤＰ By further increasing the potential at the node SNB from VSS, the potential at the node SNB approaches VDD. Therefore, by activating the inverter loop in the period T06, it is possible to speed up the change in potential at the node SN to VSS and the change in potential at the node SNB to VDD.

[0196] As described above, by providing the capacitors C3a and C3b in the circuit SA, the potential at the node SNB is further varied by the bootstrap of the capacitor C3a due to the output of the potential from the output terminal of the inverter IVa, and the potential at the node SN is further varied by the bootstrap of the capacitor C3b due to the output of the potential from the output terminal of the inverter IVb. This increases the operating speed of the circuit SA. As a result, the data read speed in the driver circuit SAS can be increased.

[0197] <Operation Example 2 of Memory Device> Next, an example of the operation of writing data to the memory cell MC included in the memory device MDV shown in FIG. 2 will be described.

[0198] 4, the circuits SA[1] to SA[n] in the memory device MDV in FIG. 2 refer to the circuit SA in FIG. 1. The memory cells MC[1,1] to MC[m,n] in the memory device MDV in FIG. 2 refer to the memory cell MC in FIG. 3A. The memory cells MCr0[1] to MCr0[n] in the memory device MDV in FIG. 2 refer to the memory cell MCr0 in FIG. 3B, and the memory cells MCr1[1] to MCr1[n] refer to the memory cell MCr1 in FIG. 3B.

[0199] 5 is a timing chart showing an example of the operation of the memory device MDV. In FIG. 5, potential changes of the wirings WLr, PLr, REQ, RFL, RFLB, WL, PL, BL, STLx, STLy, RSTL, DRVL, the nodes SN, and SNB are shown during the periods T10 to T15 as a data write operation to the memory cell MC. Also, in FIG. 5, as in FIG. 4, a high-level potential is indicated as "High" and a low-level potential is indicated as "Low."

[0200] In this operation example, the inverters IVa and IVb in the circuit SA can be stopped. Therefore, in the periods T10 to T15, a low-level potential is applied to the wirings RSTL and DRVL from the control circuit CTLD. Therefore, a low-level potential is applied to the gates of the transistors MN2a, MN2b, MN3a, and MN3b, turning these transistors off.

[0201] In this operation example, the potentials of the nodes SN and SNB are not particularly limited. Therefore, the potentials of the nodes SN and SNB in ​​the periods T10 to T15 in the timing chart of FIG. 5 are indefinite, as indicated by diagonal hatching.

[0202] <<Period T10>> During period T10, the memory device MDV performs an initial operation for writing data to the memory cell MC. Specifically, the control circuit CTLD applies a high-level potential to each of the wirings STLx and STLy. As a result, the high-level potential is applied to the gates of the transistors MN4a, MN4b, MN5a, and MN5b included in the circuit SA, turning these transistors on. In other words, conduction is established between the wirings RFL and BL.

[0203] In addition, during the period T10, as an example, V ＨＬ The potential V ＨＬRegarding V, which is explained in the operation example 1 of the storage device, ＨＬ can be referred to.

[0204] During the period T10, the driving circuit RFWD applies a low-level potential to the wiring WLr, thereby applying a low-level potential to the gate of the transistor M10 included in the memory cell MCr0 and the gate of the transistor M11 included in the memory cell MCr1, turning these transistors off.

[0205] In addition, in the period T10, for example, while the wiring RFL and the wiring BL are in electrical conduction, the driver circuit WRBD applies a potential V ＨＬ is given.

[0206] In addition, in the period T10, a low-level potential is applied from the drive circuit WRWD to the wiring WL, so that the low-level potential is applied to the gate of the transistor M1 included in the memory cell MC, turning the transistor M1 off.

[0207] In addition, in the period T10, the driver circuit RFPD applies a potential V ＨＬ is applied to the wiring PL from the driving circuit PD. ＨＬ Therefore, the second terminals of the ferroelectric capacitors CF10, CF11, and CF1 are supplied with V ＨＬ is given.

[0208] In addition, in the period T10, a low-level potential is applied from the driver circuit RQD to the wiring REQ. As a result, a low-level potential is applied to the gate of the transistor M21, and the transistor M21 is turned off. Note that in this operation example, in the period T10, the potential V ＨＬ While the potential is applied, a high-level potential may be applied from the driver circuit RQD to the wiring REQ to turn on the transistor M21.

[0209] The above operations complete the initial operation for writing data into the memory cells MC.

[0210] <<Period T11>> During period T11, a high-level potential is applied from the drive circuit WRWD to the wiring WL. This applies the high-level potential to the gate of the transistor M1 included in the memory cell MC. This turns the transistor M1 on. In other words, conduction is established between the wiring BL and the first terminal of the ferroelectric capacitor CF1.

[0211] As a result, the first terminal of the ferroelectric capacitor CF1 receives V from the drive circuit WRBD. ＨＬ is applied via the wiring RFB and the wiring BL. The second terminal of the ferroelectric capacitor CF1 is supplied with a potential V ＨＬ is given, no dielectric polarization occurs in the ferroelectric capacitor CF1.

[0212] <<Period T12>> During the period T12, data is written to the memory cells MC. Here, the cases where the logic of the data is "0" and "1" will be described.

[0213] When the logic of the data written to the memory cell MC is “0”, the potential V ＷＤ is given. Note that V ＷＤ is V ＨＬ and the voltage between the first terminal and the second terminal of each of the ferroelectric capacitors CF10 and CF11 is V ＷＤ -V ＨＬ When the potential V is high, the potential V is set to a level at which dielectric polarization occurs in the direction from the high potential side to the low potential side. ＨＬ is continuously applied. As a result, dielectric polarization occurs in the direction from the second terminal to the first terminal (negative direction) of the ferroelectric capacitor CF1 included in the memory cell MC. As a result, data with a logic value of "0" is written to the ferroelectric capacitor CF1 of the memory cell MC. In the timing chart of FIG. 5, the potential changes in the wiring RFL, wiring PL, and wiring BL in this case (when data with a logic value of "0" is held in the ferroelectric capacitor CF1) are indicated by thick dashed lines.

[0214] Furthermore, when the logic of the data written to the memory cell MC is “1”, in the period T12, the driving circuit PD applies a potential V ＨＬ Further, the potential V ＷＤ is applied. As a result, dielectric polarization occurs in the direction from the first terminal to the second terminal (positive direction) of the ferroelectric capacitor CF1 included in the memory cell MC. As a result, data with a logic value of "1" is written to the ferroelectric capacitor CF1 of the memory cell MC. In the timing chart of FIG. 5, the potential changes in the wiring RFL, wiring PL, and wiring BL in this case (when data with a logic value of "1" is held in the ferroelectric capacitor CF1) are shown by solid lines.

[0215] <<Period T13>> When the logic of the data written to the memory cell MC in the period T12 is “0”, in the period T13, V ＨＬ In addition, in the period T13, V is applied from the driver circuit WRBD to the wirings BL and RFL, continuing from the period T12. ＨＬ is given.

[0216] Also, when the logic of the data written to the memory cell MC in the period T12 is “1”, in the period T13, V is supplied from the drive circuit WRBD to the wiring BL via the wiring RFL. ＨＬ In addition, during the period T13, the driving circuit PD applies V to the wiring PL, continuing from the period T12. ＨＬ is given.

[0217] As described above, in the ferroelectric capacitor CF1 of the memory cell MC, the potential of the first terminal is V ＨＬ and the potential of the second terminal is V ＨＬ Even so, the ferroelectric capacitor CF1 continues to maintain the dielectric polarization generated inside as remanent polarization.

[0218] <<Period T14>> In the period T14, the driver circuit WRWD applies a low-level potential to the wiring WL, thereby applying the low-level potential to the gate of the transistor M1 included in the memory cell MC and turning off the transistor M1.

[0219] <<Period T15>> During the period T15, the control circuit CTLD applies a low-level potential to each of the wirings STLx and STLy. As a result, the low-level potential is applied to the gates of the transistors MN4a, MN4b, MN5a, and MN5b included in the circuit SA, turning these transistors off. In other words, there is no conduction between the wirings RFL and BL.

[0220] By performing the operation method from the period T10 to the period T15 in the timing chart shown in FIG. 5, data with a logic value of "0" or "1" can be written to the ferroelectric capacitor CF1 of the memory cell MC.

[0221] <Operation Example 3 of Memory Device> Next, an example of the operation of writing reference data to each of the memory cells MCr0 and MCr1 included in the memory device MDV shown in FIG. 2 will be described.

[0222] 4 and 5, the circuits SA[1] to SA[n] in the memory device MDV in Fig. 2 refer to the circuit SA in Fig. 1. The memory cells MCr0[1] to MCr0[n] in the memory device MDV in Fig. 2 refer to the memory cell MCr0 in Fig. 3B, and the memory cells MCr1[1] to MCr1[n] refer to the memory cell MCr1 in Fig. 3B.

[0223] 6 is a timing chart showing an example of the operation of the memory device MDV. In FIG. 6, the write operation of reference data to the memory cells MCr0 and MCr1 shows the potential changes of the wirings WLr, PLr, REQ, RFL, RFLB, STLx, STLy, RSTL, DRVL, the nodes SN, and SNB during periods T20 to T25. Also, in FIG. 6, as in FIGS. 4 and 5, a high-level potential is indicated as "High" and a low-level potential is indicated as "Low."

[0224] 6, unlike in FIGS. 4 and 5, the memory cell MC is not operated, and therefore potential changes in the wirings WL, PL, and BL are not shown in FIG.

[0225] In this operation example, the inverters IVa and IVb in the circuit SA can be stopped. Therefore, in the periods T20 to T25, a low-level potential is applied to the wirings RSTL and DRVL. Therefore, a low-level potential is applied to the gates of the transistors MN2a, MN2b, MN3a, and MN3b, turning these transistors off.

[0226] In this operation example, as described above, in order to stop the operations of the memory cell MC and the circuit SA, a low-level potential is applied to each of the wirings STLx and STLy in the periods T20 to T25. Therefore, a low-level potential is applied to each of the gates of the transistors MN4a, MN4b, MN5a, and MN5b, turning these transistors off.

[0227] In this operation example, the potentials of the node SN and the node SNB are not particularly limited. Therefore, the potentials of the node SN and the node SNB in ​​the periods T20 to T25 in the timing chart of FIG. 6 are indefinite, as indicated by diagonal hatching.

[0228] In this operation example, since the wirings RFL and RFLB are always disconnected from each other, a low-level potential is applied to the wiring REQ in the periods T20 to T25. As a result, the low-level potential is applied to the gate of the transistor M21, turning the transistor M21 off.

[0229] <<Period T20>> During period T20, a high-level potential is applied from the drive circuit RFWD to the wiring WLr. This applies the high-level potential to the gate of the transistor M10 included in the memory cell MCr0 and the gate of the transistor M11 included in the memory cell MCr1, turning these transistors on. In other words, conduction is established between the wiring RFL and the first terminal of the ferroelectric capacitor CF0, and between the wiring RFLB and the first terminal of the ferroelectric capacitor CF1.

[0230] In addition, in the period T20, the driver circuit RFPD applies a potential V ＨＬ The potential V ＨＬ Regarding V, which is explained in the operation example 1 of the storage device, ＨＬ As a result, the second terminal of the ferroelectric capacitor CF10 and the second terminal of the ferroelectric capacitor CF11 are connected to V ＨＬ is given.

[0231] In addition, in the period T20, as an example, the driver circuit WRBD supplies V ＨＬ As a result, the first terminals of the ferroelectric capacitors CF10 and CF11 are supplied with V from the drive circuit WRBD. ＨＬ The second terminals of the ferroelectric capacitors CF10 and CF11 are supplied with a potential V ＨＬ is given, no dielectric polarization occurs in either the ferroelectric capacitor CF10 or the ferroelectric capacitor CF11.

[0232] <<Period T21>> During the period T21, V ＷＤAs a result, V is applied to the second terminal of the ferroelectric capacitor CF10 included in the memory cell MCr0 and the second terminal of the ferroelectric capacitor CF11 included in the memory cell MCr1. ＷＤ The potential V ＷＤ Regarding V, which is explained in the operation example 1 of the storage device, ＷＤ can be referred to.

[0233] The potential V ＨＬ As a result, the voltage between the first terminal and the second terminal of the ferroelectric capacitor CF10 is V ＨＬ -V ＷＤ Therefore, dielectric polarization occurs in the direction from the second terminal to the first terminal (negative direction) of the ferroelectric capacitor CF10, whereby reference data with a logic value of "0" is written to the ferroelectric capacitor CF10 of the memory cell MCr0.

[0234] <<Period T22>> During period T22, in order to write reference data whose logic is “1” into memory cell MCr1, V ＷＤ Furthermore, since the transistor M11 is in an on state, the high-level potential is applied to the first terminal of the ferroelectric capacitor CF11 from the wiring RFLB via the source-drain of the transistor M11.

[0235] This causes dielectric polarization in the direction from the second terminal to the first terminal (positive direction) of the ferroelectric capacitor CF11 included in the memory cell MCr1, thereby writing reference data with a logic value of "1" to the ferroelectric capacitor CF11 of the memory cell MCr1.

[0236] <<Period T23>> During the period T23, V ＨＬ As a result, V is applied to the second terminal of the ferroelectric capacitor CF10 included in the memory cell MCr0 and the second terminal of the ferroelectric capacitor CF11 included in the memory cell MCr1. ＨＬ is given.

[0237] As a result of the above, the first terminal of the ferroelectric capacitor CF10 of the memory cell MCr0 is supplied with a potential V ＨＬ is applied to the second terminal of the ferroelectric capacitor CF10, and a potential V ＨＬ The ferroelectric capacitor CF10 has a first terminal and a second terminal, each of which is connected to V ＨＬ Even if a voltage Vcc is applied, the dielectric polarization generated in the ferroelectric capacitor CF10 during the period T21 continues to be maintained as remanent polarization.

[0238] <<Period T24>> During period T24, V is applied from the drive circuit WRBD to the wiring RFLB. ＨＬ As a result, V is applied to the first terminal of the ferroelectric capacitor CF11 included in the memory cell MCr1. ＨＬ is given.

[0239] As a result of the above, the first terminal of the ferroelectric capacitor CF11 of the memory cell MCr1 is supplied with V ＨＬ is applied to the second terminal of the ferroelectric capacitor CF11, and V ＨＬ The ferroelectric capacitor CF11 has a first terminal and a second terminal, each of which is connected to V ＨＬ Even if a voltage Vcc is applied, the dielectric polarization generated in the ferroelectric capacitor CF11 during the period T22 continues to be maintained as remanent polarization.

[0240] <<Period T25>> During period T25, the drive circuit RFWD applies a low-level potential to the wiring WLr, which applies the low-level potential to the gate of the transistor M10 included in the memory cell MCr0 and the gate of the transistor M11 included in the memory cell MCr1, turning these transistors off.

[0241] By performing the operation method from period T20 to period T25 of the timing chart shown in Figure 6, reference data with a logic value of "0" can be written to the ferroelectric capacitor CF10 of memory cell MCr0, and reference data with a logic value of "1" can be written to the ferroelectric capacitor CF11 of memory cell MCr1.

[0242] <Configuration Example 2 of Driver Circuit> Next, a configuration example of the inverter IVa and the inverter IVb included in the circuit SA of FIG. 2 etc. will be described.

[0243] The circuit SA1 shown in Fig. 7 is a circuit diagram showing a specific example of the configuration of the inverter IVa and the inverter IVb in the circuit SA shown in Fig. 2. As shown in Fig. 7, as an example, the inverter IVa has a transistor MP1a and a transistor MN1a, and the inverter IVb has a transistor MP1b and a transistor MN1b.

[0244] 7, the transistors MP1a and MP1b are p-channel transistors, and the transistors MN1a and MN1b are n-channel transistors, i.e., the inverters IVa and IVb are CMOS (Complementary MOS) circuits.

[0245] Furthermore, when the inverters IVa and IVb are each a CMOS circuit, it is preferable that the transistors MP1a, MN1a, MP1b, and MN1b are each a Si transistor, since Si transistors have a large on-state current. By using Si transistors for each of the above transistors, the driving speed of the inverters IVa and IVb can be increased.

[0246] Furthermore, Si transistors may be used as the p-channel transistors MP1a and MP1b, and OS transistors may be used as the n-channel transistors MN1a and MN1b. In particular, IO transistors are preferably used as the OS transistors. Because IO transistors have a large on-state current, they can be used in combination with p-channel Si transistors that also have a large on-state current to increase the driving speed of the inverters IVa and IVb.

[0247] In the inverter IVa, the gates of the transistors MP1a and MN1a are connected to each other, the first terminals of the transistors MP1a and MN1a are connected to each other, the second terminal of the transistor MP1a is connected to the wiring VDE, and the transistor MN1a is connected to the wiring VSE.

[0248] In particular, the gate of the transistor MP1a and the gate of the transistor MN1a function as input terminals of the inverter IVa, and the first terminal of the transistor MP1a and the first terminal of the transistor MN1a function as output terminals of the inverter IVa.

[0249] In inverter IVb, similarly to inverter IVa, the gates of transistors MP1b and MN1b are connected to each other, the first terminals of transistors MP1b and MN1b are connected to each other, the second terminal of transistor MP1b is connected to wiring VDE, and transistor MN1b is connected to wiring VSE.

[0250] In particular, the gate of the transistor MP1b and the gate of the transistor MN1b function as input terminals of the inverter IVb, and the first terminal of the transistor MP1b and the first terminal of the transistor MN1b function as output terminals of the inverter IVb.

[0251] For example, the wiring VDE functions as a wiring that applies a fixed potential. Specifically, the wiring VDE functions as a wiring that applies a high power supply potential for driving the inverters IVa and IVb. The high power supply potential may be, for example, a positive potential. Depending on the situation, the wiring VDE may also function as a wiring that applies a variable potential such as a pulse potential or a clock potential instead of a fixed potential.

[0252] The wiring VSE also functions as a wiring that applies a fixed potential, for example. Specifically, the wiring VSE functions as a wiring that applies a low power supply potential for driving the inverters IVa and IVb. The low power supply potential may be, for example, a ground potential or a negative potential. Depending on the situation, the wiring VSE may also function as a wiring that applies a variable potential such as a pulse potential or a clock potential instead of a fixed potential.

[0253] When the driving of the inverters IVa and IVb is stopped, for example, the wirings VDE and VSE may be applied with a ground potential or a high impedance.

[0254] Note that the semiconductor device of one embodiment of the present invention is not limited to a structure in which each of the inverters IVa and IVb is a CMOS circuit as shown in Figure 7. For example, in the semiconductor device of one embodiment of the present invention, each of the inverters IVa and IVb may be a unipolar circuit (a circuit including transistors with only one polarity, either n-channel transistors or p-channel transistors).

[0255] <Configuration Example 3 of Driver Circuit> Next, a modification of the circuit SA shown in FIG. 1 will be described.

[0256] The circuit SA2 shown in FIG. 8 is a modified example of the circuit SA in FIG. 1, and differs from the circuit SA in that the capacitive elements C3a and C3b are not provided.

[0257] 1, the capacitors C3a and C3b are capacitors for performing bootstrap and have a function of speeding up the potential changes at the nodes SN and SNB due to the inverter loop formed by the inverters IVa and IVb. Therefore, if it is not necessary to speed up the potential changes at the nodes SN and SNB due to the inverter loop, the capacitors C3a and C3b do not have to be provided as in the circuit SA2 of FIG.

[0258] 8, by employing a configuration in which the capacitors C3a and C3b are not provided, the circuit area of ​​the circuit SA2 can be reduced compared to the circuit area of ​​the circuit SA in Fig. 1. This allows the circuit area of ​​the driver circuit SAS and the circuit area of ​​the memory device MDV shown in Fig. 2 to be reduced.

[0259] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0260] Embodiment 2 In this embodiment, indium oxide that can be used as a metal oxide for a channel formation region of the IO transistor according to one embodiment of the present invention described in the above embodiment will be described.

[0261] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0262] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0263] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 9A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 9B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0264] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 9B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 9A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 9A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 9A.

[0265] 9A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0266] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0267] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0268] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties. In addition to the above elements, examples include elements contained in the conductive layer that can be used for the source electrode or the drain electrode, which will be described in Embodiment 3.

[0269] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 24A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0270] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0271] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0272] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0273] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0274] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0275] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0276] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0277] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0278] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0279] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 9C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0280] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0281] 9C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or, as mentioned above, reacts with oxygen contained in the film and is released as water molecules.

[0282] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0283] The table below shows the properties of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in the table below, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, because the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in the table below, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0284]

[0285] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0286] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0287] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0288] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0289] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0290] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0291] Embodiment 3 In this embodiment, a configuration example of a memory device, which is the semiconductor device described in Embodiment 1, will be described.

[0292] 10 is a perspective view schematically illustrating the memory device described in the above embodiment. The memory device MDV shown in FIG. 10 includes, as an example, a circuit layer SICL, a circuit layer IOCL, wiring layers ELRL1 and ELRL2, and a memory layer MCAL. The circuit layer SICL is located below the circuit layer IOCL, the wiring layer ELRL1 is located above the circuit layer IOCL, the wiring layer ELRL2 is located above the wiring layer ELRL1, and the memory layer MCAL is located above the wiring layer ELRL2.

[0293] The stacked structure of the circuit layer SICL and the circuit layer IOCL can be fabricated by directly forming the circuit layer IOCL on the circuit layer SICL, or by mounting the circuit layer IOCL on a substrate on which circuit elements such as transistors and capacitors are provided.

[0294] The circuit layer SICL can be formed by providing circuit elements such as transistors and capacitors on a substrate. A semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium) can be used as the substrate. Other than a semiconductor substrate, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film can be used. In this embodiment, unless otherwise specified, the substrate included in the circuit layer SICL will be described as a semiconductor substrate having silicon.

[0295] The substrate included in the circuit layer SICL is a semiconductor substrate having silicon, and by separately creating a low-resistance region and a semiconductor region in the semiconductor substrate, Si transistors can be formed in the circuit layer SICL. Si transistors have high field-effect mobility and can therefore pass large on-currents. As a result, by using Si transistors as transistors in each of the drive circuits listed above, it is possible to increase the drive speed of each drive circuit, widen the signal range, and so on.

[0296] Furthermore, when the circuit layer IOCL is formed directly on the circuit layer SICL, the circuit layer IOCL preferably includes an OS transistor. OS transistors can be formed not only on a semiconductor substrate but also on an insulating substrate, a conductive substrate, or even on a conductive film, an insulating film, or a semiconductor film, and therefore can be easily provided on the semiconductor substrate (on the circuit layer SICL) on which the OS transistor is formed. As a result, the memory device MDV can have a stacked structure of Si transistors and OS transistors. Furthermore, using an IO transistor as the OS transistor allows a large on-current to flow, thereby enabling the driving speed of a driver circuit including the IO transistor to be increased and the signal range to be widened.

[0297] Specifically, the circuit layer IOCL may be provided with transistors MN2a to MN5a and transistors MN2b to MN5b included in the circuit SA1 shown in Fig. 7. Furthermore, the circuit layer SICL may be provided with Si transistors included in the inverters IVa and IVb. That is, the circuit layer SICL may be provided with transistors MP1a, MP1b, MN1a, and MN1b included in the circuit SA1 shown in Fig. 7.

[0298] Furthermore, when circuit elements such as transistors and capacitors are formed on a substrate as the circuit layer IOCL and the substrate is mounted on the circuit layer SICL, flip-chip bonding or wire bonding can be used. Alternatively, a first bonding layer may be provided on the circuit layer SICL side, a second bonding layer may be provided on the substrate of the circuit layer IOCL, and the first and second bonding layers may be bonded together using one or both of a surface activated bonding method and a hydrophilic bonding method, thereby mounting the circuit layer IOCL on the circuit layer SICL. For example, Cu-Cu (copper-copper) direct bonding may be used, in which copper (Cu) is used as the conductor contained in each of the first and second bonding layers and copper is bonded to each other.

[0299] Furthermore, the stacked structure of the circuit layer IOCL and the wiring layer ELRL1 can be fabricated by forming the wiring layer ELRL1 directly on top of the circuit layer IOCL. Similarly, the stacked structure of the wiring layer ELRL1 and the wiring ELRL2 can be fabricated by forming the wiring layer ELRL2 directly on top of the wiring layer ELRL1, and the stacked structure of the wiring layer ELRL2 and the memory layer MCAL can be fabricated by forming the memory layer MCAL on top of the wiring layer ELRL2.

[0300] 7 shows two wiring layers, a wiring layer ELRL1 and a wiring layer ELRL2. Note that one aspect of the present invention is not limited to the above, and the number of wiring layers provided in the memory device MDV may be one layer or three or more layers.

[0301] Each of the wiring layers ELRL1 and ELRL2 includes, for example, wiring for transmitting signals for driving the circuit SA. Specifically, for example, the wiring layer ELRL1 includes wiring RSTL and wiring DRVL, and for example, the wiring layer ELRL2 includes wiring STLx and wiring STLy.

[0302] 2. Therefore, the memory layer MCAL has a plurality of memory cells MC, a plurality of memory cells MCr0, and a plurality of memory cells MCr1. Also, from FIG. 3A and FIG. 3B, it can be said that the memory layer MCAL includes a transistor M1 and a ferroelectric capacitor CF1 included in the memory cell MC, a transistor M10 and a ferroelectric capacitor CF10 included in the memory cell MCr0, a transistor M11 and a ferroelectric capacitor CF11 included in the memory cell MCr1, and a transistor M21.

[0303] <Example of memory device layout> Fig. 11A is a plan view schematic diagram showing an example of the configuration of a circuit included in the circuit layer SICL shown in Fig. 10, and Fig. 11B is a plan view schematic diagram showing an example of the configuration of a circuit included in the circuit layer IOCL shown in Fig. 10. Fig. 12 is a plan view schematic diagram showing an example of the configuration of wiring included in the wiring layer ELRL1, and Figs. 13A and 13B are each a part of a plan view schematic diagram showing an example of the configuration of wiring included in the wiring layer ELRL2. In particular, Figs. 11A to 13B are each an example of a plan view schematic diagram showing the circuit configuration of the circuit SA shown in Fig. 7.

[0304] 11A, the circuit layer SICL includes, for example, a conductive layer 131, a conductive layer 132, a conductive layer 135, conductive layers 136[1] to 136[4], a semiconductor region 171, a low-resistance region 172, a semiconductor region 173, and a low-resistance region 174. In order to clearly show the schematic plan view, insulating layers included in the circuit layer SICL are not shown in FIG.

[0305] 11B, the circuit layer IOCL includes, for example, a conductive layer 231, a conductive layer 232, a conductive layer 235, a conductive layer 236, a conductive layer 237, conductive layers 238[1] to 238[8], conductive layers 136[1] to 136[4], and a semiconductor layer 251. Note that, in order to clearly show the schematic plan view, insulating layers included in the circuit layer IOCL are not shown in FIG.

[0306] First, in FIG. 11A , consider a case where the channel formation regions of transistors MN1a, MP1a, MN1b, and MP1b are included in a single-crystal substrate made of silicon. That is, assume that each of these transistors is a Si transistor. In this case, a circuit pattern including semiconductor region 171, low-resistance region 172, semiconductor region 173, and low-resistance region 174 can be formed on the single-crystal substrate by performing exposure and development processes, etching processes, resist stripping and cleaning processes, etc. Furthermore, semiconductor region 171, low-resistance region 172, semiconductor region 173, and low-resistance region 174 can be separately formed by adjusting the amount of carriers injected.

[0307] 11A, the transistors MN1a, MP1a, MN1b, and MP1b each have a fin-type transistor structure. A fin-type transistor, for example, is a transistor having a structure in which, in a plan view, the channel width d5p or d5n of the semiconductor region 173 is shorter than the width d0 of the low-resistance region 174. A fin-type transistor, for example, is a transistor having a structure in which, in a cross-sectional view in the channel width direction, the semiconductor region 173 has a convex shape and the conductive layer 231 is formed so as to cover the convex shape of the semiconductor region 173. As described above, by forming the semiconductor region 173 to have a convex shape and the conductive layer 131 so as to cover the convex shape, the effective channel width of the semiconductor region 173 can be increased, thereby improving the on-state characteristics. Furthermore, the contribution of the electric field from the conductive layer 131 to the inside of the semiconductor region 173 is increased, thereby reducing the off-state current. For this reason, by applying fin-type transistors to the transistors MN1a, MP1a, MN1b, and MP1b, the on-state characteristics of these transistors can be improved and the off-state current can be reduced. Fin-type transistors will be described in detail later.

[0308] Specifically, for example, d5p or d5n is preferably 0.5 times or more and less than 1 time of d0, more preferably 0.1 times or more and less than 0.5 times, and even more preferably 0.01 times or more and less than 0.1 times.

[0309] Each of the channel widths d5p and d5n is, for example, preferably 1000 μm or more and 3000 μm or less, more preferably 100 μm or more and less than 1000 μm, even more preferably 10 μm or more and less than 100 μm, even more preferably 1000 nm or more and less than 10 μm, even more preferably 100 nm or more and less than 1000 nm, and even more preferably 10 nm or more and less than 100 nm.

[0310] Furthermore, when it is desired to increase the on-state current of each of transistors MN1a, MP1a, MN1b, and MP1b, it is preferable to shorten the channel length d6n of transistor MN1a or MN1b and the channel length d6p of transistor MP1a or MP1b. Note that d6n and d6p do not have to be equal in length. For example, in order to equalize the field-effect mobilities of transistors MN1a and MP1a, it is preferable that d6n of transistor MN1a and d6p of transistor MP1a are each appropriately tuned. Note that the same applies to d6n of transistor MN1b and d6p of transistor MP1b.

[0311] Furthermore, each of the channel lengths d6p and d6n is, for example, preferably 1000 μm or more and 3000 μm or less, more preferably 100 μm or more and less than 1000 μm, even more preferably 10 μm or more and less than 100 μm, even more preferably 1000 nm or more and less than 10 μm, even more preferably 100 nm or more and less than 1000 nm, and even more preferably 10 nm or more and less than 100 nm.

[0312] 11A may be an IO transistor instead of a Si transistor. Also, a low resistance region included in the IO transistor may include a conductive layer.

[0313] For example, the conductive layer 131 is provided above the semiconductor region 171, the low-resistance region 172, the semiconductor region 173, or the low-resistance region 174. The conductive layer 131 also functions as a wiring and as the gates of the transistors MN1a, MP1a, MN1b, and MP1b.

[0314] For example, the conductive layer 132 is provided above the semiconductor region 171 , the low resistance region 172 , the semiconductor region 173 , the low resistance region 174 , or the conductive layer 131 .

[0315] The conductive layer 132 also functions as a wiring. For example, part of the conductive layer 132 may extend as a wiring VSE or a wiring VDE.

[0316] Part of the conductive layer 131 functions as a wiring. For example, part of the conductive layer 131 can serve as a wiring for connecting to part of the conductive layer 132 through the conductive layer 135.

[0317] An insulating layer (not shown) functioning as a first interlayer film is provided between the semiconductor region 171, the low-resistance region 172, the semiconductor region 173, the low-resistance region 174, or the conductive layer 131 and the conductive layer 132. Openings are provided in a partial region of the insulating layer where the low-resistance region 172 and the conductive layer 132 overlap, a partial region of the insulating layer where the low-resistance region 174 and the conductive layer 132 overlap, and a partial region of the insulating layer where the conductive layer 131 and the conductive layer 132 overlap. Openings are also provided in a region of the insulating layer that overlaps with a conductive layer 136[2] (described later) and a region of the insulating layer that overlaps with a conductive layer 136[4]. A conductive layer 135 is embedded in these openings.

[0318] By embedding the conductive layer 135 in the opening of the insulating layer, for example, charge can move between the low-resistance region 172 and the conductive layer 132 via the conductive layer 135, and charge can move between the low-resistance region 174 and the conductive layer 132 via the conductive layer 135. Furthermore, charge can move between the conductive layer 131 and the conductive layer 132 via the conductive layer 135. That is, in FIG. 11A , the conductive layer 135 functions as a contact plug.

[0319] Furthermore, an insulating layer (not shown) functioning as a second interlayer film is provided above each of the semiconductor region 171, the low-resistance region 172, the semiconductor region 173, the low-resistance region 174, the conductive layer 131, and the conductive layer 132. In particular, openings are provided in the insulating layer located on a part of the upper surface of the conductive layer 132, and the conductive layers 136[1] to 136[4] are embedded in the openings.

[0320] Each of the conductive layers 136[1] to 136[4] functions as a contact plug for establishing electrical connection with a circuit element included in the circuit layer IOCL.

[0321] 11B , each of the transistors MN2a to MN5a and the transistors MN2b to MN5b includes an island-shaped insulating layer, a semiconductor layer 251 formed over the insulating layer, a conductive layer 231 formed over the semiconductor layer 251, a gate insulating film formed over the semiconductor layer 251, and a conductive layer 232 formed over the gate insulating film. Each of the transistors MN2a to MN5a and the transistors MN2b to MN5b can have a gate last (GL) structure (also referred to as a trench gate self-align or top gate self-align (TGSA) structure) described later.

[0322] For example, the semiconductor layer 251 is located below the conductive layers 231 and 232. For example, the conductive layer 235 is located above the conductive layers 231 and 232. For example, the conductive layer 233 is located above the conductive layer 235. For example, the conductive layer 236 is located above the conductive layer 235. For example, the conductive layer 237 is located above the conductive layer 236. The order of formation can be as follows: first, the semiconductor layer 251, second, the conductive layer 231, third, the conductive layer 232, fourth, the conductive layer 235, fifth, and sixth, the conductive layer 236.

[0323] In the circuit layer IOCL, parts of the conductive layer 231 function as the sources or drains of the transistors MN2a to MN5a and the transistors MN2b to MN5b, for example.

[0324] In the circuit layer IOCL, a part of the conductive layer 232 functions as the gates of the transistors MN2a to MN5a and the transistors MN2b to MN5b, for example.

[0325] Note that the transistors MN2a to MN5a and the transistors MN2b to MN5b each function as a switching transistor as described above. Therefore, it is preferable that the channel width d3 of each of the transistors be short and the channel length d4 of each of the transistors be long. For example, the ratio of d4 to d3 is preferably greater than 1 and less than or equal to 2, more preferably greater than 1 and less than or equal to 5, and even more preferably greater than 1 and less than or equal to 10.

[0326] Furthermore, each of the channel widths d3 is, for example, preferably 100 μm or more and 300 μm or less, more preferably 10 μm or more and less than 100 μm, even more preferably 1 μm or more and less than 10 μm, even more preferably 100 nm or more and less than 1 μm, and even more preferably 10 nm or more and less than 100 nm.

[0327] Furthermore, each of the channel lengths d4 is, for example, preferably 1000 μm or more and 3000 μm or less, more preferably 100 μm or more and less than 1000 μm, even more preferably 10 μm or more and less than 100 μm, even more preferably 1000 nm or more and less than 10 μm, even more preferably 100 nm or more and less than 1000 nm, and even more preferably 10 nm or more and less than 100 nm.

[0328] The conductive layer 232 also functions as a wiring for electrical connection to a circuit element included in the circuit layer SICL. For this reason, the conductive layer 232 is connected to conductive layers 238[1] to 238[8] that function as contact plugs, for example. Note that the conductive layers 238[1] to 238[8] will be described later.

[0329] An insulating layer can be provided between the semiconductor layer 251 and the conductive layer 232. In particular, the insulating layer may function as a gate insulating film of each of the transistors MN2a to MN5a and the transistors MN2b to MN5b.

[0330] In the circuit layer IOCL, the conductive layer 233 functions as one of a pair of electrodes of the capacitor C1a, one of a pair of electrodes of the capacitor C1b, one of a pair of electrodes of the capacitor C3a, and one of a pair of electrodes of the capacitor C3b, for example. The conductive layer 233 also functions as a wiring for electrical connection with circuit elements included in the circuit layer SICL. Therefore, the conductive layer 233 is connected to the conductive layers 136[1] to 136[4], which function as contact plugs, for example.

[0331] An insulating layer (not shown) functioning as a third interlayer film is provided between the conductive layer 231 and the conductive layer 233. An opening is provided in a partial region of the insulating layer where the conductive layer 231 and the conductive layer 233 overlap each other, and a conductive layer 235 is embedded in the opening as a contact plug for connecting the conductive layer 231 and the conductive layer 233 to each other.

[0332] In addition, in the circuit layer IOCL, a part of the conductive layer 237 functions as the other of the pair of electrodes of the capacitor C1a, for example. In the circuit layer IOCL, another part of the conductive layer 237 functions as the other of the pair of electrodes of the capacitor C1b, for example.

[0333] An insulating layer (not shown) functioning as a fourth interlayer film is provided between the conductive layer 233 and the conductive layer 237. An opening is provided in a partial region of the insulating layer where the conductive layer 233 and the conductive layer 237 overlap each other, and a conductive layer 236 is embedded in the opening as a contact plug for connecting the conductive layer 233 and the conductive layer 237 to each other.

[0334] An insulating layer (not shown) functioning as a fifth interlayer film is provided above each of the conductive layers 232, 233, and 237. In particular, openings are provided in the insulating layer located on a part of the upper surface of the conductive layer 232, and conductive layers 238[1] to 238[8] are embedded in the openings.

[0335] Each of the conductive layers 238[5] to 238[8] functions as a contact plug for establishing electrical connection with a wiring included in the circuit layer ELRL1. Each of the conductive layers 238[1] to 238[4] functions as a contact plug for establishing electrical connection with a wiring included in the circuit layer ELRL2.

[0336] 12, the wiring layer ELRL1 includes a conductive layer 931. Note that the conductive layer 931 is formed so as to be connected to the conductive layers 238[5] to 238[8] embedded in the openings of the fifth interlayer film. The wiring layer ELRL1 also includes parts of the conductive layers 238[1] to 238[4].

[0337] The conductive layer 931 also functions as a wiring, for example. For example, a part of the conductive layer 931 extends as a wiring RSTL in the circuit SA of FIG. 1 , and another part of the conductive layer 931 extends as a wiring DRVL in the circuit SA of FIG. 1 .

[0338] 13A , the wiring layer ELRL2 includes a conductive layer 932, a conductive layer 933, and a conductive layer 934. For example, the conductive layer 932 is located above the conductive layers 238[1] to 238[4] which function as contact plugs. The conductive layer 933 is located above the conductive layer 932. The conductive layer 934 is located above the conductive layer 933.

[0339] In particular, an insulating layer (not shown) functioning as a sixth interlayer film is provided above the conductive layer 932. An opening is provided in the insulating layer located on a part of the upper surface of the conductive layer 932, and a conductive layer 933 is provided in the opening.

[0340] A conductive layer 934 is provided above the insulating layer having a function as a sixth interlayer film. In particular, the conductive layer 934 is connected to the conductive layer 932 through the conductive layer 933. That is, the conductive layer 933 functions as a contact plug for flowing charges between the conductive layer 932 and the conductive layer 934.

[0341] Each of the conductive layers 932, 933, and 934 included in the wiring layer ELRL2 functions as a wiring. For example, in Fig. 13A, a wiring STLx is formed by a part of the conductive layer 932, a part of the conductive layer 933, and a part of the conductive layer 934. Similarly, for example, in Fig. 13A, a wiring STLy is formed by a part of the conductive layer 932, a part of the conductive layer 933, and a part of the conductive layer 934.

[0342] Furthermore, for the convenience of connection with the circuit layer IOCL, the wiring STLx and the wiring STLy have an area ARE where they overlap each other. Specifically, the circuit layer IOCL includes an area ARE where the conductive layer 932 and the conductive layer 934 overlap each other. For this reason, parasitic capacitance may be formed between the wiring STLx and the wiring STLy in the area ARE. Measures for reducing this parasitic capacitance include, for example, thickening the sixth interlayer film, lowering the dielectric constant of the insulating layer used in the sixth interlayer film, and the like.

[0343] Another method is to reduce the area of ​​the region ARE where the conductive layer 932 and the conductive layer 934 overlap each other. As shown in FIG. 13A , one way to reduce this area is to make the wiring width d1 of the conductive layer 932 included in the region ARE shorter than the wiring width d2 of the conductive layer 932 outside the region ARE. The same applies to the conductive layer 934, and the wiring width of the conductive layer 934 included in the region ARE may be made shorter than the wiring width of the conductive layer 934 outside the region ARE. This reduces the area of ​​the region ARE, thereby reducing the influence of parasitic capacitance that may be formed in the region ARE.

[0344] In order to reduce the influence of parasitic capacitance by means other than those described above, it is preferable to provide the wiring STLx and the wiring STLy as shown in the schematic plan view of Fig. 13B. In the schematic plan view of Fig. 13B, the wiring STLx1, the wiring STLx2, and the wiring STLy extend in the wiring layer ELRL2.

[0345] The wiring STLx1 and the wiring STLx2 are obtained by dividing the wiring STLx shown in FIG. 13A into two. That is, a part of the conductive layer 932 is formed as the wiring STLx1, and another part of the conductive layer 932 is formed as the wiring STLx2. As shown in the schematic plan view of FIG. 13B, by dividing the wiring STLx into two, the wiring STLx1 and the wiring STLx2, there are no overlapping regions between the wiring STLy and the wiring STLx1 and between the wiring STLy and the wiring STLx2, thereby reducing the influence of parasitic capacitance. Furthermore, there is no need to provide a conductive layer 934 for crossing the wiring STLy with the wiring STLx1 or the wiring STLx2. There is also no need to embed a conductive layer 933 functioning as a plug in the sixth interlayer film. This reduces the number of steps required to manufacture the memory device MDV. This makes it possible to reduce the cost and takt time involved in manufacturing the memory device MDV.

[0346] 13B shows two wirings, wiring STLx1 and wiring STLx2, but for driving operation, it is preferable that the same signal is applied to STLx1 and wiring STLx2. As a result, the memory device MDV to which the configuration of the plan view diagram of FIG. 13B is applied can operate in the same way as when the configuration of the plan view diagram of FIG. 13A is applied.

[0347] 11A to 13B, a conductive layer 131, a conductive layer 132, a conductive layer 135, a conductive layer 136[1] to a conductive layer 136[4], a conductive layer 231, a conductive layer 232, a conductive layer 233, a conductive layer 235, a conductive layer 236, a conductive layer 237, a conductive layer 238[1] to a conductive layer 238[8], a conductive layer 931, a conductive layer 932, a conductive layer 933, and a conductive layer 934 each partially function as a wiring, and therefore, a highly conductive material is preferably used. Specific highly conductive materials will be described later.

[0348] Each of the above-described conductive layers can be formed by, for example, lithography. Specifically, for example, when forming the conductive layer 231, a conductive material to be the conductive layer 231 can be formed by one or more methods selected from a sputtering method, a chemical vapor deposition (CVD) method, a pulsed laser deposition (PLD) method, and an atomic layer deposition (ALD) method, and then a desired pattern can be formed by lithography. Furthermore, conductive layers, semiconductor layers, and insulating layers other than the conductive layer 231 can also be formed by the same methods as above.

[0349] In this specification, the lithography method includes, for example, photolithography, ion beam lithography, X-ray lithography, electron beam lithography, multiphoton lithography, interference lithography, and nanoimprinting.

[0350] Furthermore, an insulating layer can be provided between the conductive layer 233 and the conductive layer 237. In particular, in the region where the capacitance elements C1a, C1b, C3a, and C3b are provided, the insulating layer formed so as to overlap between the conductive layer 233 and the conductive layer 237 is preferably an insulating layer that functions as a dielectric in each of the capacitance elements.

[0351] 11B, the capacitance elements C1a, C1b, C3a, and C3b each have a parallel plate structure. Furthermore, since the conductive layers 233 and 237 are provided at a higher position than the other conductive layers, it is possible to easily secure an area for providing the capacitance elements, and it is possible to reduce the circuit area of ​​the memory device MDV.

[0352] Although not shown, the ferroelectric capacitor CF1, the ferroelectric capacitor CF10, and the ferroelectric capacitor CF11 shown in FIG. 3 of the first embodiment can also have a parallel plate structure, similar to the capacitive elements C1a, C1b, C3a, and C3b, respectively.

[0353] In addition, in the schematic plan view of Figure 11B, each of the capacitance elements C1p, C3p, C1n, and C3n is a parallel plate capacitance element, but they can be changed to a capacitance element in which a pair of electrodes and a dielectric are embedded in an opening in an insulating layer, as shown in the schematic cross-sectional view of Figure 19A, which will be described later.

[0354] 7, the wiring VDE is connected to the second terminal of the transistor MP1a and the second terminal of the transistor MP1b. Therefore, the layout may be designed so that the second terminal of the transistor MP1a and the second terminal of the transistor MP1b share the same wiring. For example, as shown in FIG. 11A, the transistors MP1b and MP1a are formed in a region in which, from left to right in the drawing, the low-resistance region 174, the semiconductor region 173, the low-resistance region 174, the semiconductor region 173, and the low-resistance region 174 are arranged side by side. In other words, in the schematic plan view of FIG. 11A, the transistors MP1b and MP1a are formed so as to share the low-resistance region 174 located in the center. This reduces the formation area of ​​the transistors included in the circuit SA1. This also reduces the circuit area of ​​the memory device MDV.

[0355] <Example of Cross-Sectional Configuration of Memory Device> Fig. 14 is a schematic cross-sectional view of the memory device MDV taken along the dashed line D1-D2 shown in Figs. 11A to 12 and 13B. Fig. 14 selectively shows the circuit layers SICL, IOCL, ELRL1, and ELRL2.

[0356] 14 illustrates transistors MP1a and MP1b included in the circuit layer SICL as Si transistors. By using Si transistors for the transistors MP1a and MP1b, a CMOS circuit including p-channel transistors and n-channel transistors can be configured in the circuit layer SICL. In particular, since the inverters IVa and IVb described in the above embodiment include p-channel transistors and n-channel transistors, it is preferable that the inverters IVa and IVb be provided in the circuit layer SICL as a CMOS circuit.

[0357] The stacked structure of the circuit layer SICL and the circuit layer IOCL can be fabricated by directly forming the circuit layer IOCL on the circuit layer SICL. Alternatively, the circuit layer IOCL can be fabricated by forming a substrate on which circuit elements such as transistors and capacitors are provided, and then mounting the substrate on the circuit layer SICL. When the circuit layer IOCL is formed directly on the circuit layer SICL, the circuit layer IOCL preferably includes an OS transistor. An IO transistor can be used as the OS transistor. Since an OS transistor can be formed on a substrate such as a semiconductor substrate, an insulating substrate, or a conductor substrate, or on a film such as a conductive film, an insulating film, or a semiconductor film, it can be easily provided on a semiconductor substrate (on the circuit layer SICL) on which a Si transistor is formed.

[0358] Alternatively, p-channel transistors may be provided as Si transistors in the circuit layer SICL, and n-channel transistors may be provided as OS transistors in the circuit layer IOCL. Specifically, for example, the p-channel transistors MP1a and MP1b shown in FIG. 7 may be provided in the circuit layer SICL, and the n-channel transistors MN1a and MN1b may be provided in the circuit layer IOCL. Note that the configuration in which p-channel transistors are provided as Si transistors in the circuit layer SICL and n-channel transistors are provided as OS transistors in the circuit layer IOCL can be applied not only to the circuit SA in FIG. 2 but also to other driver circuits.

[0359] The transistors MP1a and MP1b are provided on a substrate 101 and include a conductive layer 131 that functions as a gate, an insulating layer 161 and an insulating layer 111 that function as gate insulating films, a semiconductor region 173a and a semiconductor region 173b that include a part of the substrate 101, and a low-resistance region 174a, a low-resistance region 174b, and a low-resistance region 174c that function as a source region or a drain region that include a part of the substrate.

[0360] 14 , an element isolation layer 102 is provided on the substrate 101. The element isolation layer 102 is provided to isolate a plurality of transistors formed on the substrate 101 from each other. Specifically, in FIG. 14 , the element isolation layer 102 is provided to isolate a region including semiconductor regions 173 a and 173 b and low-resistance regions 174 a to 174 c from other semiconductor regions and low-resistance regions. The element isolation layer 102 can be formed using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0361] As an example, the transistors MP1a and MP1b shown in FIG. 14 may have a convex semiconductor region 171 (a part of the substrate 101) where a channel is formed, as shown in the cross-sectional view of FIG. 15 . Note that FIG. 15 is a cross-sectional view of the transistor MP1a or MP1b in the channel width direction. A conductive layer 131 is provided to cover the side and top surfaces of the semiconductor region 171 via an insulating layer 161. Note that the conductive layer 131 may be made of a material that adjusts the work function. Such transistors MP1a and MP1b are also called fin-type transistors because they utilize the convex portion of the semiconductor substrate. An insulating layer may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. While the example shown here shows the case where the convex portion is formed by processing a portion of the semiconductor substrate, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0362] 14 and 15 are merely examples, and the present invention is not limited to these structures, and appropriate transistors can be used depending on the circuit configuration or driving method. Furthermore, the transistors MN1a and MN1b in FIG. 11A, which are not shown in FIG. 14, can also be fin-type transistors similar to the transistors MP1a and MP1b shown in FIG. 14 and 15, and are not limited to these structures, and appropriate transistors can be used depending on the circuit configuration or driving method.

[0363] The memory device MDV may be provided with a wiring layer provided with an interlayer film, wiring, and plugs. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification, the wiring and the plugs connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0364] For example, an insulating layer 112, an insulating layer 181, and an insulating layer 113 are stacked in this order as an interlayer film over the transistor MP1a and the transistor MP1b. A conductive layer 135 and the like are embedded in the insulating layer 112. A conductive layer 132 and the like are embedded in the insulating layer 181 and the insulating layer 113. The conductive layer 132 and the conductive layer 135 function as contact plugs or wirings. In this case, a layer including the insulating layer 181, the insulating layer 113, and the conductive layer 132 may be used as a wiring layer.

[0365] The insulating layer serving as an interlayer film may also serve as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 112 may be planarized by a planarization treatment using a chemical mechanical polishing (CMP) method to improve the planarity.

[0366] A wiring layer may be provided over the insulating layer 113 and the conductive layer 132. For example, in FIG. 14 , an insulating layer 182, an insulating layer 114, an insulating layer 115, and an insulating layer 116 are stacked in this order over the insulating layer 113 and the conductive layer 132. In addition, a conductive layer 136 is formed in the insulating layer 182, the insulating layer 114, and the insulating layer 115. The conductive layer 136 functions as a contact plug or a wiring.

[0367] An insulating layer 281 is provided on the insulating layer 116. It is preferable that contact plugs or wiring for connecting to an upper circuit (for example, a circuit element included in a circuit included in the circuit layer IOCL) be embedded in the insulating layer 116 and the insulating layer 281.

[0368] Next, a configuration example of the transistors and capacitance elements included in the circuit layer IOCL shown in FIG. 14 will be described.

[0369] 14, transistors MN3a and MN3b are formed on an insulating layer 281. An insulating layer 285 is formed on the transistors MN3a and MN3b, and capacitive elements C1a, C1b, C3a, and C3b are formed on the insulating layer 285. In other words, the insulating layer 285 can be said to be located above the insulating layer 281. The capacitive elements C1a, C1b, C3a, and C3b can be said to be located above the transistors MN3a and MN3b, respectively.

[0370] 14 shows a cross section in the channel width direction of a transistor MN3a and a transistor MN3b, each of which has a GL structure, which will be described later. The GL structure transistor will be described later.

[0371] 14 preferably function as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, the insulating layer 181, the insulating layer 182, the insulating layer 281, and the insulating layer 285 can suppress the permeation of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (for example, N ２ O, NO or NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., through which the oxygen is less likely to permeate). Note that for materials that can be used for the insulating layer 181, the insulating layer 182, the insulating layer 281, and the insulating layer 285, the description of the insulating layers in the section on constituent materials of transistors can be referred to.

[0372] 14, the gate electrode of transistor MN3a is connected to a conductive layer 931 that will become the wiring DRVL via a conductive layer 238[7] that functions as a contact plug. Similarly, the gate electrode of transistor MN3b is connected to a conductive layer 931 that will become the wiring DRVL via a conductive layer 238[8] that functions as a contact plug.

[0373] 14 also shows a conductive layer 234, which is not shown in FIG. 11B. The conductive layer 234 functions as the back gate electrodes of the transistors MN3a and MN3b. The conductive layer 234 also functions as wiring (sometimes referred to as back gate wiring) for applying a potential to the back gates. Therefore, the conductive layer 234 extends below the transistors MN3a and MN3b.

[0374] By providing back gate electrodes in the transistors MN3a and MN3b, the threshold voltages of the transistors MN3a and MN3b can be changed. For example, in each of the transistors MN3a and MN3b, by connecting the gate electrode and the back gate electrode and applying a high-level potential to the gate electrode, the threshold voltage can be lowered and the on-current can be increased. By applying a low-level potential to the gate electrode, the threshold voltage can be increased and the off-current can be reduced. Alternatively, instead of connecting the gate electrode and the back gate electrode, the back gate electrode may be connected to a drive circuit, an external circuit, or the like, and a potential may be applied to the back gate electrode from the drive circuit, the external circuit, or the like. In other words, potentials may be applied to the gate electrode and the back gate electrode from different circuits.

[0375] In the case where a back gate electrode is provided in a transistor, it is preferable not to provide a conductive layer near the back gate electrode in order to avoid formation of parasitic capacitance with the back gate electrode.

[0376] Although not shown, a back gate electrode may also be provided for each of the transistors MN2a, MN2b, MN4a, MN4b, MN5a, and MN5b.

[0377] A conductive layer 233 functioning as one of a pair of electrodes of each of the capacitors C1a, C1b, C3a, and C3b is formed so as to be embedded in the insulating layer 217 on the insulating layer 285. An insulating layer 241 functioning as a dielectric of each of the capacitors is provided on the conductive layer 233. A conductive layer 237 functioning as the other of the pair of electrodes of the capacitors is provided on the insulating layer 241.

[0378] As shown in FIG. 14 , the conductive layer 233, which functions as one of the pair of electrodes of each of the capacitor elements C1a, C1b, C3a, and C3b, is embedded in the insulating layer 217, thereby enabling the conductive layer 233 and the insulating layer 217 to be flat and flush with each other. This allows the insulating layer 241, which functions as a dielectric, and the conductive layer 237, which functions as the other of the pair of electrodes of each of the capacitor elements, to be formed on the top surfaces of the highly flat conductive layer 233 and the insulating layer 217, respectively. By improving the flatness of both the pair of electrodes of each of the capacitor elements and the insulating layer 241, which functions as a dielectric, it is possible to suppress localized electric field concentration, thereby preventing leakage current between the pair of electrodes of each of the capacitor elements. Furthermore, one of the pair of electrodes of each of the capacitor elements (here, the lower electrode) has a smaller area than the other of the pair of electrodes of each of the capacitor elements (here, the upper electrode). This configuration makes it possible to suppress local electric field concentration that may occur in each dielectric film (insulating film sandwiched between a pair of electrodes) of the above-mentioned capacitance element, thereby realizing a highly reliable semiconductor device.

[0379] The insulating layer 241 may be made of, for example, a dielectric material that can be used for the insulating layer 441 described later.

[0380] For example, in the circuit SA of FIG. 1, by using the capacitance element C1a as the capacitance element shown in FIG. 14, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C1a between the terminal IOT and the node SN. Similarly, by using the capacitance element C1b as the capacitance element shown in FIG. 14, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C1b between the terminal IOTB and the node SNB. Furthermore, by using the capacitance element C3a as the capacitance element shown in FIG. 14, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C3b between the output terminal of the inverter IVa and the node SNB. Furthermore, by using the capacitance element C3b as the capacitance element shown in FIG. 14, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C3b between the output terminal of the inverter IVb and the node SN. Furthermore, local electric field concentration can be suppressed in the dielectrics of the capacitance elements C1a, C1b, C3a, and C3b, thereby preventing operational problems in the circuit SA.

[0381] 11B are preferably OS transistors, as described in the above embodiment. The oxide semiconductor included in the channel formation region of the OS transistor has a band gap of 2 eV or more, and therefore the off-state current is significantly small. Therefore, power consumption due to leakage current or the like in the memory device MDV can be reduced.

[0382] Furthermore, OS transistors operate stably even in high-temperature environments, with little fluctuation in characteristics. For example, the off-state current hardly increases even in high-temperature environments. Specifically, the off-state current hardly increases even in environments above room temperature and below 200° C. Furthermore, the on-state current is unlikely to decrease even in high-temperature environments. Therefore, a memory device MDV including an OS transistor in a circuit layer IOCL operates stably even in high-temperature environments.

[0383] In particular, by using indium oxide as the oxide semiconductor, that is, by using each of the transistors M2a to M5a and the transistors M2b to M5b as an IO transistor, the transistors can have a small off-state current and a large on-state current, which may enable a memory device that can be operated at a high operating speed.

[0384] <<Transistor Configuration Example 1>> Next, a specific configuration example of a transistor called a GL structure that can be applied to the transistors MN3a and MN3b shown in Fig. 14 will be described. A transistor 200 shown in Fig. 16A and 16B is an example of a transistor with a GL structure that can be applied not only to the transistors MN3a and MN3b shown in Fig. 14 but also to the transistors MN2a, MN2b, MN4a, MN4b, MN5a, and MN5b shown in Fig. 11B.

[0385] In particular, FIG. 16A shows a schematic cross-sectional view of the transistor 200 in the channel length direction, and FIG. 16B shows a schematic cross-sectional view of the transistor 200 in the channel width direction.

[0386] 16A and 16B , for example, the transistor 200 includes a semiconductor layer 251a, a semiconductor layer 251b, a conductive layer 231a, a conductive layer 231b, a conductive layer 232a, a conductive layer 232b, a conductive layer 235a, a conductive layer 235b, an insulating layer 212, insulating layers 261 to 264, insulating layers 281 to 283, and insulating layers 212 to 214. Note that the transistor 200 does not necessarily include all of the above components. For example, the conductive layer 234 functions as a backgate electrode of the transistor 200, but the transistor 200 may not include the conductive layer 234.

[0387] The insulating layer 211 is disposed above a substrate (not shown). An insulating layer 281 is located over the insulating layer 211, and a conductive layer 234 (conductive layers 234a and 234b) and the insulating layer 212 are located over the insulating layer 281. In particular, the conductive layer 234 is preferably embedded in the insulating layer 212. Specifically, the conductive layer 234a is preferably provided in contact with the bottom and sidewall of an opening provided in the insulating layer 212. Note that the bottom of the opening may be the top surface of the insulating layer 212 or the top surface of the insulating layer 281. The conductive layer 234b is preferably embedded in a recess formed in the conductive layer 234a. Note that in the transistor 200 shown in FIGS. 16A and 16B , the height of the top surface of the conductive layer 234b is approximately the same as the height of the top surface of the conductive layer 234a and the height of the top surface of the insulating layer 212.

[0388] The insulating layer 211 and the insulating layer 212 function as a planarizing film that flattens steps caused by plugs or the like, similar to the insulating layer 112. Therefore, the insulating layer 211 and the insulating layer 212 can be made of a material that functions as a planarizing film, similar to the insulating layer 112.

[0389] Furthermore, by using a material with a low dielectric constant for the insulating layers 211 and 212, parasitic capacitance between wirings can be reduced. For example, the insulating layers 211 and 212 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layers 211 and 212 can be made of, for example, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies are particularly preferred because they can easily form regions containing oxygen that is released by heating. Alternatively, the insulating layers 211 and 212 can be made of, for example, a resin. The materials used for the insulating layers 211 and 212 may be an appropriate combination of the insulating materials described above.

[0390] In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0391] The semiconductor layer 251 and the conductive layer 232 are disposed in a region overlapping the conductive layer 231. The semiconductor layer 251b is disposed on the semiconductor layer 251a. The conductive layers 231a and 231b are disposed on the semiconductor layer 251b, spaced apart from each other. The insulating layer 213 is disposed on the conductive layers 232a and 232b. In particular, an opening is formed in the insulating layer 213 in a region between the conductive layers 232a and 232b. The conductive layer 232 is disposed in the opening. The insulating layer 264 is disposed between the semiconductor layer 251b, the conductive layers 231a and 231b, and the insulating layer 213 and the conductive layer 232. Here, as shown in FIGS. 16A and 16B , it is preferable that the top surface of the conductive layer 232 substantially coincides with the top surfaces of the insulating layer 264 and the insulating layer 213. Note that hereinafter, the conductive layers 231a and 231b may be collectively referred to as conductive layers 231. The semiconductor layers 251a and 251b may be collectively referred to as semiconductor layers 251. The conductive layers 232a and 232b may be collectively referred to as conductive layers 232.

[0392] 16A , a region 271a may be formed as a low-resistance region at the interface between the semiconductor layer 251b and the conductive layer 232a and in its vicinity. Similarly, a region 271b may be formed as a low-resistance region at the interface between the semiconductor layer 251b and the conductive layer 231b and in its vicinity. In this case, the region 271a functions as one of a source region and a drain region, and the region 271b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the region 271a and the region 271b.

[0393] A metal oxide that functions as an oxide semiconductor and includes a channel formation region is preferably used for the semiconductor layer 251. In particular, the indium oxide described in Embodiment 2 is suitable as the metal oxide. Note that in the following, not only indium oxide but also various metal oxides that serve as the channel formation region of the transistor 200 will be described.

[0394] The metal oxide to be used for the channel formation region of the transistor 200 preferably has a band gap of, for example, 2 eV or more, preferably 2.5 eV or more. Specifically, in the case of the transistor 200 in FIGS. 16A and 16B, the semiconductor layer 251 preferably includes a metal oxide that functions as an oxide semiconductor.

[0395] Note that the structure of a metal oxide can be divided into a single crystal structure and other structures (non-single crystal structures). Examples of non-single crystal structures include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, a nanocrystalline (nc) structure, a pseudo-amorphous (a-like) structure, and an amorphous structure. The structure of the metal oxide of one embodiment of the present invention is not particularly limited, and any of the above structures may be used. However, the use of a crystalline metal oxide, typified by a CAAC structure or an nc structure, is preferable because a highly reliable semiconductor device can be obtained.

[0396] The metal oxide preferably contains at least indium. It may also contain indium and zinc. In addition to these, it may also contain element M. The element M may be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, the element M may be one or more selected from aluminum, gallium, yttrium, and tin. It is more preferable that the element M contains one or both of gallium and tin.

[0397] Examples of the metal oxide include indium oxide (also referred to as indium oxide or IO), gallium oxide (also referred to as gallium oxide), zinc oxide (also referred to as zinc oxide), indium zinc oxide (In-Zn oxide), indium tin oxide, indium titanium oxide, indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide, and indium gallium aluminum zinc oxide. Alternatively, indium tin oxide, gallium tin oxide, aluminum tin oxide, and the like containing silicon can be used.

[0398] As described above, the metal oxide preferably contains indium. Specifically, it is preferable to use indium oxide as the metal oxide. It is particularly preferable to use crystalline indium oxide.

[0399] The metal oxide can be preferably formed by sputtering or ALD. When the metal oxide is formed by sputtering, a film with high crystallinity or high film density can be formed. Furthermore, when the metal oxide is formed by ALD, atoms can be deposited layer by layer, which has the advantages of enabling film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. After the metal oxide is formed, it is preferable to perform an impurity removal treatment to remove impurities (typically, impurities such as water, hydrogen, carbon, and nitrogen) from the metal oxide film. Examples of impurity removal treatments include microwave plasma treatment and heat treatment.

[0400] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0401] Note that the transistor 200 has a two-layer structure of the semiconductor layer 251a and the semiconductor layer 251b stacked in the region where a channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof, but the present invention is not limited to this. For example, the semiconductor layer 251b may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the semiconductor layer 251a and the semiconductor layer 251b may have a stacked structure of two or more layers.

[0402] The conductive layer 232 functions as a first gate electrode (sometimes referred to as a top gate electrode or a front gate electrode) of the transistor, and as described above, the conductive layer 231a and the conductive layer 231b function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 232 is formed so as to be embedded in the opening of the insulating layer 213 and in the region sandwiched between the conductive layer 231a and the conductive layer 231b. Here, the conductive layer 232 is formed in a self-aligned manner with respect to the opening of the insulating layer 213. That is, in the transistor 200, the first gate electrode can be disposed between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 232 can be formed without providing a margin for alignment, which reduces the area occupied by the transistor 200. This allows for an increase in the density of processing cells in the memory device.

[0403] Note that the transistor 200 can be formed by forming an island-shaped stack of layers over an insulating layer 262, the stack of layers including an insulating layer 263 (to be described later), a semiconductor layer 251, and a conductive layer that will become the conductive layer 231a and the conductive layer 231b. Next, an insulating layer 282 and an insulating layer 213 (collectively referred to here as an interlayer film) are stacked in this order above the island-shaped stack of layers and above the insulating layer 262. An opening is then formed in a region of the interlayer film that overlaps the island-shaped stack of layers, and an insulating layer 264 and a conductive layer 232 are provided in this order in the opening. In particular, it is preferable to simultaneously form the conductive layer 231a and the conductive layer 231b by forming an opening in the interlayer film. In this specification, a transistor structure in which an opening reaching the island-shaped stack of layers and an interlayer film are formed in the interlayer film, and a conductive layer that will become the first gate electrode of the transistor is provided to fill the opening is referred to as a GL structure. Such a structure may also be called a TGSA structure.

[0404] 16A and 16B , the conductive layer 232 is shown as having a two-layer structure. Here, the conductive layer 232 preferably includes a conductive layer 232a and a conductive layer 232b disposed on the conductive layer 232a. For example, the conductive layer 232a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 232b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 232a. The conductive layer 232 may have a single-layer structure or a stacked structure of three or more layers.

[0405] The conductive layer 232a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, a conductive material that has a function of suppressing the diffusion of oxygen is preferably used. Furthermore, since the conductive layer 232a has the function of suppressing the diffusion of oxygen, it is possible to suppress a decrease in the conductivity of the conductive layer 232b, which would be caused by oxidation of the conductive layer 232b by oxygen contained in the insulating layer 213 or the like. As a conductive material that has a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

[0406] The conductive layer 232b is preferably a conductive layer with high conductivity. For example, the conductive layer 232b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 232b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0407] For the conductive layers 231a and 231b, it is preferable to use, for example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 231a and 231b. When a conductive material containing metal and nitrogen is used for the conductive layers 231a and 231b, the conductive layers 231a and 231b become conductive layers containing at least metal and nitrogen. For example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion can be selected from the materials that can be used for the conductive layers 232a and 232b described above.

[0408] The conductive layer 231a and the conductive layer 231b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 231a and the conductive layer 231b can have a stacked structure including multiple layers. In particular, the stacked structure is preferably a structure in which a conductive material having a function of suppressing permeation of impurities such as water and hydrogen and a material with high conductivity are stacked.

[0409] The conductive layer 234 may function as a second gate electrode (also referred to as a bottom gate electrode or a back gate electrode). In this case, the potential applied to the conductive layer 234 may be changed independently of the potential applied to the conductive layer 232, thereby controlling the threshold voltage V ｔｈ In particular, applying a negative potential to the conductive layer 234 can control the V ｔｈ Therefore, when a negative potential is applied to the conductive layer 234, the drain current when the potential applied to the conductive layer 232 is 0 V can be made smaller than when no negative potential is applied.

[0410] The conductive layer 234 is preferably provided to be larger than the channel formation region in the semiconductor layer 251. In particular, as shown in Fig. 16B, the conductive layer 234 preferably extends as a wiring also in a region outside the end portion intersecting with the channel width direction of the semiconductor layer 251. That is, outside the side surface of the semiconductor layer 251 in the channel width direction, the conductive layer 234 and the conductive layer 232 preferably overlap with each other with an insulating layer interposed therebetween.

[0411] For the conductive layer 234, for example, a material that can be applied to each of the conductive layers 231a and 231b described above can be selected and used.

[0412] 16A and 16B , the transistor 200 preferably includes an insulating layer 211 disposed on a substrate (not shown), an insulating layer 281 disposed on the insulating layer 211, an insulating layer 212 disposed on the insulating layer 281, a conductive layer 231 disposed so as to be embedded in the insulating layer 212, an insulating layer 261 disposed on the insulating layer 212 and the conductive layer 231, an insulating layer 262 disposed on the insulating layer 261, and an insulating layer 263 disposed on the insulating layer 262. A semiconductor layer 251 a is preferably disposed on the insulating layer 263.

[0413] 16A and 16B, an insulating layer 282 is preferably disposed between the insulating layer 262, the insulating layer 263, the semiconductor layer 251a, the semiconductor layer 251b, the conductive layer 232a, and the conductive layer 232b and the insulating layer 213. Here, the insulating layer 282 is preferably in contact with the side surfaces of the insulating layer 264, the top and side surfaces of the conductive layer 232a, the top and side surfaces of the conductive layer 232b, the side surfaces and top surfaces of the semiconductor layer 251a, the semiconductor layer 251b, and the insulating layer 263, and the top surface of the insulating layer 262, as shown in FIG.

[0414] The insulating layer 264 functions as a first gate insulating film in the transistor 200. The insulating layers 261 to 263 function as second gate insulating films. For these gate insulating films, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies can be used. In addition to the above, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ An insulating layer containing a so-called high-k material such as BST can be used as a single layer or a stacked layer. Aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulating layer material. Alternatively, these insulating layers may be nitrided.

[0415] An insulating layer 283 and an insulating layer 214 functioning as interlayer films are preferably provided over the transistor 200. Here, the insulating layer 283 is preferably provided in contact with top surfaces of the conductive layer 232, the insulating layer 264, and the insulating layer 213. In this case, the top surface of the insulating layer 213 is preferably planarized.

[0416] The circuit layer IOCL preferably includes conductive layers 235 (conductive layers 235a and 235b) that are connected to the transistor 200 and function as plugs. For this reason, the conductive layers 235 are provided in contact with inner walls of the openings of the insulating layers 282, 213, 283, and 214. In particular, a first conductive layer of the conductive layer 235 may be provided in contact with the inner walls, and a second conductive layer of the conductive layer 235 may be provided on a side surface of the first conductive layer. Here, the height of the top surface of the conductive layer 235 and the height of the top surface of the insulating layer 214 can be made approximately the same.

[0417] Specifically, for example, a first conductive layer of the conductive layer 235a is provided in contact with one of the inner walls of two openings of the insulating layer 214, the insulating layer 283, the insulating layer 213, and the insulating layer 282, and a second conductive layer of the conductive layer 235a is formed in contact with the side surface thereof. Note that the conductive layer 231a is located in part of the bottom of the opening, and the conductive layer 235a is in contact with the conductive layer 231a. Similarly, for example, a first conductive layer of the conductive layer 235b is provided in contact with the other inner wall of the two openings of the insulating layer 214, the insulating layer 283, the insulating layer 213, and the insulating layer 282, and a second conductive layer of the conductive layer 235b is formed in contact with the side surface thereof. Note that the conductive layer 231b is located in part of the bottom of the opening, and the conductive layer 235b is in contact with the conductive layer 231b.

[0418] Note that although the transistor 200 shows a structure in which the first conductive layer of the conductive layer 235 and the second conductive layer of the conductive layer 235 are stacked, the present invention is not limited to this. For example, the conductive layer 235 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0419] 16B , in a region of the semiconductor layer 251b that does not overlap with the conductive layer 231, in other words, in the channel formation region of the semiconductor layer 251, the side surface of the semiconductor layer 251 is arranged to be covered with the conductive layer 232. This makes it easier for the electric field of the conductive layer 232, which functions as the first gate electrode, to act on the side surface of the semiconductor layer 251, and as a result, the channel formation region of the semiconductor layer 251 can be electrically surrounded by the electric field of the conductive layer 232. This increases the on-state current of the transistor 200, and improves its frequency characteristics.

[0420] For example, the insulating layer 213 preferably has a lower dielectric constant than the insulating layer 262. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For this reason, the insulating layer 213 can be made of a material with a low dielectric constant that can be used for the insulating layer 212.

[0421] 14, which illustrates a structural example of a memory device that is a semiconductor device of one embodiment of the present invention, the transistors MN3a and MN3b are described as having a GL structure. Note that the structures of the transistors MN3a and MN3b according to one embodiment of the present invention are not limited thereto. Instead of the GL structure, the transistors MN3a and MN3b according to one embodiment of the present invention can have, for example, a vertical channel transistor structure described below.

[0422] 17A to 17C show examples of the configuration of a vertical channel transistor. In a vertical channel transistor, the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction).

[0423] 17A to 17C may also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or the like, other than a vertical channel transistor. In this specification, in a vertical channel transistor, one of the source electrode and the drain electrode located at the bottom may be referred to as a lower electrode. In addition, the other of the source electrode and the drain electrode located at the top may be referred to as an upper electrode.

[0424] In particular, Fig. 17A shows a schematic plan view of an example of a transistor 300, which is a vertical channel transistor, and Figs. 17B and 17C show schematic cross-sectional views of the transistor 300. Fig. 17B is a schematic cross-sectional view taken along dashed line A1-A2 in Fig. 17A, and Fig. 17C is a schematic cross-sectional view taken along dashed line A3-A4 in Fig. 17A. Fig. 18 shows a schematic perspective view of the transistor 300 and its peripheral wiring shown in Figs. 17A to 17C.

[0425] 17A to 17C and 18 includes, for example, a conductive layer 331 that functions as a wiring or an electrode, a conductive layer 332 that functions as a wiring or an electrode, a semiconductor layer 351 that is an active layer of the transistor 300, an insulating layer 361 that functions as a gate insulating film of the transistor 300, a conductive layer 333 that functions as a gate of the transistor 300, and a conductive layer 334 that functions as a wiring.

[0426] The conductive layer 331 is provided above the insulating layer 311, which functions as an interlayer film. Furthermore, the conductive layer 331 functions as wiring, and therefore extends along the direction of the dashed dotted line A3-A4 in the schematic plan view of FIG. 17A .

[0427] For the conductive layer 331, for example, a conductive layer that can be used for the conductive layers 231, 232, 234, and 235 of the transistor 200 described above can be used. The same applies to the conductive layers 332 to 334 described later.

[0428] An insulating layer 312 and a conductive layer 332, which function as interlayer films, are formed in this order on the insulating layer 311 and the conductive layer 331. In Fig. 17, the insulating layer 312 has a three-layer structure including two barrier insulating films that suppress the diffusion of impurities and an interlayer film sandwiched between these barrier insulating films. The barrier insulating films preferably have a function of suppressing oxygen diffusion to prevent the conductive layer 331 or the conductive layer 332 from being oxidized, for example. Furthermore, the conductive layer 332 functions as wiring and therefore extends along the direction of the dashed dotted line A1-A2 in the plan view schematic diagram of Fig. 17A.

[0429] Furthermore, openings reaching the conductive layer 331 are formed in the insulating layer 312 and the conductive layer 332 in regions overlapping with the conductive layer 331. A semiconductor layer 351 is formed on the side surfaces and bottom of the openings. That is, the semiconductor layer 351 is formed on the top surface of the conductive layer 331, the side surfaces of the insulating layer 312, and the side surfaces of the conductive layer 332. The semiconductor layer 351 is also formed on part of the top surface of the conductive layer 332. An insulating layer 361 is provided so as to be in contact with the conductive layer 332, the semiconductor layer 351, and the insulating layer 312 inside and outside the openings. A conductive layer 333 is formed on the top surface and side surfaces of the insulating layer 361 so as to fill the openings.

[0430] An insulating layer 313 functioning as an interlayer film is formed on the top surface of the insulating layer 361 and the top surface of the conductive layer 333. An opening reaching the conductive layer 333 is formed in the insulating layer 313 in a region overlapping with the conductive layer 333. A conductive layer 334 is embedded in the side surface and bottom of the opening. Note that part of the conductive layer 334 may be formed on the top surface of the insulating layer 313. The insulating layer 314 functioning as an interlayer film is formed on the insulating layer 313 and the conductive layer 334.

[0431] Furthermore, the conductive layer 334 functions as wiring and therefore extends along the direction of the dotted line A3-A4 in the schematic plan view of FIG. 17A.

[0432] For example, an insulating material with a low dielectric constant is preferably used for the insulating layers 311 to 314. By using an insulating material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layers 311 to 314 can each be made of a material that can be used for the insulating layer 212 or the insulating layer 213 described above.

[0433] The insulating layer 361 has a function as a gate insulating film, and therefore, for example, the material that can be used for the insulating layer 264 can be used for the insulating layer 361 .

[0434] Part of the conductive layer 331 functions as one of the source electrode and the drain electrode of the transistor 300. Part of the conductive layer 332 functions as the other of the source electrode and the drain electrode of the transistor 300. Part or all of the conductive layer 333 functions as a gate electrode of the transistor 300.

[0435] As described above, by forming the insulating layer, the conductive layer, and the semiconductor layer, a vertical channel transistor can be formed in which the channel length direction has a component in the height direction (vertical direction). The channel length of the transistor 300 depends on the film thickness of the insulating layer 312. The thinner the insulating layer 312, the shorter the channel length, and therefore the larger the on-current of the transistor 300 can be. On the other hand, the thicker the insulating layer 312, the longer the channel length, and therefore the smaller the off-current of the transistor 300 can be.

[0436] Furthermore, the wirings connecting the source, drain, or gate of the vertical channel transistor are not formed in the same process but in different processes. As a result, the wirings connecting the source, drain, or gate of the vertical channel transistor have overlapping regions in a plan view. Since the wirings connecting the source, drain, or gate of the vertical channel transistor are provided at different heights, the parasitic capacitance generated in each wiring can be reduced. This can increase the driving frequency of the transistor 300 and the driving speed of the memory device MDV, etc.

[0437] <<Configuration Example of Capacitor>> Next, a description will be given of configuration examples of the capacitive elements C1a, C1b, C3a, and C3b that can be provided in the circuit SA of the memory device MDV in Fig. 14. In addition, this configuration example can also be applied to the ferroelectric capacitors CF1, CF10, and CF11 that can be provided in the memory cells MC, MCr0, and MCr1.

[0438] The capacitance element 400 shown in the schematic cross-sectional view of Fig. 19A and the schematic plan view of Fig. 19B is a vertical capacitance element, unlike the capacitance elements C1a, C1b, C3a, and C3b, which are parallel plate capacitance elements shown in Fig. 14. Specifically, the capacitance element 400 has a configuration in which a pair of electrodes and a dielectric are included inside an opening in an insulating layer that functions as an interlayer film.

[0439] 19A includes, as an example, a portion of conductive layer 431, a portion of conductive layer 432, a portion of conductive layer 433, and an insulating layer 441. Note that FIG. 19A excerpts conductive layer 434, insulating layer 411, insulating layer 412, insulating layer 413, and insulating layer 414 as materials formed around capacitor element 400. FIG. 19B is a plan view along dashed-dotted line B1-B2 in FIG. 19A , illustrating insulating layer 412, conductive layer 432, insulating layer 441, and conductive layer 433. The dashed line in FIG. 19B represents an edge 473 of conductive layer 433 provided on insulating layer 441.

[0440] The conductive layer 431 functions as a wiring for connecting to one of a pair of electrodes of the capacitor 400. For the conductive layer 431, the description of the conductive layer 331 in FIGS.

[0441] Part of the conductive layer 432 functions as one of a pair of electrodes of the capacitor 400, part of the conductive layer 433 functions as the other of the pair of electrodes of the capacitor 400, and the insulating layer 441 functions as a dielectric of the capacitor 400. For example, the conductive layer 431 can be formed using a material that can be used for the conductive layer 331 in FIGS. 17A to 17C and 18. For the conductive layer 432, a material that can be used for the conductive layer 331 or the conductive layer 334 can be used.

[0442] The insulating layer 441 functions as a dielectric of the capacitive element 400. For example, it is preferable to use a high-k material as the insulating layer 441. Specifically, as one example, a material with a high relative dielectric constant such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide can be used for the insulating layer 441. Alternatively, as another example, it is preferable to use an oxide containing one or both of aluminum and hafnium, more preferably to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably to use hafnium oxide having an amorphous structure. Furthermore, as another example, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ By using a material with a high relative dielectric constant for the dielectric of the capacitance element C1a, the capacitance element C1b, the capacitance element C3a, or the capacitance element C3b, the capacitance value can be increased, and the voltage written to the capacitance element C1a, the capacitance element C1b, the capacitance element C3a, or the capacitance element C3b can be held for a long period of time.

[0443] Furthermore, a conductive layer 434 is formed on the conductive layer 433. In Fig. 19A, the conductive layer 434 is provided, for example, extending in a direction from the front to the back of the drawing.

[0444] The insulating layer 411 functions as a base film for forming the conductive layer 431. The insulating layer 412 functions as an interlayer film for separating the conductive layer 431 and the conductive layer 432. The insulating layer 413 functions as an interlayer film for forming a conductive layer 434, which functions as a wiring, above the conductive layer 433. Note that the insulating layer 413 has openings in regions where the conductive layers 433 and 434 overlap, and the conductive layers 433 and 434 are connected through the openings. The insulating layer 414 is an interlayer film provided above the conductive layer 434. Note that the descriptions of the insulating layers 311 to 314 in FIGS. 17B and 17C can be referred to for the insulating layers 411 to 414, respectively.

[0445] The capacitor 400 shown in FIG. 19A illustrates a configuration in which the upper surface of the conductive layer 431 has a recess. The recess can be formed by forming an opening in the insulating layer 412. Therefore, it can be said that the opening includes the side surface of the insulating layer 412 and the recess of the conductive layer 431. Therefore, the side surface of the insulating layer 412 may be referred to as the side surface of the opening, and the recess of the conductive layer 431 may be referred to as the bottom of the opening. Furthermore, the side wall of the opening includes the side surface of the insulating layer 412. In particular, FIG. 19A illustrates a first region 471 below the opening and a second region 472 above the opening as the side surface of the insulating layer 412. Furthermore, each of the first region 471 and the second region 472 can be said to be the side surface of the opening. Note that the side wall of the opening may also include the side surface of the recess of the conductive layer 431.

[0446] The conductive layer 431 has a recess at a position overlapping with the opening of the insulating layer 412, which increases the contact area between the conductive layer 431 and the conductive layer 432 compared to when the conductive layer 431 does not have the recess. This reduces the contact resistance between the conductive layer 431 and the conductive layer 432, which will be described later.

[0447] The conductive layer 432 has a region with rounded corners within the recess of the conductive layer 431. By having this region within the recess, electric field concentration in the insulating layer 441 near this region can be suppressed more effectively than, for example, when the recess has a right angle or an acute angle (a corner). Furthermore, the end of the conductive layer 432 is located at a position lower in height from the reference plane than the top surface of the insulating layer 412. In other words, the conductive layer 432 is located in a first region 471 of the opening of the insulating layer 412. Furthermore, the insulating layer 441 is provided on the top surface of the conductive layer 432, a second region 472 of the opening of the insulating layer 412, and the top surface of the insulating layer 412. Furthermore, the conductive layer 433 is provided on the insulating layer 441 so as to fill the opening of the insulating layer 412.

[0448] Since the end of the conductive layer 432 is positioned on the side surface of the opening of the insulating layer 412, electric field concentration in the insulating layer 441 near the end can be suppressed. As described above, suppressing electric field concentration in the insulating layer 441 suppresses dielectric breakdown of the insulating layer 441, and a highly reliable memory device can be provided. Furthermore, since the capacitor 400 has a pair of electrodes provided in the opening of the insulating layer 412, the circuit area of ​​the capacitor 400 in a plan view is smaller than that of a parallel-plate capacitor. Therefore, by using the capacitor 400 shown in FIG. 19A as the capacitor included in the circuit, the area of ​​the circuit can be reduced.

[0449] For example, in the circuit SA of FIG. 1 , by using the above-described capacitance element 400 for the capacitance element C1a, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C1a between the terminal IOT and the node SN. Similarly, by using the above-described capacitance element 400 for the capacitance element C1b, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C1b between the terminal IOTB and the node SNB. Furthermore, by using the above-described capacitance element 400 for the capacitance element C3a, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C3b between the output terminal of the inverter IVa and the node SNB. Furthermore, by using the above-described capacitance element 400 for the capacitance element C3b, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C3b between the output terminal of the inverter IVb and the node SN. Furthermore, local electric field concentration can be suppressed in the dielectrics of the capacitance elements C1a, C1b, C3a, and C3b, thereby preventing operational malfunctions in the circuit SA. Furthermore, since the areas of the capacitive elements C1a, C1b, C3a, and C3b can be reduced in plan view, the circuit area of ​​the memory device MDV can be reduced.

[0450] The capacitance value of the capacitor 400 is proportional to the area of ​​a region where the conductive layer 432, the insulating layer 441, and the conductive layer 433 overlap each other. This region can be, for example, a region where the conductive layer 432 and the insulating layer 441 are in contact with each other. Therefore, the height d from the bottom of the opening in the insulating layer 412 to the edge of the conductive layer 432 provided on the side surface of the opening is Ｕ The area of ​​the region can be increased by increasing the length d. Ｋ When this is the case, d Ｕ is d Ｋ For example, d Ｕ is d Ｋ In order to obtain the effect of suppressing electric field concentration in the insulating layer 441 at the end portion of the conductive layer 432 or its vicinity, it is preferable that the ratio of d Ｕ is d Ｋ It is preferable that the value is 95% or less or 85% or less of d Ｕ For example, Ｋ It is preferable that the ratio is 80% or more and 85% or less, or 80% or more and 95% or less.

[0451] Furthermore, the value of the capacitance of the capacitance element 400 is inversely proportional to the distance between the conductive layer 432 and the conductive layer 433, for example, in the schematic plan view of FIG. 19B . Specifically, the value of the capacitance is inversely proportional to the film thickness of the insulating layer 441. Therefore, in the schematic cross-sectional view of FIG. 19A or the schematic plan view of FIG. 19B , the film thickness of the insulating layer 441 is preferably 100 nm or less, more preferably 50 nm or less, and even more preferably 10 nm or less. Furthermore, when it is desired to increase the voltage resistance of the capacitance element 400, the film thickness of the insulating layer 441 is preferably 1 nm or more, more preferably 5 nm or more, and even more preferably 10 nm or more.

[0452] 19A and 19B can be made into a ferroelectric capacitor by using a material capable of exhibiting ferroelectricity for the insulating layer 441. Unlike paraelectrics, a material capable of exhibiting ferroelectricity maintains its internal dielectric polarization even when no voltage is applied (sometimes called remanent polarization). This ferroelectric capacitor can be applied to each of the ferroelectric capacitor CF1 shown in FIG. 3A and the ferroelectric capacitor CF10 and ferroelectric capacitor CF11 shown in FIG. 3B.

[0453] Examples of materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and hafnium zirconium oxide (HfZrO Ｘ (where X is a real number greater than 0), and the element J is added to hafnium oxide. １ (Element J here １ refers to one or more elements selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium), and zirconium oxide to which element J is added. ２ (Element J here ２ is one or more elements selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium) are added. Also, examples of materials that can have ferroelectricity include lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used. Furthermore, as a material that can have ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above may be used. Incidentally, hafnium oxide, zirconium oxide, zirconium hafnium oxide, and hafnium oxide containing element J may be used. １The crystal structure (characteristics) of a material to which an ion beam is added may change depending not only on the film formation conditions but also on various processes. Therefore, in this specification, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material that can have ferroelectricity.

[0454] Among these, materials having hafnium oxide or materials having hafnium oxide and zirconium oxide are preferred as materials capable of exhibiting ferroelectricity, since they can exhibit ferroelectricity even in thin films of a few nanometers. This allows the process of fabricating a ferroelectric capacitor to be shortened. In this specification, a layer of a material capable of exhibiting ferroelectricity may be referred to as a ferroelectric layer or a metal oxide film.

[0455] When the insulating layer 441 is formed by the ALD method using a material containing hafnium oxide and zirconium oxide, for example, tetrakis(ethylmethylamido)hafnium (TEMAHf) or hafnium tetrachloride can be used as a precursor containing hafnium. Also, tetrakis(ethylmethylamido)zirconium (TEMAZr) or zirconium tetrachloride can be used as a precursor containing zirconium. Also, H ２ O and O ３ However, the oxidizing agent is not limited to these. For example, O ２ , O ３ , N ２ O, NO ２ , H ２ O and H ２ O ２ It can include one or more selected from the following.

[0456] The insulating layer 441 can have a single layer structure or a stacked layer structure. In particular, when the insulating layer 441 has a stacked layer structure, each insulating layer included in the insulating layer 441 can be made of, for example, one or both of the high-k material and the material that can have ferroelectricity.

[0457] Furthermore, when the insulating layer 441 is made of a material that can have the above-mentioned ferroelectricity, the film thickness of the insulating layer 441 is preferably 1 nm or more and 30 nm or less, more preferably 2 nm or more and 20 nm or less, and even more preferably 3 nm or more and 15 nm or less.

[0458] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0459] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as Data Centers (DCs)) that can use the memory devices described in the above embodiments will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the memory devices of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0460] [Electronic Component] Fig. 20A shows a perspective view of electronic component 1700. Electronic component 1700 shown in Fig. 20A has substrate 1701, semiconductor device 1710 on substrate 1701, and mold 1711. In particular, semiconductor device 1710 is sealed by mold 1711. Note that Fig. 20A omits some parts in order to show the inside of electronic component 1700.

[0461] The substrate 1701 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0462] Electronic component 1700 is provided with, for example, lead frame 1712. A portion of lead frame 1712 located on substrate 1701 is covered with mold 1711, and another portion of lead frame 1712 is exposed to the outside of mold 1711. In particular, lead frame 1712 exposed to the outside of mold 1711 functions as, for example, a terminal for mounting electronic component 1700 on a printed circuit board.

[0463] Inside mold 1711, electrode pads 1713 are provided on lead frame 1712, and electrode pads 1713 are connected to semiconductor device 1710 via wires 1714. Electronic component 1700 is mounted on a printed circuit board, for example, by contacting lead frame 1712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and connecting them on the printed circuit board.

[0464] Next, the semiconductor device 1710 will be described. For example, as shown in FIG. 20B , the semiconductor device 1710 includes a drive circuit layer 1715 and a memory layer 1716. The memory layer 1716 may be configured with a plurality of stacked cell arrays. The cell array may include the arithmetic cells and drive cells, or memory cells, described in the above embodiments. The stacked drive circuit layer 1715 and memory layer 1716 may be configured as a monolithic stack. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology (e.g., TSV (Through Silicon Via)) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 1715 and the memory layer 1716 as a monolithic stack, for example, a so-called on-chip memory configuration can be achieved, in which memory is formed directly on a processor. The on-chip memory configuration enables the operation of the interface between the processor and memory to be faster. For example, by using the storage device described in the above embodiment as the processor, it is possible to speed up the transmission of the first data (for example, weighting coefficients) from the memory to the storage device.

[0465] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0466] Furthermore, it is preferable that the multiple memory cell arrays included in the memory layer 1716 are formed using IO transistors and the multiple memory cell arrays are monolithically stacked. By configuring the multiple memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used in the memory layer 1716, it is more difficult to achieve a monolithic stacked configuration than IO transistors. Therefore, it can be said that IO transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0467] The semiconductor device 1710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0468] Next, Fig. 20C shows a modified example of electronic component 1700. Electronic component 1700A shown in Fig. 20C differs from electronic component 1700 in that it does not use lead frame 1712, but has electrodes 1733 provided on the bottom of substrate 1701. Electrodes 1733 function as connection terminals for mounting electronic component 1700A on a printed circuit board.

[0469] 20C shows an example in which electrodes 1733 are formed using solder balls. By providing solder balls in a matrix on the bottom of substrate 1701, BGA (Ball Grid Array) mounting can be achieved. For this purpose, through-hole vias (penetrating vias) are provided in substrate 1701, and conductive layers 1732 that function as wiring are provided in these vias. Electrode pads 1713 are provided above conductive layer 1732 on substrate 1701 so as to be in contact with them, and electrodes 1733 are provided below conductive layer 1732 below substrate 1701 so as to be in contact with them.

[0470] Furthermore, the electrodes 1733 may be formed of conductive pins instead of solder balls. By providing conductive pins in a matrix on the bottom of the substrate 1701, PGA (Pin Grid Array) mounting can be achieved.

[0471] Furthermore, electronic component 1700A can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0472] The electronic component of one embodiment of the present invention may be in the form of a system in package (SiP) or a multi-chip module (MCM). For example, an electronic component 1700C illustrated in FIG. 20D includes an interposer 1731 over a package substrate 1734 (printed circuit board), and a semiconductor device 1735 and a plurality of semiconductor devices 1710 over the interposer 1731.

[0473] 20D illustrates an example in which the semiconductor device 1710 is used as a high bandwidth memory (HBM). For example, the semiconductor device 1735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0474] The package substrate 1734 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, similar to the substrate 1701. The interposer 1731 may be, for example, a silicon interposer or a resin interposer.

[0475] The interposer 1731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 1731 also functions to connect the integrated circuits provided on the interposer 1731 to electrodes provided on the package substrate 1734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 1731, and the integrated circuits and the package substrate 1734 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0476] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0477] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0478] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 1700C, the width of the terminal pitch becomes an issue, and it may be difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked configuration using IO transistors is preferable. Also, for example, a memory cell array stacked using TSVs and a monolithically stacked memory cell array can be combined. Furthermore, a structure combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array is sometimes called a hybrid structure.

[0479] Furthermore, if the temperature of the electronic component 1700C increases due to heat generated during operation, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 1700C may be degraded. Therefore, it is preferable to provide a heat sink (heat sink) on the electronic component 1700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 1731. For example, in the electronic component 1700C described in this embodiment, it is preferable to align the height of the semiconductor device 1710 and the semiconductor device 1735.

[0480] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 21A . The electronic device 6500 shown in FIG. 21A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0481] 21B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be used for the display portion 6615, the control device 6616, and the like.

[0482] The semiconductor device of one embodiment of the present invention is preferably used for the control devices 6509 and 6616 because power consumption can be reduced.

[0483] [Mainframe] Next, Fig. 21C shows a perspective view of multiple mainframe computers 5600 installed in a server room or the like. The mainframe computer 5600 shown in Fig. 21C has multiple rack-mounted computers 5620 stored in a rack 5610. The mainframe computer 5600 is sometimes called a supercomputer.

[0484] The computer 5620 has a motherboard, which is provided with a plurality of slots, a plurality of connection terminals, etc. For example, one or a plurality of PC cards can be inserted into the slot.

[0485] The PC card is an example of a processing board equipped with a processing device such as a CPU, a GPU, etc. For example, the electronic component 1700 can be used as the processing device.

[0486] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0487] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment (for example, equipment having a function of processing and storing information).

[0488] A semiconductor device according to one embodiment of the present invention can include an IO transistor. The IO transistor exhibits small changes in electrical characteristics due to radiation exposure. In other words, the IO transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the IO transistor can be suitably used in outer space.

[0489] Fig. 22 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 22, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but outer space described in this specification includes the thermosphere, mesosphere, and stratosphere.

[0490] 22, a battery management system (also referred to as BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an IO transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0491] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0492] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0493] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received, for example, by a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0494] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory circuit. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. An IO transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, an IO transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0495] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0496] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0497] As described above, IO transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance than Si transistors.

[0498] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. Data centers are required to perform long-term data management, such as ensuring data immutability. Managing long-term data requires large-scale buildings, such as the installation of storage and servers for storing huge amounts of data, ensuring a stable power supply for data retention, and ensuring cooling equipment required for data retention. In addition, the data center preferably has a function for performing data calculations, and more preferably, the calculation speed is high.

[0499] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, power required for operation can be reduced and the operation speed can be increased.

[0500] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0501] Fig. 23 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 23 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0502] The host 7001 can be a computer that accesses data stored in the storage 7003. In addition, the hosts 7001 may be connected to each other via a network.

[0503] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0504] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0505] By using IO transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.Furthermore, by using a stacked memory cell array, miniaturization is possible.

[0506] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of the above-mentioned components, devices, data centers, and the like, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0507] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0508] ARE: area, BL[1]: wiring, BL[n]: wiring, BL: wiring, CF10: ferroelectric capacitor, CF11: ferroelectric capacitor, CTLD: control circuit, DRVL: wiring, IOCL: circuit layer, IOT: terminal, IOTB: terminal, IVa: inverter, IVb: inverter, M10: transistor, M11: transistor, M21[1]: transistor, M21[n]: transistor, M21: transistor, MC[1,1]: memory cell, MC[1,n]: memory cell, MC[m,1]: memory cell, MC[m,n]: memory cell, MC: memory cell, MCA: Cell array, MCAr: cell array, MCAL: memory layer, MDV: memory device, PD: drive circuit, PL[1]: wiring, PL[m]: wiring, PL: wiring, PLr: wiring, REQ: wiring, RFB: wiring, RFL[1]: wiring, RFL[n]: wiring, RFL: wiring, RFLB[1]: wiring, RFLB[n]: wiring, RFLB: wiring, RFPD: drive circuit, RFWD: drive circuit, RQD: drive circuit, RSTL: wiring, SA[1]: circuit, SA[n]: circuit, SA: circuit, SAS: drive circuit, SICL: circuit layer, SN: node, SNB: node, STLx: wiring, ST Ly: wiring, TrP: transistor, TrQ: transistor, VDE: wiring, VSE: wiring, WL[1]: wiring, WL[m]: wiring, WL: wiring, WLr: wiring, WRBD: driving circuit, WRWD: driving circuit, 101: substrate, 102: element isolation layer, 111: insulating layer, 112: insulating layer, 113: insulating layer, 114: insulating layer, 115: insulating layer, 116: insulating layer, 131: conductive layer, 132: conductive layer, 135: conductive layer, 136[1]: conductive layer, 136[2]: conductive layer, 136[3]: conductive layer, 136[4]: conductive layer, 136: conductive layer, 161: insulating layer, 171: semiconductor region, 172: low resistance region, 173: semiconductor region, 173a: semiconductor region, 173b: semiconductor region, 174: low resistance region, 174a: low resistance region, 174b: low resistance region, 174c: low resistance region, 181: insulating layer, 182: insulating layer, 200: transistor, 211: insulating layer, 212: insulating layer, 213: insulating layer, 214: insulating layer, 217: insulating layer, 231: conductive layer, 231a: conductive layer, 231b: conductive layer, 232: conductive layer, 232a: conductive layer, 232b: conductive layer, 233: conductive layer, 234: conductive layer, 234a: conductive layer, 234b: conductive layer, 235: conductive layer,235a: Conductive layer, 235b: Conductive layer, 236: Conductive layer, 237: Conductive layer, 238[1]: Conductive layer, 238[2]: Conductive layer, 238[3]: Conductive layer, 238[4]: Conductive layer, 238[5]: Conductive layer, 238[6]: Conductive layer, 238[7]: Conductive layer, 238[8]: Conductive layer, 241: Insulating layer, 251: Semiconductor layer, 251a: Semiconductor layer, 251b: Semiconductor layer, 261: Insulating layer, 262: Insulating layer, 263: Insulating layer, 264: Insulating layer, 271a: Region, 271b: Region, 281: Insulating layer, 282: Insulating layer, 283: Insulating layer, 285: Insulating layer, 300: Transistor Transistor, 311: insulating layer, 312: insulating layer, 313: insulating layer, 314: insulating layer, 331: conductive layer, 332: conductive layer, 333: conductive layer, 334: conductive layer, 351: semiconductor layer, 361: insulating layer, 400: capacitance element, 411: insulating layer, 412: insulating layer, 413: insulating layer, 414: insulating layer, 431: conductive layer, 432: conductive layer, 433: conductive layer, 434: conductive layer, 441: insulating layer, 471: first region, 472: second region, 473: edge, 931: conductive layer, 932: conductive layer, 933: conductive layer, 934: conductive layer, 1700: electronic component, 1700A: electronic component , 1700C: electronic component, 1701: substrate, 1710: semiconductor device, 1711: mold, 1712: lead frame, 1713: electrode pad, 1714: wire, 1715: drive circuit layer, 1716: memory layer, 1731: interposer, 1732: conductive layer, 1733: electrode, 1734: package substrate, 1735: semiconductor device, 5600: mainframe computer, 5610: rack, 5620: computer, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 65 07: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device,

Claims

1. A semiconductor memory device comprising a first cell, a second cell, a third cell, a circuit, and a first transistor, wherein each of the first cell to the third cell has a ferroelectric capacitor, wherein first data is held in the first cell, wherein second data is held in the second cell, and wherein third data is held in the third cell, and wherein the second data and the third data are inverses of each other in logic, wherein the circuit has a first terminal and a second terminal, wherein the first cell has a function of applying a first potential corresponding to the first data to a first wiring by a read operation, wherein the second cell has a function of applying a second potential corresponding to the second data to a second wiring by a read operation, and wherein the third cell has a function of applying a third potential corresponding to the third data to a third wiring by a read operation, and wherein the first transistor has a function of redistributing charge between the second wiring and the third wiring by turning on the first transistor, and generating a fourth potential based on the second potential and the third potential, and wherein the circuit comprises: a function of establishing a conductive state between the first wiring and the first terminal to obtain the first potential from the first terminal and establishing a conductive state between the second wiring and the second terminal to obtain the fourth potential from the second terminal; a function of establishing a conductive state between the second wiring and the first terminal to redistribute charge between the second wiring and the first terminal to change the first potential to a fifth potential and establishing a conductive state between the first wiring and the second terminal to redistribute charge between the first wiring and the second terminal to change the fourth potential to a sixth potential; and a function of amplifying the fifth potential of the first terminal to one of a high-level potential and a low-level potential and amplifying the sixth potential of the second terminal to the other of the high-level potential and the low-level potential, depending on whether an amount of change from the first potential to the fifth potential at the first terminal and an amount of change from the fourth potential to the sixth potential at the second terminal are high or low.

2. A transistor including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance element, a second capacitance element, a first inverter, and a second inverter, wherein one of a pair of electrodes of the first capacitance element, one of a source or a drain of the first transistor, one of a source or a drain of the fourth transistor, and an input terminal of the first inverter are electrically connected to each other; one of a pair of electrodes of the second capacitance element, one of a source or a drain of the second transistor, one of a source or a drain of the third transistor, and an input terminal of the second inverter are electrically connected to each other; the other of the source or the drain of the first transistor, the other of the source or the drain of the second transistor, and an output terminal of the first inverter are electrically connected to each other; the other of the source or the drain of the third transistor, the other of the source or the drain of the fourth transistor, and an output terminal of the second inverter are electrically connected to each other; and the gate of the first transistor and the gate of the third transistor are each electrically connected to a first wiring. a gate of the second transistor and a gate of the fourth transistor are each electrically connected to a second wiring.

3. A semiconductor device according to claim 2, comprising a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein the other of the pair of electrodes of the first capacitance element, one of the source or drain of the fifth transistor, and one of the source or drain of the sixth transistor are electrically connected to one another, the other of the pair of electrodes of the second capacitance element, one of the source or drain of the seventh transistor, and one of the source or drain of the eighth transistor are electrically connected to one another, the other of the source or drain of the fifth transistor and the other of the source or drain of the seventh transistor are each electrically connected to a third wiring, the other of the source or drain of the sixth transistor and the other of the source or drain of the eighth transistor are each electrically connected to a fourth wiring, the gate of the fifth transistor and the gate of the eighth transistor are each electrically connected to a fifth wiring, and the gate of the sixth transistor and the gate of the seventh transistor are each electrically connected to a sixth wiring.

4. A semiconductor device according to claim 3, comprising a first cell, a second cell, a third cell, and a ninth transistor, each of the first cell to the third cell comprising a third capacitance element and a tenth transistor, wherein in each of the first cell to the third cell, one of the source or drain of the tenth transistor is electrically connected to one of the first terminals of the third capacitance element, wherein in the first cell, the other of the source or drain of the tenth transistor is electrically connected to the third wiring, wherein in the second cell, the other of the source or drain of the tenth transistor is electrically connected to the fourth wiring, wherein in the third cell, the other of the source or drain of the tenth transistor is electrically connected to a seventh wiring, wherein one of the source or drain of the ninth transistor is electrically connected to the fourth wiring, and wherein the other of the source or drain of the ninth transistor is electrically connected to the seventh wiring.

5. A semiconductor device according to claim 4, wherein the third capacitance element is a ferroelectric capacitor, and the material that can have ferroelectricity and is sandwiched between a pair of electrodes of the third capacitance element has an oxide containing one or both of hafnium and zirconium.

6. The semiconductor device according to claim 4, wherein each of the first to tenth transistors is an n-channel transistor, and each of the first to tenth transistors has an oxide containing indium in a channel formation region.

7. A semiconductor device according to claim 2, wherein the first inverter comprises an eleventh transistor and a twelfth transistor; the second inverter comprises a thirteenth transistor and a fourteenth transistor; the eleventh transistor and the thirteenth transistor are each p-channel transistors; the twelfth transistor and the fourteenth transistor are each n-channel transistors; the gate of the eleventh transistor and the gate of the twelfth transistor function as input terminals of the first inverter; one of the source or drain of the eleventh transistor and one of the source or drain of the twelfth transistor function as output terminals of the first inverter; the gate of the thirteenth transistor and the gate of the fourteenth transistor function as input terminals of the second inverter; and one of the source or drain of the thirteenth transistor and one of the source or drain of the fourteenth transistor function as output terminals of the second inverter.

8. A semiconductor device according to claim 7, wherein the 11th transistor and the 13th transistor each have silicon in a channel formation region, and the 12th transistor and the 14th transistor each have an oxide containing indium in a channel formation region.

9. A semiconductor device according to claim 7, wherein each of the eleventh to fourteenth transistors has silicon in a channel formation region.

10. A semiconductor device according to any one of claims 2 to 9, comprising a fourth capacitive element and a fifth capacitive element, wherein a first terminal of the fifth capacitive element is electrically connected to a first terminal of the first capacitive element, one of the source or drain of the first transistor, one of the source or drain of the fourth transistor, and an input terminal of the first inverter, a first terminal of the fourth capacitive element is electrically connected to a first terminal of the second capacitive element, one of the source or drain of the second transistor, one of the source or drain of the third transistor, and an input terminal of the second inverter, a second terminal of the fourth capacitive element is electrically connected to the other of the source or drain of the first transistor, the other of the source or drain of the second transistor, and an output terminal of the first inverter, and a second terminal of the fifth capacitive element is electrically connected to the other of the source or drain of the third transistor, the other of the source or drain of the fourth transistor, and an output terminal of the second inverter.

Images