Wiring board, method for manufacturing same, and semiconductor package

Abstract

A wiring board comprises: a core substrate that includes a first surface, a second surface positioned on the opposite side from the first surface, and a plurality of through-holes penetrating from the first surface to the second surface, the core substrate being provided with a core layer that is made of glass; a plurality of through-electrodes positioned in each of the plurality of through-holes; a first rewiring layer that is positioned on the first surface; and a second rewiring layer that is positioned on the second surface. Each of the first rewiring layer and the second rewiring layer is provided with: a plurality of insulating layers that are laminated in the thickness direction; and an electrically conductive portion that includes a penetrating portion that penetrates the insulating layers, and wiring or pads that are positioned on the surfaces of the insulating layers. Each of the first rewiring layer and the second rewiring layer is provided with a low expansion portion that includes at least one insulating layer among the plurality of insulating layers. The insulating layer of the low expansion portion of the first rewiring layer and the insulating layer of the low expansion portion of the second rewiring layer both include a fiber member made of glass fiber, and a resin impregnated in the fiber member.

Description

Wiring board, manufacturing method thereof, and semiconductor package

[0001] An embodiment of the present disclosure relates to a wiring substrate, a manufacturing method thereof, and a semiconductor package.

[0002] The semiconductor package includes a semiconductor element and a wiring layer electrically connected to terminals of the semiconductor element. The wiring layer includes an insulating layer containing an organic material and a conductive layer located in an opening in the insulating layer and on the surface. The semiconductor element contains, for example, silicon as a main component.

[0003] JP 2012-156251 A

[0004] The thermal expansion coefficient of a semiconductor element is smaller than that of the wiring layer. After the process of mounting the semiconductor element on the wiring layer at a high temperature is performed, when the temperature of the semiconductor package decreases, thermal stress occurs between the semiconductor element and the wiring layer due to the difference in thermal expansion coefficients. If the thermal stress is large, the reliability of the semiconductor package will decrease.

[0005] An object of the embodiments of the present disclosure is to provide a wiring board, a manufacturing method thereof, and a semiconductor package that can effectively solve these problems.

[0006] Embodiments of the present disclosure relate to the following [1] to

[18] .

[0007] [1] A wiring board comprising: a core substrate including a first surface, a second surface opposite to the first surface, and a plurality of through holes penetrating from the first surface to the second surface, the core substrate comprising a core layer made of glass; a plurality of through electrodes located in each of the plurality of through holes; a first rewiring layer located on the first surface; and a second rewiring layer located on the second surface, wherein each of the first rewiring layer and the second rewiring layer comprises a plurality of insulating layers stacked in a thickness direction, and a conductive portion including a through portion penetrating the insulating layer and a wiring or pad located on a surface of the insulating layer, each of the first rewiring layer and the second rewiring layer comprises a low expansion portion including at least one insulating layer of the plurality of insulating layers, and each of the insulating layer of the low expansion portion of the first rewiring layer and the insulating layer of the low expansion portion of the second rewiring layer comprises a fiber member made of glass fiber and a resin impregnated in the fiber member.

[0008] [2] In the wiring board according to [1], the core layer may have a first thermal expansion coefficient C1 at 25°C, and the insulating layer of the low expansion portion of the first redistribution layer and the insulating layer of the low expansion portion of the second redistribution layer may both have a second thermal expansion coefficient C2 at 25°C, and the following relationship may be established: 0.80 x C1 ≦ C2 ≦ 1.20 x C1

[0009] [3] In the wiring board according to [2], the first thermal expansion coefficient C1 may be 7.0 ppm / K or more and 9.0 ppm / K or less.

[0010] [4] In the wiring board according to any one of [1] to [3], the insulating layer in the low expansion portion of the first redistribution layer and the insulating layer in the low expansion portion of the second redistribution layer may each have a glass occupancy ratio of 0.40 or more, where the glass occupancy ratio is a ratio of a cross-sectional area of ​​the glass fiber to a cross-sectional area of ​​the insulating layer in the low expansion portion.

[0011] [5] In the wiring board described in any one of [1] to [4], the insulating layer of the low expansion portion of the first redistribution layer and the insulating layer of the low expansion portion of the second redistribution layer may both contain epoxy resin impregnated in the fiber material.

[0012] [6] In the wiring board according to any one of [1] to [5], the core layer may have a first thickness T1, and the low expansion portion of the first redistribution layer and the low expansion portion of the second redistribution layer may both have a second thickness T2, and the following relational expression may be satisfied: 0.10×T1≦T2≦0.50×T1

[0013] [7] In the wiring substrate described in any one of [1] to [6], the number of the insulating layers included in the low expansion portion of the first redistribution layer may be equal to the number of the insulating layers included in the low expansion portion of the second redistribution layer.

[0014] [8] In the wiring board described in any one of [1] to [7], the first redistribution layer and the second redistribution layer may both have a surface layer that is the insulating layer located between the low expansion portion and the core substrate, and the surface layer of the first redistribution layer and the surface layer of the second redistribution layer may both be made of resin.

[0015] [9] In the wiring board described in [8], the surface layer of the first redistribution layer and the surface layer of the second redistribution layer may both have a third thermal expansion coefficient C3 at 25°C, and the third thermal expansion coefficient C3 may be 40.0 ppm / K or more and 60.0 ppm / K or less.

[0016]

[10] In the wiring board according to [8] or [9], the core layer may have a first thickness T1, and the surface layer of the first redistribution layer and the surface layer of the second redistribution layer may both have a third thickness T3, and the following relational expression may be satisfied: 0.10×T2≦T3≦0.50×T2

[0017]

[11] In the wiring substrate according to any one of [1] to

[10] , the first redistribution layer and the second redistribution layer may both be located on the low expansion portion and have a low elasticity portion including at least one of the insulating layers, and the insulating layer of the low elasticity portion of the first redistribution layer and the insulating layer of the low elasticity portion of the second redistribution layer may both have a modulus of elasticity lower than the modulus of elasticity of the insulating layer of the low expansion portion.

[0018]

[12] In the wiring board described in

[11] , the insulating layer of the low elasticity section of the first redistribution layer and the insulating layer of the low elasticity section of the second redistribution layer may both contain a resin and a plurality of fillers dispersed in the resin.

[0019]

[13] In the wiring board according to

[11] or

[12] , the elastic modulus of the insulating layer in the low expansion portion may be 20.0 GPa or more and 40.0 GPa or less, and the elastic modulus of the insulating layer in the low elasticity portion may be 1.0 GPa or more and 20.0 GPa or less.

[0020]

[14] In the wiring substrate according to any one of

[11] to

[13] , the low expansion portion of the first redistribution layer and the low expansion portion of the second redistribution layer may both have a second thickness T2, and the low elasticity portion of the first redistribution layer and the low elasticity portion of the second redistribution layer may both have a fourth thickness T4, and the following relational expression may be established: T4<T2

[0021]

[15] In the wiring board described in any one of [1] to

[14] , the core substrate may include a first core surface layer located between the core layer and the first surface, and a second core surface layer located between the core layer and the second surface, and both the first core surface layer and the second core surface layer may include a fiber member made of glass fiber and a resin impregnated in the fiber member.

[0022]

[16] A semiconductor package comprising: the wiring board according to any one of [1] to

[15] ; and at least one semiconductor element disposed on an outer surface of the first redistribution layer of the wiring board.

[0023]

[17] In the semiconductor package according to

[16] , the at least one semiconductor element may include at least one logic IC and at least one memory IC.

[0024]

[18] A method for manufacturing a wiring board, comprising: a step of preparing a core substrate including a first surface, a second surface opposite to the first surface, and a core layer including glass, the core substrate including a first surface, a second surface opposite to the first surface, and a plurality of through holes penetrating from the first surface to the second surface; a step of forming a through electrode in each of the plurality of through holes; a step of forming a first rewiring layer on the first surface; and a step of forming a second rewiring layer on the second surface, wherein each of the first rewiring layer and the second rewiring layer comprises a plurality of insulating layers stacked in a thickness direction, and a conductive portion including a through portion penetrating the insulating layer and a wiring or a pad located on a surface of the insulating layer, each of the first rewiring layer and the second rewiring layer comprises a low expansion portion including at least one insulating layer of the plurality of insulating layers, and the insulating layer of the low expansion portion of the first rewiring layer and the insulating layer of the low expansion portion of the second rewiring layer both comprise a fiber member made of glass fiber and a resin impregnated in the fiber member.

[0025] According to the embodiments of the present disclosure, it is possible to reduce thermal stress between a semiconductor element and a wiring layer.

[0026] 1 is a cross-sectional view showing a wiring board according to an embodiment; FIG. 2 is a cross-sectional view showing a semiconductor package according to an embodiment; FIG. 3 is a plan view showing a semiconductor package according to an embodiment; FIG. 4 is a cross-sectional view showing a semiconductor package according to an embodiment; FIG. 5 is a cross-sectional view showing an example of a layer configuration of a wiring board; FIG. 6 is a cross-sectional view showing an example of a low expansion portion; FIG. 7 is a cross-sectional view showing an example of a low elasticity portion; FIG. 8 is a diagram showing an indenter used in a nanoindentation test; FIG. 9 is a cross-sectional view showing the indenter being pressed into an object; FIG. 10 is a cross-sectional view showing the object after the indenter has been removed; FIG. 11 is a graph showing the relationship between indentation depth and load; FIG. 12 is a cross-sectional view showing an example of a conductive portion; FIG. 13 is a cross-sectional view showing an example of an application of a semiconductor package; FIG. 14 is a cross-sectional view showing a step of forming a through hole in a core substrate; FIG. 15 is a cross-sectional view showing a step of forming a through electrode in the through hole; FIG. 16 is a cross-sectional view showing a step of forming surface layers on first and second surfaces of a core substrate; FIG. 17 is a cross-sectional view showing a step of forming an opening in the surface layer; FIG. 18 is a cross-sectional view showing a step of forming a conductive portion on the opening and outer surface of the surface layer; FIG. 19 is a cross-sectional view showing a step of forming a low expansion layer on the surface layer; FIG. 19 is a cross-sectional view showing a step of forming an opening in the low expansion layer; FIG. 19 is a cross-sectional view showing a step of forming a conductive portion on the opening and outer surface of the low expansion layer; 10A and 10B are cross-sectional views showing a step of forming a low elastic layer on a low expansion layer; FIG. 10B are cross-sectional views showing a step of forming a conductive portion on an opening and an outer surface of the low elastic layer; FIG. 10C are cross-sectional views showing a step of forming a second low elastic layer; FIG. 10D are cross-sectional views showing a wiring board according to a first modified example; FIG. 10E are cross-sectional views showing a step of forming a through electrode in a through hole of a core substrate in the first modified example; FIG. 10F are cross-sectional views showing a step of filling a through hole with resin in the first modified example; FIG. 10F are cross-sectional views showing a wiring board according to a second modified example; FIG. 10H are cross-sectional views showing a step of forming a through hole in a core substrate in the second modified example; FIG. 10H are cross-sectional views showing a step of forming a through electrode in a through hole in the second modified example; and FIG. 10H are diagrams showing examples of products on which a wiring board is mounted. A cross-sectional view showing a wiring board according to a fourth modified example. A cross-sectional view showing a wiring board according to example D.

[0027] The configuration of a wiring board and a manufacturing method thereof will be described in detail with reference to the drawings. The following embodiments are examples of embodiments of the present disclosure, and the present disclosure should not be construed as being limited to these embodiments. Terms such as "substrate," "base material," "sheet," and "film" are not distinguished from one another solely based on differences in name. For example, the concept of "substrate" includes materials that may be called sheets or films. "Surface" refers to a surface that coincides with the planar direction of a target plate-like member when viewed holistically and comprehensively. The normal direction used with respect to a plate-like member refers to the normal direction to the surface of the member. As used in this specification, terms such as "parallel" and "orthogonal," as well as values ​​of length and angle, that specify shape, geometric conditions, and their degrees, are interpreted without being bound by strict meanings but include a range within which similar functions can be expected.

[0028] In this specification, when multiple upper limit value candidates and multiple lower limit value candidates are listed for a certain parameter, the numerical range of the parameter may be constructed by combining any one upper limit value candidate with any one lower limit value candidate. For example, consider a description that reads, "Parameter B is, for example, A1 or more, or may be A2 or more, or may be A3 or more. Parameter B is, for example, A4 or less, or may be A5 or less, or may be A6 or less." In this case, the numerical range of parameter B may be A1 or more and A4 or less, A1 or more and A5 or less, A1 or more and A6 or less, A2 or more and A4 or less, A2 or more and A5 or less, A2 or more and A6 or less, A3 or more and A4 or less, A3 or more and A5 or less, or A3 or more and A6 or less.

[0029] In the drawings referred to in this embodiment, the same parts or parts having similar functions are denoted by the same or similar reference numerals, and repeated explanations thereof may be omitted. Furthermore, the dimensional ratios of the drawings may differ from the actual ratios for the convenience of explanation, and some components may be omitted from the drawings.

[0030] 1 is a cross-sectional view showing an example of a wiring substrate 10. The wiring substrate 10 includes a core substrate 12, a plurality of through electrodes 20, a first redistribution layer 30, and a second redistribution layer 40.

[0031] (Core Substrate) The core substrate 12 includes a first surface 121 and a second surface 122 located on the opposite side of the first surface 121. The core substrate 12 includes a plurality of through holes 15 that penetrate from the first surface 121 to the second surface 122. A through electrode 20 is located in each of the plurality of through holes 15.

[0032] The core substrate 12 includes at least a core layer 13. In this embodiment, the core substrate 12 is made of the core layer 13. That is, the core layer 13 constitutes the first surface 121 and the second surface 122 of the core substrate 12.

[0033] The core layer 13 is made of an insulating inorganic material, such as glass, that has high rigidity. By increasing the rigidity of the core layer 13, deformation such as warping of the core substrate 12 can be suppressed.

[0034] An example of the glass used in the core layer 13 is alkali-free glass. The alkali-free glass is glass that does not contain alkali components such as sodium or potassium. The alkali-free glass contains, for example, boric acid instead of an alkali component. The alkali-free glass also contains, for example, an alkaline earth metal oxide such as calcium oxide or barium oxide.

[0035] The thickness of the core layer 13 is also referred to as a first thickness T1. The first thickness T1 is, for example, 100 μm or more, and may be 200 μm or more, 300 μm or more, 400 μm or more, or 600 μm or more. The first thickness T1 is, for example, 1600 μm or less, 1400 μm or less, 1200 μm or less, 1000 μm or less, 800 μm or less, or 600 μm or less. The thickness direction of the core layer 13 determines the thickness direction of the wiring substrate 10. In the following description, the thickness direction of the wiring substrate 10 is also referred to as a third direction D3.

[0036] The core layer 13 has a low thermal expansion coefficient. The thermal expansion coefficient of the core layer 13 is also referred to as a first thermal expansion coefficient C1. The first thermal expansion coefficient C1 is calculated based on the thermal expansion that occurs in the core layer 13 as the temperature changes from 20°C to 250°C. The thermal expansion that occurs in the core layer 13 is measured using a cantilever. Specifically, a probe attached to the tip of the cantilever is used to measure the displacement of the core layer 13 due to thermal expansion. The probe is attached to an atomic force microscope. The measurement conditions are as follows: Atomic force microscope: AFM-IR device "Dimension IconIR" manufactured by Bruker Japan Probe tip diameter: 10 nm to 30 nm Analysis depth: 30 nm Temperature change: 20°C to 250°C

[0037] The first thermal expansion coefficient C1 is, for example, 2.0 ppm / K or more, or may be 4.0 ppm / K or more, or 7.0 ppm / K or more. The first thermal expansion coefficient C1 is, for example, 12.0 ppm / K or less, or may be 10.0 ppm / K or less, or may be 9.0 ppm / K or less.

[0038] (Through electrode) The through electrode 20 extends in the third direction D3 at least along the wall surface 16 of the through hole 15 from the first surface 121 to the second surface 122. In this embodiment, the through electrode 20 is located throughout the entire area of ​​the through hole 15. That is, the entire space of the through hole 15 is occupied by the through electrode 20. As will be described later, the through electrode 20 does not have to occupy the entire space of the through hole 15.

[0039] The through electrode 20 includes a conductive material. The conductive material is, for example, a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc. The conductive material may also be an alloy containing the above-mentioned metal.

[0040] (First Redistribution Layer) The first redistribution layer 30 is located on the first surface 121 of the core substrate 12. The first redistribution layer 30 includes an inner surface 301 and an outer surface 302. The inner surface 301 is the surface of the first redistribution layer 30 facing the core substrate 12 in the third direction D3. The outer surface 302 is the surface of the first redistribution layer 30 located opposite the inner surface 301 in the third direction D3.

[0041] The surfaces of the layers constituting the wiring board 10 all include an inner surface and an outer surface. In this application, the "inner surface" is the surface facing the core substrate 12 in the third direction D3. In this application, the "outer surface" is the surface located opposite the "inner surface" in the third direction D3.

[0042] The first redistribution layer 30 includes a plurality of insulating layers 31 and a plurality of conductive portions 32 stacked in the third direction D3. The plurality of conductive portions 32 include, for example, through portions 321, wiring 322, and pads 323. One through portion 321 penetrates one insulating layer 31. The wiring 322 and the pad 323 are located on the surface of one through portion 321. For example, the wiring 322 and the pad 323 are located on the outer surface of one through portion 321. The wiring 322 extends along the surface direction of the wiring substrate 10. The pad 323 may be connected to another through portion 321 in the third direction D3. The pad 323 may be connected to a terminal or pad of a component to be combined with the wiring substrate 10, such as a terminal of a semiconductor element 50 described below.

[0043] (Second Redistribution Layer) The second redistribution layer 40 is located on the second surface 122 of the core substrate 12. The second redistribution layer 40 includes an inner surface 401 and an outer surface 402.

[0044] The second redistribution layer 40 includes a plurality of insulating layers 41 and a plurality of conductive portions 42 stacked in the third direction D3. Similar to the conductive portions 32, the plurality of conductive portions 42 may include through-holes 421, wirings 422, and pads 423. Each through-hole 421 penetrates one insulating layer 41. The wirings 422 and pads 423 are located on the surface of one through-hole 421. For example, the wirings 422 and pads 423 are located on the outer surface of one through-hole 421. The wirings 422 extend along the surface direction of the wiring substrate 10. The pads 423 may be connected to other through-holes 421 in the third direction D3. The pads 423 may be connected to terminals or pads of a component to be combined with the wiring substrate 10, such as a motherboard 80 (described later).

[0045] 2 is a cross-sectional view showing an example of a semiconductor package 60. The semiconductor package 60 includes a wiring substrate 10 and at least one semiconductor element 50 disposed on the outer surface of the wiring substrate 10. The semiconductor element 50 includes a terminal electrically connected to a pad 323 of the first redistribution layer 30. A bump 53 may be located between the terminal of the semiconductor element 50 and the pad 323 of the first redistribution layer 30. The bump 53 may include, for example, solder.

[0046] The semiconductor element 50 includes a transistor formed of a semiconductor such as silicon. The semiconductor element may be a logic IC or a memory IC. The logic IC may be, for example, a CPU, a GPU, an FPGA, a sensor, or the like.

[0047] 3 is a plan view showing an example of a semiconductor package 60. The semiconductor package 60 may include a plurality of semiconductor packages 60. For example, the semiconductor package 60 may include a logic IC 51 and a memory IC 52. As shown in FIG. 3 , the first redistribution layer 30 may include wiring 322 including a first end electrically connected to the logic IC 51 and a second end electrically connected to the memory IC 52.

[0048] The wiring 322 may extend in the first direction D1 or the second direction D2. The first direction D1 and the second direction D2 are included in the surface direction of the wiring substrate 10. That is, the first direction D1 and the second direction D2 are parallel to the surface direction of the wiring substrate 10. The surface direction of the wiring substrate 10 is, for example, the surface direction of the first surface 121 of the core substrate 12. The first direction D1 is perpendicular to the second direction D2. The above-mentioned third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0049] 4 is a cross-sectional view showing an example of a semiconductor package 60. The semiconductor package 60 may include a molded resin 55 that protects the semiconductor element 50. The molded resin 55 is in contact with the side surfaces of the semiconductor element 50 so as to surround the semiconductor element 50 in a plan view. "Planar view" means that the object is viewed along the third direction D3. Examples of materials for the molded resin 55 include polyimide, epoxy resin, and acrylic resin.

[0050] In the conventional semiconductor package 60, an organic material such as epoxy resin is used as the material for the core substrate. The thermal expansion coefficient of organic materials such as epoxy resin is larger than that of inorganic materials. The semiconductor element 50 is mostly made of silicon, which has a low thermal expansion coefficient. Therefore, in the conventional semiconductor package 60, there is a large difference between the thermal expansion coefficient of the core substrate and the thermal expansion coefficient of the semiconductor element 50.

[0051] In the present embodiment, core substrate 12 includes core layer 13 made of glass. The thermal expansion coefficient of core substrate 12 in the present embodiment is smaller than the thermal expansion coefficient of the core substrate of conventional semiconductor package 60. According to the present embodiment, the difference between the thermal expansion coefficient of core substrate 12 and the thermal expansion coefficient of semiconductor element 50 can be reduced.

[0052] The first redistribution layer 30 located between the core substrate 12 and the semiconductor element 50 also preferably has a low thermal expansion coefficient. By reducing the thermal expansion coefficient of the first redistribution layer 30, the thermal stress occurring between the core substrate 12 and the first redistribution layer 30 and the thermal stress occurring between the first redistribution layer 30 and the semiconductor element 50 can be reduced.

[0053] The second redistribution layer 40 located on the second surface 122 of the core substrate 12 preferably has a thermal expansion coefficient equivalent to that of the first redistribution layer 30. In other words, it is preferable that the difference between the thermal expansion coefficient of the second redistribution layer 40 and the thermal expansion coefficient of the first redistribution layer 30 is small. This can reduce the difference between the thermal stress generated between the core substrate 12 and the first redistribution layer 30 and the thermal stress generated between the core substrate 12 and the second redistribution layer 40. Reducing the difference in thermal stress can suppress deformation such as warping of the semiconductor package 60.

[0054] The configurations of the first redistribution layer 30 and the second redistribution layer 40 will be described in detail below.

[0055] The first redistribution layer 30 will be described.

[0056] [Low Expansion Layer] The first redistribution layer 30 includes at least a low expansion portion 34. The low expansion portion 34 includes at least one of the insulating layers 31 included in the first redistribution layer 30. The insulating layer 31 that constitutes the low expansion portion 34 is also referred to as a low expansion layer 35. In the example shown in FIG. 5 , the low expansion portion 34 includes two low expansion layers 35 stacked in the third direction D3.

[0057] 6 is a cross-sectional view showing an example of the low-expansion section 34. The low-expansion layer 35 of the low-expansion section 34 includes a fibrous member 35a and a resin 35d impregnated in the fibrous member 35a. The fibrous member 35a is a member made of glass fiber. For example, the fibrous member 35a includes a plurality of first fibrous members 35b extending in the first direction D1 and a plurality of second fibrous members 35c in contact with the first fibrous members 35b and extending in the second direction D2. The plurality of first fibrous members 35b and the plurality of second fibrous members 35c may be woven together.

[0058] The resin 35d may contain an organic material, such as an epoxy resin or a bismaleimide triazine resin.

[0059] The low-expansion layer 35 has a thickness T21. The thickness T21 is, for example, 20 μm or more, or may be 25 μm or more, or 30 μm or more. The thickness T21 is, for example, 50 μm or less, or may be 45 μm or less, or may be 40 μm or less.

[0060] The low expansion layer 35 has a low thermal expansion coefficient, which is also referred to as a second thermal expansion coefficient C2.

[0061] The second thermal expansion coefficient C2 of the low expansion layer 35 is measured using a cantilever, similar to the first thermal expansion coefficient C1 of the core layer 13. Specifically, a probe attached to the tip of the cantilever is used to measure the displacement of the low expansion layer 35 due to thermal expansion. The probe is attached to an atomic force microscope. The measurement conditions are as follows: Atomic force microscope: AFM-IR device "Dimension IconIR" manufactured by Bruker Japan Probe tip diameter: 10 nm to 30 nm Analysis depth: 30 nm Temperature change: 20°C to 250°C

[0062] The second thermal expansion coefficient C2 is, for example, 2.0 ppm / K or more, or may be 4.0 ppm / K or more, or 7.0 ppm / K or more. The second thermal expansion coefficient C2 is, for example, 12.0 ppm / K or less, or may be 10.0 ppm / K or less, or may be 9.0 ppm / K or less.

[0063] The ratio C2 / C1 of the second thermal expansion coefficient C2 to the first thermal expansion coefficient C1 is, for example, 0.80 or more, or may be 0.85 or more, or may be 0.90 or more, and is, for example, 1.20 or less, or may be 1.15 or less, or may be 1.10 or less.

[0064] The thickness of the low expansion portion 34 is also referred to as a second thickness T2. The second thickness T2 is, for example, 40 μm or more, or may be 50 μm or more, or 60 μm or more. The second thickness T2 is, for example, 200 μm or less, or may be 150 μm or less, or may be 100 μm or less.

[0065] The second thickness T2 of the low expansion portion 34 may be determined relative to the first thickness T1 of the core layer 13. T2 / T1, which is the ratio of the second thickness T2 to the first thickness T1, is, for example, 0.10 or more, or may be 0.15 or more, or may be 0.20 or more. T2 / T1 is, for example, 0.50 or less, or may be 0.45 or less, or may be 0.40 or less.

[0066] The second thickness T2 of the low expansion portion 34 may be determined relative to the thickness T5 of the first redistribution layer 30. T2 / T5, which is the ratio of the second thickness T2 to the thickness T5 of the first redistribution layer 30, is, for example, 0.30 or more, or may be 0.40 or more, or may be 0.50 or more. T2 / T5 is, for example, 0.90 or less, or may be 0.80 or less, or may be 0.70 or less.

[0067] The low-expansion layer 35 may have a glass occupancy ratio of 0.30 or more. The glass occupancy ratio is the ratio of the cross-sectional area of ​​the fiber component 35a to the cross-sectional area of ​​the low-expansion layer 35. The glass occupancy ratio is calculated based on an image of the cross section of the low-expansion layer 35. The image of the cross section is obtained by observing the cross section of the wiring substrate 10 using an optical microscope. The cross section is a cross section of the wiring substrate 10 cut along the second direction D2 at a position 1.0 mm in the first direction D1 from the end of the wiring substrate 10 in the first direction D1.

[0068] The glass occupancy ratio of the low expansion layer 35 may be 0.35 or more, or may be 0.40 or more. The glass occupancy ratio of the low expansion layer 35 is, for example, 0.80 or less, 0.70 or less, or 0.60 or less.

[0069] [Surface Layer] The first redistribution layer 30 may include an insulating layer 31 located between the core substrate 12 and the low expansion portion 34. The insulating layer 31 located between the core substrate 12 and the low expansion portion 34 is also referred to as a surface layer 36.

[0070] The surface layer 36 may extend in the planar direction of the first surface 121 so as to straddle the core substrate 12 and the through electrode 20 in a planar view. In this case, the surface layer 36 overlaps the first boundary 201 in a planar view, as shown in Fig. 5 . The first boundary 201 is the boundary between the core substrate 12 and the through electrode 20 on the first surface 121.

[0071] Like the other insulating layers 31 such as the low expansion layer 35, the surface layer 36 includes a through hole in which the above-described through portion 321 is disposed. As shown in Fig. 5 , the through portion 321 located in the surface layer 36 may be connected to the through electrode 20. The through portion 321 located in the surface layer 36 may be connected to the through portion 321 located in the through hole of the low expansion layer 35.

[0072] The surface layer 36 may have a higher water vapor permeability than the low-expansion layer 35 of the low-expansion portion 34. By providing the surface layer 36 between the core substrate 12 and the low-expansion portion 34, moisture present around the through electrode 20 is more easily released to the outside of the wiring substrate 10. The moisture is located, for example, between the wall surface 16 of the through hole 15 of the core substrate 12 and the through electrode 20. The moisture is released to the outside of the wiring substrate 10 through, for example, the first boundary 201 and the surface layer 36.

[0073] The material of the surface layer 36 is preferably an insulating resin. Examples of insulating resins include polyimide, polyamide, polyamideimide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyether ether ketone, polyether sulfone, polycarbonate, polyetherimide, epoxy resin, phenol resin, polyphenylene ether, acrylic resin, polyolefin, polycycloolefin, and liquid crystal polymer compound. Examples of polyolefins include polyethylene and polypropylene. Examples of polycycloolefins include polynorbornene.

[0074] The thickness of the surface layer 36 is also referred to as a third thickness T3. The third thickness T3 is, for example, 10 μm or more, or may be 15 μm or more, or may be 20 μm or more. The third thickness T3 is, for example, 50 μm or less, or may be 40 μm or less, or may be 30 μm or less.

[0075] The third thickness T3 of the surface layer 36 may be determined relative to the second thickness T2 of the low expansion portion 34. The ratio of the third thickness T3 to the second thickness T2, T3 / T2, is, for example, 0.10 or more, or may be 0.15 or more, or may be 0.20 or more. T3 / T2 is, for example, 0.50 or less, or may be 0.45 or less, or may be 0.40 or less.

[0076] The surface layer 36 may have a high coefficient of thermal expansion, also referred to as the third coefficient of thermal expansion C3.

[0077] The third thermal expansion coefficient C3 of the surface layer 36 is calculated relative to the first thermal expansion coefficient C1 of the core layer 13. Specifically, the third thermal expansion coefficient C3 of the surface layer 36 is calculated according to a ratio R2 of the displacement of the surface layer 36 due to a change in temperature to the displacement of the core layer 13 due to a change in temperature. The third thermal expansion coefficient C3 is R2 × C1. The displacement is measured using a cantilever, as in the case of the second thermal expansion coefficient C2 of the low-expansion layer 35.

[0078] The third thermal expansion coefficient C3 is, for example, 30.0 ppm / K or more, may be 35.0 ppm / K or more, or may be 40.0 ppm / K or more. The third thermal expansion coefficient C3 is, for example, 70.0 ppm / K or less, may be 65.0 ppm / K or less, or may be 60.0 ppm / K or less.

[0079] The surface layer 36 may be softer than the core layer 13 and the low expansion portion 34. For example, the thermal expansion coefficient C3 of the surface layer 36 may be greater than the thermal expansion coefficient C1 of the core layer 13 and the thermal expansion coefficient C2 of the low expansion layer 35. For example, the elastic modulus of the surface layer 36 may be smaller than the elastic modulus of the low expansion layer 35. By disposing the soft surface layer 36 between the core substrate 12 and the low expansion portion 34, stress generated in the core substrate 12 or the low expansion portion 34 can be alleviated by using the surface layer 36. As a result, stress in the entire wiring substrate 10 is reduced. Therefore, for example, defects such as cracks can be suppressed from occurring in the core substrate 12. For example, the occurrence of a "seware" (sewage), which will be described later, in the core layer 13 of the core substrate 12 can be suppressed. Furthermore, deformation such as swelling can be suppressed from occurring in the first redistribution layer 30, including the low expansion portion 34.

[0080] The ratio C3 / C1 of the thermal expansion coefficient C3 of the surface layer 36 to the thermal expansion coefficient C1 of the core layer 13 is, for example, 4.0 or more, or may be 5.0 or more, or 6.0 or more. C3 / C1 is, for example, 10.0 or less, or may be 8.0 or less, or may be 7.0 or less.

[0081] The ratio C3 / C2 of the thermal expansion coefficient C3 of the surface layer 36 to the thermal expansion coefficient C2 of the low expansion portion 34 is, for example, 4.0 or more, or may be 6.0 or more, or may be 8.0 or more. C3 / C2 is, for example, 30.0 or less, or may be 20.0 or less, or may be 10.0 or less.

[0082] [Low Elasticity Portion] The first redistribution layer 30 may include a low elasticity portion 37 located on the low expansion portion 34. The low elasticity portion 37 may be located on the outer surface of the low expansion portion 34. The low elasticity portion 37 includes at least one of the multiple insulating layers 31 included in the first redistribution layer 30. The insulating layer 31 that constitutes the low elasticity portion 37 is also referred to as a low elasticity layer 38. In the example shown in FIG. 5 , the low elasticity portion 37 includes two low elasticity layers 38 stacked in the third direction D3.

[0083] The low elasticity portion 37 has a lower elastic modulus than the low expansion portion 34. That is, the low elasticity portion 37 is softer than the low expansion portion 34. In the state of the semiconductor package 60, the low elasticity portion 37 is located between the low expansion portion 34 and the semiconductor element 50.

[0084] Even if the difference between the thermal expansion coefficient of the semiconductor element 50 and the thermal expansion coefficient of the low expansion portion 34 is small, the amount of deformation of the semiconductor element 50 caused by temperature changes is unlikely to be the same as the amount of deformation of the low expansion portion 34. By providing the low elasticity portion 37 between the low expansion portion 34 and the semiconductor element 50, it is possible to reduce the stress caused by the difference between the amount of deformation of the semiconductor element 50 and the amount of deformation of the low expansion portion 34. For example, it is possible to reduce the stress applied to the bump 53. As a result, it is possible to prevent defects such as deformation from occurring in the bump 53.

[0085] The thickness of the low elasticity portion 37 is also referred to as a fourth thickness T4. The fourth thickness T4 of the low elasticity portion 37 is, for example, 10 μm or more, or may be 15 μm or more, or may be 20 μm or more. The fourth thickness T4 is, for example, 50 μm or less, or may be 40 μm or less, or may be 30 μm or less.

[0086] The fourth thickness T4 of the low elasticity portion 37 may be smaller than the second thickness T2 of the low expansion portion 34. The ratio of the fourth thickness T4 to the second thickness T2, T4 / T2, is, for example, 0.30 or more, 0.40 or more, or 0.50 or more. T4 / T2 is, for example, 0.80 or less, 0.70 or less, or 0.60 or less.

[0087] The fourth thickness T4 of the low elasticity portion 37 may be greater than the first thickness T1 of the surface layer 36 .

[0088] 7 is a cross-sectional view showing an example of the low-elasticity portion 37. The low-elasticity layer 38 of the low-elasticity portion 37 includes an insulating resin 38a. Examples of the resin 38a include polyimide, polyamide, polyamideimide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyether ether ketone, polyether sulfone, polycarbonate, polyetherimide, epoxy resin, phenol resin, polyphenylene ether, acrylic resin, polyolefin, polycycloolefin, and liquid crystal polymer compound. Examples of polyolefins include polyethylene and polypropylene. Examples of polycycloolefins include polynorbornene.

[0089] The low-elasticity layer 38 may include a plurality of fillers 38b dispersed in a resin 38a. The fillers 38b may have, for example, a spherical shape. The fillers 38b may include an inorganic compound such as an inorganic oxide or an inorganic nitride. The inorganic oxide may be, for example, silicon oxide. The inorganic nitride may be, for example, silicon nitride.

[0090] The size of the filler 38b is, for example, 0.05 μm or more, or may be 0.10 μm or more, or 0.20 μm or more. The size of the filler 38b is, for example, 1.00 μm or less, or may be 0.80 μm or less, or may be 0.60 μm or less. The size of the filler 38b is the circle-equivalent diameter of the filler 38b. The circle-equivalent diameter is calculated based on the average value of the cross-sectional area of ​​the filler 38b calculated from an image of the cross section of the low-elastic layer 38.

[0091] The low-elasticity layer 38 may have a filler occupancy ratio of 0.50 or more. The filler occupancy ratio is the ratio of the cross-sectional area of ​​the filler 38b to the cross-sectional area of ​​the low-elasticity layer 38. The filler occupancy ratio is calculated based on an image of the cross-section of the low-elasticity layer 38.

[0092] The filler occupancy rate of the low-elasticity layer 38 may be 0.55 or more, or 0.60 or more. The filler occupancy rate of the low-elasticity layer 38 is, for example, 0.90 or less, 0.80 or less, or 0.70 or less.

[0093] The low-elasticity layer 38 may have a smaller glass occupancy ratio than the low-expansion layer 35. The glass occupancy ratio of the low-elasticity layer 38, like the glass occupancy ratio of the low-expansion layer 35, is the ratio of the cross-sectional area of ​​the fibrous member to the cross-sectional area of ​​the low-elasticity layer 38. The glass occupancy ratio of the low-elasticity layer 38 is, for example, 0.20 or less, or may be 0.15 or less, or may be 0.10 or less. The low-elasticity layer 38 may not include a fibrous member.

[0094] The image of the cross section of the low-elasticity layer 38 is obtained by using an optical microscope to observe the cross section of the wiring substrate 10. The cross section is a cross section of the wiring substrate 10 cut along the second direction D2 at a position 1.0 mm in the first direction D1 from the end of the wiring substrate 10 in the first direction D1.

[0095] The elastic modulus of the low expansion portion 34 is also referred to as the first elastic modulus E1. The elastic modulus of the low elasticity portion 37 is also referred to as the second elastic modulus E2. The second elastic modulus E2 is lower than the first elastic modulus E1. The ratio E2 / E1 of the second elastic modulus E2 to the first elastic modulus E1 is, for example, 0.50 or less, or may be 0.40 or less, or may be 0.30 or less. E2 / E1 is, for example, 0.05 or more, or may be 0.10 or more, or may be 0.20 or more.

[0096] The second elastic modulus E2 of the low elasticity portion 37 is, for example, 20.0 GPa or less, may be 15.0 GPa or less, or may be 10.0 GPa or less. The second elastic modulus E2 is, for example, 1.0 GPa or more, may be 3.0 GPa or more, or may be 5.0 GPa or more.

[0097] The first elastic modulus E1 of the low expansion portion 34 is, for example, 20.0 GPa or more, or may be 23.0 GPa or more, or 26.0 GPa or more. The first elastic modulus E1 is, for example, 40.0 GPa or less, or may be 37.0 GPa or less, or may be 34.0 GPa or less.

[0098] As described above, the low-elasticity portion 37 is relatively soft. Similarly, the surface layer 36 is also relatively soft. On the other hand, the core layer 13 and the low-expansion portion 34 are relatively hard. Therefore, the wiring board 10 has a structure in which soft and hard portions are alternately arranged along the third direction D3. That is, the hard core layer 13, the soft surface layer 36, the hard low-expansion portion 34, and the soft low-elasticity portion 37 are arranged in the third direction D3. Such a sandwich structure can improve the reliability of the wiring board 10. For example, stress generated in the core board 12 or the low-expansion portion 34 is easily alleviated. Similarly, the sandwich structure of the core layer 13, the surface layer 46 (described later), the low-expansion portion 44 (described later), and the low-elasticity portion 47 (described later) can also improve the reliability of the wiring board 10.

[0099] A method for calculating the elastic modulus by nanoindentation testing will be described with reference to Figures 8 to 11. Figure 8 is a diagram showing an indenter 70 used in nanoindentation testing. The indenter 70 includes a pyramidal surface with an apex angle of 115°.

[0100] In a nanoindentation test, an indenter 70 attached to a transducer is pressed into the surface of an object placed on a stage while applying a load with the transducer. When measuring the first elastic modulus E1 of the low expansion portion 34, the object is a cross section of the low expansion portion 34. When measuring the second elastic modulus E2 of the low elasticity portion 37, the object is a cross section of the low elasticity portion 37. The indenter 70 may be a diamond Vickers indenter, a Berkovich indenter, or the like, and is selected depending on the elastic modulus, dimensions, etc. of the layer to be measured.

[0101] Fig. 9 is a cross-sectional view showing a state in which the indenter 70 is being pressed into the object 75. The surface of the object 75 in the pressed state is also referred to as a deformed surface 76. Thereafter, the indenter 70 is removed from the object 75 by moving the indenter 70 in the direction opposite to the pressing direction. Fig. 10 is a cross-sectional view showing the object 75 after the indenter 70 has been removed. The surface of the object 75 after the indenter 70 has been removed is also referred to as a restored surface 77. In Fig. 10, the deformed surface 76 is indicated by a dotted line.

[0102] 11 is a graph showing the relationship between the indentation depth h of the indenter 70 and the load P of the indenter 70. The load P increases along a quadratic curve A as the indentation depth h of the indenter 70 increases. The curve A represents both the elastic deformation and the plastic deformation of the object 75. When the indentation is completed, the indentation depth h of the indenter 70 reaches a maximum value h ｍａｘ The load P is also at its maximum value P ｍａｘ This becomes:

[0103] After the indenter 70 has been pressed down, the indenter 70 is moved in the direction opposite to the pressing direction. As a result, as shown in FIG. 11, the load P decreases along a quadratic curve B that is steeper than the curve A. Furthermore, due to elastic recovery caused by the release of the indenter 70, the surface of the object 75 is deformed from a deformed surface 76 to a restored surface 77. ｆ represents the depth of the recess formed in the restoration surface 77.

[0104] In the nanoindentation test, the reduced elastic modulus E of the indentation contact ｒ is calculated by the following formula: ｒ = π １ / ２ / 2CA ｐ １ / ２ (1) In formula (1), C is the maximum value of the load P ｍａｘ The slope of the tangent to the curve B at ｐ is the projected area where the indenter 70 and the object 75 are in contact.

[0105] A in Equation (1) ｐ can be calculated by the following formula: ｐ = 23.96 × {h ｍａｘ−ε(h ｍａｘ -h Ｃ )} (2) In the formula (2), ε is a correction factor due to the geometric shape of the indenter I. When the indenter 70 is a diamond Vickers indenter, ε is 0.75. Ｃ is the maximum value of the load P ｍａｘ 11. The intersection point of the tangent to the curve B at the point A and the horizontal axis of FIG.

[0106] Reduced Elastic Modulus E ｒ Based on this, the indentation elastic modulus E of the object 75 ＩＴ is calculated by the following formula: ＩＴ = {1-(V Ｓ ) ２} / [(1 / E ｒ )-{1-(V ｉ ) ２} / E ｉ ] (3) In formula (3), V Ｓ is the Poisson's ratio of the object 75. ｉ is the Poisson's ratio of the indenter 70. ｉ is the elastic modulus of the indenter 70.

[0107] 12 is a cross-sectional view showing an example of the conductive portion 32. The conductive portion 32 may include a seed layer 331 and a plating layer 332. The seed layer 331 is a conductive layer formed by physical film formation such as sputtering. The plating layer 332 is a conductive layer formed on the seed layer 331 by electrolytic plating.

[0108] The seed layer 331 may contain a metal material such as copper, nickel, titanium, chromium, or zinc. The seed layer 331 may also contain a compound of these metal materials. The seed layer 331 may include multiple layers. The plating layer 332 is, for example, a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc. The plating layer 332 may also be an alloy containing the above-mentioned metals.

[0109] The thickness T6 of the conductive portion 32 located on the outer surface of the insulating layer 31 is, for example, 0.1 μm or more, or may be 0.5 μm or more, or 1.0 μm or more. The thickness T6 is, for example, 30.0 μm or less, or may be 15.0 μm or less, or 10.0 μm or less, or may be 6.0 μm or less.

[0110] The second redistribution layer 40 will now be described.

[0111] The second redistribution layer 40 includes at least a low expansion portion 44. The low expansion portion 44 includes at least one of the insulating layers 41 included in the second redistribution layer 40. The insulating layer 41 that constitutes the low expansion portion 44 is also referred to as a low expansion layer 45, similar to the insulating layer 31 that constitutes the low expansion portion 34. In the example shown in FIG. 5 , the low expansion portion 44 includes two low expansion layers 45 stacked in the third direction D3.

[0112] The configuration and characteristics of the low expansion portion 44 and the low expansion layer 45 may be the same as the configuration and characteristics of the low expansion portion 34 and the low expansion layer 35. For example, the low expansion layer 45 may have a second thermal expansion coefficient C2 and a glass occupancy rate that satisfy the above-mentioned numerical ranges. For example, the low expansion portion 44 may have a second thickness T2 and a first elastic modulus E1 that satisfy the above-mentioned numerical ranges.

[0113] The second redistribution layer 40 may include an insulating layer 41 located between the core substrate 12 and the low expansion portion 44. The insulating layer 41 located between the core substrate 12 and the low expansion portion 44 is also referred to as a surface layer 46, similar to the surface layer 36 of the first redistribution layer 30.

[0114] The surface layer 46 may extend in the planar direction of the second surface 122 so as to straddle the core substrate 12 and the through electrode 20 in a planar view. In this case, the surface layer 46 overlaps the second boundary 202 in a planar view. The second boundary 202 is the boundary between the core substrate 12 and the through electrode 20 on the second surface 122. As in the case of the surface layer 36, providing the surface layer 46 makes it easier for moisture present around the through electrode 20 to be released to the outside of the wiring substrate 10. The moisture is released to the outside of the wiring substrate 10 through, for example, the second boundary 202 and the surface layer 46.

[0115] The configuration and characteristics of the surface layer 46 may be the same as the configuration and characteristics of the surface layer 36. For example, the surface layer 46 may have a third thickness T3 and a third thermal expansion coefficient C3 that satisfy the above-mentioned numerical ranges. For example, the surface layer 46 may include a through hole in which the above-mentioned through portion 421 is disposed. The through portion 421 located in the surface layer 46 may be connected to the through electrode 20. The through portion 421 located in the surface layer 46 may be connected to the through portion 421 located in the through hole of the low expansion layer 45.

[0116] The second redistribution layer 40 may include a low-elasticity portion 47 located on the low-expansion portion 44. The low-elasticity portion 47 may be located on the outer surface of the low-expansion portion 44. The low-elasticity portion 47 includes at least one of the multiple insulating layers 41 included in the second redistribution layer 40. The insulating layer 41 that constitutes the low-elasticity portion 47 is also referred to as a low-elasticity layer 48, similar to the insulating layer 31 that constitutes the low-elasticity portion 37. In the example shown in FIG. 5 , the low-elasticity portion 47 includes two low-elasticity layers 48 stacked in the third direction D3.

[0117] The configuration and characteristics of the low elasticity portion 47 and the low elasticity layer 48 may be the same as the configuration and characteristics of the low elasticity portion 37 and the low elasticity layer 38. For example, the low elasticity portion 47 may have a fourth thickness T4 and a second elastic modulus E2 that satisfy the above-mentioned numerical ranges. For example, the low elasticity layer 48 may have a filler occupancy rate and a glass occupancy rate that satisfy the above-mentioned numerical ranges.

[0118] The layer configuration of the second redistribution layer 40 may be the same as the layer configuration of the first redistribution layer 30. For example, the number of insulating layers 41 included in the second redistribution layer 40 may be the same as the number of insulating layers 31 included in the first redistribution layer 30. For example, the number of low-expansion layers 45 included in the low-expansion portion 44 of the second redistribution layer 40 may be the same as the number of low-expansion layers 35 included in the low-expansion portion 34 of the first redistribution layer 30. For example, the number of low-elasticity layers 48 included in the low-elasticity portion 47 of the second redistribution layer 40 may be the same as the number of low-expansion layers 45 included in the low-expansion portion 44 of the second redistribution layer 40. By having the layer configuration of the second redistribution layer 40 be the same as the layer configuration of the first redistribution layer 30, warping of the core substrate 12 can be suppressed.

[0119] 13 is a cross-sectional view showing an example of an application of the semiconductor package 60. The second redistribution layer 40 of the semiconductor package 60 may be disposed on a wiring substrate other than the wiring substrate 10, such as a motherboard 80. The motherboard 80 includes a substrate 81 and terminals 82. The pads 423 of the second redistribution layer 40 are electrically connected to the terminals 82 of the motherboard 80. Bumps 83 may be located between the terminals 82 of the motherboard 80 and the pads 423 of the second redistribution layer 40. The bumps 83 may include, for example, solder.

[0120] The substrate 81 of the motherboard 80 has a larger thermal expansion coefficient than the core substrate 12 and the low expansion portion 44 of the second redistribution layer 40. By positioning the low elasticity portion 47 between the low expansion portion 44 and the motherboard 80, it is possible to reduce stress caused by the difference between the amount of deformation of the motherboard 80 and the amount of deformation of the core substrate 12 and the low expansion portion 44. For example, it is possible to reduce stress applied to the bumps 83. As a result, it is possible to prevent defects such as deformation from occurring in the bumps 83.

[0121] (Method for Manufacturing Wiring Board) A method for manufacturing the wiring board 10 will be described.

[0122] A core substrate 12 including a core layer 13 is prepared. Next, a resist layer is provided on at least one of the first surface 121 or the second surface 122. Next, openings are provided in the resist layer at positions corresponding to the through holes 15. Next, the core substrate 12 is processed through the openings in the resist layer. As a result, as shown in FIG. 14 , a plurality of through holes 15 are formed in the core substrate 12. The through holes 15 include wall surfaces 16 extending from the first surface 121 to the second surface 122. The processing method for the core substrate 12 is, for example, a dry etching method, a wet etching method, or the like. The dry etching method is, for example, a reactive ion etching method, a deep reactive ion etching method, or the like.

[0123] Subsequently, a through electrode forming step is performed to form through electrodes 20 in the through holes 15. The through electrode forming step includes a seed layer forming step and a plating layer forming step.

[0124] In the seed layer forming step, a seed layer 331 is formed on the wall surface 16 of the core substrate 12. For example, the seed layer is formed by sputtering. The seed layer may also be formed on the first surface 121 and the second surface 122.

[0125] The plating layer forming step may include a resist layer forming step, a plating step, and a resist layer removing step. In the resist layer forming step, a first resist layer is formed at least partially on the seed layer located on the first surface 121, and a second resist layer is formed partially on the seed layer located on the second surface 122. The first resist layer and the second resist layer are provided so as to cover areas of the seed layer where the plating layer is not to be formed.

[0126] In the plating process, a plating layer is formed on the seed layer by electrolytic plating. For example, the core substrate 12 on which the seed layer and the resist layer are formed may be immersed in an electrolytic plating solution. A current is passed through the seed layer, causing the plating layer to deposit on the seed layer.

[0127] In the seed layer removal step, the seed layer that overlaps the first resist layer and the second resist layer in a plan view is removed. In this manner, the through electrode 20 including the seed layer and the plating layer is obtained, as shown in Fig. 15. As shown in Fig. 15, the seed layer and the plating layer do not need to remain on the first surface 121 and the second surface 122.

[0128] Subsequently, a step of forming a first redistribution layer 30 on the first surface 121 of the core substrate 12 and a step of forming a second redistribution layer 40 on the second surface 122 of the core substrate 12 are performed.

[0129] For example, as shown in FIG. 16, a surface layer forming step is carried out in which a surface layer 36 is formed on a first surface 121 and a surface layer 46 is formed on a second surface 122 .

[0130] The surface layer forming process includes, for example, a coating process of coating the first surface 121 and the second surface 122 with a solution containing a resin that constitutes the surface layer and a solvent, and a drying process of evaporating the solvent after the coating process. Examples of the solvent include propylene glycol monomethyl ether, 2-methoxy-1-methylethyl acetate, N-methyl-2-pyrrolidone, γ-butyrolactone, ethyl lactate, and toluene. The drying process includes, for example, a step of heating the core substrate 12.

[0131] The surface layer forming step may include, instead of the coating step, a step of attaching a film including a resin layer that constitutes the surface layer to the first surface 121 and the second surface 122 .

[0132] 17 , a step of forming a plurality of openings 363, 463 in the surface layers 36, 46 is performed. If the material of the surface layers 36, 46 is photosensitive, the plurality of openings 363, 463 may be formed in the surface layers 36, 46 by an exposure step and a development step.

[0133] 18 , a step of forming the conductive portions 32, 42 on the outer surfaces 362, 462 and the openings 363, 463 of the surface layers 36, 46 is carried out. The step of forming the conductive portions 32, 42 may include a seed layer formation step and a plating layer formation step, similar to the through electrode formation step described above.

[0134] Subsequently, a low expansion portion forming step is carried out in which the low expansion portion 34 is formed on the outer surface of the surface layer 36 and the low expansion portion 44 is formed on the outer surface of the surface layer 46 .

[0135] The low-expansion portion forming step includes a step of forming a low-expansion layer 35 on the outer surface of the surface layer 36. As shown in Fig. 19 , a metal foil 91 may be located on the outer surface of the low-expansion layer 35. For example, a bonding step may be performed in which a laminate 90 including the low-expansion layer 35 and the metal foil 91 is bonded to the outer surface of the surface layer 36. The metal foil 91 is, for example, copper foil.

[0136] In the attaching step, for example, the laminate 90 may be pressed against the surface layer 36 while being heated. For example, the pressure between the surface layer 36 and the laminate 90 may be made lower than the pressure around the outer surface of the laminate 90, thereby pressing the laminate 90 against the surface layer 36. Because the laminate 90 includes the metal foil 91, adhesion of the material of the low expansion layer 35 to a member in contact with the outer surface of the laminate 90 in the attaching step is suppressed.

[0137] The low-expansion portion forming step includes a step of forming a low-expansion layer 45 on the outer surface of the surface layer 46. As in the case of the low-expansion layer 35, a metal foil 96 may be located on the outer surface of the low-expansion layer 45. For example, an attachment step may be performed in which a laminate 95 including the low-expansion layer 45 and the metal foil 96 is attached to the outer surface of the surface layer 46. The metal foil 96 is, for example, copper foil.

[0138] After the low expansion layers 35, 45 are attached to the outer surfaces of the surface layers 36, 46, the metal foils 91, 96 may be removed. For example, a wet etching process may be performed to remove the metal foils 91, 96.

[0139] 20 , a step of forming a plurality of openings 353, 453 in the low-expansion layers 35, 45 is performed. For example, the plurality of openings 353, 453 may be formed in the low-expansion layers 35, 45 by processing the low-expansion layers 35, 45 using a laser.

[0140] 21 , a step of forming conductive portions 32, 42 on the outer surfaces 352, 452 and openings 353, 453 of the low-expansion layers 35, 45 is performed. The step of forming conductive portions 32, 42 may include a seed layer formation step and a plating layer formation step, similar to the through-electrode formation step described above. In this manner, the first low-expansion layers 35, 45 and conductive portions 32 are formed.

[0141] 22 , second low-expansion layers 35, 45 and conductive portion 32 are formed on the first low-expansion layers 35, 45 and conductive portion 32. The method for forming the second low-expansion layers 35, 45 and conductive portion 32 may be the same as the method for forming the first low-expansion layers 35, 45 and conductive portion 32.

[0142] Subsequently, a low elasticity portion forming step is carried out in which the low elasticity portion 37 is formed on the outer surface of the low expansion portion 34 and the low elasticity portion 47 is formed on the outer surface of the low expansion layer 45 .

[0143] 23 , the low-elasticity portion forming step includes a step of forming a low-elasticity layer 38 on the outer surface of the low-expansion portion 34. The step of forming the low-elasticity layer 38 includes, for example, a coating step of coating the outer surface of the low-expansion portion 34 with a solution containing a resin and a solvent that constitutes the low-elasticity layer 38, and a drying step of evaporating the solvent after the coating step. Instead of the coating step, the step of forming the low-elasticity layer 38 may include a step of attaching a film containing a layer of resin that forms the low-elasticity layer 38 to the outer surface of the low-expansion portion 34.

[0144] 23 , the low-elasticity portion forming step includes a step of forming a low-elasticity layer 48 on the outer surface of the low-expansion portion 44. The step of forming the low-elasticity layer 48 may include a coating step and a drying step, similar to the step of forming the low-elasticity layer 38. The step of forming the low-elasticity layer 48 may include a step of attaching a film including a layer of resin that forms the low-elasticity layer 48 to the outer surface of the low-expansion portion 44, instead of the coating step.

[0145] Subsequently, a step of forming a plurality of openings 383, 483 in the low elastic layers 38, 48 is performed. If the material of the low elastic layers 38, 48 is photosensitive, the plurality of openings 383, 483 may be formed in the low elastic layers 38, 48 by an exposure step and a development step.

[0146] 24 , a step of forming conductive portions 32, 42 on the outer surfaces 382, ​​482 and openings 383, 483 of the low-elasticity layers 38, 48 is performed. The step of forming conductive portions 32, 42 may include a seed layer formation step and a plating layer formation step, similar to the through electrode formation step described above. In this manner, the first low-elasticity layers 38, 48 and conductive portions 32 are formed.

[0147] 25, second low-elasticity layers 38, 48 and conductive portion 32 are formed on the first low-elasticity layers 38, 48 and conductive portion 32. The method for forming the second low-elasticity layers 38, 48 and conductive portion 32 may be the same as the method for forming the first low-elasticity layers 38, 48 and conductive portion 32. In this manner, the wiring substrate 10 shown in FIG.

[0148] The first redistribution layer 30 of the wiring substrate 10 of this embodiment includes a low expansion portion 34. The low expansion portion 34 can reduce the difference in thermal expansion coefficient between the semiconductor element 50 and the first redistribution layer 30. Reducing the difference in thermal expansion coefficient can reduce thermal stress occurring between the semiconductor element 50 and the first redistribution layer 30. This can prevent defects such as deformation from occurring in the bumps 83.

[0149] The low elasticity portion 37 of the first redistribution layer 30 can reduce stress caused by the difference between the amount of deformation of the semiconductor element 50 and the amount of deformation of the low expansion portion 34. This also makes it possible to prevent defects such as deformation from occurring in the bumps 83.

[0150] The second redistribution layer 40 of the wiring substrate 10 of this embodiment includes a low expansion portion 44. Because the first redistribution layer 30 and the second redistribution layer 40 include the low expansion portion 34 and the low expansion portion 44, respectively, the difference in thermal expansion coefficient between the first redistribution layer 30 and the second redistribution layer 40 can be reduced. This reduces the difference between the thermal stress generated between the core substrate 12 and the first redistribution layer 30 and the thermal stress generated between the core substrate 12 and the second redistribution layer 40. Reducing the difference in thermal stress can suppress deformation such as warping of the semiconductor package 60.

[0151] The low elasticity portion 47 of the second redistribution layer 40 can reduce stress caused by the difference between the amount of deformation of the substrate 81 of the motherboard 80 and the amount of deformation of the core substrate 12 and the low expansion portion 44. This can prevent defects such as deformation from occurring in the bumps 83.

[0152] According to this embodiment, deformation and stress caused by temperature changes can be reduced, and the reliability of the wiring substrate 10 and the semiconductor package 60 can be improved.

[0153] The above-described embodiment can be modified in various ways. Below, modified examples will be described with reference to the drawings as necessary. In the following description and the drawings used in the following description, parts that can be configured similarly to the above-described embodiment will be designated by the same reference numerals as those used for corresponding parts in the above-described embodiment. Duplicate descriptions will be omitted. Furthermore, if it is clear that the effects obtained in the above-described embodiment can also be obtained in modified examples, the description of those effects may be omitted.

[0154] (First Modification) In the above-described embodiment, an example has been shown in which the through electrode 20 is located over the entire area of ​​the through hole 15. In the first modification, an example in which the through electrode 20 is located partially in the through hole 15 will be described.

[0155] 26 is a cross-sectional view showing a wiring substrate 10 according to a first modification. The through electrode 20 extends along the wall surface 16 of the through hole 15 from the first surface 121 to the second surface 122. Resin 25 may be located in the center of the through hole 15 in a plan view.

[0156] The resin 25 is preferably an insulating resin. Examples of insulating resins include polyimide, polyamide, polyamideimide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyether ether ketone, polyether sulfone, polycarbonate, polyetherimide, epoxy resin, phenol resin, polyphenylene ether, acrylic resin, polyolefin, polycycloolefin, and liquid crystal polymer compound. Examples of polyolefins include polyethylene and polypropylene. Examples of polycycloolefins include polynorbornene.

[0157] A method for manufacturing the wiring substrate 10 shown in FIG. 26 will now be described.

[0158] As in the case of the above-described embodiment, after the core substrate 12 is prepared, a plurality of through holes 15 are formed in the core substrate 12. Subsequently, as shown in Fig. 27, a through electrode forming step is carried out to form through electrodes 20 in the through holes 15. The through electrode forming step is carried out so that the through electrodes 20 are not located in the center of the through holes 15 in a plan view.

[0159] 28 , a step of forming resin 25 in the center of through hole 15 is performed. Surface layer 36 and surface layer 46 may be formed simultaneously with resin 25. Resin 25 may be formed, for example, by pushing a portion of surface layer 36 and a portion of surface layer 46 into through hole 15.

[0160] Next, as in the case of the above-described embodiment, a process is performed to form the low expansion portions 34 and 44. Next, as in the case of the above-described embodiment, a process is performed to form the low elasticity portions 37 and 47. In this manner, the wiring substrate 10 shown in FIG. 26 is manufactured.

[0161] 29 is a cross-sectional view showing a wiring board 10 according to a second modified example. The core substrate 12 may include a core layer 13, a first core surface layer 141, and a second core surface layer 142. The first core surface layer 141 is located between the core layer 13 and the first surface 121. The first core surface layer 141 may constitute the first surface 121. The second core surface layer 142 is located between the core layer 13 and the second surface 122. The second core surface layer 142 may constitute the second surface 122.

[0162] Like the low expansion layer 35 described above, the first core surface layer 141 and the second core surface layer 142 include fibrous members and a resin impregnated in the fibrous members. The fibrous members are members made of glass fibers. For example, the fibrous members include a plurality of first fibrous members extending in a first direction D1 and a plurality of second fibrous members contacting the first fibrous members and extending in a second direction D2. The plurality of first fibrous members and the plurality of second fibrous members may be woven together. The resin may include an organic material. Examples of the resin include epoxy resin and bismaleimide triazine resin.

[0163] The thickness of the first core surface layer 141 and the second core surface layer 142 is, for example, 20 μm or more, or may be 25 μm or more, or 30 μm or more. The thickness of the first core surface layer 141 and the second core surface layer 142 is, for example, 50 μm or less, or may be 45 μm or less, or may be 40 μm or less.

[0164] The first core surface layer 141 and the second core surface layer 142 have low thermal expansion coefficients, similar to the above-described low expansion layer 35. The numerical range of the thermal expansion coefficients of the first core surface layer 141 and the second core surface layer 142 may be the same as the numerical range of the second thermal expansion coefficient C2 of the above-described low expansion layer 35.

[0165] The first core surface layer 141 and the second core surface layer 142 may have a glass occupancy ratio of 0.30 or more, similar to the above-described low expansion layer 35. The glass occupancy ratio of the first core surface layer 141 and the second core surface layer 142 may be 0.35 or more, or 0.40 or more. The glass occupancy ratio of the first core surface layer 141 and the second core surface layer 142 is, for example, 0.80 or less, 0.70 or less, or 0.60 or less.

[0166] A method for manufacturing the wiring substrate 10 shown in FIG. 29 will now be described.

[0167] 30 , a core substrate 12 is prepared, which includes a core layer 13, a first core surface layer 141, and a second core surface layer 142, and has a plurality of through holes 15 formed therein. The first core surface layer 141 and the second core surface layer 142 may be formed on the surface of the core layer 13 after the plurality of through holes 15 are formed in the core layer 13. Alternatively, the first core surface layer 141 and the second core surface layer 142 may be formed on the surface of the core layer 13 before the plurality of through holes 15 are formed in the core layer 13.

[0168] 31 , a through electrode forming step is performed to form a through electrode 20 in the through hole 15. The through electrode forming step may be performed so that the through electrode 20 is located over the entire area of ​​the through hole 15. The through electrode forming step may be performed so that the through electrode 20 is not located in the center of the through hole 15 in a plan view. If the through electrode 20 is not located in the center of the through hole 15 in a plan view, a step of forming a resin in the center of the through hole 15 may be performed.

[0169] Next, as in the case of the above-described embodiment, a process of forming the low expansion portions 34 and 44 is performed. Next, as in the case of the above-described embodiment, a process of forming the low elasticity portions 37 and 47 is performed. A process of forming the surface layers 36 and 46 may be performed before the process of forming the low expansion portions 34 and 44. In this manner, the wiring substrate 10 shown in FIG. 29 is manufactured.

[0170] In this modification, before the plurality of through electrodes 20 are formed in the through holes 15, a first core surface layer 141 and a second core surface layer 142 are formed on the surface of the core layer 13. The first core surface layer 141 and the second core surface layer 142 can increase the toughness of the core substrate 12. This can, for example, prevent the core substrate 12 from being damaged, such as by cracks.

[0171] (Third Modification) In the above-described embodiment, an example has been shown in which the metal foil 91 is removed after the low-expansion layer 35 is formed using the laminate 90. Although not shown, the entire metal foil 91 does not have to be removed. For example, a portion of the metal foil 91 may remain and be used as the conductive portion 32. Similarly, after the low-expansion layer 45 is formed, a portion of 96 may remain and be used as the conductive portion 42.

[0172] 33 , the wiring substrate 10 does not necessarily have to include the surface layer 36. In this case, the low expansion portion 34 may be in contact with the first surface 121 of the core substrate 12.

[0173] 33 , the wiring board 10 does not have to include the surface layer 46. In this case, the low expansion portion 44 may be in contact with the second surface 122 of the core substrate 12.

[0174] 32 is a diagram showing an example of a product on which the wiring substrate 10 or the semiconductor package 60 is mounted. The wiring substrate 10 or the semiconductor package 60 can be used in a variety of products. For example, the wiring substrate 10 or the semiconductor package 60 is mounted in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, etc.

[0175] Although several modifications to the above-described embodiment have been described, it is of course possible to combine a plurality of modifications as appropriate and apply them to the above-described embodiment.

[0176] Next, the embodiments of the present disclosure will be described more specifically with reference to examples. However, the embodiments of the present disclosure are not limited to the description of the following examples as long as they do not depart from the gist of the present disclosure.

[0177] Example A The wiring substrate 10 shown in FIG. 1 was produced by the following procedure.

[0178] [Step 1] A non-alkali glass plate having a thickness of 1100 μm was prepared as the core layer 13. Subsequently, a plurality of through holes 15 were formed in the substrate 13.

[0179] [Step 2] Next, a seed layer 331 was formed by sputtering. Next, a plating layer 332 was formed on the seed layer 331 located in the through hole 15 by electrolytic plating. Next, the components on the first surface 121 and the second surface 122 of the substrate 12 were processed by chemical mechanical polishing. As a result, a through electrode 20 located in the through hole 15 was obtained.

[0180] [Step 3] Next, a solution containing a polyimide-based resin material was applied to the first surface 121 and the second surface 122. The polyimide-based resin material was subjected to a drying step, a pattern exposure step, a development step, and a heat curing step. As a result, the surface layer 36 and the surface layer 46 were obtained. The thermal expansion coefficients of the surface layer 36 and the surface layer 46 were 60 ppm / K.

[0181] [Step 4] Then, a first redistribution layer 30 was formed on the surface layer 36, and a second redistribution layer 40 was formed on the surface layer 46. The first redistribution layer 30 and the second redistribution layer 40 each included ten stacked insulating layers 31 and ten stacked insulating layers 41. Two of the ten insulating layers 31 were located on the surface layer 36 and were low-expansion layers 35 that constituted the low-expansion portion 34. Two of the ten insulating layers 41 were located on the surface layer 46 and were low-expansion layers 45 that constituted the low-expansion portion 44. The low-expansion layers 35 and 45 each included a fiber member made of glass fiber and a resin impregnated into the fiber member. The thermal expansion coefficients of the low-expansion layers 35 and 45 were within the range of 4 ppm / K to 10 ppm / K.

[0182] The produced wiring substrate 10 was cut into individual pieces using a blade dicer to prepare evaluation samples. The shape of the evaluation samples in plan view was a square with one side measuring 50 mm.

[0183] Example B An evaluation sample was prepared in the same manner as in Example A, except that the surface layer 36 and the surface layer 46 were not formed. The wiring board 10 of Example B is shown in FIG.

[0184] (Example C) An evaluation sample was prepared in the same manner as in Example A, except that the surface layer 36 and the surface layer 46 were not formed, and the thermal expansion coefficients of the low expansion layers 35 and 45 were 4 ppm / K.

[0185] (Example D) An evaluation sample was prepared in the same manner as in Example A, except that none of the ten insulating layers 31 and the ten insulating layers 41 was a low-expansion layer containing a fiber member made of glass fiber. The wiring board 100 of Example D is shown in FIG.

[0186] (Evaluation) A temperature cycle test was performed on evaluation samples of Examples A to D obtained by cutting the wiring substrate 10 into individual pieces. After the temperature cycle test, the state of each evaluation sample was checked based on the criteria of Evaluations 1 and 2 described below.

[0187] In the temperature cycle test, first, a pretreatment was carried out in accordance with JEDEC (JESD22A113) standard MSL level 3. Then, 1000 cycles of temperature cycle test condition B (-55°C or higher and 125°C or lower) described in JEDEC standard (JESD22-A104) were carried out.

[0188] [Evaluation 1] The core layer 13 of the core substrate 12 was evaluated for defects. The results of Evaluation 1 are shown in the "Evaluation 1" column in Table 1, which will be described later. "Rank 1" means that no defects such as cracks occurred in the core layer 13 throughout the series of processes. "Rank 2" means that defects such as cracks occurred in the core layer 13 after the wiring substrate 10 was cut into individual pieces or after a temperature cycle test. "Rank 3" means that, among other defects, cracks in particular occurred in the core layer 13.

[0189] [Evaluation 2] It was confirmed whether deformation such as swelling occurred in the wiring layer of the first redistribution layer 30 or the second redistribution layer 40. The results of Evaluation 2 are shown in the "Evaluation 2" column of Table 1, which will be described later. "Rank 1" means that no deformation such as swelling occurred in the wiring layer of the first redistribution layer 30 or the second redistribution layer 40 throughout the series of processes. "Rank 2" means that deformation such as swelling occurred in the wiring layer of the first redistribution layer 30 or the second redistribution layer 40. "Rank 3" means that peeling occurred in the wiring layer of the first redistribution layer 30 or the second redistribution layer 40.

[0190]

[0191] In Example A, both Evaluation 1 and Evaluation 2 were ranked 1. On the other hand, in Examples B and C, Evaluation 1 was ranked 1, but Evaluation 2 was ranked 2. It can be seen that, as in Example A, the first redistribution layer 30 includes a low expansion portion 34, and the surface layer 36 is disposed between the low expansion portion 34 and the core substrate 12, which can suppress deformation of the first redistribution layer 30. Similarly, as in Example A, it can be seen that the second redistribution layer 40 includes a low expansion portion 44, and the surface layer 46 is disposed between the low expansion portion 44 and the core substrate 12, which can suppress deformation of the second redistribution layer 40.

[0192] 34 , cracks 19 occurred in the core layer 13. The cracks 19 are cracks that spread from the side surfaces of the core layer 13 along the surface direction of the substrate 12. It can be seen that the inclusion of the low expansion portions 34 in the first redistribution layer 30 or the inclusion of the low expansion portions 44 in the second redistribution layer 40 can suppress cracks in the core layer 13.

[0193] REFERENCE SIGNS LIST 10 Wiring substrate 12 Core substrate 121 First surface 122 Second surface 13 Core layer 141 First core surface layer 142 Second core surface layer 15 Through hole 16 Wall surface 20 Through electrode 25 Resin 30 First rewiring layer 31 Insulating layer 32 Conductive portion 34 Low expansion portion 35 Low expansion layer 35a Fibre member 35b First fibre member 35c Second fibre member 35d Resin 36 Surface layer 37 Low elasticity portion 38 Low elasticity layer 38a Resin 38b Filler 40 Second rewiring layer 41 Insulating layer 42 Conductive portion 44 Low expansion portion 45 Low expansion layer 46 Surface layer 47 Low elasticity portion 48 Low elasticity layer 50 Semiconductor element 51 Logic IC 52 Memory IC 53 Bump 60 Semiconductor package 80 Motherboard

Claims

1. A wiring board comprising: a core substrate having a core layer made of glass, the core substrate including a first surface, a second surface opposite the first surface, and a plurality of through holes penetrating from the first surface to the second surface; a plurality of through electrodes located in each of the plurality of through holes; a first rewiring layer located on the first surface; and a second rewiring layer located on the second surface, wherein the first rewiring layer and the second rewiring layer each comprise a plurality of insulating layers stacked in the thickness direction, and a conductive portion including a through portion penetrating the insulating layer and a wiring or pad located on the surface of the insulating layer, wherein the first rewiring layer and the second rewiring layer each comprise a low expansion portion including at least one insulating layer of the plurality of insulating layers, and wherein the insulating layer of the low expansion portion of the first rewiring layer and the insulating layer of the low expansion portion of the second rewiring layer each comprise a fiber member made of glass fiber and a resin impregnated in the fiber member.

2. The wiring board described in claim 1, wherein the core layer has a first thermal expansion coefficient C1 at 25°C, and the insulating layer of the low expansion portion of the first redistribution layer and the insulating layer of the low expansion portion of the second redistribution layer both have a second thermal expansion coefficient C2 at 25°C, and the following relationship holds: 0.80×C1≦C2≦1.20×C1.

3. The wiring board according to claim 2, wherein the first thermal expansion coefficient C1 is 7.0 ppm / K or more and 9.0 ppm / K or less.

4. A wiring board according to any one of claims 1 to 3, wherein the insulating layer in the low expansion portion of the first redistribution layer and the insulating layer in the low expansion portion of the second redistribution layer both have a glass occupancy rate of 0.40 or more, and the glass occupancy rate is the ratio of the cross-sectional area of ​​the glass fiber to the cross-sectional area of ​​the insulating layer in the low expansion portion.

5. A wiring board described in any one of claims 1 to 3, wherein the insulating layer of the low expansion portion of the first rewiring layer and the insulating layer of the low expansion portion of the second rewiring layer both contain epoxy resin impregnated in the fiber material.

6. The wiring board according to any one of claims 1 to 3, wherein the core layer has a first thickness T1, the low expansion portion of the first redistribution layer and the low expansion portion of the second redistribution layer both have a second thickness T2, and the following relational expression is established: 0.10 x T1 ≦ T2 ≦ 0.50 x T1.

7. A wiring board according to any one of claims 1 to 3, wherein the number of insulating layers included in the low expansion portion of the first redistribution layer is equal to the number of insulating layers included in the low expansion portion of the second redistribution layer.

8. A wiring board according to any one of claims 1 to 3, wherein the first redistribution layer and the second redistribution layer each have a surface layer that is an insulating layer located between the low expansion portion and the core substrate, and the surface layer of the first redistribution layer and the surface layer of the second redistribution layer each are made of resin.

9. The wiring board according to claim 8, wherein the surface layer of the first redistribution layer and the surface layer of the second redistribution layer both have a third thermal expansion coefficient C3 at 25°C, and the third thermal expansion coefficient C3 is not less than 40.0 ppm / K and not more than 60.0 ppm / K.

10. The wiring board according to claim 8, wherein the core layer has a first thickness T1, the surface layer of the first redistribution layer and the surface layer of the second redistribution layer both have a third thickness T3, and the following relationship holds: 0.10×T2≦T3≦0.50×T2.

11. The wiring board according to any one of claims 1 to 3, wherein the first redistribution layer and the second redistribution layer are both located on the low expansion portion and have a low elasticity portion including at least one of the plurality of insulating layers, and the insulating layer of the low elasticity portion of the first redistribution layer and the insulating layer of the low elasticity portion of the second redistribution layer both have a modulus of elasticity lower than the modulus of elasticity of the insulating layer of the low expansion portion.

12. The wiring board described in claim 11, wherein the insulating layer of the low elasticity section of the first redistribution layer and the insulating layer of the low elasticity section of the second redistribution layer both contain a resin and a plurality of fillers dispersed in the resin.

13. The wiring board according to claim 11, wherein the elastic modulus of the insulating layer in the low expansion portion is 20.0 GPa or more and 40.0 GPa or less, and the elastic modulus of the insulating layer in the low elasticity portion is 1.0 GPa or more and 20.0 GPa or less.

14. The wiring board described in claim 11, wherein the low expansion portion of the first redistribution layer and the low expansion portion of the second redistribution layer both have a second thickness T2, and the low elasticity portion of the first redistribution layer and the low elasticity portion of the second redistribution layer both have a fourth thickness T4, and the following relationship holds: T4<T2.

15. A wiring board according to any one of claims 1 to 3, wherein the core substrate comprises a first core surface layer located between the core layer and the first surface, and a second core surface layer located between the core layer and the second surface, and both the first core surface layer and the second core surface layer include a fiber member made of glass fiber and a resin impregnated into the fiber member.

16. A semiconductor package comprising: a wiring board according to any one of claims 1 to 3; and at least one semiconductor element disposed on the outer surface of the first rewiring layer of the wiring board.

17. The semiconductor package of claim 16, wherein the at least one semiconductor device includes at least one logic IC and at least one memory IC.

18. A method for manufacturing a wiring board, comprising the steps of: preparing a core substrate having a core layer including a first surface, a second surface opposite the first surface, and a plurality of through holes penetrating from the first surface to the second surface, the core layer including glass; forming through electrodes in each of the plurality of through holes; forming a first rewiring layer on the first surface; and forming a second rewiring layer on the second surface, wherein each of the first rewiring layer and the second rewiring layer comprises a plurality of insulating layers stacked in the thickness direction, and a conductive portion including a through portion penetrating the insulating layer and a wiring or pad located on the surface of the insulating layer, each of the first rewiring layer and the second rewiring layer comprises a low expansion portion including at least one insulating layer of the plurality of insulating layers, and the insulating layer of the low expansion portion of the first rewiring layer and the insulating layer of the low expansion portion of the second rewiring layer both comprise a fiber member made of glass fiber and a resin impregnated in the fiber member.

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