Voltage controlled oscillator based on multiple cores

Abstract

The present invention provides a voltage controlled oscillator based on multiple cores A voltage controlled oscillator based on multiple cores, according to the present invention, comprises: a noise circulation oscillation circuit; a common tail inductor which connects a first voltage controlled oscillation core circuit including the noise circulation oscillation circuit, with a second voltage controlled oscillation core circuit including the noise circulation oscillation circuit, and is used as a noise filter and a virtual ground; two or more degenerate transistors provided as a part of the noise circulation oscillation circuit to provide a noise circulation function in a biased state in a triode region; and two or more control capacitors corresponding to the two or more degenerate transistors, respectively, to control the two or more degenerate transistors in an on or off state.

Description

Multi-core based voltage-controlled oscillator

[0001] The present invention relates to a multi-core based voltage-controlled oscillator, and more particularly, to a multi-core based voltage-controlled oscillator capable of low noise and low power.

[0002] Typically, the voltage-controlled oscillator (VCO), the fundamental component of a frequency synthesizer or phase-locked loop (PLL), directly affects key performance characteristics such as phase noise, frequency tuning range, sensitivity to supply voltage variations, robustness to startup conditions, and power consumption.

[0003] These measurements are interdependent, and optimizing overall performance, especially at millimeter-wave frequencies, is considered a challenging problem. Specifically, achieving low phase noise (PN) and wide tuning range (or VCO gain) involves significant tradeoffs in the millimeter-wave (or sub-millimeter-wave) frequency range.

[0004] Figure 1 a) Drawing shows a tail current source (M) to set the bias current and provide high impedance to the cross-coupled transistor. tail ) is a conventional cross-coupled voltage-controlled oscillator using the aforementioned tail current source (M tail ) causes a problem of increasing the overall phase noise due to the flicker noise upconversion phenomenon.

[0005] Accordingly, several attempts have been made to improve phase noise, one of which, the noise-loop topology illustrated in Fig. 1b), reduces the effective noise factor by half compared to the conventional cross-coupled oscillator topology. However, the noise-loop topology has the limitation of causing significant phase noise differences across the tuning range due to the AM-PM conversion of the low-frequency noise source.

[0006] Another approach is to connect two oscillators to a common tail inductor (L), as shown in Fig. 1c). tail ) as a method of connecting two oscillators, it has the advantage of reducing phase noise by 3 dB and enabling phase noise that is relatively less sensitive to the tuning range.

[0007] In addition, despite the advantages described above, method c) of Fig. 1 is 1 / f 3 The problem is that the phase noise in the domain is actually getting worse.

[0008] Therefore, there is a need to provide a voltage-controlled oscillator that can improve the overall performance (including noise performance, oscillation range, and flicker noise improvement) of the voltage-controlled oscillator, rather than just improving some of the performance of the voltage-controlled oscillator, by improving all of the problems of the conventional voltage-controlled oscillator mentioned above.

[0009] Accordingly, the present invention was created to solve the above problems, and the purpose of the present invention is to provide a multi-core based voltage controlled oscillator capable of improving low noise, including phase noise performance and flicker noise performance, and expanding the available power generation range and increasing low power efficiency.

[0010] The purpose of the invention is not limited to the purposes mentioned above, and other purposes not mentioned will be clearly understood by those skilled in the art from the description below.

[0011] According to an aspect of the present invention for achieving the above object, a multi-core based voltage-controlled oscillator comprises a noise-cycling oscillator circuit, a first voltage-controlled oscillator core circuit including the noise-cycling oscillator circuit, and a second voltage-controlled oscillator core circuit, and includes a common tail inductor used as a noise filter and a virtual ground, two or more degenerate transistors provided as part of the noise-cycling oscillator circuit and providing a noise-cycling function in a state biased in a triode region, and two or more controllable capacitors corresponding to the two or more degenerate transistors and controlling them to be in an on or off state, respectively.

[0012] The above two or more degenerate transistors may be PMOS (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistors.

[0013] The above two or more degenerate transistors can be connected to the common tail inductor through the drain portion.

[0014] It may further include an NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistor corresponding to each of the above two or more degenerate transistors.

[0015] Each of the two or more controllable capacitors can control on or off a set of PMOS (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistors and NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistors together.

[0016] The above second voltage control oscillator core circuit may include a PMOS cross-coupled circuit.

[0017] The first voltage-controlled oscillator core circuit and the second voltage-controlled oscillator core circuit each include a resonance tank, and two synchronization capacitors for connection and synchronization between the resonance tanks may be further included in the second voltage-controlled oscillator core circuit.

[0018] It may further include a 4-bit capacitor bank to expand and adjust the tuning range.

[0019] The bias state for the above two or more degenerate transistors can be maintained until the impulse sensitivity function (ISF) moves orthogonal to the output voltage.

[0020] Accordingly, the present invention provides a multi-core based voltage controlled oscillator capable of improving low noise, including phase noise performance and flicker noise performance, and expanding the available power generation range and increasing low power efficiency, thereby not only securing a wide tuning range while improving low phase noise and flicker noise performance even at millimeter wave frequencies, but also having the advantage of improving low power efficiency.

[0021] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

[0022] Fig. 1 is an exemplary diagram showing a voltage-controlled oscillator according to the prior art.

[0023] FIG. 2 is a schematic diagram of a multi-core based voltage controlled oscillator according to one embodiment of the present invention.

[0024] Fig. 3 is an exemplary diagram showing an example of a circuit configuration for the voltage-controlled oscillator of Fig. 2.

[0025] Figure 4 is a graph showing simulation noise for comparison with the low-noise function of the voltage-controlled oscillator of Figure 1.

[0026] Fig. 5 is a graph showing the simulation noise results of the present invention compared with Fig. 4.

[0027] Fig. 6 is a graph showing simulation results related to the operation of the transistor included in the voltage-controlled oscillator of Fig. 1.

[0028] Fig. 7 is a circuit diagram showing the equivalent output noise current for the voltage-controlled oscillator of Fig. 3.

[0029] FIG. 8 is a block diagram showing that the voltage-controlled oscillator of FIG. 1 further includes a 4-bit capacitor bank.

[0030] Figure 9 is a chip micrograph of a prototype circuit for the voltage controlled oscillator of Figure 1.

[0031] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided only to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Like reference numerals designate like elements throughout the specification.

[0032] Furthermore, the embodiments described herein will be described with reference to cross-sectional and / or schematic drawings, which are ideal illustrations of the present invention. Therefore, the form of the illustrations may be modified due to manufacturing techniques and / or tolerances. Furthermore, in each drawing illustrated in the present invention, each component may be depicted somewhat enlarged or reduced for convenience of explanation.

[0033] The multi-core based voltage controlled oscillator of the present invention is configured to enable low noise improvement including phase noise performance and flicker noise performance, and to enable expansion of the available power generation range and increase in low power efficiency.

[0034] FIG. 2 is a schematic diagram of a multi-core based voltage controlled oscillator according to one embodiment of the present invention.

[0035] As illustrated in FIG. 2, a multi-core based voltage-controlled oscillator (100) connects a noise-cycling oscillator circuit (A), a first voltage-controlled oscillator core circuit (110) including the noise-cycling oscillator circuit (A) and a second voltage-controlled oscillator core circuit (120), and includes a common tail inductor (130) used as a noise filter and a virtual ground, two or more degenerate transistors (111, 112) provided as part of the noise-cycling oscillator circuit (A) and providing a noise-cycling function in a biased state in a triode region, and two or more controllable capacitors (113, 114) corresponding to the two or more degenerate transistors (111, 112) and controlling them to be on or off, respectively.

[0036] Here, two or more degenerate transistors (111, 112) may be provided as PMOS (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistors, and may be connected to a common tail inductor (130) through the drain portion of each degenerate transistor.

[0037] The second voltage-controlled oscillator core circuit (120) may include a PMOS cross-coupled circuit (B), and may include a resonant tank (Inductor-Capacitor Circuit) in each of the first voltage-controlled oscillator core circuit (110) and the second voltage-controlled oscillator core circuit (120). For this purpose, the second voltage-controlled oscillator core circuit (120) may include synchronization capacitors (121, 122) for connection and synchronization between the aforementioned resonant tanks.

[0038] Fig. 3 is an exemplary diagram showing an example of a circuit configuration for the voltage-controlled oscillator of Fig. 2.

[0039] As illustrated in FIG. 3, the two or more degenerate transistors (111, 112) described above may be provided as PMOS (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistors and may be connected to a common tail inductor (130) through a drain portion.

[0040] In addition, the noise cyclic oscillator circuit (A) may be configured as a circuit further including an NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistor corresponding to each of the two or more degenerate transistors (111, 112).

[0041] Accordingly, it is preferable that each of the two or more control capacitors (113, 114) described above control on or off a set of PMOS (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistors and NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistors together.

[0042] That is, the circuit diagram of the voltage-controlled oscillator illustrated in FIG. 3 is a circuit configuration related to current reuse, in which a first voltage-controlled oscillator core circuit (110) including a noise-circulating oscillator circuit (A) is stacked on the upper side of a second voltage-controlled oscillator core circuit (120) including a PMOS cross-coupled circuit (B), and M1, which is an NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistor, and M3, which is a PMOS (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistor, are simultaneously turned on and off by control capacitors C1 and C2, which are to ensure smooth noise circulation.

[0043] Similarly, M2, an NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistor, and M4, a PMOS (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistor, are turned on and off simultaneously by control capacitors C1 and C2.

[0044] Control capacitors C1 and C2 (113, 114) can control M1 and M3 or M2 and M4 through a structure in which they are connected by cross-coupling with the above transistors.

[0045] In the circuit example of Fig. 3, M3 and M4 are biased in the triode region rather than the saturation region as the previously described degenerate transistors (111, 112). This allows the degenerate transistors (111, 112) to provide optimal delay effects in the loop gain, thereby enabling the impulse sensitivity function (ISF) to continue to move orthogonally to the output voltage.

[0046] This triode region bias circuit design can improve both the 1 / f² region and the 1 / f³ region.

[0047] The 1 / f² region is related to the channel thermal noise of the transistors in Fig. 3, and operates differently in the saturation and triode regions as shown in Equations 1 and 2 below.

[0048]

[0049] [Formula 1]

[0050]

[0051]

[0052] [Formula 2]

[0053]

[0054]

[0055] (where k is the Boltzmann constant, T is the temperature, γ is the experimental noise factor, and gm is the transistor transconductance)

[0056] Figure 4 is a graph showing simulation noise for comparison with the low-noise function of the voltage-controlled oscillator of Figure 1.

[0057] The experimental noise factor (γ) increases in deep submicron scale processes, which can worsen the performance of phase noise, as shown in Fig. 4, when single transistors of the same size as the degenerate transistors (M3 and M4) have different V SD We can see the performance deterioration in simulation noise when biased in .

[0058] Fig. 5 is a graph showing the simulation noise results of the present invention compared with Fig. 4.

[0059] The 1 / f³ region is related to flicker noise upconversion, and ISF-based analysis can be used to quantify the effect of noise upconversion, and the ISF at the first harmonic (ΓDS(t)) can be estimated as shown in Equation 3 below.

[0060]

[0061] [Formula 3]

[0062]

[0063]

[0064] To mitigate 1 / f noise upconversion, it is beneficial for the ISF waveform to be orthogonal to the output voltage, Φ ∈ ,DS represents a phase shift that prevents this phenomenon.

[0065] The use of the aforementioned degenerate transistors (M3 and M4) can reduce flicker noise upconversion by minimizing phase shift and improving the symmetry of vibration through predetermined resistance values.

[0066] As shown in a) of Fig. 5, the influence of transistor size on the near-field phase noise can be confirmed by changing the number of fingers for a degenerate transistor with a unit size of 4 μm / 0.6 μm.

[0067] The effect of flicker noise from active components decreases as resistance decreases until an optimal condition is reached, beyond which point the effect of flicker noise begins to increase again. Therefore, using degenerate transistors (111, 112) as degenerate devices in the triode region can improve the noise performance of the voltage-controlled oscillator (100).

[0068] In addition, if the common tail inductor (130) is connected to a virtual ground, the circuit of the voltage-controlled oscillator described above can be judged to be divided into two oscillation cores, and if the influence of the output resistance due to channel length modulation is ignored, the negative resistance for the oscillator circuit of the present invention can be derived as in Equation 4 below.

[0069] [Formula 4]

[0070]

[0071]

[0072] At this time, g mn1,2 =gmp3,4 =g mp5,6 In this case, the negative resistance can be organized as in Equation 5 below. Therefore, the voltage-controlled oscillator (100) of the present invention does not damage the start-up condition, and the simulation results as shown in b) of Fig. 5 can be confirmed. The difference between the simulation and calculated values ​​is due to the assumptions made when deriving the negative resistance.

[0073] Fig. 6 is a graph showing simulation results related to the operation of the transistor included in the voltage-controlled oscillator of Fig. 1.

[0074] As shown in Fig. 6, when the widths of the degenerate transistors (M3 and M4) are 16 μm and 52 μm, respectively, the normalized ISF for the flicker noise current of the NMOS transistors M1 and M2 can be confirmed, and the net areas of the normalized ISF are -1.36 and -0.7, respectively.

[0075] Here, it can be seen that applying a degenerate transistor width of 52 μm is beneficial in providing improved near-field phase noise, as the smaller net area of ​​the ISF described above means lower flicker noise upconversion.

[0076] The first voltage control oscillator core circuit (110) and the second voltage control oscillator core circuit (120) described above each include a resonance tank, and two synchronization capacitors (121, 122) for connection and synchronization between the resonance tanks can be added to the second voltage control oscillator core circuit (120).

[0077] In addition, the common tail inductor (130) acts as a harmonic filter, connects the first voltage-controlled oscillator core circuit (110) and the second voltage-controlled oscillator core circuit (120), and prevents the active core from applying a load to the aforementioned resonant tank when the degenerate transistors (111, 112) enter the triode region, thereby providing an impedance higher than a predetermined standard, and making it possible to maintain the quality factor of the aforementioned resonant tank higher than a predetermined standard.

[0078] Fig. 7 is a circuit diagram showing the equivalent output noise current for the voltage-controlled oscillator of Fig. 3.

[0079] As shown in Fig. 7, only a portion of the output noise current of the NMOS transistor (M1) and the PMOS transistor (M4) reaches the resonant tank, and the results for each case are as shown in Equations 5 and 6 below.

[0080]

[0081] [Formula 5]

[0082]

[0083] [Formula 6]

[0084]

[0085]

[0086] The features for the aforementioned formulas 5 and 6 are not derived from the second voltage-controlled oscillator core circuit (120) including the PMOS cross-coupled circuit (B).

[0087] Accordingly, the power spectral density (PSD) of the uncorrelated total noise current as explained above is as shown in Equation 7 below.

[0088]

[0089] [Formula 7]

[0090]

[0091]

[0092] Here, R on3,4is the on-resistance of M3 / M4, and g mn1,2 =g mp5,6 =g m and g m R on3,4 Assuming =1, the PSD of the total noise current is as shown in Equation 8 below.

[0093]

[0094] [Formula 8]

[0095]

[0096]

[0097] Additionally, the voltage-controlled oscillator (100) of the present invention may further include a 4-bit capacitor bank to reduce phase noise by applying AM-PM conversion to improve the nonlinearity of the variator used for tuning, and to expand and adjust the tuning range as shown in FIG. 8.

[0098] Figure 9 is a chip micrograph of a prototype circuit for the voltage controlled oscillator of Figure 1.

[0099] As illustrated in Fig. 9, the prototype circuit has two impedance matchings applied externally to the chip to ensure the power delivered to the measurement port, and the oscillator torque itself consumes 5.9 to 6.72 mW at a 1.2 V supply voltage, oscillates in a frequency range of 3.82 to 4.25 GHz (i.e., 15.4 to 17 GHz VCO operating frequency) or 9.4% adjustment range, and the VCO gain (KVCO) varies from 0.4 to 1 GHz / V. In addition, as confirmed in Table 1 below, it is confirmed through verified data that the voltage controlled oscillator (100) of the present invention has significantly improved the overall performance including noise reduction, power efficiency, and oscillation frequency range compared to other oscillator circuits.

[0100] RefFerq(Hz)Supply(V)Power(mW)PN@1kHz(dBc / Hz)PN@1MHz(dBc / Hz)FoM@1kHz(dBc / Hz)FoM@1MHz(dBc / Hz)Technology[0 025]2.052.471.22.532.654.950.9-132.5-131.2-177.1-174.6-194.5-194.9CMOS130nm

[0027] 6.1710.451.83241-47-12 1.6-115-157.4-182.4-179.3CMOS28nm[5]18.91.823.4-9.66-107.24141.5-179CMOS28nm[6]181.221-18*-105.9-150.4- 178.34CMOS65nm

[0029] 140.824-110-182CMOS40nm

[0035] 24.270.657.8-100.3-179.11CMOS40nm[7]173.345-116-184SiGe BiCMOS130nmThis work15.416.25171.21.21.26.726.35.9-29.2-30.3-29-109.3-111.2-109.4-163.9-165.8-165.1-184.8-187.4-186.3CMOS65nm

[0101] Although the embodiments of the present invention have been described with reference to the above and the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without altering the technical concept or essential characteristics thereof. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

[0102] In addition, the present invention is an invention having industrial applicability because it provides a multi-core-based voltage-controlled oscillator capable of improving low noise, including phase noise performance and flicker noise performance, and expanding the available power generation range and increasing low-power efficiency, and thus has sufficient possibility of being sold or sold, and can be clearly implemented in reality.

Claims

1. Noise circulating oscillator circuit; A common tail inductor connecting a first voltage-controlled oscillator core circuit including the above-mentioned noise-circulating oscillator circuit and a second voltage-controlled oscillator core circuit, and used as a noise filter and a virtual ground; Two or more degenerate transistors provided as part of the above noise circulating oscillator circuit and providing a noise circulating function in a state biased in the triode region; and A multi-core based voltage controlled oscillator comprising two or more control capacitors that correspond to the two or more degenerate transistors and control them to be in an on or off state.

2. In paragraph 1, A multi-core based voltage-controlled oscillator in which the above two or more degenerate transistors are PMOS (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistors.

3. In paragraph 2, A multi-core based voltage controlled oscillator in which the above two or more degenerate transistors are connected to the common tail inductor through the drain portion.

4. In paragraph 2, A multi-core based voltage-controlled oscillator further comprising an NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistor corresponding to each of the above two or more degenerate transistors.

5. In paragraph 4, A voltage-controlled oscillator based on a multi-core, wherein each of the two or more controllable capacitors controls on or off a set of PMOS (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistors and NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) type transistors together.

6. In paragraph 1, The second voltage-controlled oscillator core circuit is a multi-core based voltage-controlled oscillator including a PMOS cross-coupled circuit.

7. In paragraph 1, A multi-core based voltage controlled oscillator, wherein the first voltage controlled oscillator core circuit and the second voltage controlled oscillator core circuit each include a resonance tank, and the second voltage controlled oscillator core circuit further includes two synchronization capacitors for connection and synchronization between the resonance tanks.

8. In paragraph 1, A multi-core based voltage controlled oscillator with an additional 4-bit capacitor bank to expand and adjust the tuning range.

9. In paragraph 1, A multi-core based voltage controlled oscillator in which the bias state for the above two or more degenerate transistors persists until the impulse sensitivity function (ISF) moves orthogonal to the output voltage.

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