Ceramic circuit board

Abstract

A ceramic circuit board according to the present invention may comprise a substrate, and a filler metal layer which is grown on the substrate by physical vapor deposition and which is remelted and bonded by brazing. Therefore, the adhesion strength of a contact interface increases, the reliability of a ceramic circuit board and a semiconductor module including same can be improved, and the porosity of a filler metal layer can be remarkably reduced by physical vapor deposition and brazing such that the density of the filler metal layer can be increased.

Description

ceramic circuit board

[0001] The present invention relates to semiconductor technology, and more particularly to ceramic circuit boards.

[0002]

[0003] Power semiconductors, which can operate at high voltages and high currents and are used to convert and control power, are used as core components in various fields such as power supplies, inverters, solar power, artificial intelligence (AI), and mobile devices, and their demand is increasing today.

[0004] Ceramic circuit boards that make up power semiconductors require high insulation, heat dissipation, and heat resistance, and to achieve these, metallizing technology, a type of surface treatment technology, is used on ceramic substrates.

[0005] Metallizing methods include direct plated copper, thick printed copper, direct bonded copper, and vacuum deposition.

[0006] In order to form a metal layer on a ceramic substrate using a plating method, a separate seed layer must be formed on the ceramic substrate to increase reactivity, and it is difficult to control the residual stress of the film formed during the plating process, which limits the thickness of the plating film.

[0007] Fig. 1(a) and Fig. 1(b) are SAT images of a filler metal layer in a conventional ceramic circuit board. Fig. 1(a) and Fig. 1(b) are SAT images of a ceramic circuit board made by dispersing conductive powder in a binder and organic additives, extruding it by printing, and laminating it on a ceramic substrate. It can be confirmed that the filler metal layer of the conventional ceramic circuit board of Fig. 1(a) has a porosity of 39.5% per unit area. It can be confirmed that the filler metal layer of the conventional ceramic circuit board of Fig. 1(b) has a porosity of 2.5% per unit area.

[0008] In the case of the conventional ceramic circuit board of Korean Patent Publication No. 10-2020-0108393 (publication date: September 18, 2020) shown in FIG. 1(a) and FIG. 1(b), there were problems such as the need for a high-temperature drying process after forming a filler layer by printing, the lamination thickness was thick, and as the binder evaporated, voids were created in the amount of the evaporated binder, which lowered the substrate yield.

[0009] The need for ceramic circuit boards that are thinner while also having heat dissipation and heat resistance is increasing day by day.

[0010]

[0011] The technical problem to be solved by the present invention is a ceramic circuit board that improves adhesive performance and product yield by using a thin film.

[0012]

[0013] To solve the above technical problem, the present invention provides a ceramic circuit board.

[0014] A ceramic circuit board according to one embodiment of the present invention may include a substrate; and a filler layer grown on the substrate by physical vapor deposition and re-melted and joined by brazing.

[0015] In one embodiment, the substrate may be a ceramic substrate.

[0016] In one embodiment, the filler layer may be formed by sputtering an alloy or a plurality of single metals.

[0017] According to one embodiment, at least two materials forming the filler layer can be grown by physical vapor deposition and then brazed to form layers of different heights with respect to the substrate according to different reactivity.

[0018] According to one embodiment, the filler layer is formed by a plurality of elements forming a single layer without any layer distinction after brazing, and the metal layer loaded on the filler layer and the substrate can be joined via the filler layer.

[0019] According to one embodiment, the filler layer may have a plurality of elements irregularly distributed.

[0020] According to one embodiment, the filler material layer may have a porosity per unit area of ​​0.1% or more and 5% or less in an image from an ultrasonic microscope.

[0021] In one embodiment, the filler layer may not include closed pores and open pores in the ultrasound microscope image.

[0022] According to one embodiment, the filler material layer may have a porosity per unit area of ​​0.1% or more and 5% or less in an image from an ultrasonic microscope.

[0023] According to one embodiment, the thickness of the filler layer may be from 1 μm to 50 μm.

[0024]

[0025] According to an embodiment of the present invention, by forming a filler layer formed by physical vapor deposition on a ceramic substrate, the adhesion of a contact interface can be increased, and the reliability of a ceramic circuit substrate and a semiconductor module including the same can be improved.

[0026] According to one embodiment of the present invention, there is an advantage in that the porosity of the filler metal layer is significantly reduced by physical vapor deposition and brazing, thereby increasing the density of the filler metal layer.

[0027] According to another embodiment of the present invention, by brazing a filler layer made of two or more materials at low pressure, the mobility between materials with different reactivity can be controlled, thereby manufacturing a ceramic circuit board having different component content ratios and distributions according to positions in the thickness direction of the filler layer, thereby increasing manufacturing efficiency and increasing manufacturing convenience.

[0028] According to another embodiment of the present invention, a filler layer formed by brazing after physical vapor deposition has a layer uniformity, thereby having the advantage of significantly reducing the rate of layer separation.

[0029]

[0030] Figures 1(a) and 1(b) are SAT images of a filler layer in a conventional ceramic circuit board.

[0031] FIG. 2 is a cross-sectional view illustrating a ceramic circuit board according to one embodiment of the present invention.

[0032] Figure 3 is a cross-sectional image of part A in Figure 2.

[0033] Figure 4 is an enlarged view of part B in Figure 3.

[0034] FIG. 5 is a SAT image of a filler layer according to one embodiment of the present invention.

[0035] 10: Ceramic circuit board

[0036] 100: substrate

[0037] 200: Filler metal layer 201: Porosity

[0038] 202: Gap ratio

[0039] 21: Alloys 22a, 22b, 22c: Single metals

[0040]

[0041] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to sufficiently convey the spirit of the present invention to those skilled in the art.

[0042] In this specification, when a component is referred to as being on another component, it means that it can be formed directly on the other component, or a third component may be interposed between them. In addition, in the drawings, shapes and sizes are exaggerated for the purpose of effectively explaining the technical contents.

[0043] Additionally, although terms such as first, second, and third have been used to describe various components in various embodiments of this specification, these components should not be limited by these terms. These terms are merely used to distinguish one component from another. Thus, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiments. Furthermore, the term "and / or" has been used herein to mean including at least one of the components listed before and after.

[0044] In the specification, singular expressions include plural expressions unless the context clearly dictates otherwise. In addition, terms such as "comprise" or "have" are intended to specify the presence of a feature, number, step, component, or combination thereof described in the specification, and should not be construed as excluding the presence or addition of one or more other features, numbers, steps, components, or combinations thereof. In addition, the term "connection" is used in the present specification to mean both indirectly connecting multiple components and directly connecting them.

[0045] In addition, when describing the present invention below, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0046]

[0047] FIG. 1(a) and FIG. 1(b) are SAT images of a filler metal layer in a conventional ceramic circuit board, FIG. 2 is a cross-sectional view showing a ceramic circuit board (10) according to an embodiment of the present invention, FIG. 3 is a cross-sectional image of part A in FIG. 2, FIG. 4 is an enlarged view of part B in FIG. 3, and FIG. 5 is a SAT image of a filler metal layer (200) according to an embodiment of the present invention.

[0048]

[0049] Hereinafter, a ceramic circuit board (10) according to one embodiment of the present invention will be examined with reference to FIGS. 2 to 5.

[0050]

[0051] Referring to FIGS. 2 to 5, the ceramic circuit board (10) includes a substrate (100) and a filler layer (200), and may further include a metal layer (300).

[0052]

[0053] Referring again to FIG. 2, the substrate (100) may be formed of a material having high thermal conductivity and excellent mechanical properties such as strength and fracture toughness. Preferably, the substrate (100) may be formed of a ceramic material having thermal conductivity, insulation, and mechanical strength properties.

[0054] The substrate (100) may be made of alumina (Al2O3), silicon nitride (Si3N4), aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO), sapphire, or zirconia-doped alumina (ZTA).

[0055] According to one embodiment, the substrate (100) may be a ceramic substrate.

[0056] According to one embodiment, the thickness of the substrate (100) may be 0.1 mm to 1.0 mm. More preferably, the thickness of the substrate (100) according to one embodiment may be 0.2 mm to 0.8 mm.

[0057]

[0058] Referring again to FIGS. 2 to 5, the filler metal layer (200) may be formed by a physical vapor deposition method. The filler metal layer (200) may be formed on the substrate (100) by physical vapor deposition. The filler metal layer (200) may be formed on at least one surface of the substrate (100) by physical vapor deposition. According to one embodiment, the filler metal layer (200) may be formed on both surfaces of the substrate (100) by physical vapor deposition simultaneously or at different times. The filler metal layer (200) may be a brazing filler metal.

[0059] The filler metal layer (200) may be formed of heterogeneous materials. The filler metal layer (200) may use an alloy or multiple single metals as the filler material. According to one embodiment, the filler metal layer (200) may be formed using a single metal of a ternary or quaternary system as the filler material. The filler metal layer (200) may be formed by an active metal brazing (AMB) method that directly brazes an alloy or multiple single metals to the surface of the substrate (100).

[0060] In one embodiment, the filler material portion may be an alloy composed of titanium (Ti), silver (Ag), and copper (Cu). In one embodiment, the filler material portion may be a plurality of single metals. More specifically, the plurality of single metals may include titanium (Ti), silver (Ag), and copper (Cu).

[0061] According to one embodiment, the filler layer (200) can form a single film by sequentially depositing titanium (Ti), copper (Cu), and silver (Ag) through a physical vapor deposition method on at least one surface of the substrate (100).

[0062] According to one embodiment, the wt% of titanium (Ti), copper (Cu), and silver (Ag) in the filler layer (200) may be 1:19:80 to 10:19:60.

[0063]

[0064] As an alloy or a plurality of single metals are simultaneously vapor-deposited, the filler metal layer (200) may be formed as a single layer. The filler metal layer (200) may have a plurality of elements irregularly distributed. The filler metal layer (200) may be a multiphase alloy layer in which a plurality of elements are mixed. The filler metal layer (200) may have a plurality of elements unevenly distributed per unit area. The filler metal layer (200) may have different distribution ratios and shapes of the plurality of elements per unit area. The filler metal filler (200) may be a brazing filler metal formed by physical vapor deposition.

[0065] The filler metal layer (200) can be brazed after physical vapor deposition. The brazing of the filler metal layer (200) can be performed at an operating pressure of 1 mTorr to 20 mTorr in an inert gas atmosphere. The inert gas according to one embodiment can include helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), radon (Rn), and nitrogen (N2). The filler metal layer (200) can be brazed in a vacuum environment. The filler metal layer (200) can be brazed at a low temperature. The brazing of the filler metal layer (200) can be performed at a process temperature of 800°C to 900°C for 30 minutes to 120 minutes. The filler metal layer (200) can minimize the occurrence of cracks and voids by heat-treating the brazing filler metal formed by physical vapor deposition by brazing in a low-temperature and vacuum environment. The filler metal layer (200) can be melted by brazing and fused to the substrate (100) and the metal layer (300). The substrate (100) and the metal layer (300) can be fused by the filler metal layer (200). At a process temperature of less than 800°C, the filler metal layer (200) is not sufficiently melted, so diffusion of the filler material portion does not occur completely, and wettability is reduced, which may lower the physical bonding strength and cause problems of poor thermal and electrical connection. At a process temperature exceeding 900°C, the substrate (100) which is vulnerable to chemical and thermal stress may be damaged, or the substrate (100), filler layer (200), and metal layer (300) may be deteriorated.

[0066] Referring again to FIGS. 3 and 4, at least two or more materials forming the filler layer (200) may have different migration speeds and different distribution ratios per unit area depending on the reactivity of the materials when grown by physical vapor deposition and then brazed. At least two or more materials forming the filler layer (200) may form different height layers with respect to the surface of the substrate (100) depending on the different reactivity when grown by physical vapor deposition and then brazed.

[0067] According to one embodiment, the material forming the filler layer (200) may be titanium (Ti), silver (Ag), and copper (Cu). As titanium (Ti), silver (Ag), and copper (Cu) grow into the filler layer (200) by physical vapor deposition and are then brazed, titanium (Ti), silver (Ag), and copper (Cu) have different reactivity, and titanium (Ti) forms a lower layer based on the surface of the substrate (100), and may be positioned relatively closer to the substrate (100) than silver (Ag) and copper (Cu). The filler layer (200) may be titanium nitride (Ti) based on the surface of the substrate (100). x N y ), silver (Ag matrix), and copper (Cu rich Ag) gradient layers can be formed in different height layers. The filler layer (200) is formed along the height direction by titanium nitride (Ti x N y ), silver (Ag matrix), and copper (Cu-rich Ag) can form a single layer without a clear layer distinction, with a gradual change in concentration (gradient).

[0068] According to one embodiment, as shown in FIGS. 3 and 4, titanium (Ti) undergoes a chemical reaction at the interface of the substrate (100) near the surface of the substrate (100), i.e., in the lower layer within the filler layer (200), to form titanium nitride (Ti). x N y ) can be formed. The filler layer (200) is formed of titanium nitride (Ti) at the interface with the substrate (100). x Ny ) can be formed to increase the bonding strength between the substrate (100) and the filler metal layer (200). At a process temperature of 800°C to 900°C, titanium (Ti) moves closer to the substrate (100) and is sucked into the gap between the surfaces of the substrate (100) due to wettability with the substrate (100) and capillary action, thereby increasing the bonding strength between the substrate (100) and the filler metal layer (200).

[0069] Referring back to FIG. 4, silver (Ag) and copper (Cu), which have relatively lower reactivity than titanium (Ti), can be positioned at a higher layer than titanium (Ti) based on the surface of the substrate (100). At a process temperature of 800°C to 900°C, copper (Cu) and silver (Ag) move closer to the metal layer (300), thereby optimizing the interfacial reactivity between the metal layer (300) and the filler metal layer (200) due to the reactivity (wetting acid) with the metal layer (300). Depending on the content ratio of silver (Ag) and copper (Cu) forming the filler metal layer (200), silver (Ag) can be distributed in a wider and more even area than copper (Cu) (Ag matrix), and copper (Cu) can be distributed in a relatively narrow and concentrated area compared to silver (Ag) (Cu rich Ag).

[0070]

[0071] Referring again to FIG. 5, the filler layer (200) may have a dense grain boundary phase.

[0072] According to one embodiment, in an image of a scanning acoustic tomography (SAT), the porosity per unit area of ​​the filler material layer (200) may be 0.1% to 5%.

[0073] According to one embodiment, in the image of the SAT, the filler metal layer (200) may not include closed pores and open pores. A closed pore may be a cavity that forms a closed section within the filler metal layer (200), that is, a pore that is not connected to other pores within the filler metal layer (200) and to which a material such as a fluid exposed to the filler metal layer (200) cannot access. An open pore may be a cavity that forms an open section within the filler metal layer (200), that is, a region that is connectable to other pores within the filler metal layer (200) and to which a fluid exposed to the filler metal layer (200) can access. However, since the filler metal layer (200) does not include open pores as well as closed pores, the filler metal layer (200) may have a dense structure to which external materials cannot be exposed. The filler layer (200) may not include macro pores and meso pores.

[0074]

[0075] According to one embodiment, in the image of the ultrasound microscope (SAT), the void ratio per unit area of ​​the filler metal layer (200) may be 0.1% to 5%. The two or more materials constituting the filler metal layer (200) may have different area occupancies. The two or more materials constituting the filler metal layer (200) may have relatively non-uniform area occupancies.

[0076] The filler layer (200) may have a shape in which one material is centered, and the remaining materials surround the outer periphery of a material that has not undergone a phase change.

[0077]

[0078] The thickness of the filler layer (200) may be 1 μm to 50 μm.

[0079]

[0080] Referring again to FIG. 2, according to one embodiment, the metal layer (300) may be an electrically conductive layer. Since the metal layer (300) has electrically conductive properties, a predetermined circuit pattern may be formed. The metal layer (300) may be deposited on the filler metal layer (200) and then fused to the substrate by brazing the filler metal layer (200). The metal layer (300) may be bonded to the substrate (100) via the filler metal layer (200). The metal layer (300) may be formed of a single metal or an alloy. The melting point of the metal layer (300) may be higher than the melting point of the filler material portion forming the filler metal layer (200).

[0081] The thickness of the metal layer (300) may vary depending on the operating power of the semiconductor device to be mounted. According to one embodiment, the thickness of the metal layer (300) may be 0.1 nm to 1.0 nm. The metal layer (300) may be a thin film foil. The metal layer (300) may have a shape corresponding to the substrate (100). The metal layer (300) may be formed by brazing the filler layer (200) after the filler layer (200) is loaded onto the substrate (100) formed by physical vapor deposition so that the filler layer (200) covers it.

[0082] According to one embodiment, the metal layer (300) may be formed of a plurality of layers taking into account mechanical stress or thermal expansion coefficient.

[0083]

[0084] While the present invention has been described in detail using preferred embodiments, the scope of the present invention is not limited to the specific embodiments and should be construed in accordance with the appended claims. Furthermore, those skilled in the art will appreciate that numerous modifications and variations are possible without departing from the scope of the present invention.

Claims

1. Substrate; and A ceramic circuit board comprising a filler layer grown by physical vapor deposition on the substrate and re-melted and bonded by brazing.

2. In paragraph 1, The above substrate is Ceramic circuit board, a ceramic substrate.

3. In paragraph 1, The above filler layer is, A ceramic circuit board using an alloy or a plurality of single metals as a filler material.

4. In paragraph 3, At least two or more materials forming the above-mentioned filler layer are: A ceramic circuit board formed by brazing after growth through physical vapor deposition, thereby forming layers of different heights based on the substrate according to different reactivity.

5. In paragraph 1, The above-mentioned filler layer is a single layer formed by multiple elements without any layer distinction after brazing. A ceramic circuit board in which a metal layer loaded on the above filler layer and the substrate are bonded via the above filler layer.

6. In paragraph 1, The above filler layer is, A ceramic circuit board with multiple elements irregularly distributed.

7. In paragraph 1, The above filler layer is, A ceramic circuit board having a porosity per unit area of ​​0.1% to 5% in an ultrasonic microscope image.

8. In paragraph 1, The above filler layer is, A ceramic circuit board, without closed or open pores, as shown in an ultrasound microscope image.

9. In paragraph 1, The above filler layer is, A ceramic circuit board having a void ratio per unit area of ​​0.1% to 5% in an ultrasonic microscope image.

10. In paragraph 1, The above filler layer is, A ceramic circuit board having an uneven gap ratio per unit area between different materials.

11. In paragraph 1, A ceramic circuit board, wherein the thickness of the above-mentioned filler layer is 1 μm to 50 μm.

Images