High aspect ratio feature etching by multi-state pulsing

Abstract

A method of etching features in the substrate includes receiving in an etch chamber a substrate including a first layer to a first layer to be etched and a mask over the first layer, and etching features in the first layer by exposing the substrate to etch conditions including a multi-state pulsing scheme having a pulse period of at most about 3000 microseconds and including a first state S1, a second state S2, a third state S3, and a fourth state S4 all occurring once within the pulse period. Among the states S1, S2, S3, and S4, state S1 has the highest magnitude of plasma source power and plasma bias power, S2 has no bias power, S3 and S4 have source plasma powers and / or bias plasma powers that are different, and S3 has a bias power that is lower than the S1 bias power, and S4 has a bias power that is lower than the S1 bias power.

Description

11955-1WO / LAMR1P036WO HIGH ASPECT RATIO FEATURE ETCHING BY MULTI-STATE PULSING CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in their entireties and for all purposes. BACKGROUND

[0002] In semiconductor fabrication, the miniaturization of feature size is a continuously driving challenge that impacts dry etch processes such as processes that form high aspect ratio (HAR) features. Such features are commonly used in memory device fabrication such as DRAM capacitor fabrication.

[0003] The background provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent that it is described in this background or presented as contextual information in the description, that may not otherwise qualify as prior art at the time of filing, is neither expressly nor impliedly admitted as prior art against the present disclosure. SUMMARY

[0004] Provided is a method of etching features in the substrate. The method includes receiving in an etch chamber a substrate including a first layer to be etched and a mask over the first layer. The mask is patterned with openings at locations where features are to be etched. The method further includes etching features in the first layer by exposing the substrate to etch conditions. The etch conditions include a multi-state pulsing scheme having a pulse period of at most about 3000 microseconds and include a first state S1, a second state S2, a third state S3, and a fourth state S4 all occurring once within the pulse period. Among the states S1, S2, S3, and S4, state S1 has the highest magnitudes of a plasma source power and a plasma bias power, S2 has no bias power, S3 and S4 have source plasma powers and / or the bias plasma powers that are different, and S3 has a bias power that is lower than the S1 bias power, and S4 has a bias power that is lower than the S1 bias power.11955-1WO / LAMR1P036WO

[0005] In some embodiments, the source plasma power and the bias plasma power for S1 range from about 1 to 20 kW and about 10 to 100 kW, respectively.

[0006] In some embodiments, the source plasma power for S2 ranges from 0 to about 1500 W and the bias plasma power for S2 is 0 W.

[0007] In some embodiments, the source plasma power and the bias plasma power for S3 range from about 0.3 to 3 kW and 0 to about 3 kW, respectively.

[0008] In some embodiments, the source plasma power and the bias plasma power for S1 range from 0 to about 1 kW and 0 to about 300 W, respectively.

[0009] In some embodiments, the source plasma power for the states has a frequency of about 10 to 100 MHz, and the bias plasma power for the states has a frequency of about 100 to 1000 kHz.

[0010] In some embodiments, S1, S2, S3, and S4 occur in this sequential order within the pulse period.

[0011] In some embodiments, the pulse period occurs with a repetition rate of about 10 Hz to 20 kHz.

[0012] In some embodiments, S1 has a duty cycle of about 5 to 60 % of the pulse period.

[0013] In some embodiments, S2 occupies at least about 50 % of the pulse period.

[0014] In some embodiments, S1 has a pulse width of about 40 to 1000 microseconds.

[0015] In some embodiments, the etch conditions include supplying the etch chamber with an etchant gas including a fluorine-containing component and a carbon-containing component.

[0016] In some embodiments, the fluorine-containing component includes HF, NF3, CF4, PF3, SF6, SiF4, WF6, MoF6, RuF6, or any combination thereof.

[0017] In some embodiments, the carbon-containing component includes a hydrocarbon or a hydrofluorocarbon.

[0018] In some embodiments, the etch conditions include a pressure in the etch chamber of about 2 to 400 mTorr.

[0019] In some embodiments, the etch conditions include a temperature of the substrate of about -100 to 200 °C.

[0020] In some embodiments, the etch conditions include a temperature of the substrate of about -100 to 0 °C.

[0021] In some embodiments, the first layer includes a nitrogen-doped silicon oxide layer.

[0022] In some embodiments, the features to be etched are at locations of capacitors for a memory device.11955-1WO / LAMR1P036WO

[0023] The method further includes etching features in one or more additional layers beneath the first layer. Together, the one or more additional layers and the first layer form a mold stack.

[0024] Another aspect of the disclosure relates to an apparatus for processing a substrate. The apparatus includes an etch chamber configured to receive a substrate including at least one layer to be etched and a mask on the at least one layer, a plasma power source for generating a plasma within the etch chamber, one or more gas inlets for providing one or more etchant species to the etch chamber, a substrate support for supporting the substrate. The substrate support includes or is associated with an electrode configured to provide bias voltage to the substrate. The apparatus also includes a controller configured to cause: etching features in the at least one layer by exposing the substrate to etch conditions including a multi-state pulsing scheme having a pulse period of at most about 3000 microseconds and including a first state S1, a second state S2, a third state S3, and a fourth state S4 all occurring once within the pulse period. Among the states S1, S2, S3, and S4, state S1 has the highest magnitudes of a plasma source power and a plasma bias power, S2 has no bias power, S3 and S4 have source plasma powers and / or bias plasma powers that are different, and S3 has a bias power that is lower than the S1 bias power, and S4 has a bias power that is lower than the S1 bias power.

[0025] In some embodiments, the plasma power source includes a transformer coupled plasma (TCP) power source.

[0026] In some embodiments, the controller is further configured to cause the source plasma power and the bias plasma power for S1 to range from about 1 to 20 kW and about 10 to 100 kW, respectively.

[0027] In some embodiments, the controller is further configured to cause the source plasma power for S2 to range from 0 to about 1500 W and cause the bias plasma power for S2 to be 0 W.

[0028] In some embodiments, the controller is further configured to cause the source plasma power and the bias plasma power for S3 to range from about 0.3 to 3 kW and 0 to about 3 kW, respectively.

[0029] In some embodiments, the controller is further configured to cause the source plasma power and the bias plasma power for S1 to range from 0 to about 1 kW and 0 to about 300 W, respectively.11955-1WO / LAMR1P036WO

[0030] In some embodiments, the controller is further configured to cause the source plasma power for the states to have a frequency of about 10 to 100 MHz, and cause the bias plasma power for the states to have a frequency of about 100 to 1000 kHz.

[0031] In some embodiments, the controller is further configured to cause S1, S2, S3, and S4 to occur in this sequential order within the pulse period.

[0032] In some embodiments, the controller is further configured to cause the pulse period to occur with a repetition rate of about 10 Hz to 20 kHz.

[0033] In some embodiments, the controller is further configured to cause S1 to have a duty cycle of about 5 to 60 % of the pulse period.

[0034] In some embodiments, the controller is further configured to cause S2 to occupy at least about 50 % of the pulse period.

[0035] In some embodiments, the controller is further configured to cause S1 to have a pulse width of about 40 to 1000 microseconds.

[0036] These and other features of the disclosure will be presented below, sometimes with reference to drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1A shows a cross-section of a structure with layers of a mask and underlying material to be etched.

[0038] Figure 1B shows the structure of Figure 1A after some etching with a one or two state pulsing scheme. The features etched under the mask openings have (1) relatively wide bow CDs, (2) sidewall taper, and (3) non-uniform depth. Also, the mask has significant faceting and height reduction.

[0039] Figures 2A and 2B correspond to Figures 1A and 1B, but Figure 2B has narrower bow CD, less sidewall taper, wider bottom CD, and less mask height rejection. This improvement in the etch results from using a four-state pulsing regime in accordance with some embodiments of this disclosure.

[0040] Figure 3 presents an example multi-state pulsing scheme having four states. The x-axis shows pulse width (time in microseconds), and the y-axis shows plasma power in Watts. The plasma power is separated into a bias power and a plasma source power.

[0041] Figures 4A, 4B, 4C, and 4D illustrate in cartoon fashion feature cross-sections with ions and neutrals distributed on the sidewalls of the feature at each of states S1, S2, S3, and S4.11955-1WO / LAMR1P036WO

[0042] Figures 5A and 5B are graphs of experiments conducted to illustrate certain benefits of four-state pulsing, as compared to two-state and three-state pulsing.

[0043] Figure 6 presents a flow chart of an example multi-phase etch process that may be used to etch a feature in a layer. The etch process includes example etch operations during etching of a high aspect ratio (HAR) feature.

[0044] Figure 7 presents a block diagram of etching apparatus that may be used to etch HAR features in accordance with embodiments of this disclosure.

[0045] Figure 8 presents a block diagram of a system including an etch apparatus. DETAILED DESCRIPTION Introduction and Context

[0046] As mentioned, the miniaturization of feature size is a continuously driving challenge that impacts dry etch processes such as etching high aspect ratio (HAR) features such as molds for DRAM capacitors. One issue is controlling the sidewall profile of etched features. The profile may be characterized by a Max CD size, which is also called Bow CD, sidewall taper, bottom CD, etc. The Bow CD represents the size of a bow that occurs in the etched feature and results from unwanted lateral etching in the feature. Other properties that impact etch performance include etch depth non-uniformity and mask selectivity.

[0047] This Bow CD must be controlled within the target limits without other tradeoffs. Approaches to reducing the Bow CD include controlling ion scattering, sidewall passivation, and conformal deposition during feature etching. However, such measures are often insufficiently effective in preventing lateral etch that produces bowed etch profiles, as well as sidewall tapering, both of which negatively affect device performance and reliability.

[0048] These challenges are magnified by evolving requirements for the materials in which features are etched. For example, to improve electrical properties such as the dielectric constant of devices such as DRAM cells, some applications require nitrogen doping of the etch material (e.g., a silicon oxide). Such doping has been found to increase Bow CD in cutting edge etch processes.

[0049] Additionally, conventional etching chemistries often employ carbon-based etchants such as one or more volatile hydrocarbons (CxHy) and / or hydrofluorocarbons (CxHyFz, where z>0), e.g., CH2F2. In HAR feature etching, these chemistries sometimes produce a polymer that induces clogging (sometimes called capping) at or near the top of11955-1WO / LAMR1P036WO the feature. Such clogging induces further undesired etch characteristics that include not only large Bow CD but also unopened CD at the bottom of the features.

[0050] Current etch processes use one or two RF regimes (e.g., on / off) such as level-to- level RF pulsing. While pulsing provides some improvement in etch characteristics, it has been found that they are insufficient to reduce the Bow CD to an acceptable size in some HAR feature etch applications such as those employing nitrogen-doped oxides.

[0051] Certain embodiments of this disclosure conduct etching under cryogenic conditions and multi-state pulsed RF cycles with first, second, third and fourth states where each state may have a different power level or at least a different distribution of power between bias and source. Etching under such conditions have been found to reduce Bow CD in high aspect ratio features of, e.g., 30~50 or more for a DRAM capacitor mold that includes, for example, a nitrogen-doped oxide.

[0052] In multi-state etch processes, each state may have a controlled bias power, source power, and minimum pulse width. The disclosed multi-state pulsing scheme may facilitate the simultaneous realization of (1) etch feature profile control, (2) mask / etch substrate selectivity, and (3) etch feature depth uniformity.

[0053] Figure 1A is a schematic depiction of a structure 100 including one or more layers of mask 110 and an underlying structure 120 to be etched. The mask 110 may comprise carbon (e.g., high-density amorphous carbon and / or metal-doped carbon), polysilicon, or the like in the case where the underlying structure 120 comprises a dielectric such as a silicon oxide or a silicon nitride. As an example, underlying structure 120 may be a doped or undoped silicon oxide. The dopant may be nitrogen, carbon, and their combinations. The underlying structure 120 may comprise a stack of dielectric material layers, each having a different composition and material property. For example, the underlying structure 120 may comprise a first layer 130 of a first dielectric material and a second layer 140 of a second dielectric material stacked on the first layer 130. In some cases, the underlying structure 120 includes three or more layers, which may comprise alternating layers of dielectric materials such as a stack of alternating silicon oxide and silicon nitride layers. In some embodiments, the structure 120 may be disposed on a substrate such as a semiconductor or glass wafer.

[0054] Figure 1B is a schematic depiction of a structure 150 after performing some etching of the structure 100 in Figure 1A according to a conventional etch process such as one that employs a one or two-state pulsing scheme. As depicted, structure 150 includes a mask layer 115 and features 160 formed under the mask layer 150. The features 160 may be11955-1WO / LAMR1P036WO formed by exposing structure 100 to etch conditions including an etchant gas in the presence of a plasma. The etch conditions remove material from the underlying structure 120 in Figure 1A under the openings in the patterned mask layer 100. The etch conditions primarily remove material from structure 120, but they also remove some material from mask 100, leaving a modified mask structure 115 as illustrated in Figure 1B. The features 160 may have high aspect ratios (HARs) such as about 30-300. Each feature 160 is formed in the one or more dielectric materials of the underlying structure 120 in Figure 1A, for example, the layer of the first dielectric material 130 and the layer of the second dielectric material 140. After etching, the mask may have significant faceting and height reduction due to the etching environment. The individual features 160 may have non-uniform depths and profiles beyond acceptable ranges. For example, features may have unacceptable critical dimensions (CDs), e.g., bow CDs, sidewall tapers, bottom CDs, etc. These problems are exacerbated in features having small openings and high aspect ratios. As illustrated, the features 160 have unacceptably wide bow CDs 170 that extend along at least a portion of their sidewalls. Also, as illustrated, the etch profiles of features 160 may transition to a gradual taper 180 (i.e., taper profile), which may lead to an unacceptably narrow bottom CD 185. Collectively, the depths of the features 160 vary from one feature to another and the depth non-uniformity 190 may be unacceptable.

[0055] Figure 2A corresponds to a structure in Figure 1A, and schematically depicts a structure 200 having a patterned mask 210 and an underlying structure 220 to be etched, which corresponds to structure 120 illustrated in Figure 1A. In some embodiments, as with structure 120, the structure 220 comprises a dielectric material and may include one or more layers stacked relative to each other. In the depicted example of Figure 2A, structure 220 comprises a first layer 230 of a first dielectric material and a second layer 240 of a second dielectric material.

[0056] Figure 2B schematically depicts a structure 250 after some etching is performed on structure 200 using a multi-state pulsing scheme (e.g., a four-state pulsing scheme) according to some embodiments of this disclosure. The structure 250 includes a modified patterned mask 215 (after mask 110 is exposed to etching) and etched features 260. Compared to the etched features 160 in Figure 1B based on a one or two-state pulsing scheme, features 260 have a narrower bow CD 270, a steep taper 280, and a wider bottom CD 285, which characteristics may be obtained by employing a four-state pulsing scheme. Further, compared to etched features 160, features 260 have a reduced non-uniformity 290 in their depths. In other words, the depths of the etched features may be more uniform11955-1WO / LAMR1P036WO relative to features produced using fewer than four states in a pulsing scheme. Still further, compared to etching employed in the Figures 1A-B process, the etching employed in the Figures 2A-B process exhibits a greater etch selectivity between the mask and the etched features. Thus, mask faceting and height reduction are reduced during etching. Etch Process Plasma generation

[0057] In certain embodiments, a plasma etch chamber comprises a plasma source generator and associated electrode (e.g., an inductively coupled plasma (ICP) electrode). In certain embodiments, the plasma etch chamber comprises a plasma bias generator and an electrode (e.g., an electrode within or proximate a wafer pedestal, chuck, or other support). In the following example, plasma process conditions assume that the etch chamber includes both sources. It also assumes that these sources are pulsed, such that each cycle includes at least four states, including a high-power state (or first state) S1, a lower power state (or second state) S2, and two intermediate power states (or third and fourth states) S3 and S4. Pulsing is described further below, such as with reference to Figures 3 and 4A-4D. Note that in some embodiments, a portion of the overall etch process does not employ the four-state multi-state pulsing or even, in some cases, any pulsing.

[0058] In certain embodiments, the disclosed pulsing regime is supported in a commercially available plasma etch tool available from Lam Research of Fremont, CA. Examples of such tools include the Flex™ and the Vantex™. Multi-State Pulsing Characteristics

[0059] Multi-state pulsing schemes may be characterized by various parameters. For example, the number of distinct pulse states may include four or more. Additionally, each state may be characterized by the total power applied, the fraction of a pulse period occupied by the state (e.g., a duty cycle), and the pulse width. Still further, the multi-state pulsing scheme may be characterized by the repetition rate of a pulse period, the order sequence of the states, the total duration of the pulse period, or any combination of these.

[0060] As explained, the pulsing may be applied to the source RF power, the bias RF power, or both. In multi-state pulsing schemes herein, each pulsed RF cycle has at least a first state, a second state, a third state, and a fourth state. In one example of a multi-state pulse scheme, (a) the first state (S1) is defined by a first source RF power level and a first bias RF power level, both of which are high power levels, (b) the second state (S2) is defined by a second source RF power of 0 or a low value and a second bias RF power of11955-1WO / LAMR1P036WO 0 or substantially 0 power, (c) the third state (S3) is defined by a third source RF power level that is less than the first source RF power level and a third bias RF power level of 0 or a low value, and (d) the fourth state (S4) is defined by a fourth source RF power level that is 0 or a least substantially less than the first source RF power level, and a fourth bias power level of 0 or a low value.

[0061] Figure 3 presents a timing diagram of an example four-state pulsing scheme, in which an S1 state has the highest power (both 60 megahertz (MHz) source (ICP) power (solid line) and 400 kilohertz (kHz) bias power (dotted line)), an S2 state that has 0 plasma power from either source, an S3 state that has some 60 MHz power and some 400 kHz power that may be substantially similar to 60 MHz power, and an S4 state that has a small amount of both the 400 kHz and 60 MHz powers.

[0062] The S1 state has the highest power for both the plasma source and the bias, among all the states (i.e., S1, S2, S3, and S4) in an exemplary four-state pulsing scheme described herein. In some embodiments, the S1 state has a short duration time (or short pulse width).

[0063] Compared to the S1 state, the S2 state has a low power and a long duration time. For example, the S2 state may have 0 or relatively low plasma source power and 0 bias power. The S2 state may have a long duration time relative to other states (i.e., S1, S3, or S4) in an exemplary four-state pulsing scheme. In some embodiments, S2 may have a duration time that is at least about 50 % of a pulse period.

[0064] The S3 state has a plasma source power that may be less than the plasma source power for S1 and a bias power that is 0 or at least lower than the bias power for S1. In some embodiments, the plasma source power and bias power levels of S3 may be substantially similar to each other. The duration time for S3 state may range from about 5 to 50 % of a pulse period for a four-state pulsing scheme. In some embodiments, the duration of the S3 state is less than that of the S1 state. For the S4 state, the plasma source power and / or the bias power may be 0 or at least lower than those in the S1 and S3 states. The duration time for S4 state may range from about 5 to 50 % of a single sour-state pulsing scheme. In some embodiments, the duration of the S4 state is less than that of the S1 state.

[0065] Incorporating at least two intermediate power states (e.g., S3 and S4) in a multi-state RF pulsing scheme may overcome process development limits and barriers in existing etch technologies. Overall, the multi-state RF pulsing can have the benefit of controlling the critical dimensions of neck CD (i.e., the CD of openings in the mask over the layer(s) to be etched). Controlling only the first and second states, including controlling11955-1WO / LAMR1P036WO the pulse width of the first states, has provided adequate selectivity but inadequate local etch depth non-uniformity. It has been observed that introducing a third state provides ion- assisted passivation at sidewall to reduce / protect bowing of a layer as well as low lateral etch while opening the neck CD. Additionally, it has been observed that introducing a fourth state slows the bow growth rate without impacting etch selectivity.

[0066] Figures 4A-4D schematically illustrate etch mechanisms that may be associated with states S1-S4 of a multi-step pulsing scheme in Figure 3. The etch mechanisms are shown with ions and neutrals distributed on the sidewalls of a mask 410 and an evolving etch feature 420. As an example, Figures 4A-4D may correspond to S1-S4 states, respectively, in Figure 3. In the depicted example, the feature 420 is etched in a first layer 430 of a first material and a second layer of a second material 440. Of course, this two layer structure is presented only for the purpose of illustration, and some implementations employ more than two layers having different compositions and dielectric and / or electrical properties. As an example, the first and second layers 430 and 440 may be part of a stack such as a mold stack employed for fabricating a component of a memory device such as a capacitor for a DRAM, a contact for a 3D NAND device, or other suitable component.

[0067] Figure 4A schematically illustrates a possible mechanism associated with etching while applying a high plasma source power and a high bias power according to, e.g., the conditions of the S1 state in the four-state pulsing scheme in Figure 3. As illustrated, these conditions substantially remove the material under the openings of the patterned mask 410 to form the features 420. Due in part to the high bias power, the etching operation of state S1 produces high energy ions, which are depicted in Figure 4A as vertical arrows, and are responsible for removing most of the material during the multi- state etching process. While not shown in Figure 4A, it is noted that during etching in the S1 state, a clogging deposit may form in the openings of mask 410 and / or near the top of the features 420, thereby decreasing the neck CD.

[0068] After etching under the conditions of S1, state S2 is conducted. As illustrated in Figure 4B, this facilitates passivation of the sidewalls of etched feature 420 because neutrals (open circles) are predominantly formed over ions (closed circles) and deposited on the sidewall of the etched feature 420 and the upper regions of openings of mask 410. As explained above, S2 is implemented using a relatively low plasma source power and bias power. For example, the bias power is adjusted to substantially 0, and the plasma source power is adjusted to substantially 0 or a particularly low level. Passivation may be performed under conditions that favor producing neutrals rather than ions and allow the11955-1WO / LAMR1P036WO neutrals to deposit and adhere to the sidewalls of the mask openings and feature sidewalls. Neutral passivation may reduce or prevent unacceptably large bow CD. In some embodiments, neutrals travel down the etched features 420 and deposit on or near an area where a bow would normally form underneath the mask 410 or other neighboring portions of the etched feature 420. As a consequence, the bow CD is prevented from unnecessarily widening by the impingement of ions or other energetic species in S2 or any subsequent states of the pulsing scheme. Further, due to the low energy nature of state S2, mask faceting may be limited.

[0069] As illustrated in Figure 4C, state S3 may be cause ions, in addition to neutrals, to be deposited along the length of the etched feature 420. In some embodiments, a plasma source power level that is less than that of the S1 state, and a bias power level of substantially 0 or a low value may be applied to further control lateral etching of the etched feature 420. To the extent that a clogging deposit is formed in the S1 state may, it may be removed or reduced in the S3 state.

[0070] As schematically illustrated in Figure 4D, the S4 state that follows the S3 state produces a reduced density of ions compared to the S3 state. As described herein, the S3 state may provide etch conditions that control lateral etching. Adding an additional pulse state (the S4 state here) can further tune the lateral etching and corresponding bow CD, while improving the uniformity of the etched feature depth and the selectivity between the mask and the etched features. As explained, in the S4 state, the plasma source power and the bias power levels may be less than the plasma source power and bias power levels in the S3 state. S1, S2, S3, S4 Pulse Characteristics

[0071] Table 1 below presents example power ranges for each of the four states that are employed in the multistate pulsing regime.

[0072] Alternatively, or in addition to the details in Table 1, the multi-state pulsing regime11955-1WO / LAMR1P036WO may be characterized by other features such as, for example, any one or more of the following: S1 always has the highest plasma source and bias powers. S2 always has no bias. S2 and S4 are the only states that are optionally performed with no plasma present. S1 and S3 always have plasma present. S3 and / or S4 optionally have no bias power, but when they do have bias, it has substantially lower power than the bias power of S1. Compared to S4, S3 usually has both higher source and bias powers.

[0073] In certain embodiments, the source frequency in any of the states is about 10 to 100 MHz (e.g., about 40 MHz or about 60 MHz). In certain embodiments, the bias frequency in any of the states is about 100 to 1000 kHz (e.g., 400 kHz). In some implementations, the source and / or bias frequency remains constant across all states in a cycle. In other implementations, at least one of the source and / or bias frequency varies between at least two states in a cycle.

[0074] Note that while these examples illustrate four states in a multi-state pulsing scheme, a pulse period may have additional states. For example, a pulse period may have five states, six states, etc. Further, while the multi-state scheme illustrated here shows the states occurring in a particular sequence - S1 occurs before S2, S2 occurs before S3, S3 occurs before S4, and S4 occurs before S1 - in some implementations, one or more of these states has its position adjusted within the sequence of a cycle.

[0075] A multi-state pulse period may have any of various duration. In some embodiment, the period has a duration of about 200 to 3000 microseconds or about 500 to 2000 microseconds or about 800 to 2000 microseconds. The pulsing period may also be characterized by a repetition rate, which in certain cases is about 10 Hz to 20 kHz or about 10 Hz to 10 kHz. In typical HAR etch processes, the pulse period occurs many times (e.g., at least about 1000 times) before etching is complete.

[0076] Regarding duty cycle, the S1, the state with the highest power, may have a duty cycle of about 5 to 60 % or about 5 to 50 % of a pulse period a multi-state (e.g., four-state) pulsing scheme. In one embodiment, the duration time for the S1 state occupies about 5 % of a pulse period and has a pulse width of about 40 to 1000 microseconds. In certain embodiments, S2 occupies most of the multi-state period. For example, S2 may occupy11955-1WO / LAMR1P036WO at least about 50 % of a cycle or it may occupy about 50 to 70 % of a cycle. In certain embodiments, the pulse width of the S1 state is about 40 to 1000 microseconds, about 5 to 500 microseconds, or about 50 to 100 microseconds.

[0077] Figures 5A and 5B illustrate experimental work showing how adding a third state, and then fourth state to a multi-state pulsing scheme can improve etch performance. In Figure 5A, the vertical axis represents the critical dimension (CD) growth rate, and the horizontal axis represents the total power from the source and bias generators in the S3 state. It is desirable to maintain the CD growth rate at a minimum level or close to 0 during etching. In the context of Figures 5A and 5B, the CD growth rate refers to the growth rate of the features’ bow CD related to etch depth penetration. In Figure 5B, the vertical axis represents the critical dimension growth rate, and the horizontal axis represents the power from the source generators (flux) in the S4 state. Other than as explained in the following description, the etch conditions in the processes represented by the graphs in Figures 5A and 5B are identical. For example, all experiments were conducted at a pressure of 9 mTorr, and all experiments employed the same mask pattern and mask hole geometry. The primary differences in the experiments were the number of pulse states and plasma powers applied in the S3 and S4 states.

[0078] In Figure 5A, at a value of 0 W power for the S3 state, the etching system operates with essentially only two states, S1 and S2. In the two-state experiments, one of the states has non-zero source and bias power and the other state has no source or bias power. In this two-state operating regime, the CD growth rate, as measured, is represented by a point 503 in Figure 5A. Under the two-state etch conditions, the etch performance was measured and is described below for comparison with a three-state pulsing scheme (Figure 5A) and a four-state pulsing scheme (Figure 5B).

[0079] In the experiment represented by Figure 5A, a third state S3 was introduced, and its performance was tested over five different power levels. As can be seen in Figure 5A, for a total power of about 1000 W during the S3 state, the CD growth rate reaches a minimum. See point 505. Note that when the S3 power increased from 1000 W to 1500 W, the performance as measured by CD growth rate decreased.

[0080] Thus, in the experiments conducted to produce the Figure 5A graph, a three-state pulse scheme in which S3 had a total power of 1000 W produced the best CD growth rate performance. Note that other than the differences in power during S3, the process conditions were not changed in any way between the various points represented in the plot of Figure 5A.11955-1WO / LAMR1P036WO

[0081] Figure 5B illustrates further advantages that may be achieved by introducing a fourth state, S4. In this graph, the first three states employed in the experiments of Figure 5A at point 505 are fixed, and an additional state S4 is added. Thus, the S3 state employed in the experiments of Figure 5B has a total power of about 1000 W, representing the best performance achieved using the three-state pulse regime.

[0082] The etch conditions of point 505 from Figure 5A are illustrated as point 511 in Figure 5B. This point corresponds to a flux power of zero for the S4 state. In other words, point 511 in Figure 5B represents a three-state pulsing regime. All other points in Figure 5B were represent results of etch processes using four pulse states.

[0083] As shown in Figure 5B, with increasing flux power applied to state S4, the CD growth rate improves (i.e., the CD growth rate decreases) significantly until at least about 500 W. See point 515. The CD growth rate may further improve modestly to a power level of 1000 W. However, when the power level reaches 1500 W, the CD growth rate becomes worse. Thus, the experiments conducted to prepare the graphs in Figures 5A and 5B indicate that a four-state pulse scheme employing 1000 W total power for the S3 state and 500 to 1000 W flux power for the S4 state produced the best results in terms of CD growth rate.

[0084] Further characterization of the etch performance at points 503 (two states) and 515 (four states with 1000 W for S3 and 500 W for S4) was conducted. At point 503, the bow CD was measured to be 19.2 nanometers, the etch depth nonuniformity was measured to be 118 nm, and the mask selectivity was measured to be 4.97. These values are provided for an average etch depth of 550 nm. By contrast, when etching under the conditions shown at point 515, for the same average etch depth, 550 nm, the bow CD was 17.0 nm, the etch depth nonuniformity was 78 nm, and the mask selectivity was 6.56. Thus, introduction of the four-state pulsing regime provided a significant benefit in terms of controlling the bow CD, etch depth nonuniformity, and mask selectivity. Etchant Chemistry

[0085] Etch processes disclosed herein may be partially characterized by, for example, their process gas composition.

[0086] In certain embodiments, the etchant chemistry includes a fluorine source and a carbon source. Examples of fluorine sources include hydrogen fluoride (HF), phosphorus trifluoride (PF3), carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), silicon tetrafluoride (SiF4), tungsten hexafluoride (WF6), molybdenum hexafluoride11955-1WO / LAMR1P036WO (MoF6), and ruthenium hexafluoride (RuF6). Examples of carbon sources include all volatile hydrocarbons (CxHy) and hydrofluorocarbons (CxHyFz, where z>0), e.g., CH2F2.

[0087] In certain embodiments, the etchant chemistry includes a fluorine source and a carbon source as described above, and additionally one or more additional gases. Examples of such additional gases include hydrogen chloride (HCl), hydrogen bromide (HBr), hydrogen iodide (HI), carbon trifluoro iodide (CF3I), helium (He), and carbonyl sulfide (COS). In certain embodiments, the etch chemistry includes a reducing agent (e.g., molecular hydrogen) and / or an oxidizer (e.g., molecular oxygen).

[0088] In some implementations, the etchant chemistry includes hydrogen fluoride, phosphorus trifluoride (PF3), molecular hydrogen (H2), and nitrogen trifluoride (NF3). In some implementations, the etchant chemistry additionally includes a fluorocarbon such as carbon tetrafluoride (CF4) and / or a hydrofluorocarbon such as difluoromethane (CH2F2).

[0089] The components of the etchant process gas may be present in any of various ratios. As examples, etchant gases used to process a 300 mm wafer may have flow rates in the following ranges: NF3: 0-100sccm; CF4: 0-100 sccm; CH2F2: 0-100 sccm; HF: 0-500 sccm; H2: 0-1000 sccm; PF3: 0-100sccm.

[0090] In some implementations, non-reactive gases such as nitrogen (N2), argon (Ar), and / or helium (He) may be used to modulate plasma properties. Examples of the flow rates for a 300 mm wafer include the following: N20-500sccm Ar 0-500 sccm He 0-300 sccm Temperature

[0091] In some embodiments, the temperature range of the substrate or the substrate support is about 80°C to 150°C. In some embodiments supporting cryogenic processing, the temperature of the substrate or the substrate support is about -100 to 200 °C, about - 100 to 0 °C, about -80 to 40°C, or about -40 to 0°C. In some embodiments, the etch process11955-1WO / LAMR1P036WO proceeds using both cryogenic and non-cryogenic temperature domains. Thus, the temperature may change or even alternate over the course of a feature etch. For example, part of a feature etch process may be run at -60°C, and then the process has a temperature equilibration step, and finally, the remaining part of the feature etch process is run at 20°C. In some implementations, the etch apparatus comprises a multiple-channel chiller to change substrate temperature to utilize both cryogenic and non-cryogenic etching regimes. Pressure

[0092] In some embodiments, the pressure in the plasma etch chamber is at least a partial vacuum. For example, the pressure may be about 1 to 1000 mTorr, about 2 to 400 mTorr, or about 2 to 200 mTorr.

[0093] Very low pressures such as down to about 2 mTorr or even 1 mTorr may facilitate deep, HAR etching. Such applications require a very narrow angular distribution of ions reaching the substrate surface. Ideally, all ions would reach the surface in a direction that is perpendicular to the plane of the surface. However, this is not possible because some ions contact gas molecules or atoms in the etch chamber. Any ions that contact gas molecules or atoms as they travel toward the substrate will deflect and introduce some deviation from the ideal perfectly perpendicular ion angle distribution. Very low pressures such as about 2 mTorr or even 1 mTorr may reduce the occurrence of such collisions and therefore improve the ion angle distribution. Process Sequence

[0094] In some embodiments, different process conditions are used for different phases of the etch process as disclosed herein. For example, an aspect ratio dependent RF power modulation may be employed. In one implementation, a first set of etch conditions may be employed to etch an upper portion of the feature, where for example, some of a first silicon nitride-based mold layer may reside. Thereafter, a second set of etch conditions may be employed to etch an intermediate or lower portion of the feature.

[0095] In some embodiments, different phases based on the aspect ratio of the feature being etched are associated with different purposes such as opening a neck CD, reducing a Bow CD, and improving a bottom CD. As an example, applying low power regime at the beginning of the mold etch may provide a relatively radical-dominant regime to open a neck CD while the feature is being etched. Thereafter, the process may apply a relatively higher power regime to introduce more directional ions to make the profile straight.11955-1WO / LAMR1P036WO

[0096] Figure 6 is a flow chart illustrating an example etch process 600 as disclosed herein. For example, the example etch process 600 may comprise etch conditions applied to a structure comprising two or more layers having different compositions. As illustrated, the process begins with the system (e.g., a plasma etch chamber as described herein) receiving a substrate having a layer to be etched and a patterned mask as disclosed herein. See block 610. Next, the substrate is positioned on a wafer support such as a chuck, e.g., an electrostatic chuck. See block 620. Thereafter, the substrate is subjected to a multi- phase etch process that employs at least two different etch process windows applied in sequence, each optionally associated with a distinct aspect ratio in the small feature being etched. At least one of the different etch process windows employs a multi-state pulsing scheme employing at least four states, S1-S4, as described herein. More specifically, the process employs successive etch operations 630, 640, 650, and 660 that employ different etch process windows, or at least each successive etch process window is different than the previous one, allowing that one or more of the process windows may repeat. Integration and Applications

[0097] The etch processes described herein may be employed to etch any of many different types of features and many different types of materials and mold structures. As indicated, such features may be etched using particular etch conditions comprising multi-state plasma control (e.g., source and bias multi-state pulsing), process gas chemistries (e.g., hydrogen- fluoride containing etchants), low temperatures (e.g., cryogenic), and any combination thereof. The etched features may have shapes such as cylindrical, polygonal, trench, etc.

[0098] In certain embodiments, the feature etched in accordance with this disclosure has as an aspect ratio of at least about 10:1 or at least about 20:1 or at least about 30:1. In some cases, the feature has an aspect ratio of about 45:1 to about 70:1.

[0099] In certain embodiments, a feature etched in accordance with this disclosure is used in a memory application such as fabrication of a DRAM array or 3D NAND memory device. In the context of DRAM fabrication, an etched feature may be used as a mold for a capacitor.

[0100] In certain embodiments, the material to be etched may comprise a doped or undoped silicon oxide. The dopant may be one or more of nitrogen, carbon, or their combination. For example, the material may include a silicon nitride, a silicon oxynitride, a silicon oxycarbide, or a silicon oxycarbonitride. The material to be etched may be two11955-1WO / LAMR1P036WO or more layers, each layer made of the doped or undoped silicon oxide described herein, depending on the dielectric or electrical properties of the application.

[0101] It should be understood that the disclosed etch processes and apparatus are not limited etching mold stacks or other structures for memory devices. The etch process and apparatus according to some embodiments may be applied to any application requiring forming a plurality of small sized features having a high aspect ratio.

[0102] An etch stop layer is optionally present at bottom of the material to be etched (e.g., a mold stack). An etch stop layer may comprise tungsten or other suitable etch stop material for the feature etch conditions as known to those of skill in the art.

[0103] In some embodiments, the mask is made from amorphous carbon and is patterned with openings corresponding to the locations, sizes, and shapes of the features to be etched in the mold stack. In certain embodiments, a carbon mask layer is characterized by its sp2-content. Apparatus and System

[0104] Figure 7 illustrates a schematic diagram of a plasma processing system according to some embodiments. Figure 7 illustrates a schematic diagram of a control module for controlling the systems described in Figure 6 according to some embodiments.

[0105] Various implementations described herein may be performed in a plasma processing system. With reference to FIG. 7, an example plasma processing system or apparatus may include a chamber 701 having a gas injector / showerhead / nozzle 703 for distributing gases (705, 707, 709) (e.g. reactant and purge gases) or other chemistries (e.g., one or more etch process gas chemistries as described herein, such as hydrogen fluoride (HF), phosphoric trifluoride (PF3), nitrogen trifluoride (NF3), molecular hydrogen (H2), etc) into the chamber 701, chamber walls 711, a chuck 713 for holding a substrate or wafer 715 to be processed (e.g., etched) which may include electrostatic electrodes for chucking and dechucking the substrate or wafer. The chuck 713 is heated for thermal control, enabling heating or cooling of the substrate or wafer 715 to a desired temperature during a substrate processing such as etching the substrate having a layer to be etched. In some embodiments, the temperature of the substrate may be controlled between about - 100 to 200 °C. In some implementations, the chuck 713 may include an electrode to be electrically charged using a plasma bias generator 717 to provide a bias RF power to the substrate or wafer 715 in accordance with embodiments of the disclosure.11955-1WO / LAMR1P036WO

[0106] A plasma source generator 719 is configured to supply source RF power to an electrode, e.g., an inductively coupled plasma electrode to generate a plasma 725 in the process space over the substrate 715. In some implementations, the chamber walls 711 are heated to support thermal management and efficiency. A vacuum source 727 provides a vacuum to evacuate gases from the chamber 701. The system or apparatus may include a system controller 729 for controlling some or all of the operations of the chamber or apparatus such as modulating the chamber pressure, inert gas flow, source RF power, source frequency, reactive gas flow; bias RF power, bias frequency, temperature, vacuum settings; and other process conditions.

[0107] In some implementations, a system / apparatus may include more than one chamber for processing substrates.

[0108] FIG.8 shows a control module 800 for controlling the systems described above, in accordance with implementations of the disclosure. For instance, the control module 800 may include a processor, memory, and one or more interfaces. The control module 800 may be employed to control devices in the system based in part on sensed values. For example, the control module 800 may control one or more of valves 802, filter heaters 804, pumps 806, and other devices 808 based on the sensed values and other control parameters. The control module 800 receives the sensed values from, for example only, pressure manometers 810, flow meters 812, temperature sensors 814, and / or other sensors 816. The control module 800 may also be employed to control process conditions during reactant delivery and plasma processing. The control module 800 will typically include one or more memory devices and one or more processors.

[0109] The control module 800 may control activities of the reactant delivery system and plasma processing apparatus. The control module 800 executes computer programs including sets of instructions for controlling process timing, delivery system temperature, pressure differentials across the filters, valve positions, mixture of gases, chamber pressure, chamber temperature, wafer temperature, RF power levels, e.g., source RF power level and / or bias RF power level, wafer ESC or pedestal position, and other parameters of a particular process. The control module 800 may also monitor the pressure differential and automatically switch vapor reactant delivery from one or more paths to one or more other paths. Other computer programs stored on memory devices associated with the control module 800 may be employed in some implementations.

[0110] Typically, there will be a user interface associated with the control module 800. The user interface may include a display 818 (e.g., a display screen and / or graphical11955-1WO / LAMR1P036WO software displays of the apparatus and / or process conditions), and user input devices 820 such as pointing devices, keyboards, touch screens, microphones, etc.

[0111] Computer programs for controlling delivery of reactant, plasma processing and other processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C,Pascal, Fortran or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program.

[0112] The control module parameters relate to process conditions such as, for example, filter pressure differentials, process gas composition and flow rates, substrate temperature, chamber pressure, plasma conditions such as RF power levels, e.g., source RF power levels and / or bias RF power level, and the RF frequency, e.g., source RF frequency and / or bias RF frequency, duty cycle, cooling gas pressure, and chamber wall temperature.

[0113] The system software may be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control operation of the chamber components necessary to carry out the inventive deposition processes. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, heater control code, and plasma control code. Conclusion

[0114] In the foregoing description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments are described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.

[0115] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, structures, systems, and apparatus of the present embodiments. Accordingly, the present11955-1WO / LAMR1P036WO embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

11955-1WO / LAMR1P036WO CLAIMS what is claimed is:

1. A method of etching features in the substrate, the method comprising: receiving in an etch chamber a substrate comprising a first layer to be etched and a mask over the first layer, wherein the mask is patterned with openings at locations where features are to be etched; and etching features in the first layer by exposing the substrate to etch conditions comprising a multi-state pulsing scheme having a pulse period of at most about 3000 microseconds and comprising a first state S1, a second state S2, a third state S3, and a fourth state S4 all occurring once within the pulse period, wherein among the states S1, S2, S3, and S4, state S1 has the highest magnitudes of a plasma source power and a plasma bias power, wherein S2 has no bias power, wherein S3 and S4 have source plasma powers and / or the bias plasma powers that are different, and wherein S3 has a bias power that is lower than the S1 bias power, and S4 has a bias power that is lower than the S1 bias power.

2. The method of claim 1, wherein the source plasma power and the bias plasma power for S1 range from about 1 to 20 kW and about 10 to 100 kW, respectively.

3. The method of claim 1 or claim 2, wherein the source plasma power for S2 ranges from 0 to about 1500 W and wherein the bias plasma power for S2 is 0 W.

4. The method of any of claims 1-3, wherein the source plasma power and the bias plasma power for S3 range from about 0.3 to 3 kW and 0 to about 3 kW, respectively.

5. The method of any of claims 1-4, wherein the source plasma power and the bias plasma power for S1 range from 0 to about 1 kW and 0 to about 300 W, respectively.11955-1WO / LAMR1P036WO 6. The method of claim 1, wherein the source plasma power for the states has a frequency of about 10 to 100 MHz, and wherein the bias plasma power for the states has a frequency of about 100 to 1000 kHz.

7. The method of any one of claims 1-6, wherein S1, S2, S3, and S4 occur in this sequential order within the pulse period.

8. The method of any one of claims 1-7, wherein the pulse period occurs with a repetition rate of about 10 Hz to 20 kHz.

9. The method of any one of claims 1-8, wherein S1 has a duty cycle of about 5 to 60 % of the pulse period.

10. The method of any one of claims 1-9, wherein S2 occupies at least about 50 % of the pulse period.

11. The method of any one of claims 1-10, wherein S1 has a pulse width of about 40 to 1000 microseconds.

12. The method of any one of claims 1-11, wherein the etch conditions comprise supplying the etch chamber with an etchant gas comprising a fluorine-containing component and a carbon-containing component.

13. The method of claim 12, wherein the fluorine-containing component comprises HF, NF3, CF4, PF3, SF6, SiF4, WF6, MoF6, RuF6, or any combination thereof.

14. The method of claim 12, wherein the carbon-containing component comprises a hydrocarbon or a hydrofluorocarbon.

15. The method of any one of claims 1-14, wherein the etch conditions comprise a pressure in the etch chamber of about 2 to 400 mTorr.11955-1WO / LAMR1P036WO 16. The method of any one of claims 1-15, wherein the etch conditions comprise a temperature of the substrate of about -100 to 200 °C.

17. The method of any one of claims 1-16, wherein the etch conditions comprise a temperature of the substrate of about -100 to 0 °C.

18. The method of any one of claims 1-17, wherein the first layer comprises a nitrogen- doped silicon oxide layer.

19. The method of any one of claims 1-18, wherein the features to be etched are at locations of capacitors for a memory device.

20. The method of any one of claims 1-19, further comprising etching features in one or more additional layers beneath the first layer, wherein, together, the one or more additional layers and the first layer form a mold stack.

21. An apparatus for processing a substrate comprising: an etch chamber configured to receive a substrate comprising at least one layer to be etched and a mask on the at least one layer; a plasma power source for generating a plasma within the etch chamber; one or more gas inlets for providing one or more etchant species to the etch chamber; a substrate support for supporting the substrate, wherein the substrate support comprises or is associated with an electrode configured to provide bias voltage to the substrate; and a controller configured to cause: etching features in the at least one layer by exposing the substrate to etch conditions comprising a multi-state pulsing scheme having a pulse period of at most about 3000 microseconds and comprising a first state S1, a second state S2, a third state S3, and a fourth state S4 all occurring once within the pulse period, wherein among the states S1, S2, S3, and S4, state S1 has the highest magnitudes of a plasma source power and a plasma bias power, wherein S2 has no bias power,11955-1WO / LAMR1P036WO wherein S3 and S4 have source plasma powers and / or bias plasma powers that are different, and wherein S3 has a bias power that is lower than the S1 bias power, and S4 has a bias power that is lower than the S1 bias power.

22. The apparatus of claim 21, wherein the plasma power source comprises a transformer coupled plasma (TCP) power source.

23. The apparatus of claim 21 or claim 22, wherein the controller is further configured to cause the source plasma power and the bias plasma power for S1 to range from about 1 to 20 kW and about 10 to 100 kW, respectively.

24. The apparatus of any one of claims 21-23, wherein the controller is further configured to cause the source plasma power for S2 to range from 0 to about 1500 W and cause the bias plasma power for S2 to be 0 W.

25. The apparatus of any one of claims 21-24, wherein the controller is further configured to cause the source plasma power and the bias plasma power for S3 to range from about 0.3 to 3 kW and 0 to about 3 kW, respectively.

26. The apparatus of any one of claims 21-25, wherein the controller is further configured to cause the source plasma power and the bias plasma power for S1 to range from 0 to about 1 kW and 0 to about 300 W, respectively.

27. The apparatus of claim 21, wherein the controller is further configured to cause the source plasma power for the states to have a frequency of about 10 to 100 MHz, and cause the bias plasma power for the states to have a frequency of about 100 to 1000 kHz.

28. The apparatus of any one of claims 21-27, wherein the controller is further configured to cause S1, S2, S3, and S4 to occur in this sequential order within the pulse period.11955-1WO / LAMR1P036WO 29. The apparatus of any one of claims 21-28, wherein the controller is further configured to cause the pulse period to occur with a repetition rate of about 10 Hz to 20 kHz.

30. The apparatus of any one of claims 21-29, wherein the controller is further configured to cause S1 to have a duty cycle of about 5 to 60 % of the pulse period.

31. The apparatus of any one of claims 21-30, wherein the controller is further configured to cause S2 to occupy at least about 50 % of the pulse period.

32. The apparatus of any one of claims 21-31, wherein the controller is further configured to cause S1 to have a pulse width of about 40 to 1000 microseconds.

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