Ldmos power chip packaging structure under large-scale array

Abstract

An LDMOS power chip packaging structure under a large-scale array. The LDMOS power chip packaging structure under a large-scale array comprises a plurality of sub-regions; the sub-regions are arranged in an array; a plurality of LDMOS transistors connected in parallel are provided in each sub-region; gates / drains / sources of LDMOS transistors in the same sub-region are respectively connected to the same gate / drain / source PAD; the sources of the LDMOS transistors in the same sub-region are arranged in a plurality of rows along a first direction; the drains of the LDMOS transistors in the same sub-region are arranged in a plurality of rows along the first direction; all source PADs are connected to source strips in an RDL1; all drain PADs are connected to drain strips in the RDL1; all gate PADs are connected to a control IC signal pin of an IC drive circuit; all source strips are connected to source PADs in an RDL2; all drain strips are connected to drain PADs in the RDL2; the source PADs are packaged by means of a Cu Clip packaging process and then led out as input terminals of a power chip; and the drain PADs are packaged by means of the Cu Clip packaging process and then led out as output terminals of the power chip.

Description

LDMOS power chip packaging structure under large-scale array TECHNICAL FIELD

[0001] The present application relates to the field of LDMOS power chips, in particular to an LDMOS power chip packaging structure under large-scale array. BACKGROUND

[0002] For power devices, as shown in FIG. 1, the existing technical solution is to connect the control IC and the power tube using a dedicated aluminum bonding wire (wire bonding) method, which requires connecting the metal lead and the chip pad (windowed pin). Since the power tube needs to be designed separately, the IC and the power tube need to be combined and sealed before product production. Common power tubes include Power DMOS, IGBT, etc. Since the resistivity of aluminum is higher than that of other metals, when the current is too large, the aluminum bonding wire lead will continuously emit a lot of heat. In addition, the bonding surface is a Cu-Al interface, which will cause stability problems over time. Due to the poor stability of aluminum wire bonding, high-frequency parasitic parameters, insufficient heat dissipation, low temperature resistance, insufficient insulation strength, and other problems limit the performance of power devices. Because of the combined packaging form, the actual driving IC can only be designed as a simple power driver, making it difficult to complete complex function design such as power tube and driving IC integration. At the same time, for some technical solutions in certain scenarios, the cost of traditional GaN and SiC power devices is high, so it is difficult to make a low-cost universal product.

[0003] Therefore, integrating the power tube and the control chip is a better solution that can ensure the same effect while achieving high reliability and high complexity chip design. If LDMOS is directly used to replace power devices, the back-end metal trace will be difficult to layout well for ultra-low Rdson (on-resistance) applications, and a large parasitic resistance will also be introduced, thereby increasing Rdson. Since a lower Rdson is required, a large number of LDMOS devices are connected in parallel to achieve a lower impedance level. Since the source-drain IO interface is very large, it is impossible to use it scientifically in the later packaging and wire bonding. If this problem is not solved, it will be difficult to replace it with a low-cost LDMOS solution.

[0004] If the aluminum bonding wire method is used, the direct impact is that the Rdson will increase significantly. Since the contact surface is limited by the aluminum bonding wire, the Rdson will be severely reduced. For applications that require high on-resistance, it undoubtedly increases unnecessary power consumption and causes a series of energy dissipation problems. Aluminum wire bonding also introduces the risk of aluminum-copper interface failure. If this method is used, the efforts to optimize Rdson in LDMOS will be severely lost in packaging.

[0005] Therefore, to realize low-cost power drive, the layout planning and packaging form of LDMOS need to be solved to replace power devices in high-voltage applications, and a chip integrated with power devices and drive is designed, so that a replacement with excellent performance can be realized.

[0006] SUMMARY

[0007] The present application provides a large-scale array LDMOS power chip packaging structure to solve the technical problems existing in the prior art.

[0008] To achieve the above purpose, the present application provides a large-scale array LDMOS power chip packaging structure, which integrates LDMOS tubes and IC drive circuits on the same power chip. The plan view of the power chip is rectangular, and the IC drive circuit is located at one corner of the rectangle,

[0009] The large-scale array LDMOS power chip packaging structure includes a plurality of sub-regions arranged in an array form. Each sub-region includes a plurality of parallel LDMOS tubes. The gates of the LDMOS tubes in the same sub-region are connected to the same gate PAD. The sources of the LDMOS tubes in the same sub-region are connected to the same source PAD. The drains of the LDMOS tubes in the same sub-region are connected to the same drain PAD. The sources of the LDMOS tubes in the same sub-region are arranged in multiple rows along a first direction. The drains of the LDMOS tubes in the same sub-region are arranged in multiple rows along the first direction,

[0010] All the source PADs are connected to the source strips in the RDL1 layer,

[0011] All the drain PADs are connected to the drain strips in the RDL1 layer,

[0012] All the gate PADs are connected to the control IC signal pins of the IC drive circuit,

[0013] All the source strips are connected to the source PADs in the RDL2 layer,

[0014] All the drain strips are connected to the drain PADs in the RDL2 layer,

[0015] The source PADs are packaged by Cu Clip packaging process and led out as input pins of the power chip,

[0016] The drain PADs are packaged by Cu Clip packaging process and led out as output pins of the power chip.

[0017] In an embodiment of the present application, the connection of the gate, drain and source of the LDMOS tubes in the same sub-region to the same gate, drain and source PAD is achieved by using the front-end process FEOL.

[0018] The large-scale array LDMOS power chip packaging structure provided by the present application introduces the design form of LDMOS array, not only realizes a lower Rdson, but also greatly reduces the cost compared with the existing power devices (such as PDMOS, GaN, SiC, etc.); the two-layer RDL layer is introduced to complete the large-scale array LDMOS back-end packaging design, the source / drain electrodes are introduced, and the back-end metal wiring and metal overcurrent capacity problems are further solved; the Cu Clip method (the existing technology uses aluminum wire) can realize high-reliability packaging design and high-heat dissipation packaging design, the source / drain PAD is introduced through the RDL, so that the additional on-resistance introduced at the packaging level can be reduced, and the excellent on-state performance is maintained. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] FIG. 1 is a schematic diagram of the existing power device using a dedicated aluminum bonding wire (wire bonding) to connect the control IC and the power tube;

[0021] FIG. 2 is a cross-sectional schematic diagram of a large-scale array LDMOS power chip packaging structure according to an embodiment of the present application;

[0022] FIG. 3 is a schematic diagram of the planar layout of the LDMOS tube and the IC driving circuit on the power chip;

[0023] FIG. 4 is a schematic diagram of a sub-region;

[0024] FIG. 5 is a schematic diagram of the RDL1 layer;

[0025] FIG. 6 is a schematic diagram of the RDL2 layer;

[0026] FIG. 7 is a schematic diagram of the power chip packaging forming input / output pins. DETAILED DESCRIPTION

[0027] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below, obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application.

[0028] The present application provides a packaging scheme for LDMOS power application under large-scale array, through a special packaging mode, the LDMOS under large-scale array is used for the power scene application of ultra-low resistance, high current and high stability. Under the application of large array LDMOS combination, a higher reliability integrated IC conduction scheme can be provided. For the LDMOS array combination application under a larger area, most of the prior art is realized by parallel connection of a large number of LDMOS tubes. Due to the existence of a large number of IO port interconnections, the back-end metal wiring and packaging become complex, and the introduction of a large number of parasitic increases the source-drain conduction resistance (hereinafter referred to as Rdson). In addition, the traditional aluminum bonding line (wire bonding) packaging technology faces problems such as aluminum line heating failure, large high-frequency parasitic parameters, insufficient heat dissipation capacity, low temperature resistance, insufficient insulation strength, etc. Therefore, the scheme is difficult to play the performance of the power tube, and the scheme of combining the power tube and the control IC for packaging is expensive and has a single function.

[0029] The present application provides a new packaging scheme for LDMOS power application under large-scale array, which replaces the traditional combined packaging power device with LDMOS as the main power device, introduces two redistribution layers (RDL (ReDistribution Layer), hereinafter referred to as RDL1, RDL2), and the PAD (window) of the source (Source) and drain (Drain) is connected out through the Cu Clip (copper strip bonding) mode, which realizes the design of the MOS tube under large-scale array as a power MOS application, can realize lower Rdson, and can solve the problems of weak heat dissipation capacity, insufficient insulation strength, poor stability and other disadvantages under the traditional wire bonding.

[0030] Figure 2 is a cross-sectional view of a large-scale array LDMOS power chip packaging structure according to an embodiment of the present application, and Figure 3 is a planar layout diagram of an LDMOS tube and an IC driving circuit on a power chip. The present application provides a large-scale array LDMOS power chip packaging structure, which integrates the LDMOS tube and the IC driving circuit (chip IC control part) on the same power chip, as shown in Figure 3. The plan view of the power chip is rectangular, and the IC driving circuit is located at one corner of the rectangle. In fact, Figure 3 is only a schematic, and the area of the IC driving circuit is generally small, and the position of the IC driving circuit can also be arranged according to actual needs.

[0031] The LDMOS power chip packaging structure under large-scale array includes multiple sub-regions, and a schematic diagram of one sub-region is shown in Fig. 4. Generally, each sub-region is identical and includes source and drain in the same direction. The multiple sub-regions are arranged in an array form. Each sub-region includes multiple parallel LDMOS tubes. The gates of the LDMOS tubes in the same sub-region are connected to the same gate PAD. The sources of the LDMOS tubes in the same sub-region are connected to the same source PAD. The drains of the LDMOS tubes in the same sub-region are connected to the same drain PAD. The sources of the LDMOS tubes in the same sub-region are arranged in multiple rows along a first direction. The drains of the LDMOS tubes in the same sub-region are arranged in multiple rows along the first direction. As shown in Figs. 4 and 5, the sources and the drains are divided into lines. The rows of the sources and the rows of the drains are staggered.

[0032] All the source PADs are connected to the source strips in the RDL1 layer. A schematic diagram of the RDL1 layer is shown in Fig. 5.

[0033] All the drain PADs are connected to the drain strips in the RDL1 layer. As shown in Fig. 5, the RDL1 layer includes multiple source strips and multiple drain strips.

[0034] All the gate PADs are connected to the control IC signal pins of the IC driving circuit.

[0035] All the source strips are connected to the source PADs (source windowing) in the RDL2 layer. A schematic diagram of the RDL2 layer is shown in Fig. 6.

[0036] All the drain strips are connected to the drain PADs (drain windowing) in the RDL2 layer.

[0037] The source PADs are packaged as input pins of the power chip through the Cu Clip packaging process. A schematic diagram of the power chip packaging to form input / output pins is shown in Fig. 7.

[0038] The drain PADs are packaged as output pins of the power chip through the Cu Clip packaging process.

[0039] In an embodiment of the present application, the gates, the drains and the sources of the LDMOS tubes in the same sub-region are connected to the same gate, drain and source PADs through the FEOL process.

[0040] The LDMOS power chip packaging structure under a large-scale array provided by the application introduces the design form of the LDMOS array, realizes a lower Rdson, and greatly reduces the cost compared with existing power devices (such as PDMOS, GaN, SiC, etc.); the two-layer RDL layer is introduced to complete the large-scale array LDMOS back-end packaging design, the source / drain electrodes are introduced, and the back-end metal wiring and metal current-carrying capacity problems are further solved; the Cu Clip method (the existing technology uses aluminum wires) can realize high-reliability packaging design and high-heat-dissipation packaging design, the source / drain PAD is introduced through the RDL, so that the additional on-resistance introduced at the packaging level can be reduced, and the excellent on performance is maintained.

[0041] Those skilled in the art can understand that the drawings are only schematic diagrams of an embodiment, and the modules or flows in the drawings are not necessarily necessary for implementing the application.

[0042] Those skilled in the art can understand that the modules in the device in the embodiment can be distributed in the device in the embodiment according to the embodiment description, or can be changed and located in one or more devices different from the embodiment. The modules in the above embodiment can be combined into one module, or can be further split into multiple sub-modules.

[0043] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the application, and not to limit them; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the application.

Claims

1. A large scale array down LDMOS power chip package structure, characterized in that, The LDMOS power chip packaging structure under large-scale array integrates the LDMOS tube and the IC driving circuit on the same power chip, the plan view of the power chip is rectangular, and the IC driving circuit is located at one corner of the rectangle, The LDMOS power chip packaging structure under large-scale array includes a plurality of sub-regions, the plurality of sub-regions are arranged in an array form, each sub-region internally includes a plurality of parallel LDMOS tubes, the gates of the LDMOS tubes located in the same sub-region are respectively connected to the same gate PAD, the sources of the LDMOS tubes located in the same sub-region are respectively connected to the same source PAD, the drains of the LDMOS tubes located in the same sub-region are respectively connected to the same drain PAD, the sources of the LDMOS tubes located in the same sub-region are arranged into multiple rows along a first direction, and the drains of the LDMOS tubes located in the same sub-region are arranged into multiple rows along the first direction, All the source PADs are connected to the source strips in the RDL1 layer, All the drain PADs are connected to the drain strips in the RDL1 layer, All the gate PADs are connected to the control IC signal pins of the IC driving circuit, All the source strips are connected to the source PADs in the RDL2 layer, All the drain strips are connected to the drain PADs in the RDL2 layer, The source PADs are packaged by a Cu Clip packaging process and led out as input pins of the power chip, The drain PADs are packaged by a Cu Clip packaging process and led out as output pins of the power chip.

2. The LDMOS power chip package structure under large scale array according to claim 1, characterized in that, The gates / drains / sources of the LDMOS tubes located in the same sub-region are respectively connected to the same gate / source / drain PADs by using a front-end-of-line process FEOL.

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