Flash memory die, chip, device, and data processing method

Abstract

The present application relates to the field of data processing, and provides a flash memory die, a chip, a device, and a data processing method. The flash memory die comprises a control module and a plurality of plane groups. At least two plane groups among the plurality of plane groups may start to perform a data processing operation at different start moments, thereby avoiding insufficient power supply caused by excessive peak current during the operation of the flash memory die.

Description

Flash memory die, chip, device and data processing method

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411111121.3, filed on August 13, 2024, and entitled "Flash memory die, chip, device and data processing method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of computer technology, and in particular to a flash memory die, chip, device and data processing method. BACKGROUND

[0004] Flash memory has the advantages of fast read speed, fast write speed, high reliability, strong durability, etc. These advantages make flash memory a common storage solution. NAND flash memory is a typical flash memory. NAND flash memory includes a flash memory chip (or referred to as a storage chip). The flash memory chip includes one or more flash memory dies, which can also be referred to as logic units (LUs) or bare chips. A flash memory die includes multiple planes, each of which includes a cache and multiple blocks, and each block includes multiple pages.

[0005] In the process of storing data in NAND flash memory, data can be cached in the cache of each of the multiple planes in the flash memory die, respectively, and then the data is concurrently written into the pages corresponding to each plane in the flash memory die. However, concurrent writing of data by multiple flash memory dies results in a large peak current of the NAND flash memory, which in turn causes a power supply shortage problem. SUMMARY

[0006] The present application provides a flash memory die, chip, device and data processing method to solve the problem of power supply shortage.

[0007] In a first aspect, an embodiment of the present application provides a flash memory grain. The flash memory grain can also be referred to as a logical unit, or a bare chip, etc. The flash memory grain includes a plurality of plane groups, a first plane group in the plurality of plane groups performs a first data processing operation on first data at a first start time; a second plane group in the plurality of plane groups performs a second data processing operation on second data at a second start time, the first start time is different from the second start time, the first data and the second data are data expected to be processed simultaneously, and the first data processing operation and the second data processing operation are operations of the same type. For example, the first data processing operation and the second data processing operation are both programming operations, or both erasing operations. Optionally, one of the plane groups includes one or more planes, one plane includes a plurality of blocks, and one block includes a plurality of pages.

[0008] In an embodiment of the present application, because the current generated when a plane group starts to perform a data processing operation is large, the start times of the first plane group and the second plane group performing the data processing operation are staggered in the embodiment of the present application, so that the times when the two plane groups generate large currents are staggered, thereby reducing the peak current of the flash memory grain and avoiding the problem of insufficient power supply.

[0009] In a possible implementation, the flash memory grain further includes a first trigger module and a second trigger module; the first trigger module is connected with the first plane group, and the first trigger module is configured to trigger one or more planes included in the first plane group to perform the first data processing operation on the first data at the first start time; the second trigger module is connected with the second plane group, and the second trigger module is configured to trigger one or more planes included in the second plane group to perform the second data processing operation on the second data at the second start time.

[0010] In this way, the trigger module can accurately trigger the planes in the plane group to perform the data processing operation, and one trigger module can trigger a plurality of planes in one plane group to perform the data processing operation, so that the number of trigger modules can be relatively reduced, thereby saving the volume and cost of the flash memory grain.

[0011] In a possible implementation, each plane group in the plurality of plane groups includes one plane; and the start times of any two planes in the plurality of planes included in the plurality of plane groups performing the same type of data processing operation are different.

[0012] In this way, the times when the peak current is generated by each plane can be staggered to the greatest extent, and the peak current of the flash memory grain can be reduced to the greatest extent. In addition, the flexibility of the plurality of planes performing the data processing operation is increased.

[0013] In a possible implementation, the start times of the plurality of planes included in the first plane group performing the first data processing operation on the first data are the same; and the start times of the plurality of planes included in the second plane group performing the second data processing operation on the second data are the same.

[0014] In this way, the two plane groups can be managed in groups, and the multiple planes in one plane group can be uniformly and efficiently managed.

[0015] In a possible implementation, the first time interval is a first time length.

[0016] In this way, the time length of the interval between the start times at which the same type of data processing operation is started to be performed between the two plane groups is determined, and the start times at which the data processing operation is started to be performed by the two plane groups can be accurately controlled.

[0017] In a possible implementation, the first plane group includes multiple planes, and the second plane group includes multiple planes; the flash memory particle further includes multiple first trigger modules and multiple second trigger modules, the multiple first trigger modules are connected to the multiple planes in the first plane group one by one respectively, and each first trigger module is configured to trigger one plane in the first plane group to perform a first data processing operation on first data at a first start time; the multiple second trigger modules are connected to the multiple planes in the second plane group one by one respectively, and each second trigger module is configured to trigger the multiple planes in the second plane group to perform a second data processing operation on second data at the first start time.

[0018] In this way, the number of trigger modules can be the same as the number of planes, and the multiple planes can be triggered by the multiple trigger modules to perform the data processing operation, so as to independently control the start times at which the multiple planes perform the data processing operation, and the peak current of the flash memory particle can be minimized.

[0019] In a possible implementation, the first data processing operation and the second data processing operation are both programming operations, and the first time length is less than or equal to a second time length, where the second time length is a time length required for any plane group in the multiple plane groups to receive data from the host chip, and the data is data to be written into the flash memory particle. Optionally, the data amount of the data can be equal to the product of the data storage amount of one page and a first number, and the first number is the number of planes included in one plane group in the multiple plane groups.

[0020] In this way, during the time period in which one plane group receives data, the other plane group can perform the programming operation, that is, the time period in which the programming operation is performed can be reused for the time period in which the plane group receives data, so that the overall time length of the flash memory particle performing the data processing operation can be shortened, and the efficiency of the flash memory particle performing the data processing operation can be ensured.

[0021] In a possible implementation, the control module is further configured to receive the first time length configured by the host chip; or the control module is configured with the first time length out of the factory.

[0022] In this way, the first time length can be flexibly set by the user through the master chip, thereby improving the flexibility of setting the first time length. Alternatively, the first time length is configured out of the factory, which is conducive to reducing the interaction times between the flash memory particles and the master chip.

[0023] In a second aspect, the embodiments of the present application provide a flash memory chip. The flash memory chip includes a plurality of flash memory particles packaged in a package form, and any flash memory particle in the plurality of flash memory particles is the flash memory particle in the first aspect and any possible implementation manner.

[0024] In the embodiments of the present application, since the current generated when the plane group starts to perform the data processing operation is large, the start time of the data processing operation of the first plane group and the second plane group is staggered in the embodiments of the present application, so that the time when the two plane groups generate large current is staggered, thereby reducing the peak current of the flash memory particle and avoiding the problem of insufficient power supply. In addition, in the case of deploying a plurality of flash memory particles in a NAND flash memory, the plurality of flash memory particles can still perform the data processing operation concurrently, thereby ensuring the efficiency of the NAND flash memory in performing the data processing operation and ensuring the performance of the NAND flash memory.

[0025] In a third aspect, the embodiments of the present application provide a storage device. The storage device includes the flash memory chip as described in the second aspect, and a master chip, wherein the master chip is configured to control the storage chip to perform a data processing operation.

[0026] The storage device can be a device or component with a storage function, for example, a solid-state disk (SSD) or a universal flash storage (UFS).

[0027] In a fourth aspect, the embodiments of the present application provide an electronic device. The electronic device includes the storage device in the third aspect. The electronic device can be a terminal device or a server.

[0028] In a fifth aspect, an embodiment of the present application provides a data processing method. The method can be applied to a flash memory chip. Optionally, the method can be executed by the flash memory chip or a module in the flash memory chip, such as a control module in the flash memory chip, without specific limitation. The flash memory chip includes a plurality of plane groups. The method includes: controlling a first plane group in the plurality of plane groups to perform a first data processing operation on first data at a first start time; and controlling a second plane group in the plurality of plane groups to perform a second data processing operation on second data at a second start time; wherein the first start time is different from the second start time, the first data and the second data are data expected to be processed simultaneously, and the first data processing operation and the second data processing operation are operations of the same type. Optionally, one plane group includes one or more planes, one plane includes a plurality of blocks, and one block includes a plurality of pages.

[0029] In a possible implementation, the first data processing operation and the second data processing operation are both programming operations, and the flash memory chip further includes a first trigger module and a second trigger module; the controlling of the first plane group in the plurality of plane groups to perform the first data processing operation on the first data at the first start time includes: triggering, by the first trigger module, the first plane group to start writing the first data at the first start time, the first data being data received by the first plane group from a host chip; and the controlling of the second plane group in the plurality of plane groups to perform the second data processing operation on the second data at the second start time includes: triggering, by the second trigger module, the second plane group to start writing the second data at the second start time, the second data being data received by the second plane group from the host chip.

[0030] In a possible implementation, each plane group in the plurality of plane groups includes one plane; and any two planes in the plurality of planes included in the plurality of plane groups perform the data processing operation at different start times.

[0031] In a possible implementation, the plurality of planes included in the first plane group perform the first data processing operation at the same start time; and the plurality of planes included in the second plane group perform the second data processing operation at the same start time.

[0032] In a possible implementation, the first start time and the second start time are separated by a first time length.

[0033] In a possible implementation, the first data processing operation and the second data processing operation are both programming operations, and the first time length is less than or equal to a second time length, wherein: the second time length is a time length required for any plane group in the plurality of plane groups to receive data from a host chip, the data being data to be written into the flash memory chip. The data amount of the data can be equal to a product of a page data storage amount and a first number, the first number being a number of planes included in one plane group in the plurality of plane groups.

[0034] In a possible implementation, the method further includes: the control module receives the first time length configured by the master chip; or the control module is configured with the first time length out of the factory.

[0035] In a possible implementation, the method further includes: the control module receives the number of planes included in any plane group configured by the master chip; or the control module is configured with the number of planes included in any plane group out of the factory.

[0036] In a sixth aspect, an embodiment of the present application provides a data processing apparatus. The data processing apparatus can be the flash memory particle in the fifth aspect, or a component or device including the flash memory particle, or a module capable of implementing the function of the flash memory particle. The data processing apparatus includes means or modules for performing the corresponding functions of the fifth aspect or any possible implementation. For example, the data processing apparatus includes a communication unit (also referred to as a communication module). Optionally, the communication apparatus further includes a processing unit (also referred to as a processing module). The communication unit is configured to perform a transceiving operation, such as functions related to sending and receiving; the communication unit can be referred to as a transceiving unit; optionally, the communication unit includes a receiving unit and a sending unit. The processing unit is configured to perform a processing operation. Alternatively, the communication unit can be a transmitter and a receiver, or the communication unit is a transmitter and a receiver.

[0037] For example, the processing unit is configured to control a first plane group in the plurality of plane groups to perform a data processing operation at a first start time; and control a second plane group in the plurality of plane groups to perform a data processing operation at a second start time; wherein the first start time is different from the second start time.

[0038] The data processing apparatus can also perform the content of any possible implementation of the fifth aspect, which will not be listed one by one.

[0039] In a seventh aspect, an embodiment of the present application provides a computer program product. When the computer program product is executed, the method in the fifth aspect and any possible implementation is executed.

[0040] In an eighth aspect, an embodiment of the present application provides a computer readable storage medium. The computer readable storage medium stores a computer program or instructions, when the computer program or instructions are executed, the method in the fifth aspect and any possible implementation is executed. BRIEF DESCRIPTION OF DRAWINGS

[0041] FIG. 1 is a structural schematic diagram of a storage device according to an embodiment of the present application;

[0042] FIG. 2 is a structural schematic diagram of an SSD according to an embodiment of the present application;

[0043] FIG. 3 is a structural schematic diagram of a flash chip according to an embodiment of the present application;

[0044] FIG. 4A is a structural schematic diagram of a flash grain according to an embodiment of the present application;

[0045] FIG. 4B is a structural schematic diagram of another flash grain according to an embodiment of the present application;

[0046] FIG. 5 is a structural schematic diagram of yet another flash grain according to an embodiment of the present application;

[0047] FIG. 6 is a process schematic diagram of a master chip processing data according to an embodiment of the present application;

[0048] FIG. 7 is a timing schematic diagram of a plurality of plane groups performing a programming operation according to an embodiment of the present application;

[0049] FIGS. 8-10 are structural schematic diagrams of three kinds of flash grains according to embodiments of the present application;

[0050] FIG. 11 is a current change schematic diagram of a plurality of plane groups concurrently performing a programming operation;

[0051] FIG. 12 is a current change schematic diagram of a flash grain performing a programming operation according to an embodiment of the present application;

[0052] FIG. 13 is a structural schematic diagram of an electronic device according to an embodiment of the present application;

[0053] FIG. 14 is a schematic diagram of a data processing method according to an embodiment of the present application;

[0054] FIG. 15 is a schematic diagram of a data processing apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0055] The embodiments of the present application will be described in further detail below with reference to the drawings.

[0056] The following explains some terms in the embodiments of the present application to facilitate understanding by those skilled in the art.

[0057] 1、Data processing operation refers to some operations on data processing. The data processing operation involved in the embodiments of the present application includes an operation that can or can be able to cause a NAND flash to generate a large current (or current spike), for example, a program operation or an erase operation. The program operation refers to an operation of writing data into a storage medium (such as a NAND flash). The program operation can also be referred to as a write operation or a data write operation, etc. The erase operation refers to an operation of deleting data in a NAND flash, and also deleting metadata of the data in the NAND flash.

[0058] The first data processing operation and the second data processing operation involved in the embodiments of the present application can be taken as two examples of data processing operations. The first data processing operation and the second data processing operation can be operations of the same type, such as both being program operations or both being erase operations.

[0059] 2、Flash grain, which can also be referred to as a bare chip or a logic unit, etc., is a product form before a semiconductor component is manufactured and packaged. After packaging, it is referred to as a component part of a semiconductor element. The flash grain is a basic unit that accepts and executes a flash command in a NAND flash.

[0060] 3、Flash chip, which can also be referred to as package (PKG), refers to a semiconductor chip that is packaged by multiple flash grains and presents as a whole to the outside. The flash chip referred to in the embodiments of the present application is a packaged NAND flash chip. Generally, one flash chip is composed of one or more flash grains. Optionally, one or more flash grains can constitute a target, and one target corresponds to one chip enable (CE) line, or a chip enable pin. Correspondingly, one flash chip can include one or more targets. The chip enable line is used to select or deselect a target.

[0061] 4、Plane, a flash grain has multiple planes. The number and type of planes included in a flash grain are different according to different manufacturers. Concurrent operation of multiple planes under the same flash grain can be referred to as a multi-plane (MP) operation. One plane includes a cache and multiple blocks, and one block includes multiple pages. The cache includes one or more cache registers, for example.

[0062] 5、Block, also can be called as flash block. Each plane can include a plurality of blocks, and the block is the minimum unit (or unit) for the NAND flash to perform an erase operation. The size of the block refers to the total storage amount of the block, including the total amount of valid data and check data of the valid data that the block can store. One block can include a plurality of pages. The check data can be used to assist in recovering data. The valid data refers to the data useful to the user, which can also be called as user data.

[0063] 6、Page, is the minimum unit (or unit) for the NAND flash to perform a programming operation. The size of the page refers to the total storage amount of the page, including the valid data and check data that the page can store. The total storage amount of the page includes a valid data storage space and a redundancy space (or a spare space). The valid data storage space is used to store valid data, and the redundancy space can be used to store check data and the like. The data storage amount of the page in the embodiment of the present application can be the total storage amount of the page, or the maximum capacity of the valid data that the page can store. For example, the size of the valid storage space of a page is 16 kilobytes (KB), and the size of the redundancy space of a page is 2 KB, and the data storage amount of the page can be 16 KB. The size of the valid data storage space and the size of the redundancy space can be arbitrary, and the embodiment of the present application does not make specific limitation thereto.

[0064] 7、Plane group, refers to one or more planes are divided into a group to realize that one or more planes are uniformly operated and managed. The number of planes included in any two plane groups can be the same or different, and no specific limitation is made thereto.

[0065] In the embodiment of the present application, the number of nouns, unless otherwise specified, indicates "a singular noun or a plural noun", that is, "one or more". "At least one" refers to one or more, and "a plurality of" refers to two or more. "And / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, and B exists alone, wherein A and B can be singular or plural. The character " / " generally represents that the associated objects before and after are in an "or" relationship. For example, A / B represents: A or B. "At least one of the following" or the like refers to any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b, or c, represents: a, b, c, a and b, a and c, b and c, or a and b and c, wherein a, b, and c can be single or multiple.

[0066] Unless specifically stated, the ordinal numbers "first", "second", etc. mentioned in the embodiments of the present application are used to distinguish the multiple objects, and are not used to limit the position, sequence, time sequence, priority or importance of the multiple objects. For example, "first plane group" and "second plane group" in the embodiments of the present application are used to distinguish two plane groups, but do not limit the setting positions or the number of included planes of the two plane groups.

[0067] In order to solve the problem of power shortage of the NAND flash memory, the embodiments of the present application provide a flash memory grain. In the flash memory grain, the time when multiple plane groups start to perform a data processing operation can be staggered, that is, the multiple plane groups perform the data processing operation in staggered parallel or peak-shifting parallel, so that the peak current of the flash memory grain can be reduced, and thus the peak current of the NAND flash memory can be reduced to avoid the problem of power shortage. For the NAND flash memory including multiple flash memory grains, the multiple flash memory grains can still perform the data processing operation concurrently, which ensures the efficiency of the NAND flash memory in performing the data processing operation and also ensures the performance of the NAND flash memory.

[0068] The flash memory grain in the embodiments of the present application can be applied (or set) in a storage device for storing data. The storage device can be a device or storage medium with a storage function, for example, a solid-state disk (SSD), a universal flash storage (UFS), a network card, a redundant array of independent disks (RAID) card, an embedded multimedia card (eMMC) / embedded multi-chip package (eMCP) card, or a flash disk (USB flash drive), which can also be referred to as a U disk, etc. The embedded multi-chip package card is a device in which the eMMC and low power double data rate (LPDDR) memory are packaged together.

[0069] Please refer to FIG. 1, which is a structural schematic diagram of a storage device provided by the embodiments of the present application. As shown in FIG. 1, the storage device 100 includes a flash memory chip 110 and a master control chip 120. The number of the flash memory chip 110 included in the storage device 100 can be one or more, which is not specifically limited. The flash memory chip 110 includes one or more flash memory grains. The flash memory chip 110 is used for storage. The master control chip 120 can be an embedded microchip. The master control chip 120 is the brain center of the storage device 100, which is responsible for some complex tasks, such as managing data storage, maintaining the performance and service life of the storage device 100, etc.

[0070] Optionally, the storage device further comprises a power management unit (PMU) for powering the flash chips 110 and the master chip 120.

[0071] The structure of the storage device will be exemplarily introduced below in combination with a structural schematic diagram of an SSD shown in FIG. 2.

[0072] The SSD 200 is a storage device mainly using flash memory as a permanent memory. As shown in FIG. 2, the SSD 200 comprises a NAND flash memory and a master chip 210. The NAND flash memory comprises a plurality of flash chips 214 for storing data. The content of the master chip 210 can refer to the content of the master chip 120 in the foregoing FIG. 1, or the master chip 210 can be an example of the master chip 120 shown in FIG. 1. The master chip 210 shown in FIG. 2 can comprise a processor 212, which functions like a command center to issue all operation instructions of the SSD 200. For example, the processor 212 can execute functions such as reading / writing data, garbage collection and wear leveling through the firmware of the processor 212.

[0073] In the embodiment of the present application, the processor 212 can process data write instructions, data read instructions and data erase instructions and the like from a host. For example, in response to the data write instruction, data is stored in the flash chips 214. For another example, in response to the data read instruction, data is read from the flash chips 214 and fed back to the host. For another example, in response to the data erase instruction, data in the flash chips 214 is erased.

[0074] The master chip 210 of the SSD 200 further comprises a host interface 211 and a plurality of channel controllers 213. The host interface 211 is used for communication with a host. Each channel corresponds to a channel controller 213, and the channels are channel 0, channel 1, …, channel n and the like as shown in FIG. 2. Each channel controller 213 is used for controlling the flash chips 214 in the corresponding channel. Through the plurality of channel controllers 213, the master chip 210 can operate a plurality of flash chips 214 in parallel, thereby improving the underlying bandwidth. For example, assuming that there are 8 channels between the master chip 210 and the flash chips 214, the master chip 210 reads and writes data to the 8 flash chips 214 in parallel through the 8 channels.

[0075] Any of the flash memory chips 214 can include a plurality of flash memory dies packaged in a package form. The package form is used to define a packaging method of the flash memory chip, which specifically defines a packaging structure and / or a packaging process of the flash memory chip, etc. The packaging structure, for example, includes at least one of a physical structure, a size, a pin layout, or a manner of connecting to an external circuit of the flash memory chip. The package form, for example, includes a thin outline package (TSOP), a ball grid array (BGA), or a chip on board (COB).

[0076] The TSOP is a thin outline package form, which is characterized by having chip pins on both sides of the flash memory chip. The TSOP package is suitable for being directly attached to a surface of a printed circuit board (PCB) using a surface-mount technology (SMT), has a low parasitic parameter, is suitable for high-frequency applications, is easy to operate, and has a high reliability. The BGA package technology is a ball grid array package form, which is characterized by having a large number of signal contacts in a ball-shaped solder form on the bottom of the flash memory chip. The BGA package can provide a higher pin density, improve the electrical and thermal performance, and provide better heat dissipation performance and signal transmission quality due to the solder being located on the bottom of the flash memory chip.

[0077] The COB is a method of directly connecting the flash memory dies to the PCB, for example, by using a microelectrode array and an adhesive to precisely connect the chip to the PCB. This packaging technology can reduce the materials required for packaging, improve the reliability and stability of the circuit, and is particularly suitable for applications requiring miniaturization and high performance.

[0078] Please refer to FIG. 3, which is a structural schematic diagram of a flash memory chip provided by an embodiment of the present application. The flash memory chip 300 shown in FIG. 3 can be used as an example of the flash memory chip 110 in FIG. 1 or the flash memory chip 214 in FIG. 2. In FIG. 3, the flash memory chip 300 includes at least one target, such as the targets 310a and 310b shown in FIG. 3. The target 310a includes the flash memory dies 311a and 311b. The flash memory dies 311a and 311b share at least one enable line. The target 310b includes the flash memory dies 311c and 311d. The flash memory dies 311c and 311d share at least one enable line. The flash memory dies 311a and 311c share at least one signal line. The flash memory dies 311b and 311d share at least one signal line. The signal line is used to transmit an electrical signal, such as an analog signal or a digital signal. The signal line, for example, includes an input / output (I / O) line.

[0079] The structure of the flash memory grain involved in the embodiments of the present application will be introduced below in combination with FIG. 4A. The flash memory grain shown in FIG. 4A can be taken as an example of any of the flash memory grains in FIG. 3 (such as the flash memory grain 311a, the flash memory grain 311b, the flash memory grain 311c or the flash memory grain 311d).

[0080] As shown in FIG. 4A, the flash memory grain 400 includes a plurality of plane groups, such as the plane group 410a and the plane group 410b. Any of the plurality of plane groups can include one or more planes. Correspondingly, the plurality of plane groups include a plurality of planes. The number of planes included in any two plane groups can be the same or different, which is not limited specifically. FIG. 4A is taken as an example that the plane group 410a and the plane group 410b each include one plane, which does not limit the number of planes included in one plane group in practice.

[0081] Any of the plane group 410a and the plane group 410b contains a plurality of blocks, for example, the plane group 410a includes the block 411a and the block 411b, and the plane group 410b includes the block 411c and the block 411d. The numbering of the blocks in the plane group 410a and the plane group 410b can be single-double cross.

[0082] A block is composed of a plurality of pages, for example, the block 411a includes the page 421a, the page 421b, the page 421c and the page 421d, the block 411b includes the page 421e, the page 421f, the page 421g and the page 421h, the block 411c includes the page 421i, the page 421j, the page 421k and the page 421m, and the block 411d includes the page 421n, the page 421o, the page 421p and the page 421q. The embodiments of the present application can have different specifications for the size of the page, the capacity of the block and the capacity of the flash memory grain, which are not limited.

[0083] The plane group 410a and the plane group 410b in the embodiments of the present application perform the same type of data processing operation at different time points, for example, the plane group 410a performs a first data processing operation on first data at a first start time point, and the plane group 410b performs a second data processing operation on second data at a second start time point different from the first start time point. The content of the first data processing operation and the second data processing operation can be respectively referred to the content of the first data processing operation and the second data processing operation discussed above. The first data and the second data are data expected to be processed simultaneously. Alternatively, it can be said that the scheme of the embodiments of the present application is applicable to the scenario that a plurality of plane groups are expected to perform data processing operations simultaneously or in parallel.

[0084] The first data and the second data are data expected to be processed simultaneously, for example, the first data and the second data are data for which the host expects the flash grain 400 to perform a programming operation simultaneously or in parallel, or the first data and the second data are data for which the host expects the flash grain 400 to perform an erasing operation simultaneously or in parallel. Specifically, the first data and the second data are data requested by a same data processing request, and then it can be considered that the host expects the flash grain 400 to process the first data and the second data simultaneously or in parallel. The data processing request is, for example, a data writing request for requesting to write the first data and the second data simultaneously or in parallel. Alternatively, the data processing request is, for example, a data erasing request for requesting to erase the first data and the second data simultaneously or in parallel.

[0085] Since the plane group 410a and the plane group 410b perform the same type of data processing operation at different time points, the peak current of the two plane groups is staggered, and the peak current of the flash grain 400 is reduced.

[0086] In a possible implementation, the flash grain further includes a control module, and the control module controls the plane group 410a and the plane group 410b to respectively perform the first data processing operation and the second data processing operation at different time points.

[0087] The following is an example description in combination with the flash grain 400 shown in FIG. 4B. The flash grain 400 shown in FIG. 4B can be used as an example of any of the flash grains in FIG. 3 (for example, the flash grain 311a, the flash grain 311b, the flash grain 311c, or the flash grain 311d) or the flash grain 400 in FIG. 4A.

[0088] As shown in FIG. 4B, the flash grain 400 includes a control module 420, a plane group 410a, and a plane group 410b. FIG. 4B shows two plane groups, and the number of plane groups is not limited in practice. The plane group 410a and the plane group 410b in FIG. 4B can be used as an example of the plane group 410a and the plane group 410b in FIG. 4A, respectively.

[0089] The control module 420 is a module with a control capability. The control module 420 can be implemented by a circuit. Based on a control instruction from a host chip, the control module 420 controls the plane group 410a and the plane group 410b to respectively perform the first data processing operation and the second data processing operation at different starting time points, respectively.

[0090] The following is an example description of the structure of the control module 420 in combination with the schematic diagram of the flash grain shown in FIG. 5.

[0091] As shown in FIG. 5, the flash memory particle 400 includes a control module 420, a plane group 410a and a plane group 410b. The control module 420 includes an input / output control circuit 510, a control circuit 520, an instruction register 530 and an address register 540. FIG. 5 exemplarily shows a structure of the control module 420, but in fact, the control module 420 can have various structures, which are not specifically limited.

[0092] The plane group 410a includes a plane 550a, which includes a block 551a and a block 551b. The block 551a includes a page 552a and a page 552b, and the block 551b includes a page 552c and a page 552d. Optionally, the plane 550a further includes a page register 553a and a cache 554a.

[0093] The plane group 410b includes a plane 550b, which includes a block 551c and a block 551d. The block 551c includes a page 552e and a page 552f. The block 551d includes a page 552g and a page 552h. Optionally, the plane 550b further includes a page register 553b and a cache 554b.

[0094] The contents of the first data processing operation and the second data processing operation are different, and the processes of the plane group 410a and the plane group 410b for performing the first data processing operation and the second data processing operation are also different, which will be introduced in the following cases.

[0095] A1, the first data processing operation and the second data processing operation are both programming operations, and the control module 420 controls the plane group 410a and the plane group 410b to start performing the programming operations at different start times.

[0096] Exemplarily, the host can send a data write request to the master control chip, where the data write request is used to request writing data. The data write request can carry the data to be written and the logical address of the data to be written. The data to be written includes, for example, first data and second data.

[0097] After receiving the data write request, the master control chip can map the logical address of the data to be written into a physical address of the flash memory particle 400, so as to obtain first address information of the first data and second address information of the second data. The master control chip can also perform the writing data in various ways, which are not specifically limited.

[0098] In the embodiment of the application, the first address information refers to an address for storing the first data in the flash memory particle 400, for example, the page 552a. The second address information refers to an address for storing the second data, for example, the page 552e.

[0099] Further, the master chip sends a first write instruction to the flash memory chip 400. The first write instruction includes a first program command, first data to be written, and first address information. The first program command is used to instruct to write the first data. The flash memory chip 400 performs a program operation based on the first write instruction.

[0100] For example, the input / output control circuit 510 receives the first write instruction from the master chip and transmits the first address information to the address register 540. The address register 540 stores the first address information. The input / output control circuit 510 transmits the first program command to the instruction register 530. In addition, the input / output control circuit 510 can cache the first data in the cache 554a or the page register 553a.

[0101] After the plane group 410a caches the first data, the master chip can send a second write instruction to the flash memory chip 400. The second write instruction includes a program command, second data to be written, and second address information. The second program command is used to instruct to write the second data. The flash memory chip 400 performs a program operation based on the second write instruction.

[0102] For example, the input / output control circuit 510 receives the second write instruction from the master chip and transmits the second address information to the address register 540. The address register 540 stores the second address information, which can indicate that the address is the page 552e. The input / output control circuit 510 transmits the second program command to the instruction register 530. In addition, the input / output control circuit 510 can cache the second data in the cache 554b or the page register 553b.

[0103] After the plane group 410b caches the second data, the control circuit 520 reads the first program command in the instruction register 530 and controls the plane group 410a to start writing the first data at a first start time. For example, the control circuit 520 can transmit a control signal to the plane group 410a at the first start time, which instructs the plane group 410a to start writing the first data.

[0104] For example, the storage address of the first data is the page 552a. The following B1 or B2 is used to introduce the way of writing the first data to the plane group 410a.

[0105] B1, the page register 553a writes the first data into the page 552a of the plane group 410a at the first time.

[0106] B2, the cache 554a writes the first data to the page register 553a, and the page register 553a writes the first data to the page register 553a of the plane group 410a. Optionally, after the cache 554a writes the first data to the page register 553a, the cache 554a can cache other data.

[0107] Further, the host chip can query whether the programming operation of the plane group 410a is completed through a first query command. If the programming operation of the plane group 410a is completed, the host chip can query whether the programming operation of the plane group 410a is successful through a second query command. If the programming operation of the plane group 410a is successful, the host chip can continue to transmit other data to the plane group 410a, and so on.

[0108] After the control circuit 520 reads the first programming command in the instruction register 530, the control circuit 520 reads a second programming command in the instruction register 530, and controls the plane group 410b to start writing the second data at a second start time different from the first start time. For example, the control circuit 520 can transmit a control signal to the plane group 410b at the second start time, and the control signal instructs the plane group 410b to start writing the first data.

[0109] Taking the storage address of the page 552e of the second data as an example, the way of writing the second data to the plane group 410b is introduced in the following C1 or C2.

[0110] C1, the page register 553b writes the second data to the page 552e of the plane group 410b.

[0111] C2, the cache 554b writes the second data to the page register 553b, and the page register 553b writes the second data to the page 552e of the plane group 410b. Optionally, after the cache 554b writes the second data to the page register 553b, the cache 554b can cache other data.

[0112] Further, the host chip can query whether the programming operation of the plane group 410a is completed through a first query command. If the programming operation of the plane group 410a is completed, the host chip can query whether the programming operation of the plane group 410a is successful through a second query command. If the programming operation of the plane group 410a is successful, the host chip can continue to transmit other data to the plane group 410a, and so on.

[0113] If the plane group 410a and the plane group 410b each include a plurality of planes, the host chip can divide the first data into a plurality of data blocks, and the first address information can indicate the addresses of the plurality of planes of the plane group 410a for writing the data blocks, respectively. In this way, the plurality of planes of the plane group 410a can write the plurality of data blocks of the first data, respectively. Wherein, the way of writing the data blocks by any plane in the plane group 410a can refer to the content of writing the first data by the plane 550a, which will not be listed one by one here. The plurality of planes of the plane group 410a write part of the data in the first data, respectively, to complete the writing of the first data.

[0114] Similarly, the host chip can divide the second data into a plurality of data blocks, and the second address information can indicate the addresses of the plurality of planes of the plane group 410b for writing the data blocks, respectively. In this way, the plurality of planes of the plane group 410b can write the plurality of data blocks of the second data, respectively. Wherein, the way of writing the data blocks by any plane in the plane group 410b can refer to the content of writing the second data by the plane 550b, which will not be listed one by one here. The plurality of planes of the plane group 410b write part of the data in the second data, respectively, to complete the writing of the second data.

[0115] Next, taking an example that each plane group in the plurality of plane groups includes one plane, any plane included in the plurality of plane groups can be represented as plane N, and N takes values of 0, 1, etc. in turn, and combining with the schematic diagram of the process of the host chip controlling the flash memory grain shown in FIG. 6, the functions controlled by the host chip are introduced.

[0116] S601, the host chip sets the initial value of N to 0. Exemplarily, the plurality of planes can be plane 0, plane 1, etc. in turn.

[0117] S602, the host chip queries whether the plane N programming operation is completed. If the plane N programming operation is not completed, the step of S602 is repeatedly executed. If the plane N programming operation is completed, the step of S603 is executed, that is, whether the plane N programming operation is successful is queried.

[0118] If the plane N programming operation is successful, it means that the last round of programming is successful, and the step of S604 is executed by the host chip, that is, the data of the plane N and the programming instruction are transmitted, and the programming instruction is used to instruct the plane N to execute the programming operation, which is equivalent to starting the current round of programming.

[0119] If the plane N programming operation fails, the host chip executes the step of S609, that is, enters the programming failure exception processing flow, such as reporting the programming failure, marking the block for writing data as a bad block, or replacing the address for writing data, etc.

[0120] If the plane N programming operation is successful, the master chip executes the step of S605, inquires whether the plane N is the last plane. If the plane N is not the last plane, N=N+1, and continues to execute the step of S601, and the plane N executes the programming operation. If the plane N is the last plane, the master chip executes S606, that is, determines whether there is next data to be written.

[0121] If there is next data to be written, N is set to 0, and the master chip continues to execute the step of S601. If there is no next data to be written, the master chip executes the step of S607, that is, inquires whether the multiple plane programming operation is completed.

[0122] If the multiple plane programming operation is not completed, the master chip continues the step of S607. If the multiple plane programming operation is completed, the master chip executes S608, that is, inquires whether the multiple plane programming operation is successful. If the multiple plane programming operation is not successful, the step of S609 is entered. If the multiple plane programming operation is successful, the current round of programming operation is ended.

[0123] A2, the first data processing operation and the second data processing operation are both erase operations, and the control module 420 controls the plane group 410a and the plane group 410b to start the erase operation at different start moments.

[0124] For example, the control module 420 controls the plane group 410a to start erasing data at the first start moment.

[0125] For example, the host can send a data erase request to the master chip, and the data erase request is used to request to erase data. The data erase request can carry a logical address of data to be erased. After receiving the data erase request, the master chip can map the logical address of the data to be erased into a physical address of the flash memory particle 400, so as to determine address information of the data to be erased in the flash memory particle 400, for example, including third address information and fourth address information. In addition, the master chip can also have multiple ways to erase data, which is not limited here.

[0126] For example, the third address information indicates an address such as the block 551a in the plane group 410a, and the fourth address information is, for example, the block 551c in the plane group 410b.

[0127] For example, the control module 420 receives a first erase instruction from the host chip, the first erase instruction instructs to erase data in a block in the plane group 410a. For example, the first erase instruction includes a first erase command and third address information of the data to be erased, the third address information indicates an address such as the block 551a in the plane group 410a. Also, the control module 420 receives a second erase instruction from the host chip, the second erase instruction instructs to erase data in a block in the plane group 410b. For example, the second erase instruction includes a second erase command and fourth address information of the data to be erased, the fourth address information indicates an address such as the block 551c in the plane group 410b.

[0128] The control module 420 can control the plane group 410a to erase the first data at a first start time. For example, the plane group 410a erases the first data in the block 551a in the plane group 410a. Also, the control module 420 can control the plane group 410b to erase the second data at a second start time. The plane group 410b erases the second data in the block 551c.

[0129] For example, the input / output control circuit 510 receives the first erase instruction from the host chip and transmits the third address information to the address register 540. The address register 540 stores the third address information. The input / output control circuit 510 transmits the first erase command to the instruction register 530. The control circuit 520 reads the first erase command in the instruction register 530 and controls the plane group 410a to start erasing data in the block 551a at a first start time. For example, the control circuit 520 can transmit a control signal to the plane group 410a at the first start time, the control signal instructs the plane group 410a to start erasing the first data.

[0130] Similarly, the input / output control circuit 510 receives the second erase instruction from the host chip and transmits the fourth address information to the address register 540. The address register 540 stores the fourth address information. The input / output control circuit 510 transmits the second erase command to the instruction register 530. The control circuit 520 reads the second erase command in the instruction register 530 and controls the plane group 410a to start erasing data in the block 551c at a second start time different from the first start time. For example, the control circuit 520 can transmit a control signal to the plane group 410b at the second start time, the control signal instructs the plane group 410b to start erasing the second data.

[0131] If the plane group 410a and the plane group 410b each include a plurality of planes, for example, the third address information can indicate the addresses of the plurality of planes of the plane group 410a respectively used for erasing the data blocks. In this way, the plurality of planes of the plane group 410a can respectively erase the plurality of data blocks of the first data. Wherein, the way of any plane in the plane group 410a erasing the data block can refer to the foregoing plane 550a erasing the content of the first data, which will not be listed one by one here. The plurality of planes of the plane group 410a respectively erase part of the data in the first data to complete the erasure of the first data.

[0132] Similarly, the fourth address information can indicate the addresses of the plurality of planes of the plane group 410b respectively used for erasing the data blocks. In this way, the plurality of planes of the plane group 410b can respectively erase the plurality of data blocks of the second data. Wherein, the way of any plane in the plane group 410b erasing the data block can refer to the foregoing plane 550b erasing the content of the second data, which will not be listed one by one here. The plurality of planes of the plane group 410b respectively erase part of the data in the second data to complete the erasure of the second data.

[0133] Since the current of any plane group is large when starting to perform the data processing operation, in the embodiment of the present application, the starting time of at least two plane groups to start to perform the data processing operation is staggered, so that the situation that at least two plane groups generate large current at the same time is avoided, thereby the peak current of the flash memory particle as a whole can be reduced, and the problem of insufficient power supply can be avoided. In addition, the plurality of plane groups do not have to perform the data processing operation at the same time, which is beneficial to increase the flexibility of performing the data processing operation.

[0134] The number of planes included in any plane group of the plurality of plane groups can be a factory configuration, for example, the number of planes included in any plane group is 1, 2, or 4, etc., and the value thereof is not limited. Exemplarily, the number of planes included in any plane group is configured as a factory and stored in a first register of the flash memory particle 400, and the control module 420 calls the number of planes included in any plane group from the first register to group the planes of the flash memory particle 400.

[0135] Alternatively, the number of planes included in any plane group of the plurality of plane groups is set by the host chip. Exemplarily, the host chip stores the number of planes included in any plane group in the first register, and the control module 420 schedules the number of planes included in any plane group from the first register.

[0136] If the number of planes included in any plane group of the plurality of plane groups is different, the relationship of the starting time of different planes to perform the data processing operation is different, which will be listed as follows.

[0137] In a first possible case, each of the plurality of plane groups includes one plane. Correspondingly, the plurality of plane groups includes a plurality of planes.

[0138] In this case, any two of the plurality of planes start to perform the data processing operation at different start times.

[0139] For example, the plurality of plane groups includes four plane groups. Any one of the four plane groups includes one plane. Correspondingly, the plurality of plane groups includes four planes. Any two of the four planes start to perform the data processing operation at different start times.

[0140] In this case, any two of the plurality of planes start to perform the data processing operation at different start times, which can minimize the peak current of the flash memory grain.

[0141] In a second possible case, any one of the plurality of plane groups includes a plurality of planes.

[0142] In this case, the start time of the data processing operation performed by one plane group is different from the start time of the data processing operation performed by another plane group. In addition, the start times of the data processing operation performed by the plurality of planes in any one plane group are the same.

[0143] In this case, staggering the start times of the data processing operation performed by at least two plane groups can minimize the peak current of the flash memory grain. In addition, the start times of the data processing operation performed by any two planes in the same plane group are the same, which facilitates management of the plane groups.

[0144] To facilitate the control module 420 to accurately control the start times of the data processing operation performed by different plane groups, in a possible design, the start times of the data processing operation performed by two adjacent plane groups of the at least two plane groups are separated by a first time length, such as the first start time and the second start time. The first time length may, for example, be 0.5 microseconds (us), 1 us, or 2 us, and the specific value thereof is not limited.

[0145] The first time length may, for example, be configured in the control module 420 at the factory. For example, the first time length is configured in the second register of the flash memory grain at the factory, and the control module 420 calls the first time length from the second register of the flash memory grain 400. Alternatively, the first time length may, for example, be obtained by the control module 420 from the host chip, so that the user can adjust the value of the first time length through the host chip. For example, the host chip stores the first time length in the second register, and the control module 420 schedules the first time length from the second register. The second register and the first register may, for example, be the same register or different registers, and the specific implementation is not limited.

[0146] Optionally, the first time length is less than or equal to the second time length. The second time length is a time length required for any one of the plurality of plane groups to receive data from the master chip. The data is data to be written into the flash memory die, and the size of the data is the first data amount. The first data amount can be equal to a product of a data storage amount of one page and the first number. The first number is a number of planes included in one of the plurality of plane groups. The one of the plurality of plane groups can be one of the at least two plane groups that includes the least number of planes, can be any one of the at least two plane groups, and is not specifically limited. The optional mode can be applicable to a case where the data processing operation is a program operation.

[0147] For example, any one of the plurality of plane groups includes one plane, and the first data amount is a data storage amount of one page, such as 16 KB. For another example, any one of the at least two plane groups includes 2 planes, and the data storage amount of one page is 16 KB, and the first data amount is 32 KB. For another example, one of the at least two plane groups that includes the least number of planes includes 4 planes, and the data storage amount of one page is 16 KB, and the first data amount is 64 KB.

[0148] In the optional mode described above, since the first time length is less than the second time length, the time for transmitting data of one plane group can be reused for part of the time for writing data of a certain plane group. In this way, the time length required for the flash memory die 400 to perform the data processing operation can be shortened, and the efficiency of the flash memory die 400 to perform the data processing operation can be relatively improved.

[0149] For example, continuing to use the case where the data processing operation shown in A1 includes a program operation, after the master chip queries that the plane group 410a successfully writes the first data, the plane group 410a receives a third write instruction from the master chip, and the third write instruction includes third data to be written. Since the first time length is less than the second time length, the time period for the first plane group to receive the third write instruction (or the third data) overlaps with the time period for the second plane group to write the second data. In this way, from the perspective of the flash memory die 400 as a whole, the first time length between the start time of starting to perform the program operation is covered by the time period for the plane group 410a to receive the third data from the master chip. In this way, the performance of the flash memory die 400 can be ensured while avoiding the case where the peak current of the flash memory die 400 is too large.

[0150] The following describes a timing diagram for a plurality of plane groups to perform a program operation with reference to FIG. 7. In FIG. 7, it is assumed that the plurality of plane groups include four plane groups, each of which includes one plane, and the plurality of plane groups include planes 0 to 3.

[0151] Figure 7 (1) illustrates a timing diagram of concurrent programming operations performed by multiple plane groups. As shown in Figure 7 (1), planes 0-3 serially receive first round data and concurrently perform programming operations, such as starting programming operations at time t1 to write the first round data. Planes 0-3 serially receive second round data and concurrently perform programming operations to write the second round data.

[0152] Figure 7 (2) illustrates a timing diagram of concurrent programming operations performed by multiple plane groups in an embodiment of the present application. As shown in Figure 7 (2), planes 0-3 serially receive first round data and start programming operations at different starting times, such as times t1, t2, t3 and t4, to write the first round data. Planes 0-3 serially receive second round data and start programming operations at different starting times to write the second round data. The difference between any two adjacent times among times t1, t2, t3 and t4 is a first time length.

[0153] Compared with Figure 7 (1), the delay time of the multiple plane groups performing programming operations on a group of data is concealed in the time length of the transmission of the next group of data in Figure 7 (2). In the case of reducing the peak current of the flash memory particle, the programming efficiency is not affected, thereby ensuring the performance of the flash memory particle.

[0154] To facilitate the control module to control the multiple plane groups to perform data processing operations, in a possible design, the flash memory particle further includes at least one first trigger module and at least one second trigger module. Part or all of the at least one first trigger module is used to trigger one of the multiple plane groups to perform data processing operations under the action of the control module. Part or all of the at least one second trigger module is used to trigger another of the multiple plane groups to perform data processing operations under the action of the control module. Any first trigger module or any second trigger module can be referred to as a high-voltage generation and management module or a high-voltage generation circuit module. Any first trigger module and any second trigger module can be implemented in the same way, such as by an integrated circuit.

[0155] E1, the number of trigger modules included in the at least one first trigger module is equal to the number of planes included in the first plane group, the number of trigger modules included in the at least one second trigger module is equal to the number of planes included in the second plane group, and any plane group includes one plane.

[0156] The structure of the flash memory particle under E1 will be exemplarily introduced below in combination with the flash memory particle shown in Figure 8. Figure 8 is an example in which the at least one first trigger module includes one first trigger module, the at least one second trigger module includes one second trigger module, and any plane group includes one plane.

[0157] As shown in FIG. 8, the flash memory grain 800 includes a control module 810, a trigger module 820a, a trigger module 820b, a plane group 830a, and a plane group 830b. The plane group 830a includes a plane 831a, and the plane group 830b includes a plane 831b. The trigger module 820a can be regarded as an example of at least one first trigger module, and the trigger module 820b can be regarded as an example of at least one second trigger module.

[0158] For example, the trigger module 820a is connected with the plane group 830a, and the connection includes an electrical connection. The control module 810 sends a control signal to the trigger module 820a, and the control signal is used to instruct the plane group 830a (such as the plane 831a) to start performing a first data processing operation on first data at a first start time. The trigger module 820a triggers the plane group 830a (such as the plane 831a) to start performing the first data processing operation on the first data at the first start time based on the control signal. For example, the trigger module 820a generates a level signal, and the level signal triggers the plane group 830a (such as the plane 831a) to start performing the first data processing operation on the first data at the first start time. The frequency or period of the level signal can be used to control the start time of the plane group 830a (such as the plane 831a) to perform the first data processing operation on the first data to be the first start time.

[0159] Similarly, the trigger module 820b is connected with the plane group 830b. The control module 810 sends a control signal to the trigger module 820b, and the control signal is used to instruct the plane group 830b (such as the plane 831b) to start performing a second data processing operation on second data at a second start time. The trigger module 820b triggers the plane group 830b (such as the plane 831b) to start performing the second data processing operation on the second data at the second start time based on the control signal. For example, the trigger module 820b generates a level signal, and the level signal triggers the plane group 830b (such as the plane 831b) to start performing the second data processing operation on the second data at the second start time. The frequency or period of the level signal can be used to control the start time of the plane group 830b (such as the plane 831b) to perform the second data processing operation on the second data to be the second start time.

[0160] For example, the control module 810 sends a trigger signal to the trigger module 820a and the trigger module 820b at different times respectively to ensure that the first start time and the second start time are different. Or for example, the control module 810 sends a trigger signal to the trigger module 820b after a first time length after sending a trigger signal to the trigger module 820a to ensure that the first start time and the second start time are separated by the first time length.

[0161] The flash memory grain 800 shown in FIG. 8 can be an example of the flash memory grain shown in FIG. 3, FIG. 4A, FIG. 4B or FIG. 5. The control module 810 can be an example of the control module 420. The rest of the control module 810 can refer to the content of the control module 420, and will not be listed one by one here. The plane group 830a and the plane group 830b can be examples of the plane group 410a and the plane group 410b. The rest of the plane group 830a and the plane group 830b can refer to the content of the plane group 410a and the plane group 410b respectively, and will not be listed one by one here.

[0162] In the flash memory grain 800 shown in FIG. 8, each plane group / plane corresponds to a trigger module, so that each plane group / plane can perform data processing operations independently, which is beneficial to reduce peak current and increase the flexibility of each plane to perform data processing operations.

[0163] E2, the number of trigger modules included in the at least one first trigger module is less than the number of planes included in the first plane group, and the number of trigger modules included in the at least one second trigger module is less than the number of planes included in the second plane group.

[0164] The structure of the flash memory grain under E2 will be described below by taking the flash memory grain shown in FIG. 9 as an example. FIG. 9 is an example in which the at least one first trigger module includes one first trigger module, the at least one second trigger module includes one second trigger module, and one plane group includes two planes. Different from FIG. 8, FIG. 9 takes an example in which one plane group includes two planes.

[0165] As shown in FIG. 9, the flash memory grain 900 includes a control module 910, a trigger module 920a, a trigger module 920b, a plane group 930a and a plane group 930b. The plane group 930a includes a plane 931a and a plane 931b, and the plane group 930b includes a plane 931c and a plane 931d. The trigger module 920a can be regarded as an example of the at least one first trigger module, and the trigger module 920b can be regarded as an example of the at least one second trigger module.

[0166] For example, the trigger module 920a is connected with the plane group 930a, such as the plane 931a and the plane 931b respectively. The control module 910 sends a control signal to the trigger module 920a, which is used to instruct the plane group 930a to start the first data processing operation on the first data at the first start time, such as triggering the plane 931a and the plane 931b to start the first data processing operation on the first data at the first start time. For example, the trigger module 920a generates a level signal (such as a high level signal) based on the control signal to trigger the plane group 930a to start the first data processing operation on the first data at the first start time. The frequency or period of the level signal can be used to control the start time of the plane group 930a to perform the data processing operation on the first data to be the first start time.

[0167] Similarly, the trigger module 920b is connected with the plane group 930b, such as the plane 931c and the plane 931d respectively. The control module 910 sends a control signal to the trigger module 920b, which is used to instruct the plane group 930b to start the second data processing operation on the second data at the second start time, such as triggering the plane 931c and the plane 931d to start the second data processing operation on the second data at the second start time. For example, the trigger module 920b generates a level signal (such as a high level signal) based on the control signal to trigger the plane group 930b to start the second data processing operation on the second data at the second start time. The frequency or period of the level signal can be used to control the start time of the plane group 930b to perform the second data processing operation on the second data to be the second start time.

[0168] For example, the control module 910 sends the trigger signal to the trigger module 920a and the trigger module 920b at different times respectively to ensure that the first start time and the second start time are different. For example, the control module 910 sends the trigger signal to the trigger module 920b after a first time interval after sending the trigger signal to the trigger module 920a to ensure that the first start time and the second start time are separated by the first time interval.

[0169] The flash memory grain 900 shown in FIG. 9 can be an example of the flash memory grain shown in FIG. 3, FIG. 4A, FIG. 4B or FIG. 5. Among them, the control module 910 can be an example of the foregoing control module 420. The remaining content of the control module 910 can refer to the content of the foregoing control module 420, which will not be listed one by one here. The plane group 930a and the plane group 930b can be an example of the foregoing plane group 410a and the plane group 410b. The remaining content of the plane group 930a and the plane group 930b can refer to the content of the foregoing plane group 410a and the plane group 410b respectively, which will not be listed one by one here.

[0170] The flash memory grain 900 shown in FIG. 9, each plane group corresponds to a trigger module, so that each plane group can independently perform data processing operations, which is beneficial to increase the flexibility of each plane group to perform data processing operations. In addition, the number of trigger modules deployed can be relatively reduced, and the volume and cost of the flash memory grain 900 can be reduced.

[0171] E3, the number of trigger modules included in the at least one first trigger module is equal to the number of planes included in the first plane group, the number of trigger modules included in the at least one second trigger module is equal to the number of planes included in the second plane group, and any plane group includes at least two planes.

[0172] The structure of the flash memory grain under E3 will be described below by taking the flash memory grain shown in FIG. 10 as an example. FIG. 10 is an example in which the at least one first trigger module includes two trigger modules, the at least one second trigger module includes two trigger modules, and a plane group includes two planes. Different from FIG. 9, in FIG. 10, the number of first trigger modules is two, and the number of second trigger modules is two.

[0173] As shown in FIG. 10, the flash memory grain 1000 includes a control module 1010, a trigger module 1020a, a trigger module 1020b, a trigger module 1020c, a trigger module 1020d, a plane group 1030a, and a plane group 1030b. The plane group 1030a includes a plane 1031a and a plane 1031b, and the plane group 1030b includes a plane 1031c and a plane 1031d. The trigger module 1020a and the trigger module 1020b can be regarded as an example of the at least one first trigger module, and the trigger module 1020c and the trigger module 1020d can be regarded as an example of the at least one second trigger module.

[0174] For example, the trigger module 1020a is connected with the plane 1031a, and the trigger module 1020b is connected with the plane 1031b. The control module 1010 sends a control signal to the trigger module 1020a and the trigger module 1020b respectively, which is used to instruct the plane group 1030a to start to perform the first data processing operation on the first data at the first start time. For example, the trigger module 1020a generates a level signal (e.g. a high level signal) based on the control signal to trigger the plane 1031a to start to perform the first data processing operation on the first data at the first start time. The frequency or period of the level signal can be used to control the start time of the plane 1031a to perform the first data processing operation on the first data to be the first start time. In addition, the trigger module 1020b generates a level signal (e.g. a high level signal) based on the control signal to trigger the plane 1031b to start to perform the first data processing operation on the first data at the first start time. The frequency or period of the level signal can be used to control the start time of the plane 1031b to perform the first data processing operation on the first data to be the first start time.

[0175] Similarly, the trigger module 1020c is connected with the plane 1031c, and the trigger module 1020d is connected with the plane 1031d. The control module 1010 sends a trigger signal to the plane 1031c and the plane 1031d respectively, which is used to trigger the plane group 1030b to start to perform the second data processing operation on the second data at the second start time. For example, the trigger module 1020c generates a level signal (e.g. a high level signal) based on the control signal to trigger the plane 1031c to start to perform the second data processing operation on the second data at the second start time. The frequency or period of the level signal can be used to control the start time of the plane 1031c to perform the second data processing operation on the second data to be the second start time. In addition, the trigger module 1020d generates a level signal (e.g. a high level signal) based on the control signal to trigger the plane 1031d to start to perform the second data processing operation on the second data at the second start time. The frequency or period of the level signal can be used to control the start time of the plane 1031d to perform the second data processing operation on the second data to be the second start time.

[0176] For example, the control module 1010 sends a trigger signal to the at least one first trigger module (i.e., the trigger module 1020a and the trigger module 1020b) and the at least one second trigger module (i.e., the trigger module 1020c and the trigger module 1020d) at different time points, so as to ensure that the first start time point and the second start time point are different. For example, the control module 910 sends a trigger signal to the at least one second trigger module (i.e., the trigger module 1020c and the trigger module 1020d) after a first time length after sending a trigger signal to the at least one first trigger module (i.e., the trigger module 1020a and the trigger module 1020b), so as to ensure that the first start time point and the second start time point are separated by the first time length.

[0177] The flash memory grain 1000 shown in FIG. 10 can be an example of the flash memory grain shown in FIG. 3, FIG. 4A, FIG. 4B or FIG. 5. The control module 1010 can be an example of the control module 420. The remaining content of the control module 1010 can refer to the content of the control module 420, and will not be listed one by one here. The plane group 1030a and the plane group 1030b can be examples of the plane group 410a and the plane group 410b. The remaining content of the plane group 1030a and the plane group 1030b can refer to the content of the plane group 410a and the plane group 410b respectively, and will not be listed one by one here.

[0178] In the flash memory grain 1000 shown in FIG. 10, each plane corresponds to a trigger module, so that each plane can independently perform a data processing operation, which is beneficial to increase the flexibility of each plane to perform a data processing operation.

[0179] The following examples verify the peak current of the flash memory grain related to the embodiments of the present application.

[0180] For example, the example 1 takes that the plurality of plane groups include four plane groups, any plane group includes one plane, the plurality of plane groups include the plane 0, the plane 1, the plane 3 and the plane 4, the data processing operation is a programming operation, and the first time length is 1us.

[0181] For example, please refer to FIG. 11, which shows the current change diagram of the plurality of plane groups performing the programming operation concurrently. FIG. 11 (1) to FIG. 11 (4) respectively show the current change diagram of the plane 0, the plane 1, the plane 3 and the plane 4. As shown in FIG. 11, the plane 0, the plane 1, the plane 3 and the plane 4 all reach the peak current at the time t1, and the peak current is i1 to i4 respectively.

[0182] For example, refer to FIG. 12, which is a diagram of current changes of the plurality of plane groups in the embodiments of the present application. FIG. 12(1) to FIG. 12(4) respectively show the diagrams of current changes of plane 0, plane 1, plane 3 and plane 4. As shown in FIG. 12, plane 0 reaches peak current i1 at time t1, plane 1 reaches peak current i2 at time t2, plane 2 reaches peak current i3 at time t3, and plane 3 reaches peak current i4 at time t4.

[0183] The peak current within 1us and the peak current within 2us of the embodiments of the present application and the plurality of plane groups performing the programming operation concurrently can be calculated respectively by means of differentiation and the like. Analysis shows that the scheme in the embodiments of the present application can reduce the peak current within 1us of the flash memory particle by about 35% to 40% and the peak current within 2us by about 25% to 28% compared with the scheme of the plurality of plane groups performing the programming operation concurrently.

[0184] Example 2: the plurality of plane groups include two plane groups, and any plane group includes two planes, i.e., the plurality of plane groups include a first plane group and a second plane group, the first plane group includes plane 0 and plane 1, and the second plane group includes plane 3 and plane 4. The data processing operation is taken as the programming operation as an example.

[0185] Analysis shows that when the first time length is 5us, the scheme in the embodiments of the present application can reduce the peak current within 1us of the flash memory particle by 23% and the peak current within 2us by 14% compared with the scheme of the plurality of plane groups performing the programming operation concurrently. When the first time length is 8us, the scheme in the embodiments of the present application can reduce the peak current within 1us of the flash memory particle by 41% and the peak current within 2us by 21% compared with the scheme of the plurality of plane groups performing the programming operation concurrently.

[0186] Based on the same inventive concept, the embodiments of the present application provide a flash memory chip. The flash memory chip can include a plurality of flash memory particles packaged in a packaging form. The content of the packaging form can refer to the content of the packaging form discussed in the foregoing FIG. 3, which will not be repeated here. Any flash memory particle in the plurality of flash memory particles can refer to any flash memory particle discussed in the foregoing FIG. 4A, FIG. 4B, FIG. 5, FIG. 8 to FIG. 10, which will not be listed one by one here. Optionally, the structure of the flash memory chip provided by the embodiments of the present application can refer to the content of the flash memory chip discussed in the foregoing FIG. 3, which will not be repeated here.

[0187] Based on the same inventive concept, an embodiment of the present application provides a storage device. The storage device comprises a flash chip and a master chip. The content of the storage device, the content of the flash chip and the content of the master chip can refer to the content of the storage device, the content of the flash chip and the content of the master chip discussed above respectively. Optionally, the structure of the storage device can refer to the content of the storage device discussed above with reference to FIG. 1 or FIG. 2, which will not be listed again here.

[0188] Based on the same inventive concept, an embodiment of the present application provides an electronic device. The electronic device is, for example, a terminal device or a server. The terminal device is, for example, a vehicle-mounted terminal, a drone, a mobile phone, or a wearable device (such as a watch or a bracelet). Please refer to FIG. 13, which is a structural schematic diagram of an electronic device. As shown in FIG. 13, the electronic device 1300 comprises a power module 1310 and a storage device 1320. The electronic device 1300 can comprise one or more storage devices, and the number of the included storage devices is not limited. The content of the storage device can refer to the content of the storage device discussed above, which will not be described again here. The power module 1310 can be used to power the electronic device.

[0189] Based on the same inventive concept, an embodiment of the present application provides a data processing method. The method can be executed by the flash grain discussed above with reference to any one of FIG. 4A, FIG. 4B, FIG. 5, FIG. 8 to FIG. 10, the control module discussed above with reference to any one of FIG. 4B, FIG. 5, FIG. 8 to FIG. 10, or a larger component or device comprising the flash grain, such as a flash chip, a storage device or an electronic device, etc., which will not be specifically limited. For ease of introduction, the following will take the flash grain as an example to introduce the method.

[0190] Please refer to FIG. 14, which is a schematic diagram of a data processing method provided by an embodiment of the present application. The steps involved in FIG. 14 will be introduced below.

[0191] S1401, the control module controls a first plane group in a plurality of plane groups to execute a first data processing operation on first data at a first start time.

[0192] The content of the plurality of plane groups, the content of the first plane group, the content of the control module, the content of the first data processing operation, the content of the first data, the content of the first start time, and the content of controlling the first plane group to execute the first data processing operation on the first data at the first start time can refer to the content of the plurality of plane groups, the content of the first plane group, the content of the control module, the content of the first data processing operation, the content of the first start time, the content of the first data, and the content of controlling the first plane group to execute the first data processing operation on the first data at the first start time discussed above with reference to any one of FIG. 4A, FIG. 4B, FIG. 5, FIG. 8 to FIG. 10, which will not be listed again here.

[0193] S1402, the control module controls the second plane group in the second plane group to perform the second data processing operation on the second data at the second start time.

[0194] The content of the second start time, the content of the second plane group, the content of the second data processing operation, the content of the second data, and the content of controlling the second plane group to perform the second data processing operation on the second data at the second start time can be respectively referred to the content of the second start time, the content of the second plane group, the content of the second data processing operation, the content of the second data, and the content of controlling the second plane group to perform the second data processing operation on the second data at the second start time discussed in any of the foregoing FIG. 4A, FIG. 4B, FIG. 5, FIG. 8 to FIG. 10, which will not be listed here.

[0195] Optionally, the flash memory grain includes at least one first trigger module and at least one second trigger module. The control module can trigger the first plane group to perform the first data processing operation on the first data through part or all of the first trigger module in the at least one first trigger module, and the control module can trigger the second plane group to perform the second data processing operation on the second data through part or all of the second trigger module in the at least one second trigger module. The content of the at least one first trigger module and the at least one second trigger module can be respectively referred to the content of the at least one first trigger module and the at least one second trigger module discussed in any of the foregoing FIG. 8 to FIG. 10, and the repeated part will not be listed here.

[0196] In a possible implementation, each plane group in the plurality of plane groups includes one plane; and any two planes in the plurality of planes included in the plurality of plane groups perform the data processing operation at different start times. The content of the plurality of planes can be referred to the content of the plurality of planes discussed in any of the foregoing FIG. 4A, FIG. 4B, FIG. 5, FIG. 8 to FIG. 10.

[0197] In a possible implementation, the plurality of planes included in the first plane group perform the first data processing operation at the same start time; and the plurality of planes included in the second plane group perform the second data processing operation at the same start time.

[0198] In a possible implementation, the first start time at which the first plane group performs the first data processing operation and the second start time at which the second plane group performs the second data processing operation are separated by a first time length. The content of the first time length can be referred to the content of the first time length discussed in any of the foregoing FIG. 4A, FIG. 4B, FIG. 5, FIG. 8 to FIG. 10.

[0199] In a possible implementation, the data processing operation is a programming operation, and the first time length is less than or equal to the second time length. The content of the second time length can be referred to the content of the second time length discussed in any of the foregoing FIG. 4A, FIG. 4B, FIG. 5, FIG. 8 to FIG. 10.

[0200] In a possible implementation, the method further includes: the control module receiving the first time length configured by the master chip; or, the control module being configured with the first time length out of the factory. The content of the first time length can refer to the content of the first time length discussed in any of the foregoing FIG. 4A, FIG. 4B, FIG. 5, FIG. 8 to FIG. 10.

[0201] In a possible implementation, the method further includes: the control module receiving the number of planes included in any plane group configured by the master chip; or, the control module being configured with the number of planes included in any plane group out of the factory. The content of the number of planes included in any plane group can refer to the content of the number of planes included in any plane group discussed in any of the foregoing FIG. 4A, FIG. 4B, FIG. 5, FIG. 8 to FIG. 10, and the repeated part will not be listed here.

[0202] Based on the same inventive concept, the embodiment of the present application provides a data processing apparatus. The data processing apparatus can be used to realize the functions of the flash memory chip in the foregoing method embodiments, and thus can also realize the beneficial effects possessed by the foregoing method embodiments. In the embodiments of the present application, the data processing apparatus can be the control module or the flash memory grain in any of the flash memory grains involved in FIG. 4A, FIG. 4B, FIG. 5, FIG. 8 to FIG. 10, or the flash memory chip involved in FIG. 3, or the storage device involved in FIG. 1 or FIG. 2, or the electronic device including the storage device shown in FIG. 13, or the data processing apparatus can be a module or the like in these devices or components, without limitation.

[0203] The data processing apparatus shown in FIG. 15 will be introduced below. As shown in FIG. 15, the data processing apparatus 1500 can include modules or units corresponding to the foregoing method embodiments. In a possible design, the data processing apparatus 1500 includes a processing unit 1510 and a communication unit 1520. The communication unit 1520 is configured to perform transceiving operations, such as functions related to sending and receiving; the communication unit 1520 can be referred to as a transceiving unit; optionally, the communication unit 1520 includes a receiving unit and a sending unit. The processing unit 1510 is configured to perform processing operations. Alternatively, the communication unit 1520 can be an input / output circuit.

[0204] Optionally, the data processing apparatus 1500 includes one or more processing units 1510 and one or more communication units 1520. The one or more processing units 1510 can be deployed in one server or distributedly deployed in multiple servers, and the one or more communication units 1520 can also be deployed in one server or distributedly deployed in multiple servers, without specific limitation. The processing unit 1510 and the communication unit 1520 included in the data processing apparatus 1500 can be deployed in one server or distributedly deployed in multiple servers, without specific limitation.

[0205] Exemplarily, the data processing apparatus 1500 can be or implement the function of the flash memory grain in the method embodiment shown in FIG. 15.

[0206] Exemplarily, the data processing apparatus 1500 can implement the function of the flash memory grain in the method embodiment shown in FIG. 14.

[0207] In the above embodiment, the communication unit 1520 is configured to receive the control instruction, and the processing unit 1510 is configured to control the plurality of plane groups to perform the data processing operation.

[0208] The data processing apparatus 1500 can also implement other steps performed by the flash memory grain in the method embodiment shown in FIG. 14, which are not listed one by one here.

[0209] Based on the same inventive concept, an embodiment of the present application provides a computer readable storage medium. The computer readable storage medium is configured to store computer programs or instructions, which, when executed, implement the method embodiment shown in FIG. 14.

[0210] Based on the same inventive concept, an embodiment of the present application provides a program product. When the program product is executed, a processor implements the method embodiment shown in FIG. 14. The program product is, for example, a computer program product, and specifically, for example, a computer program and / or instructions, etc. The processor is, for example, a processor running in a computer.

[0211] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer programs or instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are performed. The computer can be a general purpose computer, a special purpose computer, a computer network, a network device, a user equipment or other programmable apparatus. The computer programs or instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer programs or instructions can be transferred from one website site, computer, server or data center to another website site, computer, server or data center through wired or wireless manner. The computer readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center and the like integrated with one or more available media. The available media can be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; an optical medium, such as a digital video disc; a semiconductor medium, such as a solid state disk. The computer readable storage medium can be a volatile or non-volatile storage medium, or can include both volatile and non-volatile storage media.

[0212] In various embodiments of the present application, the terms and / or descriptions of different embodiments are consistent and can be referred to each other if there is no special description and logical conflict. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0213] The various digital numbers involved in the various embodiments of the present application are only used for differentiation for convenience of description, and are not used to limit the scope of the embodiments of the present application. The size of the serial number of the above processes does not mean the execution order, and the execution order of the processes should be based on its function and inherent logic.

Claims

1. A flash memory device, comprising: The flash memory grain comprises a plurality of plane groups, one of the plane groups comprises one or more planes; A first plane group in the plurality of plane groups performs a first data processing operation on first data at a first start time; A second plane group in the plurality of plane groups performs a second data processing operation on second data at a second start time, the first start time is different from the second start time, the first data and the second data are data expected to be processed simultaneously, and the first data processing operation and the second data processing operation are operations of the same type.

2. The flash memory grain of claim 1, wherein, The flash memory grain further comprises a first trigger module and a second trigger module; The first trigger module is connected with the first plane group, and is configured to trigger one or more planes included in the first plane group to perform the first data processing operation on the first data at the first start time; The second trigger module is connected with the second plane group, and is configured to trigger one or more planes included in the second plane group to perform the second data processing operation on the second data at the second start time.

3. The flash memory grain of claim 1 or 2, wherein, The plurality of planes included in the first plane group perform the first data processing operation at the same start time; and the plurality of planes included in the second plane group perform the second data processing operation at the same start time.

4. The flash memory device of any of claims 1-3, wherein, The first start time and the second start time are separated by a first time length.

5. The flash memory grain of claim 4, wherein, The first data processing operation and the second data processing operation are both programming operations or erasing operations.

6. The flash memory grain of claim 5, wherein, The first data processing operation and the second data processing operation are both programming operations, and the first time length is less than or equal to a second time length, wherein: The second time length is a time length required for any plane group in the plurality of plane groups to receive data from a master chip, the data being data to be written into the flash memory grain.

7. A flash memory chip, characterized by The storage device comprises the flash memory chip according to claim 7, and a master chip configured to control the flash memory chip to perform a data processing operation.

8. A storage device, comprising: The storage device comprises:

9. An electronic device, comprising: a power supply module configured to supply power to the electronic device; and a storage device according to claim 8. The method is applied to a flash memory grain, the flash memory grain comprises a plurality of plane groups, one of the plane groups comprises one or more planes; and the method comprises: controlling a first plane group in the plurality of plane groups to perform a first data processing operation on first data at a first start time; and 10. A data processing method, characterized by, controlling a second plane group in the plurality of plane groups to perform a second data processing operation on second data at a second start time, the first start time being different from the second start time, the first data and the second data being data expected to be processed simultaneously, and the first data processing operation and the second data processing operation being operations of the same type. The first data processing operation and the second data processing operation are both programming operations, and the flash memory grain further comprises a first trigger module and a second trigger module; ​ 11. The method of claim 10, wherein, ​ controlling a first plane group in the plurality of plane groups to perform a first data processing operation on the first data at a first start time, comprising: triggering, by the first trigger module, the first plane group to start writing the first data at the first start time, the first data being data received by the first plane group from a master chip; controlling a second plane group in the plurality of plane groups to perform a second data processing operation on the second data at a second start time, comprising: triggering, by the second trigger module, the second plane group to start writing the second data at the second start time, the second data being data received by the second plane group from the master chip.

12. The method of claim 11, wherein, a plurality of planes included in the first plane group perform the first data processing operation at a same start time; a plurality of planes included in the second plane group perform the second data processing operation at a same start time.

13. The method according to any one of claims 10-12, characterized in that, the first start time and the second start time are separated by a first time length.

14. The method of claim 13, wherein, the first data processing operation and the second data processing operation are both programming operations, and the first time length is less than or equal to a second time length, wherein: the second time length is a time length required for any plane group in the plurality of plane groups to receive data from the master chip, the data being data to be written into the flash memory chip.

15. A computer program product, characterised in that, when the computer program product is executed, the method of any one of claims 10-14 is executed.

16. A computer-readable storage medium, characterized in that, the storage medium has stored therein a computer program or instructions, which, when executed, cause the method of any one of claims 10-14 to be executed.

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