Spin logic device, spin logic memory device, and manufacturing methods

Abstract

The present disclosure provides a spin logic device, a spin logic memory device, and manufacturing methods. The spin logic device comprises: an oxide layer; a multiferroic layer, located on the oxide layer and forming, between the multiferroic layer and the oxide layer, a two-dimensional electron gas as a transport layer, and transmitting spin currents in the form of spin waves; a spin-orbit coupling layer, comprising a first spin-orbit coupling unit and a second spin-orbit coupling unit, wherein the first spin-orbit coupling unit and the second spin-orbit coupling unit are not connected to each other and are symmetrically distributed on the multiferroic layer; top electrodes, comprising first top electrodes connected to the first spin-orbit coupling unit and second top electrodes connected to the second spin-orbit coupling unit; and bottom electrodes, comprising a first bottom electrode and a second bottom electrode respectively connected to two sides of the oxide layer.

Description

Spin logic devices, spin logic memory devices and their fabrication methods Technical Field

[0001] This disclosure relates to the field of logic storage technology, and in particular to a spin logic device, a spin logic storage device, and a method for fabricating it. Background Technology

[0002] Magnetoelectric coupling devices (MEDs) have attracted widespread attention due to their ultra-low power consumption and miniaturization. However, current MED structures are relatively complex, posing challenges for experimental implementation. For example, US patent 20220076868 discloses a magnetoelectric coupling spin logic device. It injects spin current into a two-dimensional electron gas through a ferromagnetic layer, resulting in low efficiency. It generates output current through the inverse spin Hall effect. The structure of this device is more complex than that of a membrane stack. US patent 11785783B2 discloses another magnetoelectric coupling spin logic device. It injects spin current into a two-dimensional electron gas through ferromagnetic layer polarization, resulting in low efficiency. It generates output current through the inverse spin Hall effect. The direction of the output current is controlled by flipping the ferromagnetic layer via magnetoelectric coupling, resulting in high power consumption. The structure of this device is more complex than that of a membrane stack. US patent 11502188B2 discloses a magnetoelectric coupling device. It enhances spin current injection efficiency through a ferromagnetic layer and a filter layer. Its logic operation also requires flipping the ferromagnetic layer via magnetoelectric coupling to control the direction of the output current, resulting in high power consumption. Membrane stacks and device structures are more complex.

[0003] Public content

[0004] In view of the above, in order to at least partially solve at least one of the aforementioned technical problems, this disclosure provides a spin logic device, a spin logic storage device, and a method for fabricating it.

[0005] To achieve the above objectives, the technical solution disclosed herein is as follows:

[0006] According to one embodiment of this disclosure, a spin logic device is provided, comprising: an oxide layer; a multiferroic layer, located on the oxide layer and forming a two-dimensional electron gas as a transport layer between the multiferroic layer and the oxide layer, transmitting spin current in the form of a spin wave; a spin-orbit coupling layer, including a first spin-orbit coupling unit and a second spin-orbit coupling unit, wherein the first spin-orbit coupling unit and the second spin-orbit coupling unit are not connected to each other and are symmetrically distributed on the multiferroic layer; a top electrode, including a first top electrode connected to the first spin-orbit coupling unit and a second top electrode connected to the second spin-orbit coupling unit; and a bottom electrode, including a first bottom electrode and a second bottom electrode connected to both sides of the oxide layer.

[0007] According to embodiments of this disclosure, the first spin-orbit coupling unit and the second spin-orbit coupling unit are configured to respectively regulate the polarization direction of the multiferroic layer region below them and respectively inject spin flow into the multiferroic layer.

[0008] According to embodiments of this disclosure, voltages are applied between the first top electrode and the first bottom electrode, and between the second top electrode and the second bottom electrode, respectively, to flip the local multiferroic layer between the first top electrode and the first bottom electrode, and the local multiferroic layer between the second top electrode and the second bottom electrode, to different ferroelectric polarization configurations, thereby realizing different logic gates.

[0009] According to embodiments of this disclosure, when the ferroelectric polarization directions of the local multiferroic layer between the first top electrode and the first bottom electrode, and the local multiferroic layer between the second top electrode and the second bottom electrode are the same, OR logic or XNOR logic is implemented.

[0010] According to an embodiment of this disclosure, XOR logic is implemented when the ferroelectric polarization directions of the local multiferroic layer between the first top electrode and the first bottom electrode and the local multiferroic layer between the second top electrode and the second bottom electrode are opposite.

[0011] According to another aspect of this disclosure, a spin logic memory device is provided, comprising: the spin logic device described above; and a gate dielectric layer, adjacent to the oxide layer and located in the region of the plane in which the gaps between the first spin-orbit coupling unit and the second spin-orbit coupling unit are not connected.

[0012] According to the embodiments of this disclosure, by applying a gate voltage to the gate dielectric layer, the two-dimensional electron gas conductive channel can be non-volatilely controlled; when a gate voltage is applied to the gate dielectric layer, the two-dimensional electron gas below the gate dielectric layer is depleted, and the conductive channel is turned off; the heterojunctions on the left and right sides of the gate are independently controlled and read, realizing the function of a binary storage unit; when the two-dimensional electron gas is enhanced, the conductive channel is turned on, and the function of a spin logic device can be realized.

[0013] According to embodiments of this disclosure, the materials used to prepare the spin-orbit coupling layer are selected from topological materials, heavy metals, and half-metals; the materials used to prepare the multiferroic layer are selected from BiFeO3, ErFeO3, ScFeO3, HoFeO3, YFeO3, SrTiO3, BiTiO3, and KTaO3; and the materials used to prepare the oxide layer are selected from SrTiO3, LaAlO3, EuO, and AlO. x Topological materials, heavy metals, and semi-metals; materials for preparing gate dielectrics: BiFeO3, Pb(Zr) 0.2 Ti 0.8 O3、TaO x HfO x GdO x 、HfZrO.

[0014] According to another embodiment of this disclosure, a method for fabricating the above-described spin logic device is provided, comprising: S1: sequentially growing an oxide layer, a multiferroic layer, and a SOC layer on a wafer with designed interconnects; S2: processing mutually separated SOC layers through photolithography and ion beam etching to obtain a spin-orbit coupling layer; S3: growing an insulating medium in situ on the etched wafer to provide insulation protection for the device; S4: performing a second photolithography and ion beam etching, with the etching stopping at the oxide layer; S5: growing an insulating medium in situ on the etched wafer to provide insulation protection for the device; S6: performing a third photolithography and ion beam etching to open the bottom electrode via; S7: fabricating the bottom electrode on the etched wafer; S8: performing a fourth photolithography and ion beam etching to open the top electrode via; S9: fabricating the top electrode on the etched wafer.

[0015] According to another embodiment of this disclosure, a method for fabricating the above-described spin logic memory device is provided, comprising: S10: growing a gate dielectric layer on a wafer with pre-designed interconnects, and fabricating the gate pattern by photolithography and ion beam etching; after etching, growing an insulating dielectric in situ on the wafer to provide insulation protection for the device; S20: treating the wafer after growing the insulating dielectric by chemical mechanical polishing; S30: sequentially growing an oxide layer, a multiferroic layer, and a SOC layer on the polished wafer; S40: performing a second photolithography and ion beam etching to etch the SOC layers on both sides; S0: After etching, an insulating medium is grown in situ on the wafer to provide insulation protection for the device, and a third photolithography and ion beam etching is performed, with the etching stopping at the oxide layer; S60: An insulating medium is grown in situ to provide insulation protection for the device; S70: A fourth photolithography and ion beam etching is performed to open the bottom electrode via and fabricate the bottom electrode on the etched wafer; S80: A fifth photolithography and ion beam etching is performed to open the top electrode via and fabricate the top electrode on the etched wafer; S90: A sixth photolithography and ion beam etching is performed to open the gate electrode via and fabricate the gate electrode on the etched wafer.

[0016] The spin logic device, spin logic memory device, and fabrication method disclosed herein possess advantages such as multifunctionality, reconfigurability, high energy efficiency, simple structure, and ease of fabrication. Specifically, they are hybrid devices integrating topological spintronic logic and storage functions, based on structures such as programmable logic arrays or programmable gate arrays. Various combinational and sequential logic functions can be implemented through programming configuration; simultaneously, the integrated memory module can be configured for data storage, program storage, etc. The logic and storage functions can be independently programmed and configured, and can be reconfigured and modified as needed. Attached Figure Description

[0017] Figure 1 shows the structure of a spin logic device according to an embodiment of the present disclosure and a schematic diagram of the implementation principle of OR gates and XOR gates;

[0018] Figure 2 shows the structure of a spin logic device and a schematic diagram of the implementation principle of an XOR gate according to an embodiment of the present disclosure;

[0019] Figure 3 illustrates a schematic diagram of the physical mechanism of a spin logic device according to an embodiment of the present disclosure;

[0020] Figure 4 shows a process flow diagram of a specific fabrication method for a spin logic device according to an embodiment of the present disclosure;

[0021] Figure 5 shows a schematic diagram of the structure and operating mode of a spin logic memory device according to an embodiment of the present disclosure.

[0022] Figure 6 shows a process flow diagram of the fabrication method of the spin logic memory device according to an embodiment of the present disclosure. Detailed Implementation

[0023] This disclosure provides a simple and easily fabricated spin logic device, a spin logic memory device, and a fabrication method. The switching between spin logic and memory functions can be achieved by non-volatilely controlling the opening and closing of the 2DEG (two-dimensional electron gas) conductive channels via gate voltage. As a spin logic device, multifunctional and reconfigurable logic gates can be realized by adjusting different configurations of ferroelectric polarization in the multiferroic layer.

[0024] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0025] In this embodiment of the disclosure, as shown in Figures 1 and 2, a spin logic device is provided, comprising: an oxide layer (represented by Oxide in the figures); a multiferroic layer (represented by FE in the figures), located on the oxide layer and forming a two-dimensional electron gas (represented by 2DEG in the figures) as a transport layer between the oxide layer and the oxide layer, transmitting spin current in the form of a spin wave; a spin-orbit coupling layer (represented by Electrode in the figures), including a first spin-orbit coupling unit (left side) and a second spin-orbit coupling unit (right side), wherein the first spin-orbit coupling unit and the second spin-orbit coupling unit are not connected to each other and are symmetrically distributed on the multiferroic layer; a top electrode, including a first top electrode (E1) connected to the first spin-orbit coupling unit and a second top electrode (E2) connected to the second spin-orbit coupling unit; and a bottom electrode, including a first bottom electrode (E1') and a second bottom electrode (E2') connected to both sides of the oxide layer.

[0026] As can be seen, the multiferroic layer is formed on the side of the oxide layer away from the substrate, and is configured to form a two-dimensional electron gas at the interface with the oxide, serving as a transport layer to transmit spin current in the form of a spin wave. The two spin-orbit coupling layers are formed on the side of the multiferroic layer away from the oxide layer, and are not connected to each other. They are configured to respectively control the polarization direction of the multiferroic layer region below them and inject spin current into the multiferroic layer. During initialization, voltages are applied between the first top electrode and the first bottom electrode on the left, and between the second top electrode and the second bottom electrode on the right, respectively, flipping the local multiferroic layer under the left top electrode and the local multiferroic layer under the right top electrode to different ferroelectric polarization configurations. As shown in Figure 1, when the ferroelectric polarization directions of the multiferroic layers on the left and right sides are the same (as shown by the arrows representing polarization directions pointing upwards in Figure 1), OR and XNOR logic can be implemented. When the logic input is mapped to the presence or absence of the input current, and the logic output is mapped to the total loop current I... Total =(I Out1 +I Out2 When ), just input any (I) in1 I in2 If the value is not zero, the output current I Total Set to 1 to implement a logic OR gate. This maps the logic input to either positive or negative input, while the logic output maps to the total loop current (I0). Out1 +I Out2 When the two inputs are reversed (10 or 01), I Out1 I Out2 When the amplitudes are equal but the directions are opposite, the total current in the circuit (I) is... Out1 +I Out2 The value is 0. I only registers 0 when the input is in the same direction (11 or 00). Out1 I Out2 When the amplitudes are equal and the directions are the same, the total current in the loop (I) is... Out1 +I Out2 A value of 1 corresponds to a logic XOR gate. As shown in Figure 2, when the polarization directions of the multi-iron layer ferroelectrics corresponding to the top and bottom electrodes on the left and right sides are opposite, XOR logic can be implemented. When the logic input is mapped to the presence or absence of the input, and the logic output is mapped to the total loop current (I0), the logic logic can be implemented. Out1 +I Out2 When the two inputs are in the same direction (11 or 00), I Out1 I Out2 When the amplitudes are equal but the directions are opposite, the total current in the circuit (I) is... Out1 +I Out2 The value is 0. I is only 0 when the two input directions are opposite (10 or 01). Out1 I Out2 With equal amplitude and the same direction, the total loop current (I) Out1 +I Out2 The value is 1, which implements the logical XOR gate operation.

[0027] Figure 3 illustrates the physical mechanism of the spin logic device described in this disclosure. Intrinsically, a two-dimensional electron gas (2DEG) with a strong Rashba effect forms at the interface between the multiferroic layer and the oxide layer. Due to the Rashba effect, the spin bands in the 2DEG are split, and spin and momentum are locked together. The polarity of the Rashba effect is determined by the polarity of the interface electric field (E). When the input current J... in Flowing along the x-direction through the SOC layer, due to the strong spin-orbit coupling effect of the SOC layer, a spin current polarized along the y-direction (J) is generated. S Spin current is injected into the multiferroic layer along the z-direction and transported within the multiferroic layer in the form of magnons (J). M When a non-equilibrium spin current is injected into a 2DEG, the Fermi surface in k-space is translated by Δk along the kx direction. Due to this translation of the Fermi surface, an output current (J) is generated along the x-direction. out This generates the Inverse Rashba-Edelstein effect. Since the polarity of the Rashba effect is determined by the interface electric field, changing the direction of the interface electric field will reverse the direction of the output current. Therefore, when the ferropolarization (P) direction of the multiferroic layer is reversed, the direction of the interface electric field will change, and the corresponding output current under the same input will also reverse.

[0028] According to another embodiment of this disclosure, as shown in FIG4, a method for fabricating the above-described spin logic device is provided, comprising operations S1-S9:

[0029] S1: Thin film growth, on a wafer with well-designed interconnects, an oxide layer, a multiferroic layer (FE), and a spin-orbit coupling layer (SOC) are grown sequentially. In practice, a capping layer (not shown) is added on the SOC layer to prevent oxidation of the SOC layer, etc.

[0030] S2: The SOC layers on both sides (i.e., the first spin-orbit coupling unit on the left and the second spin-orbit coupling unit on the right in the figure) are fabricated by photolithography and ion beam etching; S3: An insulating medium is grown in situ on the wafer after etching to provide insulation protection for the device;

[0031] S4: Perform the second photolithography and ion beam etching, with the etching stopping at the oxide layer;

[0032] S5: After etching, an insulating medium is grown in situ on the wafer to provide insulation protection for the device.

[0033] S6: Perform the third photolithography and ion beam etching to open the bottom electrode via; S7: Form the bottom electrode (first bottom electrode E1 and second bottom electrode E2) on the etched wafer by sputtering / evaporation and stripping.

[0034] S8: Perform the fourth photolithography and ion beam etching to open the top electrode via;

[0035] S9: Top electrodes (first top electrode E1' and second top electrode E2') are formed on the etched wafer by sputtering / evaporation and lift-off. Two first top electrodes E1' are formed on both sides of the first spin-orbit coupling unit, and two second top electrodes E2' are formed on both sides of the second spin-orbit coupling unit.

[0036] In this embodiment of the disclosure, as shown in FIG5, a spin logic memory device is provided, including: the spin logic device described above; and a gate dielectric layer (represented by Dielectric in the figure), located on the oxide layer and situated between the gaps between the first spin-orbit coupling unit and the second spin-orbit coupling unit that are not connected, in the region of the vertical projection of the plane.

[0037] Figure 5 shows the device structure and different operating modes of the spin logic memory device. This spin logic memory device includes two spin-orbit coupling layers (SOCs), a multiferroic layer (FE), an oxide layer, and a gate dielectric layer. The two SOCs are formed on the substrate, are not interconnected, and are configured to respectively control the polarization direction of the multiferroic layer above them and inject spin current into the multiferroic layer. The multiferroic layer is formed on the side of the SOCs away from the substrate, acting as a transport layer to transmit the spin current in the form of a spin wave. The oxide layer is formed on the side of the multiferroic layer away from the SOCs, forming a two-dimensional electron gas (2DEG) at the interface with the multiferroic layer. The gate dielectric layer is formed on the side of the oxide layer away from the multiferroic layer, located between the two SOCs in the region perpendicularly projected onto the plane. By applying a gate voltage V to the gate dielectric layer... G It allows for non-volatile control of the 2DEG conductive channels at the interface. Initially, the channels are open, and the spin logic memory device implements the reconfigurable logic function of the spin logic device as shown in Figures 1 and 2 (as shown on the left side of Figure 5). After applying a gate voltage, the 2DEG below the gate is depleted, the channels are turned off, and the heterojunctions on the left and right sides of the gate are independently controlled and read. At this time, the spin logic memory device implements the function of a binary storage cell (as shown on the left side of Figure 5).

[0038] According to yet another embodiment of this disclosure, a method for fabricating the above-described spin logic memory device is also provided, comprising S10-S90:

[0039] S10: A gate dielectric layer is grown on the wafer with well-designed interconnects, and the gate pattern is processed by photolithography and ion beam etching. After etching, an insulating dielectric is grown in situ on the wafer to provide insulation protection for the device.

[0040] S20: Wafer after growing insulating medium has been treated with chemical mechanical polishing;

[0041] S30: An oxide layer, a multi-iron layer, and a SOC layer are sequentially grown on the polished wafer;

[0042] S40: Perform a second photolithography and ion beam etching to etch out the SOC layers on both sides;

[0043] S50: After etching, an insulating medium is grown in situ on the wafer to provide insulation protection for the device, and a third photolithography and ion beam etching are performed, with the etching stopping at the oxide layer.

[0044] S60: In-situ grown insulating medium provides insulation protection for the device;

[0045] S70: The fourth photolithography and ion beam etching open the bottom electrode via and fabricate the bottom electrode (first bottom electrode E1 and second bottom electrode E2) on the etched wafer;

[0046] S80: Perform the fifth photolithography and ion beam etching to open the top electrode via and fabricate the top electrode (first top electrode E1' and second top electrode E2') on the etched wafer;

[0047] S90: Perform the sixth photolithography and ion beam etching to open the gate electrode via and fabricate the gate electrode G on the etched wafer.

[0048] In the above-mentioned spin logic devices and spin logic memory devices, the spin-orbit coupling layer is one, more, or a combination of topological materials, heavy metals, and half-metals; the multiferroic layer is one or more of BiFeO3, ErFeO3, ScFeO3, HoFeO3, YFeO3, SrTiO3, BiTiO3, and KTaO3; the oxide layer is SrTiO3, LaAlO3, EuO, or AlO. x One or more of the following: topological materials, heavy metals, and semi-metals; the gate dielectric layer is BiFeO3, Pb(Zr) 0.2 Ti 0.8 O3(PZT), TaO x HfO x GdO x One or more of HfZrO, etc.

[0049] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the elements and methods described above are not limited to the various specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or replace them. For example: (1) the order of membrane stacking; (2) cascading of multiple devices for functional expansion; (3) simple changes in the shape, size, and relative position of devices; (4) material replacement.

[0050] Based on the above description, those skilled in the art should have a clear understanding of the spin logic device, spin logic storage device, and fabrication method disclosed herein.

[0051] In summary, this disclosure provides a spin logic device, a spin logic storage device, and a fabrication method, which possesses advantages such as multifunctionality, reconfigurability, high energy efficiency, simple structure, and ease of fabrication. It is a hybrid device integrating topological spintronics with logic and storage functions, based on structures such as programmable logic arrays or programmable gate arrays. Various combinational and sequential logic functions can be implemented through programming configuration; simultaneously, the integrated memory module can be configured for data storage, program storage, etc. The logic and storage functions can be independently programmed and configured, and can be reconfigured and modified according to requirements. It can be widely used in embedded systems, digital signal processing, control systems, communication equipment, etc. The logic storage device proposed in this disclosure combines logical flexibility and storage function, helping to reduce system complexity and shorten development cycles, making it a very practical hybrid electronic device.

[0052] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Any other corresponding changes and modifications made based on the technical concept of this disclosure should be included within the scope of protection of the claims of this disclosure.

Claims

1. A spin logic device, comprising: oxide layer; A multiferroic layer is located on the oxide layer and forms a two-dimensional electron gas as a transport layer between the oxide layer and the oxide layer, which transmits spin flow in the form of spin waves. The spin-orbit coupling layer includes a first spin-orbit coupling unit and a second spin-orbit coupling unit. The first spin-orbit coupling unit and the second spin-orbit coupling unit are not connected to each other and are symmetrically distributed on the multiferroic layer. The top electrode includes a first top electrode connected to the first spin-orbit coupling unit and a second top electrode connected to the second spin-orbit coupling unit. as well as The bottom electrode includes a first bottom electrode and a second bottom electrode respectively connected to both sides of the oxide layer.

2. The spin logic device according to claim 1, wherein the first spin-orbit coupling unit and the second spin-orbit coupling unit are configured to respectively regulate the polarization direction of the multiferroic layer region below them and respectively inject spin current into the multiferroic layer.

3. The spin logic device according to claim 1, wherein voltages are applied between the first top electrode and the first bottom electrode, and between the second top electrode and the second bottom electrode, respectively, to flip the local multiferroic layer between the first top electrode and the first bottom electrode, and the local multiferroic layer between the second top electrode and the second bottom electrode, to different ferroelectric polarization configurations, thereby realizing different logic gates.

4. The spin logic device according to claim 3, wherein when the local multiferroic layer between the first top electrode and the first bottom electrode and the ferroelectric polarization direction of the local multiferroic layer between the second top electrode and the second bottom electrode are the same, OR logic or XNOR logic is implemented.

5. The spin logic device according to claim 3, wherein XOR logic is implemented when the ferroelectric polarization directions of the local multiferroic layer between the first top electrode and the first bottom electrode and the local multiferroic layer between the second top electrode and the second bottom electrode are opposite.

6. A spin logic memory device, comprising: The spin logic device according to any one of claims 1-5; as well as The gate dielectric layer, adjacent to the oxide layer and located in the region between the first spin-orbit coupling unit and the second spin-orbit coupling unit that are not connected, is between the areas in the vertical projection of the plane.

7. The spin logic memory device according to claim 6, by applying a gate voltage to the gate dielectric layer, can non-volatilely control the two-dimensional electron gas conductive channel; If a positive gate voltage is applied to the gate dielectric layer, the two-dimensional electron gas below the gate dielectric layer is depleted, and the conductive channel is turned off; the heterojunctions on the left and right sides of the gate can be independently controlled and read, realizing the function of a binary storage cell; conversely, if a negative gate voltage is applied to the gate dielectric layer, the two-dimensional electron gas is enhanced, the conductive channel is turned on, and the function of a spin logic device can be realized.

8. The spin logic memory device according to claims 1 and 6, The materials used to prepare the spin-orbit coupling layer are selected from topological materials, heavy metals, and semi-metals; The materials used to prepare the multi-iron layer were selected from BiFeO3, ErFeO3, ScFeO3, HoFeO3, YFeO3, SrTiO3, BiTiO3, and KTaO3; The oxide layer was prepared using materials selected from SrTiO3, LaAlO3, EuO, and AlO. x Topological materials, heavy metals, and semi-metals; The gate dielectric is prepared using BiFeO3 and Pb(Zr) materials. 0.2 Ti 0.8 O3、TaO x HfO x GdO x 、HfZrO.

9. A method for fabricating a spin logic device according to any one of claims 1-5 and 8, comprising: S1: On the wafer with the designed interconnects, an oxide layer, a multi-iron layer, and a SOC layer are grown sequentially. S2: A spin-orbit coupling layer is obtained by processing mutually separated SOC layers through photolithography and ion beam etching; S3: After etching, an insulating medium is grown in situ on the wafer to provide insulation protection for the device; S4: Perform the second photolithography and ion beam etching, with the etching stopping at the oxide layer; S5: After etching, an insulating medium is grown in situ on the wafer to provide insulation protection for the device. S5: Perform the third photolithography and ion beam etching to open the bottom electrode via; S6: Fabrication of the bottom electrode on the etched wafer; S7: Perform the fourth photolithography and ion beam etching to open the top electrode via; S8: Fabricate the top electrode on the etched wafer.

10. A method for fabricating a spin logic memory device according to any one of claims 6-8, comprising: S10: A gate dielectric layer is grown on the wafer with well-designed interconnects, and the gate pattern is processed by photolithography and ion beam etching. After etching, an insulating dielectric is grown in situ on the wafer to provide insulation protection for the device. S20: Wafer after growing insulating medium has been treated with chemical mechanical polishing; S30: An oxide layer, a multi-iron layer, and a SOC layer are sequentially grown on the polished wafer; S40: Perform a second photolithography and ion beam etching to etch out the SOC layers on both sides; S50: After etching, an insulating dielectric is grown in situ on the wafer to provide insulation protection for the device, and a third photolithography and ion beam etching process is performed. Etching stops at the oxide layer; S60: In-situ grown insulating medium provides insulation protection for the device; S70: The fourth photolithography and ion beam etching open the bottom electrode via and fabricate the bottom electrode on the etched wafer; S80: Perform the fifth photolithography and ion beam etching to open the top electrode via and fabricate the top electrode on the etched wafer; S90: Perform the sixth photolithography and ion beam etching to open the gate electrode via and fabricate the gate electrode on the etched wafer.

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