Half-bridge power module, full-bridge power module and electric device

Abstract

Provided in the present application are a half-bridge power module (100), a full-bridge power module and an electric device. The half-bridge power module comprises: a substrate (1), which is provided with a conductive metal layer (11), wherein the conductive metal layer (11) comprises a direct-current positive electrode region (111) and an alternating-current region (112); and a circuit unit, which comprises an upper bridge (21) and a lower bridge (22), wherein the upper bridge (21) is disposed in the direct-current positive electrode region (111), and comprises a first wide-bandgap chipset (211), and the lower bridge (22) comprises a second wide-bandgap chipset (221). The half-bridge power module of the present application internally integrates a wide-bandgap power chip and a silicon-based power chip to form a single-phase half-bridge power module incorporating both the wide-bandgap power chip and the silicon-based power chip, such that current specifications and power levels can be well expanded, and the issues of both switching loss and cost are also taken into consideration.

Description

Half-bridge power modules, full-bridge power modules and electrical equipment Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a half-bridge power module, a full-bridge power module, and an electrical device. Background Technology

[0002] With the development of new energy vehicle technology, more and more new energy vehicle main drive inverters are adopting power semiconductor modules.

[0003] Currently, the power semiconductor modules on the market are mainly Si IGBT modules and SiC MOSFET modules. The main disadvantage of Si IGBT modules is their high switching losses, while the main disadvantage of SiC MOSFET modules is their high cost due to the limitations of the silicon carbide substrate manufacturing process, making it difficult to meet the explosive growth demand of the new energy vehicle market.

[0004] Summary of the Invention

[0005] In view of the above problems, this application provides a half-bridge power module, a full-bridge power module, and an electrical device, which integrates a wide-bandgap power chip and a silicon-based power chip, and can balance switching losses and product cost.

[0006] This application provides a half-bridge power module, comprising: a substrate having a conductive metal layer, the conductive metal layer including a DC positive region and an AC region; and a circuit unit including an upper bridge and a lower bridge, the upper bridge being disposed in the DC positive region, the upper bridge including a first wide bandgap chipset, and the lower bridge including a second wide bandgap chipset.

[0007] The half-bridge power module of this application integrates a wide-bandgap power chip and a silicon-based power chip, forming a single-phase half-bridge power module that combines wide-bandgap power chips and silicon-based power chips. This allows for better expansion of current specifications and power levels while also addressing switching losses and cost issues.

[0008] In some embodiments, both the first wide bandgap chipset and the second wide bandgap chipset include a plurality of wide bandgap power chips.

[0009] In some embodiments, the upper bridge further includes a first silicon-based chipset, and the lower bridge further includes a second silicon-based chipset, wherein at least one of the first silicon-based chipset and the second silicon-based chipset includes at least one of the silicon-based power chips.

[0010] In some embodiments, the first wide bandgap chipset and the second wide bandgap chipset are arranged along a first direction, and both the first wide bandgap chipset and the second wide bandgap chipset include a plurality of wide bandgap power chips arranged along a second direction.

[0011] In some embodiments, the multiple wide bandgap power chips of the second wide bandgap chipset correspond one-to-one with and are electrically connected to the multiple wide bandgap power chips in the first wide bandgap chipset to form a half-bridge circuit, and the multiple wide bandgap power chips in the first wide bandgap chipset are connected in parallel with each other.

[0012] In some embodiments, at least a portion of the structure of the DC positive region and the AC region extends along the second direction, the first wide bandgap chip group is disposed in the portion of the DC positive region extending along the second direction, and the second wide bandgap chip group is disposed in the portion of the AC region extending along the second direction.

[0013] In some embodiments, at least a portion of the structure of the DC negative pole region extends along the second direction.

[0014] In some embodiments, the DC positive region, the AC region, and the DC negative region are arranged sequentially along the first direction.

[0015] In some embodiments, a plurality of the wide bandgap power chips in the first wide bandgap chipset are all connected to the AC area via a first connection line.

[0016] In some embodiments, the conductive metal layer includes a DC negative region, and multiple wide bandgap power chips in the second wide bandgap chipset are connected to the DC negative region via a second connection line.

[0017] In some embodiments, a plurality of wide-bandgap power chips in at least one of the first wide-bandgap chipset and the second wide-bandgap chipset are arranged flush in the first direction.

[0018] In some embodiments, the conductive metal layer includes a DC negative electrode region, the DC positive electrode region is provided with a DC positive terminal, the DC negative electrode region is provided with a DC negative terminal, and the AC region is provided with an AC terminal.

[0019] In some embodiments, the DC positive terminal and the DC negative terminal are located on the same side of the DC positive region and the DC negative region along the second direction, respectively, and the AC terminal is located on the other side of the AC region along the second direction.

[0020] In some embodiments, any two adjacent wide-bandgap power chips in the second wide-bandgap chipset are staggered along the first direction.

[0021] In some embodiments, a plurality of wide bandgap power chips in the second wide bandgap chipset are arranged opposite to the DC negative electrode region along the first direction.

[0022] In some embodiments, the distance between the plurality of wide bandgap power chips in the second wide bandgap chipset and the DC output layer along the first direction decreases sequentially in the direction along the second direction and away from the DC negative terminal.

[0023] In some embodiments, in the second direction of the DC positive terminal region, the first wide bandgap chipset is disposed between the first silicon-based chipset and the DC positive terminal.

[0024] In some embodiments, in a second direction of the AC region, the second wide bandgap chipset is disposed between the second silicon-based chipset and the AC terminal.

[0025] In some embodiments, both the first silicon-based chipset and the second silicon-based chipset include at least one diode, which forms a chip pair with other silicon-based power chips within the chipset.

[0026] In some embodiments, the diode is made of the same substrate material as the silicon-based power chip.

[0027] In some embodiments, both the first silicon-based chipset and the second silicon-based chipset have multiple chip pairs, and the multiple chip pairs are arranged along the second direction.

[0028] In some embodiments, the silicon-based power chip and diode in each chip pair are arranged along the first direction or the second direction.

[0029] In some embodiments, the silicon-based power chips and diodes in the plurality of chip pairs are arranged in the same or opposite directions.

[0030] In some embodiments, the first silicon-based chip group and the second silicon-based chip group each have multiple chip pairs, wherein the multiple silicon-based power chips are arranged adjacent to each other along the second direction, the multiple diodes are arranged adjacent to each other along the second direction, and the multiple silicon-based power chips and the diodes are arranged along the second direction.

[0031] In some embodiments, the conductive metal layer further includes: a first driving layer group, comprising: a first SiC gate driving layer, a first IGBT gate driving layer, a first SiC source driving layer, and a first IGBT emitter driving layer, wherein the gate of the SiC MOSFET of the upper bridge is connected to the first SiC gate driving layer, the source of the SiC MOSFET of the upper bridge is connected to the first SiC source driving layer, the gate of the Si IGBT of the upper bridge is connected to the first IGBT gate driving layer, and the emitter of the Si IGBT of the upper bridge is connected to the first IGBT emitter driving layer.

[0032] In some embodiments, the first SiC source driving layer and the first IGBT emitter driving layer are connected to form a first common copper layer.

[0033] In some embodiments, the first SiC source drive layer is provided with a plurality of drive resistors that correspond one-to-one with and are connected to a plurality of wide bandgap power chips in the first wide bandgap chipset.

[0034] In some embodiments, the conductive metal layer further includes a second driving layer group, comprising: a second SiC gate driving layer, a second IGBT gate driving layer, a second SiC source driving layer, and a second IGBT emitter driving layer. The gate of the SiC MOSFET of the lower bridge is connected to the second SiC gate driving layer, the source of the SiC MOSFET of the lower bridge is connected to the second SiC source driving layer, the gate of the Si IGBT of the lower bridge is connected to the second IGBT gate driving layer, and the emitter of the Si IGBT of the lower bridge is connected to the second IGBT emitter driving layer.

[0035] In some embodiments, the second SiC source driving layer and the second IGBT emitter driving layer are connected to form a second common copper layer.

[0036] In some embodiments, the second SiC source drive layer is provided with a plurality of drive resistors that correspond one-to-one with and are connected to the plurality of wide bandgap power chips in the second wide bandgap chipset.

[0037] In some embodiments, the conductive metal layer includes a first side and a second side opposite to each other along the first direction, the first driving layer group is disposed along the first side, and the DC positive electrode region is located on the side of the first driving layer group away from the first side along the first direction.

[0038] In some embodiments, the second drive layer group is located on one side of the DC negative region toward the second side along the second direction, or the AC region at least partially surrounds the second drive layer group.

[0039] In some embodiments, the conductive metal layer includes a first driving layer region, at least a portion of which is disposed between the first wide bandgap chipset and the second wide bandgap chipset.

[0040] In some embodiments, the first driving layer region is used to form an electrical connection with the second wide bandgap chipset.

[0041] In some embodiments, both the first wide bandgap chipset and the second wide bandgap chipset include a plurality of wide bandgap power chips arranged along a first direction, and the first wide bandgap chipset and the second wide bandgap chipset are arranged along a second direction.

[0042] In some embodiments, multiple wide-bandgap power chips in the first wide-bandgap chipset are connected in series one-to-one with multiple wide-bandgap power chips in the first wide-bandgap chipset to form a half-bridge circuit, and multiple wide-bandgap power chips in the first wide-bandgap chipset are connected in parallel with each other.

[0043] In some embodiments, at least a portion of the structure of the DC positive region and the AC region extends along the first direction and is arranged along the second direction, the first wide bandgap chip group is disposed in the portion of the DC positive region extending along the first direction, and the second wide bandgap chip group is disposed in the portion of the AC region extending along the first direction.

[0044] In some embodiments, the conductive metal layer further includes a DC negative electrode region, at least a portion of the structure of which extends along the first direction.

[0045] In some embodiments, a plurality of wide-bandgap power chips in the first wide-bandgap chipset are electrically connected to the AC region, and a plurality of wide-bandgap power chips in the second wide-bandgap chipset are electrically connected to the DC negative region.

[0046] In some embodiments, the outer contour of the conductive metal layer includes a first side and a second side opposite to each other along the first direction, and a third side and a fourth side opposite to each other along the second direction; the DC positive electrode region includes a first positive electrode transmission region, the first positive electrode transmission region extends along the second direction and is disposed along the first side, and the first silicon-based chip assembly is disposed in the first positive electrode transmission region.

[0047] In some embodiments, the DC positive region further includes a second positive transmission region, which extends along the first direction and is interposed at intervals within the AC region, and the first wide bandgap chipset is disposed in the second positive transmission region.

[0048] In some embodiments, the DC negative region includes a first negative transmission region and a second negative transmission region, wherein the first negative transmission region is disposed along the third side and the second negative transmission region is disposed along the second side.

[0049] In some embodiments, the AC region includes a first AC region extending along the first direction and located between the second positive transmission region and the first negative transmission region, wherein the second wide bandgap chipset is disposed in the first AC region.

[0050] In some embodiments, the AC region further includes a second AC region, which is located between the second positive electrode transmission region and the second negative electrode transmission region, and the second silicon-based chipset is disposed in the second AC region.

[0051] In some embodiments, a recessed area is provided between the first AC region and the second AC region to accommodate the second positive electrode transmission region extending along the first direction.

[0052] In some embodiments, the half-bridge power module further includes a DC positive terminal, which is located in the first positive transmission region.

[0053] In some embodiments, the DC positive terminal is led out from the third side.

[0054] In some embodiments, the half-bridge power module further includes a DC negative terminal, which is located in the first negative transmission region.

[0055] In some embodiments, the DC negative terminal is led out from the third side.

[0056] In some embodiments, the half-bridge power module further includes an AC terminal located in the second AC zone.

[0057] In some embodiments, the AC terminal extends from the fourth side.

[0058] In some embodiments, the DC negative terminal is disposed opposite to the second wide bandgap chipset along the second direction.

[0059] In some embodiments, a plurality of wide-bandgap power chips in the first wide-bandgap chipset are all connected to the first AC area via a first connection line.

[0060] In some embodiments, multiple wide-bandgap power chips in the second wide-bandgap chipset are connected to the first negative transmission area via a second connection line.

[0061] In some embodiments, a plurality of wide bandgap power chips within at least one group of the first wide bandgap chipset and the second wide bandgap chipset are arranged flush in the second direction.

[0062] In some embodiments, at least one group of the first wide bandgap chipset and the second wide bandgap chipset contains a plurality of wide bandgap power chips, with any two adjacent wide bandgap power chips being staggered along the second direction.

[0063] In some embodiments, along the second direction of the DC positive region, the first wide bandgap chip group is disposed near the third side, and the first silicon-based chip group is disposed near the fourth side.

[0064] In some embodiments, along a second direction of the communication area, the second wide bandgap chipset is disposed near the third side, and the second silicon-based chipset is disposed near the fourth side.

[0065] In some embodiments, the first wide bandgap chipset and the second wide bandgap chipset further include a first type of diode, wherein the first type of diode of the first wide bandgap chipset is connected in series with the first type of diode of the second wide bandgap chipset, and the first type of diode is connected in parallel with the wide bandgap power chip in the same group.

[0066] In some embodiments, the first type of diode has the same substrate material type as the wide bandgap power chip.

[0067] In some embodiments, both the first silicon-based chipset and the second silicon-based chipset include at least one second type diode, wherein the second type diode of the first silicon-based chipset is connected in series with the second type diode of the second silicon-based chipset, and the second type diode is connected in parallel with the silicon-based chip in the same group.

[0068] In some embodiments, the silicon-based power chip and the second type of diode within the silicon-based chipset are connected in parallel to form a chip pair.

[0069] In some embodiments, the second type of diode has the same substrate material type as the silicon-based power chip.

[0070] In some embodiments, the chip pairs in the first silicon-based chipset and the second silicon-based chipset are multiple, and the multiple chip pairs are arranged along the second direction.

[0071] In some embodiments, the silicon-based power chip and the second type of diode in each chip pair are arranged along the first direction or the second direction.

[0072] In some embodiments, the silicon-based power chips and second-type diodes in the plurality of chip pairs are arranged in the same or opposite directions.

[0073] In some embodiments, the chip pairs in the first silicon-based chip group and the second silicon-based chip group are multiple, wherein the multiple silicon-based power chips are arranged adjacent to each other along the second direction, the multiple second-type diodes are arranged adjacent to each other along the second direction, and the multiple silicon-based power chips and the second-type diodes are arranged along the second direction.

[0074] In some embodiments, the wide bandgap power chip includes a SiC MOSFET, and the silicon-based power chip includes a Si IGBT.

[0075] In some embodiments, the first driving layer region includes: a first SiC gate driving layer and a first SiC source driving layer, wherein the gate of the SiC MOSFET of the lower bridge is connected to the first SiC gate driving layer, and the source of the SiC MOSFET of the lower bridge is connected to the first SiC source driving layer.

[0076] In some embodiments, the first SiC gate driving layer and the first SiC source driving layer are disposed between the first wide bandgap chipset and the second wide bandgap chipset.

[0077] In some embodiments, the first driving layer region further includes: a first IGBT gate driving layer and a first IGBT emitter driving layer, wherein the gate of the Si IGBT of the lower bridge is connected to the first IGBT gate driving layer, and the emitter of the Si IGBT of the lower bridge is connected to the first IGBT emitter driving layer.

[0078] In some embodiments, the first IGBT gate driving layer and the first IGBT emitter driving layer are disposed on the second side.

[0079] In some embodiments, the conductive metal layer further includes a second driving layer region, which is disposed close to the first wide bandgap chipset.

[0080] In some embodiments, at least a portion of the second driving layer region is disposed between the DC positive region and the AC region.

[0081] In some embodiments, the second driving layer region includes: a second SiC gate driving layer and a second SiC source driving layer, wherein the gate of the SiC MOSFET of the upper bridge is connected to the second SiC gate driving layer, and the source of the SiC MOSFET of the upper bridge is connected to the second SiC source driving layer.

[0082] In some embodiments, the second SiC gate driving layer and the second IGBT gate driving layer are disposed between the DC positive region and the AC region.

[0083] In some embodiments, the second driving layer region further includes: a second IGBT gate driving layer and a second IGBT emitter driving layer, wherein the gate of the Si IGBT of the upper bridge is connected to the second IGBT gate driving layer, and the emitter of the Si IGBT of the upper bridge is connected to the second IGBT emitter driving layer.

[0084] In some embodiments, the second IGBT gate driving layer and the second IGBT emitter driving layer are disposed on the second side.

[0085] In some embodiments, the first SiC source driving layer and the first IGBT emitter driving layer are connected to form a first common copper layer.

[0086] In some embodiments, the second SiC source driving layer and the second IGBT emitter driving layer are connected to form a second common copper layer.

[0087] In some embodiments, the first wide bandgap chip group and the second wide bandgap chip group are arranged along a first direction, and each of the first wide bandgap chip group and the second wide bandgap chip group includes a plurality of wide bandgap power chips. The plurality of wide bandgap power chips in one of the first wide bandgap chip groups and the second wide bandgap chip groups are arranged along the first direction, and the plurality of wide bandgap power chips in the other group are arranged along a second direction.

[0088] In some embodiments, the conductive metal layer includes a first driving layer region disposed near the second wide bandgap chipset of the lower bridge.

[0089] In some embodiments, the first driving layer is spaced within the AC region and is insulated from the AC region.

[0090] In some embodiments, the first driving layer is spaced between the AC region and the DC positive region.

[0091] In some embodiments, the wide bandgap power chips of the second wide bandgap chipset are connected in series one-to-one with the wide bandgap power chips in the first wide bandgap chipset to form a half-bridge circuit, and the multiple wide bandgap power chips in the first wide bandgap chipset are connected in parallel with each other.

[0092] In some embodiments, a plurality of wide bandgap power chips in the first wide bandgap chipset are arranged along the second direction, and a plurality of wide bandgap power chips in the second wide bandgap chipset are arranged along the first direction.

[0093] In some embodiments, a plurality of the wide bandgap power chips in the first wide bandgap chipset are electrically connected to the AC area.

[0094] In some embodiments, the conductive metal layer further includes a DC negative region, and a plurality of wide bandgap power chips in the second wide bandgap chipset are electrically connected to the DC negative region.

[0095] In some embodiments, at least a portion of the structure of the DC positive region extends along the second direction, and the first wide bandgap chipset is disposed in the portion of the DC positive region extending along the second direction.

[0096] In some embodiments, at least a portion of the structure of the communication region extends along the first direction, and the second wide bandgap chipset is disposed on the portion of the communication region extending along the first direction.

[0097] In some embodiments, the outer contour of the conductive metal layer includes a first side and a second side opposite to each other along the first direction, and a third side and a fourth side opposite to each other along the second direction; at least a portion of the structure of the DC positive electrode region is disposed along the first side.

[0098] In some embodiments, the upper bridge includes a first silicon-based chipset, the first wide bandgap chipset and the first silicon-based chipset are arranged side by side along a second direction of the first side.

[0099] In some embodiments, the conductive metal layer further includes a DC negative electrode region, at least a portion of the structure of which is disposed along the second side.

[0100] In some embodiments, the DC negative region includes a first negative transmission region and a second negative transmission region, wherein the first negative transmission region is disposed along the third side and the second negative transmission region is disposed along the second side.

[0101] In some embodiments, the lower bridge further includes a second silicon-based chipset, wherein the second wide-bandgap chipset and the second silicon-based chipset are disposed in the AC area.

[0102] In some embodiments, the AC region is located within the space enclosed by the DC positive region, the first negative transmission region, and the second negative transmission region, and the second wide bandgap chipset and the second silicon-based chipset are arranged side by side in the AC region along the second direction.

[0103] In some embodiments, the half-bridge power module further includes a DC positive terminal, which is electrically connected to the DC positive region.

[0104] In some embodiments, the DC positive terminal is led out from the third side.

[0105] In some embodiments, the half-bridge power module further includes a DC negative terminal, which is electrically connected to the first negative transmission region.

[0106] In some embodiments, the DC negative terminal is led out from the third side.

[0107] In some embodiments, the half-bridge power module further includes an AC terminal that is electrically connected to the AC zone.

[0108] In some embodiments, the AC terminal extends from the fourth side.

[0109] In some embodiments, in the DC positive region, the first wide bandgap chipset is positioned close to the DC positive terminal.

[0110] In some embodiments, in the AC region, the second wide bandgap chipset is positioned close to the DC negative terminal.

[0111] In some embodiments, the DC negative terminal and the second wide bandgap chipset are arranged at a distance from each other along the second direction.

[0112] In some embodiments, a plurality of wide bandgap power chips of the first wide bandgap chipset are arranged flush with each other in the first direction.

[0113] In some embodiments, any two adjacent wide-bandgap power chips in the first wide-bandgap chipset are staggered along the first direction.

[0114] In some embodiments, the plurality of wide bandgap power chips in the second wide bandgap chipset are aligned in the second direction.

[0115] In some embodiments, any two adjacent wide-bandgap power chips in the second wide-bandgap chipset are staggered along the second direction.

[0116] In some embodiments, the first wide bandgap chipset and the second wide bandgap chipset are further provided with a first type of diode, wherein the first type of diode of the first wide bandgap chipset is connected in series with the first type of diode of the second wide bandgap chipset and in parallel with the wide bandgap power chip in the group.

[0117] In some embodiments, the first type of diode has the same substrate material type as the wide bandgap power chip.

[0118] In some embodiments, both the first silicon-based chipset and the second silicon-based chipset include at least one second type diode. The second type diode of the first silicon-based chipset is connected in series with the second type diode of the second silicon-based chipset, and the silicon-based power chip and the second type diode within the same group are connected in parallel.

[0119] In some embodiments, the second type of diode has the same substrate material type as the silicon-based power chip.

[0120] In some embodiments, the silicon-based power chip and the second type of diode within the first silicon-based chipset and the second silicon-based chipset form a chip pair.

[0121] In some embodiments, both the first silicon-based chipset and the second silicon-based chipset have multiple chip pairs, and the multiple chip pairs are arranged along the second direction.

[0122] In some embodiments, the silicon-based power chip and the second type of diode in each chip pair are arranged along the first direction or the second direction.

[0123] In some embodiments, the silicon-based power chips and second-type diodes in the plurality of chip pairs are arranged in the same or opposite directions.

[0124] In some embodiments, the first silicon-based chipset and the second silicon-based chipset each have multiple chip pairs, wherein the multiple silicon-based power chips are arranged adjacent to each other along the second direction, the multiple second-type diodes are arranged adjacent to each other along the second direction, and the multiple silicon-based power chips and the second-type diodes are arranged along the second direction.

[0125] In some embodiments, the upper bridge further includes a first silicon-based chipset, and the lower bridge further includes a second silicon-based chipset. Both the first and second silicon-based chipsets include at least one silicon-based power chip. The wide-bandgap power chip includes a SiC MOSFET, and the silicon-based power chip includes a Si IGBT.

[0126] In some embodiments, the first driving layer region includes a first SiC gate driving layer and a first SiC source driving layer, wherein the gate of the SiC MOSFET of the lower bridge is connected to the first SiC gate driving layer, and the source of the SiC MOSFET of the lower bridge is connected to the first SiC source driving layer.

[0127] In some embodiments, the first driving layer region further includes: a first IGBT gate driving layer and a first IGBT emitter driving layer, wherein the gate of the Si IGBT of the lower bridge is connected to the first IGBT gate driving layer, and the emitter of the Si IGBT of the lower bridge is connected to the first IGBT emitter driving layer.

[0128] In some embodiments, the conductive metal layer further includes a second driving layer region, which includes a second SiC gate driving layer and a second SiC source driving layer. The gate of the SiC MOSFET of the upper bridge is connected to the second SiC gate driving layer, and the source of the SiC MOSFET of the upper bridge is connected to the second SiC source driving layer.

[0129] In some embodiments, the second driving layer region further includes: a second IGBT gate driving layer and a second IGBT emitter driving layer, wherein the gate of the Si IGBT of the upper bridge is connected to the second IGBT gate driving layer, and the emitter of the Si IGBT of the upper bridge is connected to the second IGBT emitter driving layer.

[0130] In some embodiments, the half-bridge power module further includes a drive terminal, wherein one or more of the first SiC gate drive layer, the first SiC source drive layer, the first IGBT gate drive layer, the first IGBT emitter drive layer, the second SiC gate drive layer, the second SiC source drive layer, the second IGBT gate drive layer, and the second IGBT emitter drive layer are led out perpendicularly to the substrate through the drive terminal.

[0131] In some embodiments, the first SiC source driving layer and the first IGBT emitter driving layer are connected to form a first common copper layer.

[0132] In some embodiments, the second SiC source driving layer and the second IGBT emitter driving layer are connected to form a second common copper layer.

[0133] In some embodiments, the half-bridge power module includes: a substrate; a DC positive region, an AC region, and a DC negative region located on the substrate; and an upper bridge chip group located on the DC positive region, and a lower bridge chip group located on the AC region. The upper bridge chip group includes a first wide bandgap chip group, and the lower bridge chip group includes a second wide bandgap chip group. The first wide bandgap chip group is connected to the AC region, and the second wide bandgap chip group is connected to the DC negative region. The first wide bandgap chip group and the second wide bandgap chip group are arranged along a second direction, and each of the first wide bandgap chip group and the second wide bandgap chip group includes a plurality of wide bandgap power chips arranged along the second direction.

[0134] In some embodiments, the upper bridge chipset further includes a first silicon-based chipset, and the lower bridge chipset further includes a second silicon-based chipset. The silicon-based power chip in each of the first silicon-based chipset is connected in series with the silicon-based power chip in the second silicon-based chipset to form a half-bridge structure.

[0135] In some embodiments, the second wide bandgap chipset is connected in series with the wide bandgap power chips in the first wide bandgap chipset to form a half-bridge circuit, and the multiple wide bandgap power chips in the wide bandgap chipset are connected in parallel with each other.

[0136] In some embodiments, the half-bridge power module includes a second DC connection terminal located on the DC negative region, and the current path length between the wide bandgap power chip of each of the second wide bandgap chipsets and the second DC connection terminal is the same.

[0137] In some embodiments, at least a portion of the AC region is structurally spaced and embedded in the DC positive region to connect to the wide bandgap power chip in the first wide bandgap chipset.

[0138] In some embodiments, on the shown DC negative region, the second DC connection terminal is positioned close to the second wide bandgap chipset.

[0139] In some embodiments, the half-bridge power module further includes a first DC connection terminal located on the DC positive region, and the current path length between each wide-bandgap power chip of the first wide-bandgap chipset and the first DC connection terminal is the same.

[0140] In some embodiments, the DC positive region includes a first interconnect layer and a second interconnect layer that are interconnected; the first wide bandgap chipset is located on the first interconnect layer, and the first silicon-based chipset is located on the second interconnect layer.

[0141] In some embodiments, a recess is formed between the first connection layer and the second connection layer to accommodate at least a portion of the protruding structure of the AC region, the protruding at least a portion of the structure being spaced apart from the DC positive region for electrically connecting to a plurality of wide bandgap power chips in the first wide bandgap chipset.

[0142] In some embodiments, the arrangement of the plurality of wide bandgap power chips includes at least one of the following: each wide bandgap power chip is arranged flush with the second direction; two adjacent wide bandgap power chips are staggered in the first direction; each wide bandgap power chip is staggered in the first direction; the first direction and the second direction are two mutually perpendicular directions on a plane.

[0143] In some embodiments, the first silicon-based chipset further includes a plurality of diode chips.

[0144] In some embodiments, the second silicon-based chipset further includes a plurality of diode chips.

[0145] In some embodiments, a plurality of diode chips in each of the first silicon-based chipsets are connected in series with a plurality of diode chips in the second silicon-based chipset.

[0146] In some embodiments, the arrangement of multiple silicon-based power chips and multiple diode chips within any silicon-based chipset includes at least one of the following: the silicon-based power chips and the diode chips are arranged in a cross-arrangement in a first direction; and, a first chip combination and a second chip combination are arranged in the first direction, the first chip combination including multiple silicon-based power chips arranged in the first direction, and the second chip combination including multiple diode chips arranged in the first direction; and, multiple third chip combinations are arranged in the first direction, the third chip combination including silicon-based power chips and diode chips arranged in the second direction; and, multiple fourth chip combinations and multiple fifth chip combinations are arranged in a cross-arrangement in the first direction, the fourth chip combination and the fifth chip combination including silicon-based power chips and diode chips arranged in the second direction, and in the fourth chip combination and the fifth chip combination, the silicon-based power chips and the diode chips are arranged in opposite directions; wherein, the first direction and the second direction are two mutually perpendicular directions on a plane.

[0147] In some embodiments, the arrangement of multiple silicon-based power chips and multiple diode chips within any silicon-based chipset includes at least one of the following: the silicon-based power chips and the diode chips are arranged in a cross-arrangement in the second direction; and, a first chip combination and a second chip combination are arranged in the second direction, the first chip combination including multiple silicon-based power chips arranged in the second direction, and the second chip combination including multiple diode chips arranged in the second direction; multiple third chip combinations are arranged in the second direction, the third chip combination including silicon-based power chips and diode chips arranged in the first direction; multiple fourth chip combinations and multiple fifth chip combinations are arranged in a cross-arrangement in the second direction, the fourth chip combination and the fifth chip combination including silicon-based power chips and diode chips arranged in the first direction, and in the fourth chip combination and the fifth chip combination, the silicon-based power chips and the diode chips are arranged in opposite directions.

[0148] In some embodiments, the half-bridge power module includes: an upper bridge driving layer located on the substrate, the upper bridge driving layer including a first gate driving layer and a first emitter driving layer; the gate of each wide bandgap power chip in the first wide bandgap chip group is connected to the first gate driving layer, and the source of each wide bandgap power chip in the first wide bandgap chip group is connected to the first source driving layer.

[0149] In some embodiments, the upper bridge chipset further includes a second gate driving layer and a first emitter driving layer, wherein the base of each silicon-based power chip in the first silicon-based chipset is connected to the second gate driving layer, and the emitter of each silicon-based power chip in the first silicon-based chipset is connected to the first emitter driving layer.

[0150] In some embodiments, the half-bridge power module includes: a lower bridge driving layer located on the substrate, the lower bridge driving layer including a third gate driving layer and a second emitter driving layer; the gate of each wide bandgap power chip in the second wide bandgap chip group is connected to the third gate driving layer, and the source of each wide bandgap power chip in the second wide bandgap chip group is connected to the second source driving layer.

[0151] In some embodiments, the downbridge chipset further includes a fourth gate driving layer and a second emitter driving layer, wherein the base of each silicon-based power chip in the second silicon-based chipset is connected to the fourth gate driving layer, and the emitter of each silicon-based power chip in the second silicon-based chipset is connected to the second emitter driving layer.

[0152] In some embodiments, the first source driving layer and the first emitter driving layer are the same driving layer.

[0153] In some embodiments, the half-bridge power module includes: a first gate driving terminal disposed in the first gate driving layer, a second gate driving terminal disposed in the second gate driving layer, a first source driving terminal disposed in the first source driving layer, and a first emitter driving terminal disposed in the first emitter driving layer.

[0154] In some embodiments, the second source driving layer and the second emitter driving layer are the same driving layer.

[0155] In some embodiments, at least one of the first gate driving terminal, the second gate driving terminal, the first source driving terminal, and the first emitter driving terminal is led out perpendicularly to the substrate.

[0156] In some embodiments, the half-bridge power module includes: a third gate driving terminal disposed in the third gate driving layer, a fourth gate driving terminal disposed in the fourth gate driving layer, a second source driving terminal disposed in the second source driving layer, and a second emitter driving terminal disposed in the second emitter driving layer.

[0157] In some embodiments, at least one of the third gate driving terminal, the fourth gate driving terminal, the second source driving terminal, and the second emitter driving terminal is led out perpendicularly to the substrate. In some embodiments, the half-bridge power module includes: two interconnected first source driving layers, each of which has a plurality of driving resistors; a first end of each driving resistor is interconnected and connected to the first gate driving layer, and a second end of each driving resistor is connected to the gate of one of the first wide bandgap power chips in the first wide bandgap chipset.

[0158] In some embodiments, the half-bridge power module includes: two interconnected second source driving layers, each of which has a plurality of driving resistors; the first end of each driving resistor is interconnected and connected to the third gate driving layer, and the second end of each driving resistor is connected to the gate of one of the wide bandgap power chips in the second wide bandgap chipset.

[0159] In some embodiments, the first wide bandgap chipset includes a plurality of wide bandgap power chips; the half-bridge power module includes an AC connection terminal located on the AC region, and the current path length between each wide bandgap power chip in the first wide bandgap chipset and the AC connection terminal is the same.

[0160] In some embodiments, at least a portion of the structure of the AC region embedded in the DC positive region includes an AC connection terminal, and the current path length between each wide bandgap power chip in the first wide bandgap chipset and the AC connection terminal is the same.

[0161] In some embodiments, the DC negative region is further provided with a second DC connection terminal, which is led out along a first direction.

[0162] In some embodiments, the DC positive region is further connected to a first DC connection terminal, which is led out along a first direction.

[0163] In some embodiments, the AC area is further provided with an AC connection terminal, which extends out along a first direction.

[0164] In some embodiments, at least one of the DC positive region, the DC negative region, and the AC region is a copper layer.

[0165] In some embodiments, the wide bandgap power chip includes a silicon carbide metal-oxide-semiconductor field-effect transistor or a gallium nitride high electron mobility transistor.

[0166] In some embodiments, the silicon-based power chip includes a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field-effect transistor; the diode chip includes a silicon fast recovery diode chip or a silicon carbide Schottky diode chip.

[0167] In some embodiments, the half-bridge power module includes: a substrate; a DC positive region and an AC region located on the substrate, wherein the AC region includes a first AC region and a second AC region separated on both sides of the DC positive region; an upper bridge chipset disposed on the DC positive region; and a lower bridge chipset, wherein a portion of the chips in the lower bridge chipset are disposed in the first AC region and another portion of the chips are disposed in the second AC region; the chips in the upper bridge chipset are electrically connected to the AC region.

[0168] In some embodiments, the DC positive region is disposed between the first AC region and the second AC region, and the first AC region and the second AC region are electrically connected by leads or terminals.

[0169] In some embodiments, the lower bridge chipset includes a second wide bandgap chipset, and the chips in the upper bridge chipset are electrically connected to the first AC region, with the second wide bandgap chipset disposed in the first AC region.

[0170] In some embodiments, the downbridge chipset further includes a second silicon-based chipset disposed in the second AC area.

[0171] In some embodiments, the upper bridge chipset includes a first wide bandgap chipset, the first wide bandgap chipset and the second wide bandgap chipset are arranged along a first direction, and both the first wide bandgap chipset and the second wide bandgap chipset include a plurality of wide bandgap power chips arranged along a second direction.

[0172] In some embodiments, the second wide bandgap chipset is connected in series with the wide bandgap power chips in the first wide bandgap chipset in a one-to-one correspondence.

[0173] In some embodiments, the upper bridge chipset further includes a first silicon-based chipset, wherein the chips in the first silicon-based chipset are connected in series with the chips in the second silicon-based chipset.

[0174] In some embodiments, the first AC region includes a first AC connection terminal, and the current path length between each wide bandgap power chip in the first wide bandgap chipset and the first AC connection terminal is the same.

[0175] In some embodiments, the half-bridge power module further includes a DC negative region, and the second wide bandgap chipset is electrically connected to the DC negative region.

[0176] In some embodiments, the half-bridge power module includes a second DC connection terminal located on the DC negative region; the current path length between each wide-bandgap power chip in the second wide-bandgap chipset and the second DC connection terminal is the same.

[0177] In some embodiments, the upper bridge chipset includes a first silicon-based chipset and a first wide bandgap chipset, wherein the first silicon-based chipset and the first wide bandgap chipset are arranged along a first direction on the DC positive region.

[0178] In some embodiments, the downbridge chipset further includes a second silicon-based chipset, wherein the second silicon-based chipset and the second wide bandgap chipset are arranged in a first direction.

[0179] In some embodiments, on the DC negative region, the second DC connection terminal is disposed close to the second wide bandgap chipset.

[0180] In some embodiments, the first silicon-based chipset includes a plurality of silicon-based power chips and a plurality of diode chips, wherein the silicon-based power chips and the diode chips are connected in parallel in a one-to-one correspondence.

[0181] In some embodiments, the second silicon-based chipset includes a plurality of silicon-based power chips and a plurality of diode chips, wherein the silicon-based power chips and the diode chips are connected in parallel in a one-to-one correspondence.

[0182] In some embodiments, the DC negative electrode region includes a first DC negative electrode connection layer and a second DC negative electrode connection layer, wherein the first DC negative electrode connection layer and the second DC negative electrode connection layer are connected.

[0183] In some embodiments, the first AC region, the DC positive region, and the second AC region are disposed between the first DC negative connection layer and the second DC negative connection layer.

[0184] In some embodiments, the first AC region is disposed close to the first DC negative electrode connection layer in a first direction, and the second AC region is disposed close to the second DC negative electrode connection layer in the first direction.

[0185] In some embodiments, the first DC negative electrode connection layer and the second DC negative electrode connection layer enclose the first AC region, the DC positive electrode region and the second AC region.

[0186] In some embodiments, the second DC negative electrode connection layer is disposed at least partially close to the DC positive electrode region.

[0187] In some embodiments, the current direction of the second DC negative electrode connection layer is opposite to the current direction of the DC positive electrode region.

[0188] In some embodiments, the second AC area includes a second AC connection terminal, and the chip of the first silicon-based chipset is connected to the second AC connection terminal.

[0189] In some embodiments, on the second AC area, the second AC connection terminal is disposed close to the first silicon-based chipset.

[0190] In some embodiments, the half-bridge power module includes two first DC terminals, which are respectively located on the first DC negative connection layer and the second DC negative connection layer.

[0191] In some embodiments, the arrangement of the plurality of wide bandgap power chips includes at least one of the following: each wide bandgap power chip is aligned in a second direction; two adjacent wide bandgap power chips are staggered in a first direction; wherein the first direction and the second direction are two mutually perpendicular directions on a plane.

[0192] In some embodiments, a silicon-based chipset includes: wherein the arrangement of a plurality of silicon-based power chips and a plurality of diode chips includes at least one of the following: a first chip assembly, a second chip assembly, and a third chip assembly are arranged sequentially in a second direction, the first chip assembly including at least one silicon-based power chip arranged sequentially in the second direction, the second chip assembly including at least one diode chip arranged sequentially in the second direction, and the third chip assembly including at least one silicon-based power chip arranged sequentially in the second direction; and a fourth chip assembly, a fifth chip assembly, and a sixth chip assembly are arranged sequentially in the second direction, the fourth chip assembly including at least one diode chip arranged sequentially in the second direction, the fifth chip assembly including at least one silicon-based power chip arranged sequentially in the second direction, and the sixth chip assembly including at least one diode chip arranged sequentially in the second direction; and a plurality of silicon-based power chips and a plurality of diode chips are arranged in a cross arrangement in the second direction; and wherein the first direction and the second direction are two mutually perpendicular directions on a plane.

[0193] In some embodiments, the half-bridge power module includes: a first gate driving layer and a first source driving layer located on the substrate, wherein the gate of each wide bandgap power chip in the first wide bandgap chip group is connected to the first gate driving layer, and the source of each wide bandgap power chip in the first wide bandgap chip group is connected to the first source driving layer.

[0194] In some embodiments, the half-bridge power module includes: a second gate driving layer and a first emitter driving layer located on the substrate; the base of each silicon-based power chip in the first silicon-based chipset is connected to the second gate driving layer, and the emitter of each silicon-based power chip in the first silicon-based chipset is connected to the first emitter driving layer.

[0195] In some embodiments, the half-bridge power module includes: a third gate driving layer and a second source driving layer located on the substrate; the gate of each wide bandgap power chip in the second wide bandgap chip group is connected to the third gate driving layer; and the source of each wide bandgap power chip in the second wide bandgap chip group is connected to the second source driving layer.

[0196] In some embodiments, the half-bridge power module includes: a fourth gate driving layer and a second emitter driving layer located on the substrate; the base of each silicon-based power chip in the second silicon-based chipset is connected to the fourth gate driving layer via a bonding wire, and the emitter of each silicon-based power chip in the second silicon-based chipset is connected to the second emitter driving layer.

[0197] In some embodiments, the half-bridge power module includes: a first gate driving terminal disposed in the first gate driving layer and a first source driving terminal disposed in the first source driving layer.

[0198] In some embodiments, the half-bridge power module includes: a second gate driving terminal disposed in the second gate driving layer and a first emitter driving terminal disposed in the first emitter driving layer.

[0199] In some embodiments, the half-bridge power module includes a third gate driving terminal disposed in the third gate driving layer and a second source driving terminal disposed in the second source driving layer.

[0200] In some embodiments, the half-bridge power module includes: a fourth gate driving terminal disposed in the fourth gate driving layer and a second emitter driving terminal disposed in the second emitter driving layer.

[0201] In some embodiments, at least one of the DC positive region, the DC negative region, and the AC region is a copper layer.

[0202] In some embodiments, the wide bandgap power chip includes a silicon carbide metal-oxide-semiconductor field-effect transistor or a gallium nitride high electron mobility transistor.

[0203] In some embodiments, the silicon-based power chip includes a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field-effect transistor; the diode chip includes a silicon fast recovery diode chip or a silicon carbide Schottky diode chip.

[0204] In some embodiments, a half-bridge power module includes: a substrate; and a circuit unit disposed on the substrate. The circuit unit includes an upper bridge and a lower bridge, each of which includes a variety of power components. The various power components include wide-bandgap power chips, silicon-based power chips, and diodes. There are multiple wide-bandgap power chips, and at least one silicon-based power chip and one diode. In the arrangement of the wide-bandgap power chips, the silicon-based power chips, and the diodes, any two adjacent power components belong to different types of power components.

[0205] In some embodiments, the power elements of the lower bridge are electrically connected to the power elements of the same type in the upper bridge to form a half-bridge circuit, and the various power elements in the upper bridge are connected in parallel with each other.

[0206] In some embodiments, a conductive metal layer is provided on the substrate, the conductive metal layer including a DC positive region, an AC region and a DC negative region; the upper bridge is disposed in the DC positive region, and a plurality of power elements of the upper bridge are electrically connected to the AC region; the lower bridge is disposed in the AC region, and a plurality of power elements of the lower bridge are electrically connected to the DC negative region.

[0207] In some embodiments, at least a portion of the structure of each of the DC positive region, the AC region, and the DC negative region extends along a second direction and is arranged along a first direction, the first direction being perpendicular to the second direction.

[0208] In some embodiments, the plurality of power elements in the upper bridge are arranged in at least one row.

[0209] In some embodiments, the power elements in the upper bridge are arranged in multiple rows.

[0210] In some embodiments, when the plurality of power elements in the upper bridge are arranged in multiple rows, the multiple rows are arranged along the first direction.

[0211] In some embodiments, the plurality of power elements in the lower bridge are arranged in at least one row.

[0212] In some embodiments, the power elements in the lower bridge are arranged in multiple rows.

[0213] In some embodiments, when the plurality of power elements in the lower bridge are arranged in multiple rows, the multiple rows are arranged along the first direction.

[0214] In some embodiments, each row includes a plurality of the power elements arranged along the second direction.

[0215] In some embodiments, power elements of the same type are arranged in the same row.

[0216] In some embodiments, the power components in the upper bridge and the lower bridge are arranged in the same way.

[0217] In some embodiments, the power components in the upper bridge and the lower bridge are arranged differently.

[0218] In some embodiments, the two power elements of the upper bridge and the lower bridge that are opposite each other along the first direction are of different types.

[0219] In some embodiments, the two power elements of the upper bridge and the lower bridge that are opposite each other along the first direction are of the same type.

[0220] In some embodiments, the half-bridge power module further includes a DC positive terminal, which is located within the DC positive region and is led out from a direction perpendicular to the substrate, or from a side of the DC positive region.

[0221] In some embodiments, the half-bridge power module further includes a DC negative terminal, which is located within the DC negative region and is led out from a direction perpendicular to the substrate, or from a side of the DC negative region.

[0222] In some embodiments, the half-bridge power module further includes an AC terminal disposed within the AC region and extending out from a direction perpendicular to the substrate, or from a side portion of the AC region.

[0223] In some embodiments, the DC positive terminal and the DC negative terminal are located on the same side of the substrate along the first direction, and the AC terminal is located on the side of the substrate opposite to the DC positive terminal along the first direction.

[0224] In some embodiments, when the power elements in the upper bridge and the lower bridge are divided into multiple rows arranged along the first direction, the row containing the wide bandgap power chip is closer to the DC positive terminal and the DC negative terminal along the first direction.

[0225] In some embodiments, the outer contour of the conductive metal layer includes a first side and a second side opposite to each other along the first direction, and a third side and a fourth side opposite to each other along the second direction; the DC positive electrode region includes a first transmission region extending along the second direction, and the upper bridge is disposed in the first transmission region.

[0226] In some embodiments, the DC negative terminal region is disposed along the second side and is opposite to and spaced from the first transmission region along the first direction, and the DC negative terminal is led out from the second side.

[0227] In some embodiments, the AC region includes a first AC region located between the first transmission region and the DC negative region, and the lower bridge is disposed in the first AC region.

[0228] In some embodiments, the DC positive region further includes a second transmission region and a third transmission region, the second transmission region being disposed along the third side and the third transmission region being disposed along the fourth side, both the second transmission region and the third transmission region extending to the second side along the first direction, the first AC region and the DC negative region being arranged along the first direction and located between the second transmission region and the third transmission region, and the DC positive terminal being disposed on at least one of the second transmission region and the third transmission region.

[0229] In some embodiments, the DC positive terminal is led out from the second side of the conductive metal layer.

[0230] In some embodiments, each of the second transmission region and the third transmission region has an extension extending along the second side at one end away from the first transmission region along the first direction. There are two DC positive terminals, which are respectively disposed on the extensions of the second transmission region and the third transmission region, and the DC negative terminal is disposed between the two DC positive terminals.

[0231] In some embodiments, the communication area further includes a second communication area, which is located on the side of the first transmission area facing the first side. The second communication area is disposed along the first side and is connected to the first communication area via a connecting line. The communication terminal is disposed in the second communication area.

[0232] In some embodiments, the second AC area further includes an AC main area and a connection area. The AC main area is disposed along the first side. There are two connection areas, which are respectively located on both sides of the first transmission area along the second direction. The first end of each connection area is connected to the AC main area, and the second end extends toward the direction close to the first AC area. The second end is connected to the first AC area through a connection line.

[0233] In some embodiments, the wide bandgap power chip includes a SiC MOSFET, and the silicon-based power chip includes a Si IGBT.

[0234] In some embodiments, a conductive metal layer is provided on the substrate, and the conductive metal layer further includes: a first driving layer group, including: a first SiC gate driving layer, a first IGBT gate driving layer, a first SiC source driving layer and a first IGBT emitter driving layer, the gate of the SiC MOSFET of the upper bridge is connected to the first SiC gate driving layer through a connection line, the source of the SiC MOSFET of the upper bridge is connected to the first SiC source driving layer through a connection line, the gate of the Si IGBT of the upper bridge is connected to the first IGBT gate driving layer through a connection line, and the emitter of the Si IGBT of the upper bridge is connected to the first IGBT emitter driving layer through a connection line.

[0235] In some embodiments, the conductive metal layer further includes a second driving layer group, comprising: a second SiC gate driving layer, a second IGBT gate driving layer, a second SiC source driving layer, and a second IGBT emitter driving layer. The gate of the SiC MOSFET of the lower bridge is connected to the second SiC gate driving layer via a connection line. The source of the SiC MOSFET of the lower bridge is connected to the second SiC source driving layer via a connection line. The gate of the Si IGBT of the lower bridge is connected to the second IGBT gate driving layer via a connection line. The emitter of the Si IGBT of the lower bridge is connected to the second IGBT emitter driving layer via a connection line.

[0236] In some embodiments, the first SiC source driving layer and the first IGBT emitter driving layer are connected to form a first common copper layer.

[0237] In some embodiments, the second SiC source driving layer and the second IGBT emitter driving layer are connected to form a second common copper layer.

[0238] In some embodiments, there are multiple first driving layer groups, each of which is used to connect at least one SiC MOSFET and at least one Si IGBT in the upper bridge.

[0239] In some embodiments, there are multiple second driving layer groups, each second driving layer group being used to connect at least one of the SiC MOSFETs and one of the Si IGBTs in the lower bridge.

[0240] In some embodiments, the half-bridge power module includes: a base plate; a first substrate and a second substrate, the first substrate and the second substrate being arranged side by side and spaced apart along a first direction on the base plate, the first substrate having a first half-bridge unit including a plurality of wide bandgap power chips, the second substrate having a second half-bridge unit including a plurality of silicon-based power chips, and the substrate being electrically connected to the second substrate.

[0241] In some embodiments, the half-bridge power module further includes a DC positive terminal, a DC negative terminal, and an AC terminal, wherein the DC positive terminal and the DC negative terminal are located on the same substrate.

[0242] In some embodiments, the DC positive terminal and the DC negative terminal are disposed on the first substrate.

[0243] In some embodiments, either the DC positive terminal or the DC negative terminal is located on a different substrate from the AC terminal.

[0244] In some embodiments, a first conductive metal layer is provided on the first substrate, the first conductive metal layer includes a first DC positive electrode region, and the DC positive terminal is disposed in the first DC positive electrode region.

[0245] In some embodiments, the first conductive metal layer further includes a first DC negative electrode region, wherein the DC negative terminal is disposed in the first DC negative electrode region.

[0246] In some embodiments, the first conductive metal layer further includes a first AC region, the first half-bridge unit includes a first upper bridge chip group and a first lower bridge chip group, the first upper bridge chip group is disposed in the first DC positive region, the first lower bridge chip group is disposed in the first AC region, and both the first upper bridge chip group and the first lower bridge chip group include a plurality of the wide bandgap power chips.

[0247] In some embodiments, the first upper bridge chipset and the first lower bridge chipset are arranged along a second direction.

[0248] In some embodiments, the wide bandgap power chips in the first upper bridge chipset and the first lower bridge chipset are arranged along a first direction.

[0249] In some embodiments, a plurality of wide-bandgap power chips in the first upper bridge chipset are connected to the first AC region via a first connection line, and a plurality of wide-bandgap power chips in the first lower bridge chipset are connected to the first DC negative region via a second connection line.

[0250] In some embodiments, at least a portion of the first DC positive region, the first AC region, and the first DC negative region extend along the first direction and are arranged along the second direction.

[0251] In some embodiments, the first upper bridge chipset and the first lower bridge chipset further include a first type of diode, which is arranged along a first direction with the wide bandgap power chip.

[0252] In some embodiments, the first type of diode of the first upper bridge chipset is connected in series with the first type of diode of the first lower bridge chipset, and the first type of diode is connected in parallel with the wide bandgap power chip in the same chipset.

[0253] In some embodiments, the first type of diode uses the same substrate material as the wide bandgap power chip.

[0254] In some embodiments, the first type of diode is a wide-bandgap Schottky diode.

[0255] In some embodiments, the diodes and the wide-bandgap power chip are arranged alternately along the first direction.

[0256] In some embodiments, a second conductive metal layer is provided on the second substrate, the second conductive metal layer includes a second DC positive electrode region, and the first DC positive electrode region is electrically connected to the second DC positive electrode region.

[0257] In some embodiments, the second conductive metal layer further includes a second DC negative electrode region, wherein the first DC negative electrode region is electrically connected to the second DC negative electrode region.

[0258] In some embodiments, the second conductive metal layer further includes a second AC region, wherein the first AC region is electrically connected to the second AC region.

[0259] In some embodiments, the AC terminal is located in the second AC area.

[0260] In some embodiments, the second half-bridge unit includes a second upper-bridge chip group and a second lower-bridge chip group. The second upper-bridge chip group is located in the second DC positive region, and the second lower-bridge chip group is located in the second AC region. Both the second upper-bridge chip group and the second lower-bridge chip group include a plurality of the silicon-based power chips.

[0261] In some embodiments, the second upper bridge chip group and the second lower bridge chip group are arranged along a second direction.

[0262] In some embodiments, each of the second upper bridge chip group and the second lower bridge chip group includes a plurality of the silicon-based power chips arranged along the first direction.

[0263] In some embodiments, a plurality of silicon-based power chips in the second upper bridge chipset are connected to the second AC region via a third connection line, and a plurality of silicon-based power chips in the second lower bridge chipset are connected to the second DC negative region via a fourth connection line.

[0264] In some embodiments, at least a portion of the second DC positive region, the second AC region, and the second DC negative region extend along the first direction and are arranged along the second direction.

[0265] In some embodiments, the first DC positive region and the second DC positive region are arranged opposite to each other along the first direction.

[0266] In some embodiments, the first DC negative region and the second DC negative region are arranged opposite to each other along the first direction.

[0267] In some embodiments, the first communication area and the second communication area are arranged opposite to each other along the first direction.

[0268] In some embodiments, the second upper bridge chipset and the second lower bridge chipset further include a second type of diode, which is arranged along a first direction with the silicon-based power chip.

[0269] In some embodiments, the second type of diode of the second upper bridge chip group is connected in series with the second type of diode of the second lower bridge chip group, and the second type of diode is connected in parallel with the silicon-based power chip in the same chip group.

[0270] In some embodiments, the second type of diode is made of the same substrate material as the silicon-based power chip.

[0271] In some embodiments, the second type of diode is a silicon substrate fast recovery diode.

[0272] In some embodiments, the second type of diode and the silicon-based power chip are arranged alternately along the first direction.

[0273] In some embodiments, the wide bandgap power chip includes a SiC MOSFET, and the silicon-based power chip includes a Si IGBT.

[0274] In some embodiments, the first conductive metal layer further includes a first SiC driving layer group, comprising a first SiC gate driving layer and a first SiC source driving layer, wherein the gate of the SiC MOSFET of the first upper bridge chip group is electrically connected to the first SiC gate driving layer, and the source of the SiC MOSFET of the first upper bridge chip group is electrically connected to the first SiC source driving layer.

[0275] In some embodiments, the first conductive metal layer further includes a second SiC driving layer group, including a second SiC gate driving layer and a second SiC source driving layer, wherein the gate of the SiC MOSFET of the first lower bridge chip group is electrically connected to the second SiC gate driving layer, and the source of the SiC MOSFET of the first lower bridge chip group is electrically connected to the second SiC source driving layer.

[0276] In some embodiments, the second conductive metal layer further includes: a first IGBT driving layer group, including: a first IGBT gate driving layer and a first IGBT emitter driving layer, wherein the gate of the Si IGBT in the second upper bridge chip group is electrically connected to the first IGBT gate driving layer, and the emitter of the Si IGBT in the second upper bridge chip group is electrically connected to the first IGBT emitter driving layer.

[0277] In some embodiments, the second conductive metal layer further includes a second IGBT driving layer group, comprising a second IGBT gate driving layer and a second IGBT emitter driving layer, wherein the gate of the Si IGBT in the second lower bridge chip group is electrically connected to the second IGBT gate driving layer, and the emitter of the Si IGBT in the second lower bridge chip group is electrically connected to the second IGBT emitter driving layer.

[0278] In some embodiments, the base plate includes a first side and a second side opposite to each other along a second direction, and a third side and a fourth side opposite to each other along the first direction; the first SiC driving layer group is located on the side of the first DC positive electrode region facing the first side.

[0279] In some embodiments, the second SiC driving layer group is located on the side of the first DC negative electrode region facing the second side.

[0280] In some embodiments, the first IGBT drive layer group is located on the side of the second DC positive region facing the first side.

[0281] In some embodiments, the second IGBT drive layer group is located on the side of the second DC negative electrode region facing the second side.

[0282] In some embodiments, the wide bandgap power chip is connected to the first substrate using a first connection process, which is one of a sintering process and a welding process.

[0283] In some embodiments, the silicon-based power chip is connected to the second substrate using a second connection process, which is one of a sintering process and a welding process.

[0284] In some embodiments, one of the first connection process and the second connection process is a sintering process, and the other is a welding process.

[0285] In some embodiments, both the first connection process and the second connection process are sintering processes, or both the first connection process and the second connection process are welding processes, and the process parameters of the first connection process and the second connection process are different, including process temperature and process duration.

[0286] Secondly, this application provides a method for manufacturing a half-bridge power module, used to manufacture the half-bridge power module described in the first aspect above, comprising the following steps:

[0287] The wide-bandgap power chip is fixed to the first substrate, and the silicon-based power chip is fixed to the second substrate;

[0288] The wide-bandgap power chip is bonded to the first substrate via interconnecting wires, and the silicon-based power chip is bonded to the second substrate via interconnecting wires.

[0289] Electrical tests were performed on the first half-bridge unit formed by the wide bandgap power chip and the second half-bridge unit formed by the silicon-based power chip, respectively.

[0290] The first substrate and the second substrate, which have passed the electrical test, are respectively fixed to the base plate;

[0291] The first substrate and the second substrate are connected by a connecting line;

[0292] Install housing and connection terminals.

[0293] In some embodiments, fixing the wide bandgap power chip to the first substrate and fixing the silicon-based power chip to the second substrate respectively includes: fixing the wide bandgap power chip to the first substrate through a first connection process, and fixing the silicon-based power chip to the second substrate through a second connection process; the first connection process is one of a sintering process and a welding process; the second connection process is one of a sintering process and a welding process.

[0294] In some embodiments, one of the first connection process and the second connection process is a sintering process, and the other is a welding process.

[0295] In some embodiments, both the first connection process and the second connection process are sintering processes, or both the first connection process and the second connection process are welding processes, and the process parameters of the first connection process and the second connection process are different, including process temperature and process duration.

[0296] In some embodiments, fixing the first substrate and the second substrate, which have passed the electrical test, to the base plate includes: soldering both the first substrate and the second substrate to the base plate.

[0297] Thirdly, this application provides a full-bridge power module, including: the above-mentioned half-bridge power module, wherein there are multiple half-bridge power modules, and the multiple half-bridge power modules are connected to form a full-bridge power module.

[0298] Fourthly, this application provides an electrical device, characterized in that it includes a power module, the power module including the half-bridge power module described in the first aspect above, and / or the full-bridge power module described in the second aspect above.

[0299] Fifthly, this application provides a control circuit for a switch, wherein the signal input terminal of the control circuit is used to receive a modulation signal and a control signal; the signal output terminal of the control circuit is connected to the switch, and the control circuit is used to process the modulation signal based on the control signal to output a drive signal; wherein the drive signal is used to drive the switch.

[0300] Sixthly, this application provides a switch module, including: the control circuit and switch as described above.

[0301] In a seventh aspect, this application provides a switching system, comprising: a controller, a switch, and a control circuit as described above; the switch is connected to the output terminal of the control circuit; the controller is connected to the control circuit and is used to provide a modulation signal and a control signal corresponding to the control circuit.

[0302] Eighthly, this application also provides a control method, the method comprising: receiving a modulation signal and a control signal; controlling the modulation signal based on the control signal to output a drive signal; wherein the drive signal is used to drive the switch.

[0303] Ninthly, this application provides a driving method for a hybrid switch, applied to the switching system described above. The method includes: a controller acquiring signal parameters of a driving signal; the signal parameters characterizing the timing of the driving signal; and the controller outputting a modulation signal and a control signal according to the signal parameters.

[0304] In a tenth aspect, this application provides a driving method for a hybrid switch, the hybrid switch being applied in an inverter circuit, the hybrid switch including a first switch (Q1) and a second switch (Q2); the method includes: detecting a current value of a first current at the AC terminal of the hybrid switch; changing the driving mode of the hybrid switch according to the current value of the first current and a first switching current value; the switching loss ratio is different in different driving modes; wherein, the switching loss ratio in the driving mode is the ratio of the loss of the first switch and the second switch under the driving mode.

[0305] Eleventhly, this application provides a driving device for a hybrid switch, the hybrid switch including a first switch (Q1) and a second switch (Q2); the device includes: a detection module for detecting the current value of a first current at the AC terminal of the hybrid switch; a processing module for changing the driving mode of the hybrid switch according to the current value of the first current and the first switching current value; the switching loss ratio is different in different driving modes; wherein, the switching loss ratio in the driving mode is the ratio of the loss of the first switch and the second switch under the driving mode.

[0306] In a twelfth aspect, this application provides a control circuit for a hybrid switch, used to execute the hybrid switch driving method described above. Attached Figure Description

[0307] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0308] Figure 1 is a schematic diagram of the internal layout of a half-bridge power module according to an embodiment of this application;

[0309] Figure 2 is a schematic diagram of the internal layout of another embodiment of the half-bridge power module of this application;

[0310] Figure 3 is a schematic diagram of the internal layout of another embodiment of the half-bridge power module of this application;

[0311] Figure 4 is a schematic diagram of the internal layout of another embodiment of the half-bridge power module of this application;

[0312] Figure 5 is a schematic diagram of the structure of a wide bandgap power chip according to an embodiment of this application;

[0313] Figure 6 is a schematic diagram of the structure of a silicon-based power chip according to an embodiment of this application;

[0314] Figure 7 is a schematic diagram of the diode structure according to an embodiment of this application;

[0315] Figure 8 is a schematic diagram of the arrangement direction and bus direction of wide bandgap power chips in some embodiments of this application;

[0316] Figure 9 is a schematic diagram of the arrangement direction and bus direction of wide bandgap power chips in some other embodiments of this application;

[0317] Figure 10 is a schematic diagram showing the layout of some embodiments of the wide bandgap chipset of this application;

[0318] Figure 11 is a schematic diagram showing the layout of some other embodiments of the wide bandgap power group of this application;

[0319] Figure 12 is a schematic diagram showing the layout of some other embodiments of the wide bandgap power group of this application;

[0320] Figure 13 is a schematic diagram showing the layout of some embodiments of the silicon-based chipset according to the present application;

[0321] Figure 14 is a schematic diagram showing the layout of some other embodiments of the silicon-based chipset according to the present application;

[0322] Figure 15 is a schematic diagram showing the layout of some other embodiments of the silicon-based chipset according to the present application;

[0323] Figure 16 is a schematic diagram showing the arrangement of some other embodiments of the silicon-based chipset according to the present application;

[0324] Figure 17 is a schematic diagram showing the arrangement of some embodiments of the driver layer group in this application;

[0325] Figure 18 is a schematic diagram showing the arrangement of some other embodiments of the driver layer group in this application;

[0326] Figure 19 shows the equivalent circuit diagram and commutation schematic of a typical half-bridge power module;

[0327] Figure 20 shows the switching waveforms of a typical half-bridge power module;

[0328] Figure 21 is a schematic diagram of the structure of a full-bridge power module according to some embodiments of this application;

[0329] Figure 22 is a schematic diagram of the internal layout of a half-bridge power module according to an embodiment of this application;

[0330] Figure 23 is a schematic diagram of the internal bonding of the half-bridge power module shown in Figure 22;

[0331] Figure 24 is a schematic diagram of the internal layout of another embodiment of the half-bridge power module of this application;

[0332] Figure 25 is a schematic diagram of the internal layout of another embodiment of the half-bridge power module of this application;

[0333] Figure 26 is a schematic diagram of the structure of a wide bandgap power chip according to an embodiment of this application;

[0334] Figure 27 is a schematic diagram of the structure of a silicon-based power chip according to an embodiment of this application;

[0335] Figure 28 is a schematic diagram of the diode structure according to an embodiment of this application;

[0336] Figure 29 is a schematic diagram of the arrangement direction and bus direction of wide bandgap power chips in some embodiments of this application;

[0337] Figure 30 is a schematic diagram of the arrangement direction and bus direction of wide bandgap power chips in some other embodiments of this application;

[0338] Figure 31 is a schematic diagram showing the layout of some embodiments of the wide bandgap chipset of this application;

[0339] Figure 32 is a schematic diagram showing the layout of some other embodiments of the wide bandgap power group of this application;

[0340] Figure 33 is a schematic diagram showing the layout of some embodiments of the silicon-based chipset of this application;

[0341] Figure 34 is a schematic diagram showing the layout of some other embodiments of the silicon-based chipset according to the present application;

[0342] Figure 35 is a schematic diagram showing the layout of some other embodiments of the silicon-based chipset according to the present application;

[0343] Figure 36 is a schematic diagram showing the arrangement of some further embodiments of the silicon-based chipset according to the present application;

[0344] Figure 37 is a schematic diagram of the layout of some embodiments of the driving layer region of this application;

[0345] Figure 38 is a schematic diagram showing the arrangement of the driver layer region in some other embodiments of this application;

[0346] Figure 39 shows the equivalent circuit diagram and commutation schematic of a typical half-bridge power module;

[0347] Figure 40 shows the switching waveforms of a typical half-bridge power module;

[0348] Figure 41 is a schematic diagram of the structure of a full-bridge power module according to some embodiments of this application;

[0349] Figure 42 is a schematic diagram of the internal layout of a half-bridge power module according to an embodiment of this application;

[0350] Figure 43 is a schematic diagram of the internal bonding of the half-bridge power module shown in Figure 42;

[0351] Figure 44 is a schematic diagram of the internal layout of another embodiment of the half-bridge power module of this application;

[0352] Figure 45 is a schematic diagram of the internal layout of another embodiment of the half-bridge power module of this application;

[0353] Figure 46 is a schematic diagram of the structure of a wide bandgap power chip according to an embodiment of this application;

[0354] Figure 47 is a schematic diagram of the structure of a silicon-based power chip according to an embodiment of this application;

[0355] Figure 48 is a schematic diagram of the diode structure according to an embodiment of this application;

[0356] Figure 49 is a schematic diagram of the arrangement direction and bus direction of wide bandgap power chips in some embodiments of this application;

[0357] Figure 50 is a schematic diagram of the arrangement direction and bus direction of wide bandgap power chips in some other embodiments of this application;

[0358] Figure 51 is a schematic diagram showing the layout of some embodiments of the wide bandgap chipset of this application;

[0359] Figure 52 is a schematic diagram showing the layout of some other embodiments of the wide bandgap power group of this application;

[0360] Figure 53 is a schematic diagram showing the layout of some embodiments of the silicon-based chipset of this application;

[0361] Figure 54 is a schematic diagram showing the layout of some other embodiments of the silicon-based chipset according to the present application;

[0362] Figure 55 is a schematic diagram showing the layout of some other embodiments of the silicon-based chipset according to the present application;

[0363] Figure 56 is a schematic diagram showing the arrangement of some further embodiments of the silicon-based chipset according to the present application;

[0364] Figure 57 is a schematic diagram of the layout of some embodiments of the driving layer region of this application;

[0365] Figure 58 is a schematic diagram showing the arrangement of the driver layer region in some other embodiments of this application;

[0366] Figure 59 shows the equivalent circuit diagram and commutation schematic of a typical half-bridge power module;

[0367] Figure 60 shows the switching waveforms of a typical half-bridge power module;

[0368] Figure 61 is a schematic diagram of the structure of a full-bridge power module according to some embodiments of this application;

[0369] Figure 62 is a schematic diagram of the layout of a half-bridge power module provided in an embodiment of this application;

[0370] Figure 63 is a schematic diagram of the layout of a half-bridge power module provided in an embodiment of this application;

[0371] Figure 64 is a schematic diagram of the layout and wiring of a half-bridge power module provided in an embodiment of this application;

[0372] Figure 65 is a schematic diagram of the structure of a wide bandgap power chip provided in an embodiment of this application;

[0373] Figure 66 is a schematic diagram of the current path of a wide bandgap chipset provided in an embodiment of this application;

[0374] Figure 67 is a schematic diagram of the equivalent circuit and switching waveform of a half-bridge power module provided in an embodiment of this application;

[0375] Figure 68 is a schematic diagram of the layout of a wide bandgap chipset provided in an embodiment of this application;

[0376] Figure 69 is a layout schematic diagram of a half-bridge power module provided in another embodiment of this application;

[0377] Figure 70 is a schematic layout diagram of a silicon-based chipset provided in an embodiment of this application;

[0378] Figure 71 is a schematic diagram of the layout of another half-bridge power module provided in an embodiment of this application;

[0379] Figure 72 is a schematic diagram of the drive circuit and drive terminal connection provided in an embodiment of this application;

[0380] Figure 73 is a layout schematic diagram of a half-bridge power module provided in another embodiment of this application;

[0381] Figure 74 is a schematic diagram of a multiphase half-bridge power module provided in an embodiment of this application;

[0382] Figure 75 is a schematic diagram of the layout of a hybrid power module provided in an embodiment of this application;

[0383] Figure 76 is a layout schematic diagram of a hybrid power module provided in another embodiment of this application;

[0384] Figure 77 is a layout schematic diagram of a hybrid power module provided in another embodiment of this application;

[0385] Figure 78 is a schematic diagram of the current path of the first chip provided in an embodiment of this application;

[0386] Figure 79 is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0387] Figure 80 is a schematic diagram of an AC terminal provided in an embodiment of this application;

[0388] Figure 81 is a schematic diagram of the equivalent circuit and switching waveform of a hybrid power module provided in an embodiment of this application;

[0389] Figure 82 is a schematic layout diagram of a first chipset provided in an embodiment of this application;

[0390] Figure 83 is a layout schematic diagram of a hybrid power module provided in another embodiment of this application;

[0391] Figure 84 is a schematic layout diagram of a second chipset provided in an embodiment of this application;

[0392] Figure 85 is a schematic diagram of a multiphase hybrid power module provided in an embodiment of this application;

[0393] Figure 86 is a schematic diagram of the internal layout of some embodiments of the half-bridge power module of this application;

[0394] Figure 87 is a schematic diagram of the internal bonding of the half-bridge power module shown in Figure 86;

[0395] Figure 88 is a schematic diagram of the internal bonding of some other embodiments of the half-bridge power module of this application;

[0396] Figure 89 is a schematic diagram of the internal bonding of some other embodiments of the half-bridge power module of this application;

[0397] Figure 90 is a schematic diagram of the structure of a wide bandgap power chip according to an embodiment of this application;

[0398] Figure 91 is a schematic diagram of the structure of a silicon-based power chip according to an embodiment of this application;

[0399] Figure 92 is a schematic diagram of the structure of the diode according to an embodiment of this application;

[0400] Figure 93 is a schematic diagram of the arrangement of power components in the upper or lower bridge of some embodiments of this application;

[0401] Figure 94 is a schematic diagram of the arrangement of power components in the upper or lower bridge of some other embodiments of this application;

[0402] Figure 95 is a schematic diagram of the arrangement of power components in the upper or lower bridge of some embodiments of this application;

[0403] Figure 96 is a schematic diagram of the arrangement of power components in the upper or lower bridge in some embodiments of this application;

[0404] Figure 97 is a schematic diagram of the power element arrangement when the upper and lower bridges are arranged adjacently in an embodiment of this application;

[0405] Figure 98 is a schematic diagram of the power element arrangement when the upper and lower bridges are spaced apart according to an embodiment of this application;

[0406] Figure 99 is a schematic diagram of the driver layer group according to an embodiment of this application;

[0407] Figure 100 is a schematic diagram of the current path when the power module is turned on;

[0408] Figure 101 is a schematic diagram of the current path of the power module during freewheeling;

[0409] Figure 102 is a schematic diagram of the structure of a full-bridge power module according to some embodiments of this application;

[0410] Figure 103 is a schematic diagram of the internal layout of an embodiment of the half-bridge power module of this application;

[0411] Figure 104 is a schematic diagram of the internal bonding of the half-bridge power module shown in Figure 103;

[0412] Figure 105 is a schematic diagram of the internal bonding of another embodiment of the half-bridge power module of this application;

[0413] Figure 106 is a schematic diagram of the structure of a wide bandgap power chip according to some embodiments of this application;

[0414] Figure 107 is a schematic diagram of the structure of a silicon-based power chip according to some embodiments of this application;

[0415] Figure 108 is a schematic diagram of the structure of a diode according to some embodiments of this application;

[0416] Figure 109 is a schematic diagram of the structure of a full-bridge power module according to some embodiments of this application;

[0417] Figure 110 is a schematic diagram of a manufacturing method for a half-bridge power module according to an embodiment of this application;

[0418] Figure 111 is a detailed manufacturing process diagram of the half-bridge power module according to an embodiment of this application;

[0419] Figure 112 is a manufacturing process diagram of the hybrid module in the related technology;

[0420] Figure 113 is a schematic diagram of a hybrid switch in an example;

[0421] Figure 114 is a schematic diagram of the structure of a hybrid switch in another example;

[0422] Figure 115 is a schematic diagram of a half-bridge circuit in an example;

[0423] Figure 116 is a schematic diagram of the control circuit provided in an embodiment of this application;

[0424] Figure 117 is a second schematic diagram of the control circuit provided in an embodiment of this application;

[0425] Figure 118 shows the timing diagram of the driving signals in an example;

[0426] Figure 119 is a schematic diagram of the control circuit provided in an embodiment of this application;

[0427] Figure 120 is a schematic diagram of the control circuit provided in an embodiment of this application;

[0428] Figure 121 is a schematic diagram of the control circuit provided in an embodiment of this application;

[0429] Figure 122 is a schematic diagram of the control circuit provided in an embodiment of this application;

[0430] Figure 123 is a schematic diagram of the control circuit provided in an embodiment of this application;

[0431] Figure 124 is a schematic diagram of the control circuit provided in an embodiment of this application.

[0432] Figure 125 is a schematic diagram of the control circuit provided in an embodiment of this application.

[0433] Figure 126 is a schematic diagram of the control circuit provided in an embodiment of this application;

[0434] Figure 127 is a schematic diagram of the control circuit provided in an embodiment of this application;

[0435] Figure 128 shows the timing diagram of the drive signals in another example;

[0436] Figure 129 shows the timing diagram of the drive signals in another example;

[0437] Figure 130 shows the timing diagram of the drive signals in another example;

[0438] Figure 131 is a schematic diagram of the control circuit provided in an embodiment of this application.

[0439] Figure 132 is a schematic diagram of the control circuit provided in an embodiment of this application.

[0440] Figure 133 is a schematic diagram of the control circuit provided in an embodiment of this application.

[0441] Figure 134 is a schematic diagram of a switching system provided in an embodiment of this application;

[0442] Figure 135 is a schematic diagram of another switching system provided in an embodiment of this application;

[0443] Figure 136 is a schematic diagram of another switching system provided in an embodiment of this application;

[0444] Figure 137 is a schematic diagram of another switching system provided in an embodiment of this application;

[0445] Figure 138 is a flowchart illustrating a control method for a hybrid switch provided in an embodiment of this application;

[0446] Figure 139 is a schematic flowchart of a hybrid switch driving method provided in an embodiment of this application;

[0447] Figure 140 is a structural schematic diagram of a hybrid switch provided in an embodiment of this application;

[0448] Figure 141 is a schematic diagram of a hybrid switch provided in an embodiment of this application;

[0449] Figure 142 is a schematic diagram of a half-bridge circuit in an example;

[0450] Figure 143 is a schematic flowchart of a hybrid switch driving method provided in this application;

[0451] Figure 144 is a waveform diagram of a first current provided in this application;

[0452] Figure 145 is a waveform diagram of another first current provided in this application;

[0453] Figure 146 is a waveform diagram of the first current during testing provided in this application;

[0454] Figure 147 is a timing diagram of drive signals in a first drive mode provided in an embodiment of this application;

[0455] Figure 148 is a timing diagram of the drive signals in another first drive mode provided in an embodiment of this application;

[0456] Figure 149 is a timing diagram of drive signals in a second drive mode provided in an embodiment of this application;

[0457] Figure 150 is a timing diagram of the drive signals in another second drive mode provided in an embodiment of this application;

[0458] Figure 151 is a timing diagram of the driving signals in another second driving mode provided in the embodiments of this application;

[0459] Figure 152 is a schematic flowchart of a hybrid switch driving method provided in this application (II).

[0460] Figure 153 is a schematic flowchart of a hybrid switch driving method provided in this application.

[0461] Figure 154 is a schematic flowchart of a hybrid switch driving method provided in this application.

[0462] Figure 155 is a schematic diagram of the structure of the hybrid switch driving device provided in this application. Detailed Implementation

[0463] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0464] With the development of new energy vehicle technology, more and more new energy vehicle main drive inverters are adopting power semiconductor modules. Currently, the power semiconductor modules on the market are mainly Si IGBT modules and SiC MOSFET modules. The main disadvantage of Si IGBT modules is their high switching losses, while the main disadvantage of SiC MOSFET modules is their high cost due to limitations in the manufacturing process of silicon carbide substrates, making it difficult to meet the explosive growth in demand from the new energy vehicle market. The technology of combining Si IGBTs and SiC MOSFETs in parallel is still in its early stages, and related technologies lack consideration for the dynamic current sharing problem in the parallel connection of Si IGBTs and SiC MOSFETs.

[0465] In view of this, this application provides a half-bridge power module that integrates parallel wide-bandgap power chips and silicon-based power chips, which can better expand current specifications and power levels while taking into account switching losses and cost issues. Furthermore, it can improve the uniform distribution of current and thermal stress among the wide-bandgap power chips, thereby improving the electrical performance and reliability of the half-bridge power module.

[0466] Referring to Figures 1-4, the half-bridge power module 100 of this embodiment includes: a substrate 1 and a circuit unit 2.

[0467] The substrate 1 can be one of the following: thick film printed ceramic substrate (TPC), direct bonded copper ceramic substrate (DBC), active metal welded ceramic substrate (AMB), direct electroplated copper ceramic substrate (DPC), or other types of substrate.

[0468] The substrate 1 may include a first surface and a second surface opposite to each other. The first surface is provided with a conductive metal layer 11. For example, the substrate 1 may include a ceramic layer 10 and copper layers located on both sides of the ceramic layer 10. The ceramic layer 10 may be at least one of alumina, silicon nitride, and aluminum nitride. One of the copper layers may serve as the conductive metal layer 11. The conductive metal layer 11 may be divided into multiple conductive areas according to the circuit layout requirements. Each conductive area may be used to set up a power chip and a connection circuit for connecting different power chips (this connection circuit is not shown in the figure and may be reasonably set according to the arrangement of each power chip, and will not be described in detail below). The other copper layer may serve as a heat dissipation surface of the substrate 1.

[0469] The conductive metal layer 11 may include a DC positive region 111, an AC region 112, and a DC negative region 113. Any one of the DC positive region 111, AC region 112, and DC negative region 113 can be square or irregularly shaped with multiple sides, and any one of the sides can be a right-angled side or a hypotenuse. Of course, this application is not limited to this; the shapes of the DC positive region 111, AC region 112, and DC negative region 113 can be flexibly set according to circuit layout requirements.

[0470] The DC positive region 111 can be connected to the positive terminal of a DC power supply, the DC negative region 113 can be connected to the negative terminal of a DC power supply, and the AC region 112 can be connected to an AC output load to achieve DC-AC conversion; or, the AC region 112 can be connected to an AC power supply, the DC positive region 111 can be connected to the positive terminal of a DC load, and the DC negative region 113 can be connected to the negative terminal of a DC load to achieve AC-DC conversion.

[0471] Circuit unit 2 may include an upper bridge 21 and a lower bridge 22. The upper bridge 21 is located in the DC positive region 111, and the lower bridge 22 is located in the AC region 112. Each of the upper bridge 21 and the lower bridge 22 includes a wide bandgap chipset and a silicon-based chipset. Specifically, the upper bridge 21 includes a first wide bandgap chipset 211 and a first silicon-based chipset 212, and the lower bridge 22 includes a second wide bandgap chipset 221 and a second silicon-based chipset 222.

[0472] The first wide bandgap chipset 211 and the second wide bandgap chipset 221 are arranged along a first direction (the Y direction as shown in Figure 1). Both the first wide bandgap chipset 211 and the second wide bandgap chipset 221 include multiple wide bandgap power chips 23 arranged along a second direction (the X direction as shown in Figure 1). The multiple wide bandgap power chips 23 in the first wide bandgap chipset 211 are connected in parallel. Here, "multiple" means two or more. It can be understood that the wide bandgap power chips 23 in the first wide bandgap chipset 211 and the second wide bandgap chipset 221 can correspond one-to-one. The corresponding two wide bandgap power chips 23 can form a half-bridge circuit. Furthermore, since multiple half-bridge circuits are connected in parallel, a half-bridge circuit with a current amplification factor of N times (the number of half-bridge circuits is N) can be formed, which is beneficial to improving the power level of the half-bridge power module 100.

[0473] Multiple wide-bandgap power chips 23 in the first wide-bandgap chipset 211 are electrically connected to the AC region 112, and multiple wide-bandgap power chips 23 in the second wide-bandgap chipset 221 are electrically connected to the DC negative region 113. The electrical connection can be made through a connecting wire 26, which can be a gold wire, silver wire, copper wire, aluminum wire, copper strip, aluminum strip, metal connecting piece, or other conductive metal wire.

[0474] Among them, the wide bandgap semiconductor material can include SiC, GaN, etc., that is, the wide bandgap power chip 23 is a SiC device or a GaN device. The SiC device can be a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0475] Referring to Figure 1, during the operation of the half-bridge power module 100, part of the current flows from the DC positive region 111 to the DC negative region 113. Multiple wide-bandgap power chips 23 (as shown in Figure 2) in the first wide-bandgap chip group 211 are arranged along the second direction, and each wide-bandgap power chip 23 is connected to the AC region 112 via a connecting line 26 (i.e., the first connecting line 261) along the first direction. This makes the arrangement direction of the multiple wide-bandgap power chips 23 perpendicular to the current flow direction between the first wide-bandgap chip group 211 and the AC region 112. Simultaneously, each wide-bandgap power chip 23 in the first wide-bandgap chip group 211 has a relatively close or even identical current path, improving the current distribution. This results in good dynamic current sharing performance for each wide-bandgap power chip 23 in the first wide-bandgap chip group 211, which is beneficial for ensuring a uniform distribution of current and thermal stress among the wide-bandgap power chips 23.

[0476] Similarly, when multiple wide-bandgap power chips 23 in the second wide-bandgap chipset 221 are arranged along the second direction, and each wide-bandgap power chip 23 is connected to the DC negative terminal region 113 via a connection line 26 (i.e., the second connection line 262) along the first direction, when the current output direction within the DC negative terminal region 113 is the same as the current direction between each wide-bandgap power chip 23 and the DC negative terminal region 113, the wide-bandgap power chips 23 in the second wide-bandgap chipset 221 can have good dynamic current sharing performance, which is beneficial to ensuring the uniform distribution of current stress and thermal stress among the wide-bandgap power chips 23. Of course, the current output direction within the DC negative terminal region 113 is related to the location of the DC negative terminal 118, and this embodiment does not limit this.

[0477] In other words, by setting it up as described above, it can be ensured that each wide bandgap power chip 23 of the first wide bandgap chipset 211 has good dynamic current sharing performance, which is conducive to ensuring the uniform distribution of current stress and thermal stress among each wide bandgap power chip 23.

[0478] Both the first silicon-based chipset 212 and the second silicon-based chipset 222 may include at least one silicon-based power chip 24. For example, there may be one or more silicon-based power chips 24, where "more" refers to two or more. The silicon-based power chip 24 is a Si-based fully controllable power chip, such as a Si IGBT (Insulated Gate Bipolar Transistor) or a Si MOSFET.

[0479] In other words, the half-bridge power module 100 in this embodiment is a hybrid half-bridge power module that integrates wide-bandgap semiconductor devices and silicon semiconductor devices.

[0480] The silicon-based power chips 24 of the first silicon-based chipset 212 and the second silicon-based chipset 222 can be matched one-to-one. The two corresponding wide-bandgap power chips 23 can form a half-bridge circuit. Multiple half-bridge circuits can be connected in parallel to form a half-bridge circuit with a current specification amplification of N (the number of half-bridge circuits is N).

[0481] The half-bridge power module 100 of this application embodiment integrates a wide-bandgap power chip 23 and a silicon-based power chip 24 connected in parallel, forming a single-phase half-bridge power module 100 that combines the wide-bandgap power chip 23 and the silicon-based power chip 24. This can better expand the current specifications and power levels, while also taking into account switching losses and cost issues. Furthermore, the first wide bandgap chip group 211 and the second wide bandgap chip group 221 are arranged along the first direction. Both the first wide bandgap chip group 211 and the second wide bandgap chip group 221 include a plurality of wide bandgap power chips 23 arranged along the second direction. The plurality of wide bandgap power chips 23 in the first wide bandgap chip group 211 are all connected to the AC region 112 through the connecting line 26 along the first direction. The plurality of wide bandgap power chips 23 in the second wide bandgap chip group 221 are all connected to the DC negative region 113 through the connecting line 26 along the first direction. This can at least ensure that each wide bandgap power chip 23 in the first wide bandgap chip group 211 has good dynamic current sharing performance, which is conducive to ensuring the uniform distribution of current stress and thermal stress among each wide bandgap power chip 23, thereby improving the electrical performance and reliability of the half-bridge power module 100.

[0482] For ease of description, the following explanation will use the wide bandgap power chip 23 as a SiC MOSFET and the silicon-based power chip 24 as a Si IGBT as examples.

[0483] In some embodiments, referring to Figures 1-4, at least a portion of the structures of each of the DC positive region 111, AC region 112, and DC negative region 113 extend along a second direction and are arranged sequentially along a first direction. For example, the DC positive region 111 may be integrally formed as a square extending along the second direction, or a portion of the DC positive region 111 may extend along the second direction while the other portion may extend along the first direction; the DC negative region 113 may be integrally formed as a square extending along the second direction, or a portion of the DC negative region 113 may extend along the second direction while the other portion may extend along the first direction; the AC region 112 may be integrally formed as a square extending along the second direction, or a portion of the AC region 112 may extend along the second direction while the other portion may extend along the first direction; the shape and size of any two of the DC positive region 111, AC region 112, and DC negative region 113 may be the same or different, and can be reasonably set according to actual needs. The portions of the DC positive region 111, AC region 112 and DC negative region 113 extending along the second direction can be arranged along the first direction. The first wide bandgap chip group 211 is located in the portion of the DC positive region 111 extending along the second direction, and the second wide bandgap chip group 221 is located in the portion of the AC region 112 extending along the second direction.

[0484] In this way, it is possible for multiple wide bandgap power chips 23 arranged along the second direction on the DC positive region 111 to be connected to the AC region 112 through the connection line 26 along the first direction, and for multiple wide bandgap power chips 23 in the AC region 112 to be connected to the DC negative region 113 through the connection line 26 along the first direction, so as to improve the current sharing among the wide bandgap power chips 23.

[0485] In some embodiments, referring to Figures 1-4, the plurality of wide bandgap power chips 23 in the first wide bandgap chipset 211 are aligned in the first direction. This can maximize the current sharing of the plurality of wide bandgap power chips 23 in the first wide bandgap chipset 211, and the layout is relatively simple and compact, which can reduce the space occupied and improve the space utilization rate.

[0486] In some embodiments, referring to Figures 1 and 4, the plurality of wide-bandgap power chips 23 in the second wide-bandgap chipset 221 are aligned in a first direction. This simplifies the layout of the multiple wide-bandgap power chips 23 in the second wide-bandgap chipset 221, reducing the space occupied by the second wide-bandgap chipset 221 and improving space utilization. As an optional example, the DC negative terminal 118 can be located on the side of the DC negative terminal region 113 opposite to the AC region 112 to ensure current sharing among the multiple wide-bandgap chips in the second wide-bandgap chipset 221. Of course, this application does not limit this.

[0487] In some embodiments, referring to Figures 1-4, the substrate 1 may further include a DC positive terminal 117, a DC negative terminal 118, and an AC terminal 119. The DC positive terminal 117 is located in the DC positive region 111, the DC negative terminal 118 is located in the DC negative region 113, and the AC terminal 119 is located in the AC region 112. The DC positive terminal 117, the DC negative terminal 118, and the AC terminal 119 can all be led out from their respective conductive regions to facilitate connection with external circuits.

[0488] In this configuration, the DC positive terminal 117 and the DC negative terminal 118 are located on the same side of the DC positive region 111 and the DC negative region 113 along the second direction, respectively. Both the DC positive terminal 117 and the DC negative terminal 118 can be led out along the second direction. The AC terminal 119 is located on the other side of the AC region 112 along the second direction and can be led out along the second direction. This arrangement of the DC terminals on one side and the AC terminals on the other side helps to reduce the switching commutation loop of the SiC MOSFET, lower the inductance, improve dynamic current sharing, and simplify the construction of the external circuitry used to connect the half-bridge power module 100.

[0489] At this time, with multiple wide bandgap chips in the second wide bandgap chip group 221 arranged along the second direction, the current confluence direction in the DC negative electrode region 113 is along the second direction, which is perpendicular to the current direction between the multiple wide bandgap chips in the second wide bandgap chip group 221 and the DC negative electrode region 113. The dynamic current sharing of each wide bandgap chip can be adjusted by changing the distance between each wide bandgap chip in the second wide bandgap chip group 221 and the DC negative electrode region 113 in the first direction.

[0490] In some embodiments, referring to Figures 11 and 12, any two adjacent wide-bandgap power chips 23 in the second wide-bandgap chipset 221 are staggered along a first direction. This helps to reduce the thermal coupling of the multiple similar wide-bandgap power chips 23 in the second wide-bandgap chipset 221, thereby reducing the thermal impact in this area and improving heat dissipation performance.

[0491] For example, as shown in Figure 12, the second wide bandgap chipset 221 has three wide bandgap power chips 23, which are arranged sequentially along the second direction and toward the AC terminal 119 as wide bandgap power chip 23a, wide bandgap power chip 23b, and wide bandgap power chip 23c. Among them, wide bandgap power chips 23a and wide bandgap power chips 23c are located on the side of wide bandgap power chip 23b away from the DC negative electrode region 113 along the first direction. In this way, on the one hand, it is beneficial to improve the current sharing between wide bandgap power chips 23a and wide bandgap power chips 23b to a certain extent, and on the other hand, it can reduce the thermal coupling between wide bandgap power chips 23a, wide bandgap power chips 23b, and wide bandgap power chips 23c.

[0492] Alternatively, both wide-bandgap power chips 23a and 23c can be located on the side of wide-bandgap power chip 23b facing the DC negative electrode region 113 along the first direction. This can also reduce the thermal coupling between wide-bandgap power chips 23a, 23b, and 23c, and improve heat dissipation performance.

[0493] In addition, referring to Figure 11, the multiple wide bandgap power chips (23) in the second wide bandgap chipset 221 are arranged opposite to the DC negative terminal region along the first direction. The distance between the multiple wide bandgap power chips 23 of the second wide bandgap chipset 221 and the DC output layer along the first direction decreases in the direction along the second direction and away from the DC negative terminal 118. In other words, the wide bandgap power chip 23 that is closest to the DC negative terminal 118 in the second direction has the farthest distance from the DC negative terminal region 113 in the first direction, and the wide bandgap power chip 23 that is farthest from the DC negative terminal 118 in the second direction has the shortest distance from the DC negative terminal region 113 in the first direction. That is, the connection line 26 between the wide bandgap power chip 23 that is closest to the DC negative terminal 118 in the second direction and the DC negative terminal region 113 has the longest length, and the connection line 26 between the wide bandgap power chip 23 that is farthest from the DC negative terminal 118 in the second direction and the DC negative terminal region 113 has the shortest length. At this time, the multiple wide bandgap power chips 23 of the second wide bandgap chipset 221 are distributed in a stepped manner.

[0494] In this way, on the one hand, the spacing between each wide bandgap chip and the DC negative terminal 113 in the first direction can be used to compensate for the spacing between each wide bandgap chip and the DC negative terminal 118 in the second direction, thereby maximizing the current sharing of the multiple wide bandgap power chips 23 in the second wide bandgap chipset 221. On the other hand, it can also minimize the thermal coupling between the various wide bandgap power chips 23, reduce the heat dissipation pressure in this area, improve the heat dissipation performance in this area, thereby improving the overall heat dissipation performance of the half-bridge power module 100, and thus simultaneously taking into account both the current sharing and heat dissipation performance of the multiple wide bandgap power chips 23 in the second wide bandgap chipset 221.

[0495] Of course, as another alternative to improve heat dissipation performance, the distance between the multiple wide bandgap power chips 23 of the second wide bandgap chipset 221 and the DC output layer along the first direction decreases in the direction along the second direction and away from the DC negative terminal 118. In other words, the wide bandgap power chip 23 that is closest to the DC negative terminal 118 in the second direction has the shortest distance from the DC negative terminal 113 in the first direction, and the wide bandgap power chip 23 that is farthest from the DC negative terminal 118 in the second direction has the farthest distance from the DC negative terminal 113 in the first direction.

[0496] Referring to Figures 19 and 20, Figure 19 shows the equivalent circuit of the hybrid half-bridge power module 100 considering parasitic inductance, and Figure 20 shows a typical switching waveform diagram of the hybrid half-bridge power module 100. In the hybrid module application shown in Figure 19, the circuit turn-on process typically begins with the SiC MOSFE turning on first. At this time, the voltage drops, and the SiC MOSFE carries the entire current. Then, the Si IGBT turns on, and the SiC MOSFE and Si IGBT commutate, with each carrying a portion of the current. During the turn-off process, the Si IGBT turns off first. At this time, the SiC MOSFE and Si IGBT commutate, and the SiC chip carries the entire current. Then, the SiC chip turns off, and the voltage rises, resulting in a turn-off voltage spike. The voltage spike generated during the turn-off process has an adverse effect on the normal operation of the half-bridge power module 100 and needs to be minimized. SiC MOSFE switches faster than Si IGBT switches slower. Under the same inductance, the voltage spike generated by SiC MOSFE is much higher than that of IGBT. That is, the turn-off voltage spike caused by the inductance of the switching commutation circuit of SiC MOSFE is more severe.

[0497] Referring to Figures 1-4, to reduce the voltage spike, in this embodiment, the first wide bandgap chipset 211 is located on the side of the first silicon-based chipset 212 along the second direction, closer to the DC positive terminal 117, and the second wide bandgap chipset 221 is located on the side of the second silicon-based chipset 222 along the second direction, away from the AC terminal 119. This significantly shortens the switching commutation loop length of the SiC MOSFE, thereby reducing parasitic inductance, lowering the turn-off voltage spike, improving the stability and reliability of the half-bridge power module 100, and reducing interference to other electronic components in the circuit.

[0498] In some embodiments, the first wide bandgap chipset 211 and the second wide bandgap chipset 221 are also provided with diodes 25. The diodes 25 are made of the same material as the wide bandgap power chip 23, for example, the diodes 25 can be SiC SBDs (Schottky diodes 25), etc. The diodes 25 are connected in parallel with the wide bandgap power chip 23. The diodes 25 can be used to protect the SiC MOSFE and prevent reverse voltage or excessive voltage from damaging the SiC MOSFE. In addition, by connecting the SiC SBD in parallel, the reverse recovery charge of the SiC SBD is lower when the SiC MOSFE is turned off during the dead time, which can greatly reduce power loss, and also help to eliminate parasitic inductance, reduce energy loss, and improve conversion efficiency, thereby improving the performance of the half-bridge power module 100. The diodes 25 in the first wide bandgap chipset 211 can be connected to the AC region 112 through the connecting line 26, and the diodes 25 in the second wide bandgap chipset 221 can be connected to the DC negative region 113 through the connecting line 26.

[0499] Furthermore, referring to Figures 1-4, considering that the silicon-based power chip 24, such as a Si IGBT, has a long internal capacitance and reverse recovery time during operation, it may experience delayed turn-off and overvoltage, or even damage to the Si IGBT. Therefore, in this embodiment, both the first silicon-based chip group 212 and the second silicon-based chip group 222 include at least one diode 25. That is, there can be one or more diodes 25, where "multiple" refers to two or more. Each diode 25 corresponds one-to-one with a silicon-based power chip 24, and the corresponding silicon-based power chip 24 and diode 25 are connected in parallel to form a chip pair. For example, the diode 25 can be a fast recovery diode 25, and the diode 25 can be connected in reverse parallel with the silicon-based power chip 24.

[0500] In this embodiment, by connecting a diode 25 in reverse parallel to the silicon-based power chip 24, the response speed of the silicon-based power chip 24, such as a Si IGBT, during the turn-off process can be enhanced, overvoltage can be reduced, current cut-off speed can be improved, the Si IGBT can be better protected, and the overall efficiency and reliability of the half-bridge power module 100 can be improved. Specifically, the diode 25 in the first silicon-based chipset 212 can be connected to the AC region 112 via a connecting line 26, and the diode 25 in the second silicon-based chipset 222 can be connected to the DC negative region 113 via a connecting line 26.

[0501] Optionally, only the first wide bandgap chipset 211 and the second wide bandgap chipset 221 may have diodes 25 with the same substrate material as the wide bandgap power chip 23; or, only the first silicon-based chipset 212 and the second silicon-based chipset 222 may have diodes 25 with the same substrate material as the silicon-based power chip 24; or, the first wide bandgap chipset 211 and the second wide bandgap chipset 221 may have diodes 25 with the same substrate material as the wide bandgap power chip 23, while the first silicon-based chipset 212 and the second silicon-based chipset 222 may have diodes 25 with the same substrate material as the silicon-based power chip 24.

[0502] For ease of description, the following description will only take the example of the first silicon-based chipset 212 and the second silicon-based chipset 222 having diodes 25 made of the same material as the silicon-based power chip 24.

[0503] In some embodiments, referring to Figures 1-4 and 13-16, there are multiple silicon-based power chips 24 and diodes 25 in the first silicon-based chipset 212 and the second silicon-based chipset 222. Thus, multiple chip pairs are formed in both the first silicon-based chipset 212 and the second silicon-based chipset 222. The multiple chip pairs are arranged along the second direction, which can amplify the current specification, expand the power level, and improve the power load.

[0504] Furthermore, the silicon-based power chip 24 and diode 25 in each chip pair are arranged along a first direction or a second direction.

[0505] As shown in Figures 13, 15, and 16, there are two chip pairs, meaning there can be two silicon-based power chips 24 and two diodes 25. In this case, the silicon-based power chips 24 and diodes 25 can be arranged alternately in the second direction. In this configuration, the silicon-based power chips 24 and diodes 25 in the first silicon-based chip group 212 are connected to the AC region 112 via a connecting line 26 along the first direction, and the silicon-based power chips 24 and diodes 25 in the second silicon-based chip group 222 are connected to the DC negative region 113 via the connecting line 26 along the first direction. This separates silicon-based chips of the same type (including the aforementioned silicon-based power chips 24 and diodes 25) in each conductive region, which helps avoid thermal coupling between similar silicon-based chips, reduces heat dissipation pressure, and minimizes the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 along the first direction, thus improving space utilization.

[0506] Alternatively, as shown in Figures 15 and 16, the silicon-based power chip 24 and diode 25 in each chip pair are arranged along a first direction.

[0507] In some embodiments, the silicon-based power chips 24 and diodes 25 in multiple chip pairs are arranged in the same or opposite directions.

[0508] For example, as shown in Figure 15, there are two chip pairs. The silicon-based power chip 24 and diode 25 in each chip pair are arranged along the first direction, and the silicon-based power chip 24 in each chip pair is located on the same side of the corresponding diode 25 along the first direction. In this way, the current sharing performance of the silicon-based power chip 24 in the two chip pairs is better, and the current sharing performance of the diode 25 in the two chip pairs is better. In addition, the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 along the second direction is smaller.

[0509] Alternatively, as shown in Figure 16, there are two chip pairs. In each chip pair, the silicon-based power chip 24 and diode 25 are arranged along a first direction. In one chip pair, the silicon-based power chip 24 is located on one side of the corresponding diode 25 along the first direction, and in the other chip pair, the silicon-based power chip 24 is located on the other side of the corresponding diode 25 along the first direction. Furthermore, the silicon-based power chip 24 and diode 25 in one chip pair are arranged side-by-side along a second direction. This arrangement, with the silicon-based power chips 24 and diodes 25 in multiple chip pairs facing opposite directions, helps reduce thermal coupling of the same type of silicon-based chip, improves heat dissipation performance, and reduces the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 along the second direction.

[0510] Understandably, when the silicon-based power chip 24 and diode 25 in each chip pair are arranged along the first direction, the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 in the first direction increases and the space occupied in the second direction decreases. Therefore, the size of the area of ​​the DC positive region 111 corresponding to the first silicon-based chip group 212 can be adjusted to match the space occupied by the first silicon-based chip group 212 in the first and second directions. At the same time, the size of the area of ​​the AC region 112 corresponding to the second silicon-based chip group 222 can also be adjusted to match the space occupied by the second silicon-based chip group 222 in the first and second directions.

[0511] In some embodiments, referring to FIG14, both the first silicon-based chipset 212 and the second silicon-based chipset 222 have multiple chip pairs. Multiple silicon-based power chips 24 are arranged adjacent to each other along a second direction, and multiple diodes 25 are arranged adjacent to each other along the second direction. In other words, in this embodiment, chips of the same type are adjacent to each other and connected to corresponding conductive areas via connecting lines 26 along the first direction. This chip arrangement in this embodiment facilitates the setting of the driving connecting lines 26, and the smaller dimensions of the first silicon-based chipset 212 and the second silicon-based chipset 222 along the first direction improve the space utilization of the first silicon-based chipset 212 and the second silicon-based chipset 222 along the first direction.

[0512] In some embodiments, referring to Figures 1-7, the wide-bandgap power chip 23 includes a SiC MOSFET, and the silicon-based power chip 24 includes a Si IGBT. That is, in this embodiment, the copper layers of the SiC half-bridge and the IGBT half-bridge are not electrically connected inside the power module. This reduces the commutation inductance between the SiC device and the IGBT device, shortens the commutation time, and improves efficiency.

[0513] Referring to Figure 5, the SiC MOSFET includes a source 231, a gate 232, and a drain 233. The drain 233 is located on the side of the SiC MOSFET facing the conductive metal layer 11 and is connected to the conductive region thereon through a welding or sintering process. The source 231 and the gate 232 are located on the side of the SiC MOSFET away from the conductive metal layer 11 and are used to connect to other conductive regions.

[0514] Referring to Figure 6, the Si IGBT includes an emitter 241, a gate 242, and a collector 243. The collector 243 is located at the bottom of the Si IGBT (the side of the Si IGBT facing the conductive metal layer 11) and is used to connect with the conductive region thereon by means of sintering, welding, etc. The emitter 241 and the gate 242 are located on the side of the Si IGBT away from the conductive metal layer 11 and are used to connect with other conductive regions.

[0515] Referring to Figure 7, diode 25 can be a Si FRD (fast recovery diode). Diode 25 includes a cathode 252 and an anode 251. The anode 251 is located at the top of diode 25 (i.e., the side of diode 25 facing away from conductive metal layer 11) and is used for electrical connection with other conductive areas. The cathode 252 is located at the bottom of diode 25 (i.e., the side of diode 25 facing conductive metal layer 11) and is connected to the conductive area thereon by sintering or welding.

[0516] In other words, the half-bridge power module 100 of this embodiment packages a SiC MOSFET and a Si IGBT in parallel. This allows the SiC MOSFET to perform the switching action using drive signals with different timings, while the Si IGBT bears most of the conduction current. This solves the problems of high switching losses and low switching frequency of IGBTs. Furthermore, a larger current can be controlled by a SiC MOSFET with a smaller current carrying capacity, thus solving the problem of high SiC cost. In this way, both the performance and cost of the half-bridge power module 100 can be balanced.

[0517] In some embodiments, referring to Figures 1-4, 17 and 18, the conductive metal layer 11 may further include two driving layer groups, which correspond to the upper bridge 21 and the lower bridge 22 respectively, and the two driving layer groups are the first driving layer group 114 and the second driving layer group 115 respectively.

[0518] The first driving layer group 114 may include: a first SiC gate driving layer 1141, a first IGBT gate driving layer 1142, a first SiC source driving layer 1143, and a first IGBT emitter driving layer 1144. The gate 232 of the SiC MOSFET of the upper bridge 21 is connected to the first SiC gate driving layer 1141 via a connection line 26, the source 231 of the SiC MOSFET of the upper bridge 21 is connected to the first SiC source driving layer 1143 via a connection line 26, the gate 242 of the Si IGBT of the upper bridge 21 is connected to the first IGBT gate driving layer 1142 via a connection line 26, and the emitter 241 of the Si IGBT of the upper bridge 21 is connected to the first IGBT emitter driving layer 1144 via a connection line 26.

[0519] The second driving layer group 115 may include: a second SiC gate driving layer 1151, a second IGBT gate driving layer 1152, a second SiC source driving layer 1153, and a second IGBT emitter driving layer 1154. The gate 232 of the SiC MOSFET of the lower bridge 22 is connected to the second SiC gate driving layer 1151 through the connection line 26. The source 231 of the SiC MOSFET of the lower bridge 22 is connected to the second SiC source driving layer 1153 through the connection line 26. The gate 242 of the Si IGBT of the lower bridge 22 is connected to the second IGBT gate driving layer 1152 through the connection line 26. The emitter 241 of the Si IGBT of the lower bridge 22 is connected to the second IGBT emitter driving layer 1154 through the connection line 26.

[0520] Thus, by setting up the first driving layer group 114 and the second driving layer group 115, it is possible to facilitate the connection between each wide bandgap power chip 23, silicon-based power chip 24 and external circuits.

[0521] Optionally, driving terminals 116 are provided on the first SiC gate driving layer 1141, the first IGBT gate driving layer 1142, the first SiC source driving layer 1143, the first IGBT emitter driving layer 1144, the second SiC gate driving layer 1151, the second IGBT gate driving layer 1152, the second SiC source driving layer 1153, and the second IGBT emitter driving layer 1154. Each driving terminal 116 can be led out perpendicular to the substrate 1 to simplify the internal circuit structure of the half-bridge power module 100, reduce space occupation, and facilitate the connection of the half-bridge power module 100 with external circuits.

[0522] Optionally, the first SiC source driving layer 1143 is disposed on the side of the first SiC source driving layer 1143 near the DC positive region 111, and correspondingly, the second SiC source driving layer 1153 is disposed on the side of the second SiC source driving layer 1153 near the AC region 112. This can minimize the transmission path of the driving signal, further shorten the commutation loop of the SiC MOSFET, reduce parasitic inductance, and improve dynamic current sharing.

[0523] In some embodiments, referring to FIG4, a first SiC source drive layer 1143 is provided with a plurality of drive resistors corresponding one-to-one with and connected to a plurality of wide bandgap power chips 23 in a first wide bandgap chipset 211; a second SiC source drive layer 1153 is provided with a plurality of drive resistors corresponding one-to-one with and connected to a plurality of wide bandgap power chips 23 in a second wide bandgap chipset 221. The drive resistors can connect the gate 232 of the corresponding wide bandgap power chip 23, such as a SiC MOSFET, to the copper layer on which it resides. By setting the drive resistors, the gate current 232 of the SiC MOSFET can be limited, ensuring the switching speed and performance of the SiC MOSFET. Additionally, it can protect the drive circuit from damage caused by overcurrent and overvoltage.

[0524] Optionally, the multiple driving resistors on the first SiC source driving layer 1143 can be connected in series or in parallel as needed, and the multiple driving resistors on the second SiC source driving layer 1153 can be connected in series or in parallel as needed.

[0525] Understandably, since the first SiC source drive layer 1143 is located on the side of the first SiC source drive layer 1143 closer to the DC positive region 111, and the second SiC source drive layer 1153 is located on the side of the second SiC source drive layer 1153 closer to the AC region 112, the driving resistors are brought closer to the corresponding SiC MOSFETs, minimizing the resistance and capacitance of the drive signal transmission, which is beneficial to improving the system's response speed and stability.

[0526] In some embodiments, referring to Figures 1-4 and Figure 17, the first SiC source driving layer 1143 and the first IGBT emitter driving layer 1144 are connected to form a first common copper layer 1145. In this case, the first SiC source driving layer 1143 and the first IGBT emitter driving layer 1144 can share the same driving terminal 116. This simplifies the internal structure of the half-bridge power module 100.

[0527] In some embodiments, the second SiC source driving layer 1153 and the second IGBT emitter driving layer 1154 are connected to form a second common copper layer 1155. In this case, the second SiC source driving layer 1153 and the second IGBT emitter driving layer 1154 can share the same driving terminal 116. This simplifies the internal structure of the half-bridge power module 100.

[0528] In some embodiments, referring to FIG1, the conductive metal layer 11 may include a first side 110a and a second side 110b opposite to each other along a first direction, and a third side 110c and a fourth side 110d opposite to each other along a second direction.

[0529] The first driving layer group 114 is disposed along the first side 110a, and at least a portion of the structure of the DC positive region 111 is located on the side of the first driving layer group 114 away from the first side 110a along the first direction. For example, the DC positive region 111 may be entirely located on the side of the first driving layer group 114 away from the first side 110a along the first direction; or, the DC positive region 111 may partially surround the first driving layer group 114, in which case a portion of the DC positive region 111 is located on the side of the first driving layer group 114 away from the first side 110a along the first direction, and another portion is disposed along the first side 110a and arranged side by side with the first driving layer group 114 along the second direction. In this way, the distance between the wide bandgap power chip 23 and the silicon-based power chip 24 in the DC positive region 111 and the first driving layer group 114 can be shortened as much as possible, thereby shortening the length of the connection lines 26 of each chip in the upper bridge 21, which is beneficial to reducing parasitic inductance.

[0530] The second driving layer group 115 is located on the side of the DC negative electrode region 113 facing the second side 110b along the first direction. That is, the second driving layer group 115 is disposed along the second side 110b, and at least a portion of the structure of the DC negative electrode region 113 is located on the side of the second driving layer group 115 away from the second side 110b along the first direction. For example, the DC negative electrode region 113 may be entirely located on the side of the second driving layer group 115 away from the second side 110b along the first direction; or, the DC negative electrode region 113 may partially surround the second driving layer group 115. In this case, a portion of the DC negative electrode region 113 is located on the side of the second driving layer group 115 away from the second side 110b along the first direction, and another portion is disposed along the second side 110b and arranged side by side with the second driving layer group 115 along the second direction.

[0531] The AC region 112 at least partially surrounds the second driving layer group 115. In this way, the distance between the wide bandgap power chip 23 and the silicon-based power chip 24 in the AC region 112 and the second driving layer group 115 can be shortened as much as possible, thereby shortening the length of the connection line 26 of each chip in the lower bridge 22, which is beneficial to reducing parasitic inductance.

[0532] Referring to Figure 21, the full-bridge power module 300 of this embodiment may include the half-bridge power module 100 described in the above embodiment. Specifically, there may be three half-bridge power modules 100, which are connected together to form a three-phase full-bridge power module 300. Each half-bridge power module 100 corresponds to one single phase. For example, the three half-bridge power modules 100 include a first half-bridge power module 100, a second half-bridge power module 100, and a third half-bridge power module 100. The first half-bridge power module 100 corresponds to phase U, the second half-bridge power module 100 corresponds to phase V, and the third half-bridge power module 100 corresponds to phase W. The first half-bridge power module 100 corresponding to phase U, the second half-bridge power module 100 corresponding to phase V, and the third half-bridge power module 100 corresponding to phase W can be arranged sequentially, or the order can be adjusted as needed.

[0533] In addition, the full-bridge power module 300 may also include a heat sink 200, and the three half-bridge power modules 100 may all be mounted on the same heat sink 200.

[0534] The full-bridge power module 300 according to the embodiments of this application is composed of three half-bridge power modules 100 as described in the above embodiments. Since each half-bridge power module 100 is a plurality of parallel half-bridge circuits formed by wide-bandgap power chips 23 and silicon-based power chips 24, the current specification of the full-bridge power module 300 is greatly amplified, which can better convert DC power into AC power for use by electrical devices. It has stronger electrical performance and is more suitable for use as an automotive-grade power module.

[0535] Referring to Figures 22-25, the half-bridge power module 100 of this embodiment includes: a substrate 1 and a circuit unit 2.

[0536] The substrate 1 can be one of the following: thick film printed ceramic substrate 1 (TPC), direct bonded copper ceramic substrate 1 (DBC), active metal welded ceramic substrate 1 (AMB), direct electroplated copper ceramic substrate 1 (DPC), or it can be other types of substrate 1.

[0537] The substrate 1 may include a first surface and a second surface opposite to each other. The first surface is provided with a conductive metal layer 11. For example, the substrate 1 may include a ceramic layer 10 and copper layers located on both sides of the ceramic layer 10. The ceramic layer 10 may be at least one of alumina, silicon nitride, and aluminum nitride. One of the copper layers may serve as the conductive metal layer 11. The conductive metal layer 11 may be divided into multiple conductive areas according to the circuit layout requirements. Each conductive area may be used to set up a power chip and a connection circuit for connecting different power chips (this connection circuit is not shown in the figure and may be reasonably set according to the arrangement of each power chip, and will not be described in detail below). The other copper layer may serve as a heat dissipation surface of the substrate 1.

[0538] The conductive metal layer 11 may include a DC positive region 111, an AC region 112, and a DC negative region 113. Any one of the DC positive region 111, AC region 112, and DC negative region 113 can be square or irregularly shaped with multiple sides, and any one of the sides can be a right-angled side or a hypotenuse. Of course, this application is not limited to this; the shapes of the DC positive region 111, AC region 112, and DC negative region 113 can be flexibly set according to circuit layout requirements.

[0539] The DC positive region 111 can be connected to the positive terminal of a DC power supply, the DC negative region 113 can be connected to the negative terminal of a DC power supply, and the AC region 112 can be connected to an AC output load to achieve DC-AC conversion; or, the AC region 112 can be connected to an AC power supply, the DC positive region 111 can be connected to the positive terminal of a DC load, and the DC negative region 113 can be connected to the negative terminal of a DC load to achieve AC-DC conversion.

[0540] Circuit unit 2 may include an upper bridge 21 and a lower bridge 22. The upper bridge 21 is located in the DC positive region 111, and the lower bridge 22 is located in the AC region 112. Each of the upper bridge 21 and the lower bridge 22 includes a wide bandgap chipset and a silicon-based chipset. Specifically, the upper bridge 21 includes a first wide bandgap chipset 211 and a first silicon-based chipset 212, and the lower bridge 22 includes a second wide bandgap chipset 221 and a second silicon-based chipset 222.

[0541] Both the first wide-bandgap chipset 211 and the second wide-bandgap chipset 221 include multiple wide-bandgap power chips 23 arranged along a first direction (the Y direction as shown in Figure 22). The multiple wide-bandgap power chips 23 in the first wide-bandgap chipset 211 are connected in parallel; here, "multiple" refers to two or more. The first wide-bandgap chipset 211 and the second wide-bandgap chipset 221 are arranged along a second direction (the X direction as shown in Figure 22). The wide-bandgap power chips 23 in the first wide-bandgap chipset 211 and the second wide-bandgap chipset 221 can correspond one-to-one. Corresponding two wide-bandgap power chips 23 can form a half-bridge circuit. Furthermore, since multiple half-bridge circuits are connected in parallel, a half-bridge circuit with a current amplification factor of N times (the number of half-bridge circuits is N) can be formed, which is beneficial for improving the power level of the half-bridge power module 100.

[0542] In the first wide-bandgap chipset 211, multiple wide-bandgap power chips 23 are electrically connected to the AC region 112, and in the second wide-bandgap chipset 221, multiple wide-bandgap power chips 23 are electrically connected to the DC negative region 113. The electrical connection can be made via connecting wires 26, which can be gold wire, silver wire, copper wire, aluminum wire, copper strip, aluminum strip, metal connecting piece, or other conductive metal wire.

[0543] Among them, the wide bandgap semiconductor material can include SiC, GaN, etc., that is, the wide bandgap power chip 23 is a SiC device or a GaN device. The SiC device can be a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0544] Referring to Figures 22-25, 29, and 30, during the operation of the half-bridge power module 100, part of the current flows from the DC positive region 111 to the DC negative region 113. Multiple wide-bandgap power chips 23 in the first wide-bandgap chip group 211 are arranged along a first direction, and the first wide-bandgap chip group 211 and the AC region 112 are opposite each other along a second direction. At this time, the arrangement direction of the multiple wide-bandgap power chips 23 is perpendicular to the current flow direction between the first wide-bandgap chip group 211 and the AC region 112. Thus, each wide-bandgap power chip 23 in the first wide-bandgap chip group 211 has a relatively close or even identical current path, improving the current distribution. This results in each wide-bandgap power chip 23 in the first wide-bandgap chip group 211 having good dynamic current sharing performance, which is beneficial for ensuring the uniform distribution of current stress and thermal stress among the wide-bandgap power chips 23.

[0545] Similarly, when multiple wide-bandgap power chips 23 in the second wide-bandgap chipset 221 are arranged along the first direction, and each wide-bandgap power chip 23 is opposite to the DC negative electrode region 113 along the second direction, when the current output direction in the DC negative electrode region 113 is the same as the current direction between each wide-bandgap power chip 23 and the DC negative electrode region 113, each wide-bandgap power chip 23 in the second wide-bandgap chipset 221 can have good dynamic current sharing performance, which is beneficial to ensuring the uniform distribution of current stress and thermal stress among each wide-bandgap power chip 23 in the second wide-bandgap chipset 221.

[0546] In other words, by setting it as described above, it is possible to ensure that the first wide bandgap chipset 211 and each wide bandgap power chip 23 of the first wide bandgap chipset 211 have good dynamic current sharing performance, which is conducive to ensuring the uniform distribution of current stress and thermal stress among each wide bandgap power chip 23.

[0547] Of course, in addition to the above methods, the direction of the current output in the DC negative pole region 113 is related to the setting position of the DC negative terminal 118, and this embodiment does not limit this.

[0548] Both the first silicon-based chipset 212 and the second silicon-based chipset 222 may include at least one silicon-based power chip 24. The silicon-based power chip 24 is a silicon device. For example, there may be one or more silicon-based power chips 24, where "more" refers to two or more. The silicon-based power chip 24 is a Si-based fully controllable power chip, such as a Si IGBT (Insulated Gate Bipolar Transistor) or a Si MOSFET.

[0549] In other words, the half-bridge power module 100 in this embodiment is a hybrid half-bridge power module 100 that integrates wide-bandgap semiconductor devices and silicon semiconductor devices.

[0550] The silicon-based power chips 24 of the first silicon-based chipset 212 and the second silicon-based chipset 222 can be matched one-to-one. The two corresponding wide-bandgap power chips 23 can form a half-bridge circuit. Multiple half-bridge circuits can be connected in parallel to form a half-bridge circuit with a current specification amplification of N (the number of half-bridge circuits is N).

[0551] The half-bridge power module 100 of this application embodiment integrates a wide-bandgap power chip 23 and a silicon-based power chip 24 connected in parallel, forming a single-phase half-bridge power module 100 that combines the wide-bandgap power chip 23 and the silicon-based power chip 24. This can better expand the current specifications and power levels, while also taking into account switching losses and cost issues. Furthermore, the first wide bandgap chipset 211 and the second wide bandgap chipset 221 are arranged along the second direction. Both the first wide bandgap chipset 211 and the second wide bandgap chipset 221 include a plurality of wide bandgap power chips 23 arranged along the first direction. The plurality of wide bandgap power chips 23 in the first wide bandgap chipset 211 are connected to the AC region 112 through the connecting line 26 (such as the first connecting line 261) along the second direction. The plurality of wide bandgap power chips 23 in the second wide bandgap chipset 221 are connected to the DC negative region 113 through the connecting line 26 (such as the second connecting line 262) along the second direction. This can at least ensure that each wide bandgap power chip 23 in the first wide bandgap chipset 211 has good dynamic current sharing performance, which is conducive to ensuring the uniform distribution of current stress and thermal stress among each wide bandgap power chip 23, thereby improving the electrical performance and reliability of the half-bridge power module 100.

[0552] For ease of description, the following explanation will use the wide bandgap power chip 23 as a SiC MOSFET and the silicon-based power chip 24 as a Si IGBT as examples.

[0553] In some embodiments, referring to Figures 22-25, at least a portion of the structures of each of the DC positive region 111, AC region 112, and DC negative region 113 extend along a first direction and are arranged sequentially along a second direction. For example, the DC positive region 111 may be integrally formed as a square extending along the first direction, or a portion of the DC positive region 111 may extend along the first direction and another portion may extend along the second direction; the DC negative region 113 may be integrally formed as a square extending along the first direction, or a portion of the DC negative region 113 may extend along the first direction and another portion may extend along the second direction; the AC region 112 may be integrally formed as a square extending along the first direction, or a portion of the AC region 112 may extend along the first direction and another portion may extend along the second direction; the shape and size of any two of the DC positive region 111, AC region 112, and DC negative region 113 may be the same or different, and can be reasonably set according to actual needs. The portions of the DC positive region 111, AC region 112 and DC negative region 113 extending along the first direction can be arranged along the second direction. The first wide bandgap chip group 211 is located in the portion of the DC positive region 111 extending along the first direction, and the second wide bandgap chip group 221 is located in the portion of the AC region 112 extending along the first direction.

[0554] In this way, it is possible to facilitate the connection of multiple wide bandgap power chips 23 arranged along the first direction on the DC positive region 111 to the AC region 112 through the connection line 26 along the second direction, and to facilitate the connection of multiple wide bandgap power chips 23 in the AC region 112 to the DC negative region 113 through the connection line 26 along the second direction, so as to improve the current sharing among the wide bandgap power chips 23.

[0555] Referring to Figures 22-25, in some embodiments, the outer contour of the conductive metal layer 11 includes a first side 110a and a second side 110b opposite to each other along a first direction, and a third side 110c and a fourth side 110d opposite to each other along a second direction.

[0556] The DC positive region 111 may include a first positive transmission region 1111 and a second positive transmission region 1112. The first positive transmission region 1111 may extend along a second direction and is disposed along a first side 110a. The second positive transmission region 1112 extends along a first direction. A first wide bandgap chip group 211 is disposed in the second positive transmission region 1112. A first silicon-based chip group 212 is disposed in the first positive transmission region 1111 and is located on the side of the second positive transmission region 1112 near the fourth side 110d.

[0557] The DC negative pole region 113 may include a first negative pole transmission region 1131 and a second negative pole transmission region 1132. The first negative pole transmission region 1131 extends along a second direction and is disposed along a third side 110c. The second negative pole transmission region 1132 is disposed along a second side 110b and extends along a first direction. The second negative pole transmission region 1132 and the first positive pole transmission region 1111 are arranged opposite to each other along the first direction.

[0558] The AC region 112 may include a first AC region 1121 and a second AC region 1122, wherein the first AC region 1121 and the second AC region 1122 are provided with recessed areas to accommodate a second positive electrode transmission region 1112 extending along a first direction. The first AC region 1121 extends along the first direction and is located between the second positive electrode transmission region 1112 and the first negative electrode transmission region 1131, and the second AC region 1122 is located between the second positive electrode transmission region 1112 and the second negative electrode transmission region 1132. A second wide bandgap chipset 221 is disposed in the first AC region 1121, and a second silicon-based chipset 222 is disposed in the second AC region 1122 and is located on the side of the first AC region 1121 near the fourth side 110d. In the first wide bandgap chipset 211, multiple wide bandgap power chips 23 are connected to the first AC region 1121 via a connection line 26 (i.e., the first connection line 261) along the second direction; in the second wide bandgap chipset 221, multiple wide bandgap power chips 23 are connected to the first negative transmission region 1131 via a connection line 26 (i.e., the second connection line 262) along the second direction.

[0559] In this way, the first negative transmission region 1131, the first AC region 1121, and the second positive transmission region 1112 are arranged sequentially along the second direction and from the third side 110c to the fourth side 110d, so that the multiple wide bandgap power chips 23 arranged along the first direction on the DC positive region 111 can be connected to the DC negative region 113 through the connecting line 26 (such as the first connecting line 261), and so that the multiple wide bandgap power chips 23 in the AC region 112 can be connected to the DC negative region 113 through the connecting line 26 (such as the second connecting line 262). The connecting line 26 can be parallel to the second direction or have an angle to improve the current sharing among the wide bandgap power chips 23.

[0560] In some embodiments, referring to Figures 22-25, the substrate 1 may further include a DC positive terminal 117, a DC negative terminal 118, and an AC terminal 119. The DC positive terminal 117 is disposed in the first positive transmission region 1111 and led out from the third side 110c, the DC negative terminal 118 is disposed in the first negative transmission region 1131 and led out from the third side 110c, and the AC terminal 119 is disposed in the second AC region 1122 and led out from the fourth side 110d.

[0561] Thus, the DC positive terminal 117 and the DC negative terminal 118 are located on the same side of the DC positive region 111 and the DC negative region 113 along the second direction, respectively. Both the DC positive terminal 117 and the DC negative terminal 118 can be led out along the second direction. The AC terminal 119 is located on the other side of the AC region 112 along the second direction, and the AC terminal 119 can be led out along the second direction. Arranging the DC terminals on the same side and the AC terminals on the other side helps to shorten the switching commutation loop of the SiC MOSFET, reduce inductance, improve dynamic current sharing, and simplify the construction of the external circuitry used to connect the half-bridge power module 100.

[0562] Furthermore, since the current confluence direction in the DC negative region 113 is along the second direction, which is parallel to the current direction between the multiple wide bandgap chips in the second wide bandgap chip group 221 and the DC negative region 113, the various wide bandgap power chips 23 in the second wide bandgap chip group 221 have relatively close or even identical current paths, which improves the current distribution. As a result, the various wide bandgap power chips 23 in the second wide bandgap chip group 221 have good dynamic current sharing performance, which is beneficial to ensuring the uniform distribution of current stress and thermal stress among the various wide bandgap power chips 23.

[0563] In some embodiments, in conjunction with Figures 22-25, the DC negative terminal 118 and the second wide bandgap chipset 221 are opposite each other along the second direction. This can further shorten the distance between the multiple wide bandgap chips in the second wide bandgap chipset 221 and the DC negative terminal 118, thereby shortening the SiC MOSFET commutation circuit, reducing parasitic inductance, and improving dynamic current sharing.

[0564] In some embodiments, in conjunction with Figures 22-25 and Figure 31, the plurality of wide bandgap power chips 23 in the first wide bandgap chipset 211 are aligned in the first direction. This ensures that the plurality of wide bandgap power chips 23 in the first wide bandgap chipset 211 are at the same distance from the first AC region 1121 in the second direction. This maximizes the current sharing of the plurality of wide bandgap power chips 23 in the first wide bandgap chipset 211, and the layout is relatively simple and compact, which can reduce the space occupied and improve the space utilization rate.

[0565] Referring to Figures 22-24 and Figure 31, the multiple wide bandgap power chips 23 in the second wide bandgap chipset 221 are aligned in the second direction. This ensures that the multiple wide bandgap power chips 23 in the second wide bandgap chipset 221 are at the same distance from the first negative electrode transmission region 1131 in the second direction. This maximizes the current sharing of the multiple wide bandgap power chips 23 in the second wide bandgap chipset 221, and the layout is relatively simple and compact, which can reduce the space occupied and improve the space utilization rate.

[0566] In some embodiments, referring to FIG32, any two adjacent wide-bandgap power chips 23 in the first wide-bandgap chipset 211 are staggered along the second direction. This helps to reduce the thermal coupling of the multiple similar wide-bandgap power chips 23 in the first wide-bandgap chipset 211, thereby reducing the thermal impact in this area, improving heat dissipation performance, and providing better current distribution.

[0567] In some embodiments, referring to Figures 25 and 32, any two adjacent wide-bandgap power chips 23 in the second wide-bandgap chipset 221 are staggered along the second direction. This helps to reduce the thermal coupling of the multiple similar wide-bandgap power chips 23 in the second wide-bandgap chipset 221, thereby reducing the thermal impact in this area, improving heat dissipation performance, and providing better current distribution.

[0568] For example, as shown in Figure 32, the first wide bandgap chipset 211 and the second wide bandgap chipset 221 each have three wide bandgap power chips 23. Along the first direction and from the first side 110a toward the second side 110b, they are arranged in sequence as wide bandgap power chip 23a, wide bandgap power chip 23b, and wide bandgap power chip 23c. Among them, wide bandgap power chips 23a and wide bandgap power chips 23c are both located on the side of wide bandgap power chip 23b away from the fourth side 110d along the second direction. In this way, on the one hand, it is beneficial to improve the current sharing between wide bandgap power chips 23a and wide bandgap power chips 23b to a certain extent, and on the other hand, it can reduce the thermal coupling between wide bandgap power chips 23a, wide bandgap power chips 23b, and wide bandgap power chips 23c.

[0569] Alternatively, both wide-bandgap power chips 23a and 23c can be located on the side of wide-bandgap power chip 23b along the second direction towards the fourth side 110d. This can also reduce the thermal coupling between wide-bandgap power chips 23a, 23b, and 23c, and improve heat dissipation performance.

[0570] Referring to Figures 39 and 40, Figure 39 shows the equivalent circuit of the hybrid half-bridge power module 100 considering parasitic inductance, and Figure 40 shows a typical switching waveform diagram of the hybrid half-bridge power module 100. In the hybrid module application shown in Figure 39, the circuit turn-on process typically begins with the SiC MOSFE turning on first. At this time, the voltage drops, and the SiC MOSFE carries the entire current. Then, the Si IGBT turns on, and the SiC MOSFE and Si IGBT commutate, with each carrying a portion of the current. During the turn-off process, the Si IGBT turns off first. At this time, the SiC MOSFE and Si IGBT commutate, and the SiC chip carries the entire current. Then, the SiC chip turns off, and the voltage rises, resulting in a turn-off voltage spike. The voltage spike generated during the turn-off process has an adverse effect on the normal operation of the half-bridge power module 100 and needs to be minimized. SiC MOSFE switches faster than Si IGBT switches slower. Under the same inductance, the voltage spike generated by SiC MOSFE is much higher than that of IGBT. That is, the turn-off voltage spike caused by the inductance of the switching commutation circuit of SiC MOSFE is more severe.

[0571] Therefore, to reduce this voltage spike, in this embodiment, the first wide bandgap chipset 211 is located on the side of the first silicon-based chipset 212 along the second direction, closer to the DC positive terminal 117, and the second wide bandgap chipset 221 is located on the side of the second silicon-based chipset 222 along the second direction, away from the AC terminal 119. This significantly shortens the switching commutation loop length of the SiC MOSFE, thereby reducing parasitic inductance, lowering the turn-off voltage spike, improving the stability and reliability of the half-bridge power module 100, and reducing interference to other electronic components in the circuit.

[0572] In some embodiments, the first wide bandgap chipset 211 and the second wide bandgap chipset 221 are also provided with diodes 25 (i.e., first-type diodes). The diodes 25 have the same substrate material type as the wide bandgap power chip 23. For example, the diodes 25 can be SiC SBDs (Schottky diodes 25), etc. The diodes 25 are connected in parallel with the wide bandgap power chip 23. The diodes 25 can be used to protect the SiC MOSFE and prevent excessive reverse current from damaging the SiC MOSFE. In addition, by connecting the SiC SBDs in parallel, the reverse recovery charge of the SiC SBDs is lower when the SiC MOSFE is turned off during the dead time, which can greatly reduce power loss, reduce energy loss, and improve conversion efficiency, thereby improving the performance of the half-bridge power module 100. The diodes 25 in the first wide bandgap chipset 211 can be connected to the AC region 112 through the connecting line 26, and the diodes 25 in the second wide bandgap chipset 221 can be connected to the DC negative region 113 through the connecting line 26.

[0573] In addition to the above-described scheme, referring to Figures 22-25 and 33-36, considering that the silicon-based power chip 24, such as a Si IGBT, lacks reverse conduction capability during operation, in this embodiment, both the first silicon-based chip group 212 and the second silicon-based chip group 222 include at least one diode 25 (i.e., a second-type diode 25a). The second-type diode 25a can have the same substrate material as the silicon-based power chip 24. There can be one or more second-type diodes 25a, where "multiple" refers to two or more. Each second-type diode 25a corresponds one-to-one with a silicon-based power chip 24. The corresponding silicon-based power chip 24 and the second-type diode 25a are connected in parallel to form a chip pair. For example, the second-type diode 25a can be a fast recovery second-type diode 25a, and it can be connected in reverse parallel with the silicon-based power chip 24. In this embodiment, by connecting the second-type diode 25a in reverse parallel with the silicon-based power chip 24, the overall reverse current carrying capacity of the module can be enhanced, which is beneficial to improving the overall efficiency and reliability of the half-bridge power module 100. In the first silicon-based chip group 212, the second type diode 25a can be connected to the AC region 112 via the connecting line 26, and the second type diode 25a in the second silicon-based chip group 222 can be connected to the DC negative region 113 via the connecting line 26.

[0574] Optionally, only the first wide bandgap chipset 211 and the second wide bandgap chipset 221 may have diodes 25 with the same substrate material as the wide bandgap power chip 23; or, only the first silicon-based chipset 212 and the second silicon-based chipset 222 may have diodes 25 with the same substrate material as the silicon-based power chip 24; or, the first wide bandgap chipset 211 and the second wide bandgap chipset 221 may have diodes 25 with the same substrate material as the wide bandgap power chip 23, while the first silicon-based chipset 212 and the second silicon-based chipset 222 may have diodes 25 with the same substrate material as the silicon-based power chip 24.

[0575] For ease of description, the following description will only take the example of the first silicon-based chipset 212 and the second silicon-based chipset 222 having diodes 25 made of the same material as the silicon-based power chip 24.

[0576] In some embodiments, there are multiple silicon-based power chips 24 and second-type diodes 25a in the first silicon-based chipset 212 and the second silicon-based chipset 222. Thus, multiple chip pairs are formed in both the first silicon-based chipset 212 and the second silicon-based chipset 222. The multiple chip pairs are arranged along the second direction, which can amplify the current specification, expand the power level, and improve the power load.

[0577] Furthermore, referring to Figures 33, 36 and 37, the silicon-based power chip 24 and the second type diode 25a in each chip pair are arranged along a first direction or a second direction.

[0578] As shown in Figure 33, there are two chip pairs, meaning there can be two silicon-based power chips 24 and two types of diodes 25a. In this case, the silicon-based power chips 24 and the second type of diodes 25a can be arranged alternately in the second direction. In this configuration, the silicon-based power chips 24 and the second type of diodes 25a in the first silicon-based chip group 212 are both connected to the AC region 112 via a connecting line 26 along the first direction. Similarly, the silicon-based power chips 24 and the second type of diodes 25a in the second silicon-based chip group 222 are connected to the DC negative region 113 via the connecting line 26 along the first direction. This method separates silicon-based chips of the same type (including the aforementioned silicon-based power chips 24 and second type of diodes 25a) in each conductive region, which helps avoid thermal coupling between similar silicon-based chips, reduces heat dissipation pressure, and minimizes the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 along the first direction, thus improving space utilization.

[0579] Alternatively, as shown in Figures 35 and 36, the silicon-based power chip 24 and the second type diode 25a in each chip pair are arranged along a first direction.

[0580] In some embodiments, the silicon-based power chips 24 and the second type diodes 25a in the multiple chip pairs are arranged in the same or opposite directions.

[0581] For example, as shown in Figure 35, there are two chip pairs. The silicon-based power chip 24 and the second type diode 25a in each chip pair are arranged along the first direction, and the silicon-based power chip 24 in each chip pair is located on the same side of the corresponding second type diode 25a along the first direction. In this way, the current sharing performance of the silicon-based power chip 24 and the second type diode 25a in the two chip pairs are better, and the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 along the second direction is smaller.

[0582] Alternatively, as shown in Figure 36, there are two chip pairs. In each chip pair, the silicon-based power chip 24 and the second-type diode 25a are arranged along a first direction. In one chip pair, the silicon-based power chip 24 is located on one side of the corresponding second-type diode 25a along the first direction, and in the other chip pair, the silicon-based power chip 24 is located on the other side of the corresponding second-type diode 25a along the first direction. Furthermore, the silicon-based power chip 24 in one chip pair and the second-type diode 25a in the other chip pair are arranged side-by-side along a second direction. This arrangement, with the silicon-based power chips 24 and the second-type diodes 25a in multiple chip pairs facing opposite directions, helps reduce thermal coupling of the same type of silicon-based chips, improves heat dissipation performance, and reduces the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 along the second direction.

[0583] Understandably, when the silicon-based power chip 24 and the second type diode 25a in each chip pair are arranged along the first direction, the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 in the first direction increases and the space occupied in the second direction decreases. Therefore, the size of the area of ​​the DC positive region 111 corresponding to the first silicon-based chip group 212 can be adjusted to match the space occupied by the first silicon-based chip group 212 in the first and second directions. At the same time, the size of the area of ​​the AC region 112 corresponding to the second silicon-based chip group 222 can also be adjusted to match the space occupied by the second silicon-based chip group 222 in the first and second directions.

[0584] In some embodiments, referring to FIG34, both the first silicon-based chipset 212 and the second silicon-based chipset 222 have multiple chip pairs. Multiple silicon-based power chips 24 are arranged adjacent to each other along a second direction, and multiple second-type diodes 25a are arranged adjacent to each other along the second direction. In other words, in this embodiment, chips of the same type are adjacent to each other and connected to corresponding conductive areas via connecting lines 26 along the first direction. This chip arrangement in this embodiment facilitates the setting of the driving connecting lines 26, and the smaller dimensions of the first silicon-based chipset 212 and the second silicon-based chipset 222 along the first direction improve the space utilization of the first silicon-based chipset 212 and the second silicon-based chipset 222 along the first direction.

[0585] In some embodiments, referring to Figures 26-28, the wide-bandgap power chip 23 includes a SiC MOSFET, and the silicon-based power chip 24 includes a Si IGBT. That is, in this embodiment, the copper layers of the SiC half-bridge and the IGBT half-bridge are electrically connected inside the half-bridge power module 100. This reduces the commutation inductance of the SiC device and the IGBT device, shortens the commutation time, and improves efficiency.

[0586] As shown in Figure 26, the SiC MOSFET includes a source 231, a gate 232, and a drain 233. The drain 233 is located on the side of the SiC MOSFET facing the conductive metal layer 11 and is connected to the conductive region thereon through a welding or sintering process. The source 231 and the gate 232 are located on the side of the SiC MOSFET away from the conductive metal layer 11 and are used to connect to other conductive regions.

[0587] As shown in Figure 27, the Si IGBT includes an emitter 241, a gate 242, and a collector 243. The collector 243 is located at the bottom of the Si IGBT (the side of the Si IGBT facing the conductive metal layer 11) and is used to connect with the conductive region thereon by means of sintering, welding, etc. The emitter 241 and the gate 242 are located on the side of the Si IGBT away from the conductive metal layer 11 and are used to connect with other conductive regions.

[0588] As shown in Figure 28, diode 25 can be a Si FRD (fast recovery diode 25). Diode 25 includes a cathode 25a and an anode 251. The anode 251 is located at the top of diode 25 (i.e., the side of diode 25 facing away from conductive metal layer 11) and is used for electrical connection with other conductive areas. The cathode 25a is located at the bottom of diode 25 (i.e., the side of diode 25 facing conductive metal layer 11) and is connected to the conductive area thereon by sintering or welding.

[0589] In other words, the half-bridge power module 100 of this embodiment packages a SiC MOSFET and a Si IGBT in parallel. This allows the SiC MOSFET to perform the switching action using drive signals with different timings, while the Si IGBT bears most of the conduction current. This solves the problems of high switching losses and low switching frequency of IGBTs. Furthermore, a larger current can be controlled by a SiC MOSFET with a smaller current carrying capacity, thus solving the problem of high SiC cost. In this way, both the performance and cost of the half-bridge power module 100 can be balanced.

[0590] In some embodiments, in conjunction with Figures 22-25, 27, and 28, the conductive metal layer 11 may further include two driving layer regions, which correspond to the upper bridge 21 and the lower bridge 22, respectively. The two driving layer regions are the first driving layer region 115 and the second driving layer region 114.

[0591] The second driving layer region 114 may include: a second SiC gate driving layer 1141, a second IGBT gate driving layer 1142, a second SiC source driving layer 1143, and a second IGBT emitter driving layer 1144. The gate 232 of the SiC MOSFET of the upper bridge 21 is connected to the second SiC gate driving layer 1141 via a connection line 26, the source 231 of the SiC MOSFET of the upper bridge 21 is connected to the second SiC source driving layer 1143 via a connection line 26, the gate 242 of the Si IGBT of the upper bridge 21 is connected to the second IGBT gate driving layer 1142 via a connection line 26, and the emitter 241 of the Si IGBT of the upper bridge 21 is connected to the second IGBT emitter driving layer 1144 via a connection line 26.

[0592] The first driving layer region 115 may include: a first SiC gate driving layer 1151, a first IGBT gate driving layer 1152, a first SiC source driving layer 1153, and a first IGBT emitter driving layer 1154. The gate 232 of the SiC MOSFET of the lower bridge 22 is connected to the first SiC gate driving layer 1151 through the connection line 26. The source 231 of the SiC MOSFET of the lower bridge 22 is connected to the first SiC source driving layer 1153 through the connection line 26. The gate 242 of the Si IGBT of the lower bridge 22 is connected to the first IGBT gate driving layer 1152 through the connection line 26. The emitter 241 of the Si IGBT of the lower bridge 22 is connected to the first IGBT emitter driving layer 1154 through the connection line 26.

[0593] Thus, by setting the first driving layer region 115 and the second driving layer region 114, it is possible to facilitate the connection between each wide bandgap power chip 23, silicon-based power chip 24 and external circuits.

[0594] Optionally, in conjunction with Figures 22-25, 27, and 28, driving terminals 116 are provided on the second SiC gate driving layer 1141, the second IGBT gate driving layer 1142, the second SiC source driving layer 1143, the second IGBT emitter driving layer 1144, the first SiC gate driving layer 1151, the first IGBT gate driving layer 1152, the first SiC source driving layer 1153, and the first IGBT emitter driving layer 1154. Each driving terminal 116 can be led out perpendicularly to the substrate 1 to simplify the internal circuit structure of the half-bridge power module 100, reduce space occupation, and facilitate the connection of the half-bridge power module 100 with external circuits.

[0595] Optionally, the second driving layer region 114 can be located between the second wide bandgap chipset 211 and the second silicon-based chipset 212, and the first driving layer region 115 can be located between the DC positive region 111 and the AC region 112. In this way, the transmission path of each driving signal can be minimized and parasitic inductance can be reduced.

[0596] Optionally, referring to Figures 22 and 27, the second SiC source driving layer 1143 and the second IGBT emitter driving layer 1144 are connected to form a second common copper layer 1145. In this case, the second SiC source driving layer 1143 and the second IGBT emitter driving layer 1144 can share the same driving terminal 116. This simplifies the internal structure of the half-bridge power module 100 and improves space utilization. Correspondingly, the first SiC source driving layer 1153 and the first IGBT emitter driving layer 1154 are connected to form a first common copper layer 1155. In this case, the first SiC source driving layer 1153 and the first IGBT emitter driving layer 1154 can share the same driving terminal 116. This also simplifies the internal structure of the half-bridge power module 100 and improves space utilization.

[0597] Optionally, referring to Figures 24, 25, and 38, the first SiC gate driving layer 1151 and the first SiC source driving layer 1153 form a first sub-layer group, and the first IGBT gate driving layer 1152 and the first IGBT emitter driving layer 1154 form a second sub-layer group. The first and second sub-layer groups can be arranged separately. For example, the first sub-layer group is located on the side of the second wide bandgap chip group 211 facing away from the second wide bandgap chip group 221 along the second direction, and the second sub-layer group can be located along the first side 110a. The second sub-layer group and the first silicon-based chip group 212 are arranged opposite to or staggered along the first direction.

[0598] The second SiC gate driving layer 1141 and the second SiC source driving layer 1143 form a third sub-layer group, and the second IGBT gate driving layer 1142 and the second IGBT emitter driving layer 1144 form a fourth sub-layer group. The third and fourth sub-layer groups can be arranged separately. For example, the third sub-layer group can be located between the first wide bandgap chip group 211 and the second wide bandgap chip group 221, or the AC region 112 can surround the third sub-layer group. The fourth sub-layer group can be arranged opposite to or offset from the second silicon-based chip group 222 along the first direction.

[0599] Of course, this application is not limited to this. The layout of the first driving layer region 114 and the second driving layer region 115 can be reasonably set according to the layout of the upper bridge 21 and the lower bridge 22 in order to minimize the transmission path of each driving signal, reduce parasitic inductance, improve efficiency, and facilitate connection with external circuits.

[0600] In some embodiments, the second SiC source drive layer 1143 is provided with a plurality of drive resistors corresponding one-to-one with and connected to the plurality of wide bandgap power chips 23 in the first wide bandgap chipset 211; the first SiC source drive layer 1153 is provided with a plurality of drive resistors corresponding one-to-one with and connected to the plurality of wide bandgap power chips 23 in the second wide bandgap chipset 221. The drive resistors can connect the gate 232 of the corresponding wide bandgap power chip 23, such as a SiC MOSFET, to the copper layer on which it is located. By setting the drive resistors, the gate current 232 of the SiC MOSFET can be limited, ensuring the switching speed and performance of the SiC MOSFET. In addition, the drive circuit can be protected from damage by overcurrent and overvoltage.

[0601] Optionally, the multiple driving resistors on the second SiC source driving layer 1143 can be connected in series or in parallel as needed, and the multiple driving resistors on the first SiC source driving layer 1153 can be connected in series or in parallel as needed.

[0602] Understandably, since the second SiC source drive layer 1143 is located on the side of the second SiC source drive layer 1143 closer to the DC positive region 111, and the first SiC source drive layer 1153 is located on the side of the first SiC source drive layer 1153 closer to the AC region 112, the driving resistors are brought closer to the corresponding SiC MOSFETs, minimizing the resistance and capacitance of the drive signal transmission, which is beneficial to improving the system's response speed and stability.

[0603] Referring to Figure 41, the full-bridge power module 300 of this embodiment may include the half-bridge power module 100 described in the above embodiment. Specifically, there may be multiple half-bridge power modules 100, such as three. The three half-bridge power modules 100 are connected to the same heat sink and form a three-phase full-bridge power module 300. Each half-bridge power module 100 corresponds to one of the single phases. For example, the three half-bridge power modules 100 include a first half-bridge power module 100, a second half-bridge power module 100, and a third half-bridge power module 100. The first half-bridge power module 100 corresponds to the U phase, the second half-bridge power module 100 corresponds to the V phase, and the third half-bridge power module 100 corresponds to the W phase. The first half-bridge power module 100, the second half-bridge power module 100, and the third half-bridge power module 100 may be arranged sequentially, or their order may be adjusted as needed.

[0604] In addition, the full-bridge power module 300 may also include a heat sink 200, and the three half-bridge power modules 100 may all be mounted on the same heat sink 200.

[0605] The full-bridge power module 300 according to the embodiments of this application is composed of three half-bridge power modules 100 as described in the above embodiments. Since each half-bridge power module 100 is a plurality of parallel half-bridge circuits formed by wide-bandgap power chips 23 and silicon-based power chips 24, the current specification of the full-bridge power module 300 is greatly amplified, which can better convert DC power into AC power for use by electrical devices. It has stronger electrical performance and is more suitable for use as an automotive-grade power module.

[0606] Referring to Figures 42-45, the half-bridge power module 100 of this embodiment includes: a substrate 1 and a circuit unit 2.

[0607] The substrate 1 can be one of the following: thick film printed ceramic substrate (TPC), direct bonded copper ceramic substrate 1 (DBC), active metal welded ceramic substrate (AMB), direct electroplated copper ceramic substrate (DPC), or other types of substrate.

[0608] The substrate 1 may include a first surface and a second surface opposite to each other. The first surface is provided with a conductive metal layer 11. For example, the substrate 1 may include a ceramic layer 10 and copper layers located on both sides of the ceramic layer 10. The ceramic layer 10 may be at least one of alumina, silicon nitride, and aluminum nitride. One of the copper layers may serve as the conductive metal layer 11. The conductive metal layer 11 may be divided into multiple conductive areas according to the circuit layout requirements. Each conductive area may be used to set up a power chip and a connection circuit for connecting different power chips (this connection circuit is not shown in the figure and may be reasonably set according to the arrangement of each power chip, and will not be described in detail below). The other copper layer may serve as a heat dissipation surface of the substrate 1.

[0609] The conductive metal layer 11 may include a DC positive region 111, an AC region 112, and a DC negative region 113. Any one of the DC positive region 111, AC region 112, and DC negative region 113 can be square or irregularly shaped with multiple sides, and any one of the sides can be a right-angled side or a hypotenuse. Of course, this application is not limited to this; the shapes of the DC positive region 111, AC region 112, and DC negative region 113 can be flexibly set according to circuit layout requirements.

[0610] The DC positive region 111 can be connected to the positive terminal of a DC power supply, the DC negative region 113 can be connected to the negative terminal of a DC power supply, and the AC region 112 can be connected to an AC output load to achieve DC-AC conversion; or, the AC region 112 can be connected to an AC power supply, the DC positive region 111 can be connected to the positive terminal of a DC load, and the DC negative region 113 can be connected to the negative terminal of a DC load to achieve AC-DC conversion.

[0611] Circuit unit 2 may include an upper bridge 21 and a lower bridge 22. The upper bridge 21 is located in the DC positive region 111, and the lower bridge 22 is located in the AC region 112. Each of the upper bridge 21 and the lower bridge 22 includes a wide bandgap chipset and a silicon-based chipset. Specifically, the upper bridge 21 includes a first wide bandgap chipset 211 and a first silicon-based chipset 212, and the lower bridge 22 includes a second wide bandgap chipset 221 and a second silicon-based chipset 222.

[0612] The first wide bandgap chipset 211 and the second wide bandgap chipset 221 are arranged along a first direction. Both the first wide bandgap chipset 211 and the second wide bandgap chipset 221 include multiple wide bandgap power chips 23, where "multiple" refers to two or more. The multiple wide bandgap power chips 23 in the first wide bandgap chipset 211 are connected in parallel. The wide bandgap power chips 23 in the first wide bandgap chipset 211 and the second wide bandgap chipset 221 can correspond one-to-one. Corresponding two wide bandgap power chips 23 can form a half-bridge circuit. Furthermore, since multiple half-bridge circuits are connected in parallel, a half-bridge circuit with a current amplification factor of N times (the number of half-bridge circuits is N) can be formed, which is beneficial for improving the power level of the half-bridge power module 100.

[0613] Referring to Figures 42-45, a plurality of wide bandgap power chips 23 of one of the first wide bandgap chipset 211 and the second wide bandgap chipset 221 are arranged along a first direction (Y direction as shown in Figure 42), and a plurality of wide bandgap power chips 23 of the other are arranged along a second direction (X direction as shown in Figure 42).

[0614] For example, multiple wide-bandgap power chips 23 in the first wide-bandgap chipset 211 can be arranged along a first direction, and multiple wide-bandgap power chips 23 in the second wide-bandgap chipset 221 can be arranged along a second direction. In this case, multiple wide-bandgap power chips 23 in the first wide-bandgap chipset 211 are all electrically connected to the AC region 112, and multiple wide-bandgap power chips 23 in the second wide-bandgap chipset 221 are all electrically connected to the DC negative region 113. Alternatively, multiple wide-bandgap power chips 23 of the first wide-bandgap chipset 211 can be arranged along the second direction, and multiple wide-bandgap power chips 23 of the second wide-bandgap chipset 221 can be arranged along the first direction. In this case, multiple wide-bandgap power chips 23 in the first wide-bandgap chipset 211 are all electrically connected to the AC region 112, and multiple wide-bandgap power chips 23 in the second wide-bandgap chipset 221 are all electrically connected to the DC negative region 113. The above-mentioned electrical connection method can be through the connection line 26. The connection line 26 can be a gold wire, silver wire, copper wire, aluminum wire, copper strip, aluminum strip, metal connecting piece, or other conductive metal wire.

[0615] Taking the arrangement of multiple wide-bandgap power chips 23 in the first wide-bandgap chipset 211 along the second direction and the arrangement of multiple wide-bandgap power chips 23 in the second wide-bandgap chipset 221 along the first direction as an example:

[0616] Among them, the wide bandgap semiconductor material can include SiC, GaN, etc., that is, the wide bandgap power chip 23 is a SiC device or a GaN device. The SiC device can be a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0617] Referring to Figures 42-45 and 51, during the operation of the half-bridge power module 100, part of the current flows from the DC positive region 111 to the DC negative region 113. Multiple wide-bandgap power chips 23 in the first wide-bandgap chip group 211 are arranged along the second direction, and each wide-bandgap power chip 23 is connected to the AC region 112 along the connecting line 26 in the first direction. This results in the arrangement direction of the multiple wide-bandgap power chips 23 being perpendicular to the current flow direction between the first wide-bandgap chip group 211 and the AC region 112. Each wide-bandgap power chip 23 in the first wide-bandgap chip group 211 has a relatively close or even identical current path, improving the current distribution. This allows each wide-bandgap power chip 23 in the first wide-bandgap chip group 211 to have good dynamic current sharing performance, which is beneficial for ensuring the uniform distribution of current stress and thermal stress among the wide-bandgap power chips 23.

[0618] Similarly, when multiple wide-bandgap power chips 23 in the second wide-bandgap chipset 221 are arranged along the first direction, and each wide-bandgap power chip 23 is connected to the DC negative terminal region 113 by a connecting line 26 along the second direction, when the current output direction within the DC negative terminal region 113 is the same as the current direction between each wide-bandgap power chip 23 and the DC negative terminal region 113, each wide-bandgap power chip 23 in the second wide-bandgap chipset 221 can have good dynamic current sharing performance, which is beneficial to ensuring the uniform distribution of current stress and thermal stress among each wide-bandgap power chip 23. Of course, the current output direction within the DC negative terminal region 113 is related to the setting position of the DC negative terminal 118, and this embodiment does not limit this.

[0619] In other words, by setting it up as described above, it can be ensured that each wide bandgap power chip 23 of the first wide bandgap chipset 211 has good dynamic current sharing performance, which is conducive to ensuring the uniform distribution of current stress and thermal stress among each wide bandgap power chip 23.

[0620] Both the first silicon-based chipset 212 and the second silicon-based chipset 222 may include at least one silicon-based power chip 24. The silicon-based power chip 24 is connected in parallel with a wide-bandgap power chip 23 on its conductive region. The silicon-based power chip 24 is a silicon device. For example, there may be one or more silicon-based power chips 24, where "multiple" refers to two or more. The silicon-based power chip 24 is a Si-based fully controllable power chip, such as a Si IGBT (Insulated Gate Bipolar Transistor) or a Si MOSFET.

[0621] In other words, the half-bridge power module 100 in this embodiment is a hybrid half-bridge power module that integrates wide-bandgap semiconductor devices and silicon semiconductor devices.

[0622] The silicon-based power chips 24 of the first silicon-based chipset 212 and the second silicon-based chipset 222 can be matched one-to-one. The two corresponding wide-bandgap power chips 23 can form a half-bridge circuit. Multiple half-bridge circuits can be connected in parallel to form a half-bridge circuit with a current specification amplification of N (the number of half-bridge circuits is N).

[0623] The half-bridge power module 100 of this application embodiment integrates a wide-bandgap power chip 23 and a silicon-based power chip 24 connected in parallel, forming a single-phase half-bridge power module 100 that combines the wide-bandgap power chip 23 and the silicon-based power chip 24. This can better expand the current specifications and power levels, while also taking into account switching losses and cost issues. Furthermore, the first wide bandgap chipset 211 and the second wide bandgap chipset 221 are arranged along a first direction. Both the first wide bandgap chipset 211 and the second wide bandgap chipset 221 include multiple wide bandgap power chips 23 arranged in parallel. The multiple wide bandgap power chips 23 of one of the first wide bandgap chipset 211 and the second wide bandgap chipset 221 are arranged along the first direction, while the multiple wide bandgap power chips 23 of the other are arranged along a second direction. This is beneficial to improving the dynamic current sharing performance of each wide bandgap power chip 23 in the first wide bandgap chipset 211, thereby improving the uniformity of current stress and thermal stress distribution among the wide bandgap power chips 23 to a certain extent, and improving the electrical performance and reliability of the half-bridge power module 100.

[0624] For ease of description, the following explanation will use the wide bandgap power chip 23 as a SiC MOSFET and the silicon-based power chip 24 as a Si IGBT as examples.

[0625] In some embodiments, referring to Figures 42-45, at least a portion of the structure of the DC positive region 111 extends along a second direction; at least a portion of the structure of the AC region 112 extends along a first direction. For example, the DC positive region 111 may be integrally formed as a square extending along the second direction, or a portion of the DC positive region 111 may extend along the second direction while another portion may extend along the first direction; the AC region 112 may be integrally formed as a square extending along the first direction, or a portion of the AC region 112 may extend along the first direction while another portion may extend along the second direction; the shape and size of any two of the DC positive region 111, the AC region 112, and the DC negative region 113 may be the same or different, and can be reasonably set according to actual needs.

[0626] The first wide bandgap chip group 211 is disposed in the portion of the DC positive region 111 extending along the second direction, and the second wide bandgap chip group 221 is disposed in the portion of the AC region 112 extending along the first direction. This facilitates the connection of multiple wide bandgap power chips 23 arranged along the second direction on the DC positive region 111 to the AC region 112 via connecting lines 26 along the first direction, and also facilitates the connection of multiple wide bandgap power chips 23 in the AC region 112 to the DC negative region 113 via connecting lines 26 along the second direction, thereby improving current sharing among the wide bandgap power chips 23.

[0627] Referring to Figures 42-45, in some embodiments, the outer contour of the conductive metal layer 11 includes a first side 110a and a second side 110b opposite to each other along a first direction, and a third side 110c and a fourth side 110d opposite to each other along a second direction.

[0628] At least a portion of the structure of the DC positive region 111 is disposed along the first side 110a. For example, a portion of the DC positive region 111 is disposed along the first side 110a, and another portion is spaced apart from the first side 110a to facilitate the arrangement of other components or conductive areas; or, the entire DC positive region 111 is disposed along the first side 110a. The first wide bandgap chip group 211 and the first silicon-based chip group 212 are arranged side by side in the DC positive region 111 along the second direction.

[0629] The DC negative region 113 includes a first negative transmission region 1131 and a second negative transmission region 1132. The first negative transmission region 1131 can be arranged along the third side 110c, and the second negative transmission region 1132 can be arranged along the second side 110b. In this case, the DC negative region 113 is formed into an L-shape. The AC region 112 is located within the space enclosed by the DC positive region 111, the first negative transmission region 1131, and the second negative transmission region 1132. The second wide bandgap chip group 221 and the second silicon-based chip group 222 are arranged side by side in the AC region 112 along the second direction.

[0630] In this way, the DC positive region 111 and the AC region 112 are arranged along the first direction, and the AC region 112 and the first negative transmission region 1131 are arranged along the second direction, so that the multiple wide bandgap power chips 23 arranged along the second direction on the DC positive region 111 are all connected to the AC region 112 through the connecting line 26 along the first direction, and so that the multiple wide bandgap power chips 23 in the AC region 112 are all connected to the DC negative region 113 through the connecting line 26 along the second direction, thereby improving the current sharing among the wide bandgap power chips 23.

[0631] In some embodiments, referring to Figures 42-45, the substrate 1 may further include a DC positive terminal 117, a DC negative terminal 118, and an AC terminal 119. The DC positive terminal 117 is disposed in the DC positive region 111 and led out from the third side 110c, the DC negative terminal 118 is disposed in the first negative transmission region 1131 and led out from the third side 110c, and the AC terminal 119 is disposed in the AC region 112 and led out from the fourth side 110d.

[0632] Thus, the DC positive terminal 117 and the DC negative terminal 118 are located on the same side of the DC positive region 111 and the DC negative region 113 along the second direction, respectively, while the AC terminal 119 is located on the other side of the AC region 112 along the second direction. The DC positive terminal 117, the DC negative terminal 118, and the AC terminal 119 can all be led out from their respective sides along the second direction. By arranging the DC terminals on the same side and the AC terminals on the other side, the construction of the external circuitry used to connect the half-bridge power module 100 can be simplified.

[0633] Furthermore, since the current confluence direction in the DC negative region 113 is along the second direction, which is parallel to the current direction between the multiple wide bandgap chips in the second wide bandgap chip group 221 and the DC negative region 113, the various wide bandgap power chips 23 in the second wide bandgap chip group 221 have relatively close or even identical current paths, which improves the current distribution. As a result, the various wide bandgap power chips 23 in the second wide bandgap chip group 221 have good dynamic current sharing performance, which is beneficial to ensuring the uniform distribution of current stress and thermal stress among the various wide bandgap power chips 23.

[0634] Referring to Figures 59 and 60, Figure 59 shows the equivalent circuit of the hybrid half-bridge power module 100 considering parasitic inductance, while Figure 60 shows a typical switching waveform diagram of the hybrid half-bridge power module 100. In the hybrid module application shown in Figure 59, the circuit's turn-on process typically begins with the SiC MOSFE turning on first. At this time, the voltage drops, and the SiC MOSFE carries the entire current. Then, the Si IGBT turns on, and the SiC MOSFE and Si IGBT commutate, with each carrying a portion of the current. During the turn-off process, the Si IGBT turns off first. At this time, the SiC MOSFE and Si IGBT commutate, and the SiC chip carries the entire current. Then, the SiC chip turns off, and the voltage rises, resulting in a turn-off voltage spike. The voltage spike generated during the turn-off process has an adverse effect on the normal operation of the half-bridge power module 100 and needs to be minimized. SiC MOSFE switches faster than Si IGBT switches slower. Under the same inductance, the voltage spike generated by SiC MOSFE is much higher than that of IGBT. That is, the turn-off voltage spike caused by the inductance of the switching commutation circuit of SiC MOSFE is more severe.

[0635] Referring to Figures 42-45, to reduce the voltage spike, in this embodiment, the first wide bandgap chipset 211 is located on the side of the first silicon-based chipset 212 along the second direction and close to the DC positive terminal 117, and the second wide bandgap chipset 221 is located on the side of the second silicon-based chipset 222 along the second direction and away from the AC terminal 119. This significantly shortens the switching commutation loop length of the SiC MOSFE, thereby reducing parasitic inductance, lowering the turn-off voltage spike, improving the stability and reliability of the half-bridge power module 100, and reducing interference to other electronic components in the circuit.

[0636] In some embodiments, in conjunction with Figures 42-45, the DC negative terminal 118 and the second wide bandgap chipset 221 are opposite each other along the second direction. This can further shorten the distance between the multiple wide bandgap chips in the second wide bandgap chipset 221 and the DC negative terminal 118, thereby shortening the SiC MOSFET commutation circuit, reducing parasitic inductance, and improving dynamic current sharing.

[0637] Referring to Figures 42, 43, 45, and 51, in some embodiments, the multiple wide-bandgap power chips 23 in the first wide-bandgap chipset 211 are aligned in the first direction. This ensures that the multiple wide-bandgap power chips 23 in the first wide-bandgap chipset 211 are at the same distance from the first AC region 1121 in the second direction. This maximizes the current sharing of the multiple wide-bandgap power chips 23 in the first wide-bandgap chipset 211, and the layout is relatively simple and compact, which can reduce the space occupied and improve the space utilization rate.

[0638] Alternatively, referring to Figures 42, 43, 45, and 52, any two adjacent wide-bandgap power chips 23 in the first wide-bandgap chipset 211 are staggered along the first direction. This helps reduce the thermal coupling of the multiple similar wide-bandgap power chips 23 in the first wide-bandgap chipset 211, thereby reducing the thermal impact in this area, improving heat dissipation performance, and providing better current distribution.

[0639] For example, as shown in Figure 52, the first wide bandgap chipset 211 has three wide bandgap power chips 23, which are arranged sequentially along the second direction from the third side 110c toward the fourth side 110d as wide bandgap power chip 23a1, wide bandgap power chip 23b1, and wide bandgap power chip 23c1. Among them, wide bandgap power chip 23a1 and wide bandgap power chip 23c1 are both located on the side of wide bandgap power chip 23b1 along the first direction toward the first side 110a. In this way, on the one hand, it is beneficial to improve the current sharing between wide bandgap power chip 23a1 and wide bandgap power chip 23b1 to a certain extent, and on the other hand, it can reduce the thermal coupling between wide bandgap power chip 23a1, wide bandgap power chip 23b1, and wide bandgap power chip 23c1.

[0640] Alternatively, the wide bandgap power chip 23a1 and the wide bandgap power chip 23c1 can both be located on the side of the wide bandgap power chip 23b1 facing the second side 110b along the first direction. This can also reduce the thermal coupling between the wide bandgap power chips 23a1, 23b1, and 23c1, and improve heat dissipation performance.

[0641] In some embodiments, in conjunction with Figures 42, 43, 45, and 51, the plurality of wide bandgap power chips 23 in the second wide bandgap chipset 221 are aligned in the second direction. This ensures that the plurality of wide bandgap power chips 23 in the second wide bandgap chipset 221 are at the same distance from the first negative electrode transmission region 1131 in the second direction, thereby maximizing the current sharing of the plurality of wide bandgap power chips 23 in the second wide bandgap chipset 221. Furthermore, the layout is relatively simple and compact, which can reduce the space occupied and improve the space utilization rate.

[0642] In some embodiments, referring to Figures 44 and 52, any two adjacent wide-bandgap power chips 23 in the second wide-bandgap chipset 221 are staggered along the second direction. This helps to reduce the thermal coupling of the multiple similar wide-bandgap power chips 23 in the second wide-bandgap chipset 221, thereby reducing the thermal impact in this area, improving heat dissipation performance, and providing better current distribution.

[0643] For example, as shown in Figure 52, the second wide bandgap chipset 221 has three wide bandgap power chips 23, which are arranged sequentially along the first direction from the first side 110a toward the second side 110b: wide bandgap power chip 23a2, wide bandgap power chip 23b2, and wide bandgap power chip 23c2. Among them, wide bandgap power chips 23a2 and wide bandgap power chips 23c2 are located on the side of wide bandgap power chip 23b2 away from the third side 110c along the second direction. In this way, on the one hand, it is beneficial to improve the current sharing between wide bandgap power chips 23a2 and wide bandgap power chips 23b2 to a certain extent, and on the other hand, it can reduce the thermal coupling between wide bandgap power chips 23a2, wide bandgap power chips 23b2, and wide bandgap power chips 23c2.

[0644] Alternatively, the wide bandgap power chip 23a2 and the wide bandgap power chip 23c2 can both be located on the side of the wide bandgap power chip 23b2 facing the third side 110c along the first direction. This can also reduce the thermal coupling between the wide bandgap power chips 23a2, 23b2, and 23c2, and improve heat dissipation performance.

[0645] In some possible embodiments, the first wide bandgap chipset 211 and the second wide bandgap chipset 221 are also respectively provided with diodes 25 (i.e., first-type diodes). The diodes 25 have the same substrate material type as the wide bandgap power chip 23. For example, the diodes 25 can be SiC SBDs (Schottky diodes 25), etc. The diodes 25 are connected in parallel with the wide bandgap power chip 23. The diodes 25 can be used to protect the SiC MOSFE and prevent excessive reverse current from damaging the SiC MOSFE. In addition, by connecting the SiC SBDs in parallel, the reverse recovery charge of the SiC SBDs is lower when the SiC MOSFE is turned off during the dead time, which can greatly reduce power loss, reduce energy loss, and improve conversion efficiency, thereby improving the performance of the half-bridge power module 100. The diodes 25 in the first wide bandgap chipset 211 can be connected to the AC region 112 through the connecting line 26, and the diodes 25 in the second wide bandgap chipset 221 can be connected to the DC negative region 113 through the connecting line 26.

[0646] In addition to the above-described scheme, referring to Figures 42-45 and 53-56, considering that the silicon-based power chip 24, such as a Si IGBT, lacks reverse conduction capability during operation, in this embodiment, both the first silicon-based chip group 212 and the second silicon-based chip group 222 include at least one diode 25 (i.e., a second type of diode 25a). The diode 25 has the same substrate material type as the silicon-based power chip 24; that is, there can be one or more diodes 25, where "multiple" refers to two or more. Each diode 25 corresponds one-to-one with a silicon-based power chip 24, and the corresponding silicon-based power chip 24 and diode 25 are connected in parallel to form a chip pair. For example, the diode 25 can be a fast recovery diode 25, and the diode 25 can be connected in reverse parallel with the silicon-based power chip 24. In this embodiment, by connecting the diode 25 in reverse parallel with the silicon-based power chip 24, the overall reverse current carrying capacity of the module can be enhanced, which is beneficial to improving the overall efficiency and reliability of the half-bridge power module 100. In the first silicon-based chipset 212, diode 25 can be connected to AC region 112 via connecting line 26, and diode 25 in the second silicon-based chipset 222 can be connected to DC negative region 113 via connecting line 26.

[0647] Optionally, only the first wide bandgap chipset 211 and the second wide bandgap chipset 221 may have diodes 25 with the same substrate material as the wide bandgap power chip 23; or, only the first silicon-based chipset 212 and the second silicon-based chipset 222 may have diodes 25 with the same substrate material as the silicon-based power chip 24; or, the first wide bandgap chipset 211 and the second wide bandgap chipset 221 may have diodes 25 with the same substrate material as the wide bandgap power chip 23, while the first silicon-based chipset 212 and the second silicon-based chipset 222 may have diodes 25 with the same substrate material as the silicon-based power chip 24.

[0648] For ease of description, the following explanation will only take the example of a second type of diode 25a made of the same material as the silicon-based power chip 24, which is provided in the first silicon-based chipset 212 and the second silicon-based chipset 222.

[0649] In some embodiments, there are multiple silicon-based power chips 24 and second-type diodes 25a in the first silicon-based chipset 212 and the second silicon-based chipset 222. Thus, multiple chip pairs are formed in both the first silicon-based chipset 212 and the second silicon-based chipset 222. The multiple chip pairs are arranged along the second direction, which can amplify the current specification, expand the power level, and improve the power load.

[0650] Furthermore, the silicon-based power chip 24 and the second type diode 25a in each chip pair are arranged along a first direction or a second direction.

[0651] As shown in Figure 53, there are two chip pairs, meaning there can be two silicon-based power chips 24 and two types of diodes 25a. In this case, the silicon-based power chips 24 and the second type of diodes 25a can be arranged alternately in the second direction. In this configuration, the silicon-based power chips 24 and the second type of diodes 25a in the first silicon-based chip group 212 are both connected to the AC region 112 via a connecting line 26 along the first direction. Similarly, the silicon-based power chips 24 and the second type of diodes 25a in the second silicon-based chip group 222 are connected to the DC negative terminal region 113 via the connecting line 26 along the first direction. This method separates silicon-based chips of the same type (including the aforementioned silicon-based power chips 24 and second type of diodes 25a) in each conductive region, which helps avoid thermal coupling between similar silicon-based chips, reduces heat dissipation pressure, and minimizes the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 along the first direction, thus improving space utilization.

[0652] Alternatively, as shown in Figures 52 and 56, the silicon-based power chip 24 and the second type diode 25a in each chip pair are arranged along a first direction.

[0653] In some embodiments, the silicon-based power chips 24 and the second type diodes 25a in the multiple chip pairs are arranged in the same or opposite directions.

[0654] For example, as shown in Figure 55, there are two chip pairs. The silicon-based power chip 24 and the second type diode 25a in each chip pair are arranged along the first direction, and the silicon-based power chip 24 in each chip pair is located on the same side of the corresponding second type diode 25a along the first direction. In this way, the current sharing performance of the silicon-based power chip 24 in the two chip pairs is better, and the current sharing performance of the second type diode 25a in the two chip pairs is better. In addition, the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 along the second direction is smaller.

[0655] Alternatively, as shown in Figure 56, there are two chip pairs. In each chip pair, the silicon-based power chip 24 and the second-type diode 25a are arranged along a first direction. In one chip pair, the silicon-based power chip 24 is located on one side of the corresponding second-type diode 25a along the first direction, and in the other chip pair, the silicon-based power chip 24 is located on the other side of the corresponding second-type diode 25a along the first direction. Furthermore, the silicon-based power chip 24 in one chip pair and the second-type diode 25a in the other chip pair are arranged side-by-side along a second direction. This arrangement, with the silicon-based power chips 24 and the second-type diodes 25a in multiple chip pairs facing opposite directions, helps reduce thermal coupling of the same type of silicon-based chips, improves heat dissipation performance, and reduces the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 along the second direction.

[0656] Understandably, when the silicon-based power chip 24 and the second type diode 25a in each chip pair are arranged along the first direction, the space occupied by the first silicon-based chip group 212 and the second silicon-based chip group 222 in the first direction increases and the space occupied in the second direction decreases. Therefore, the size of the area of ​​the DC positive region 111 corresponding to the first silicon-based chip group 212 can be adjusted to match the space occupied by the first silicon-based chip group 212 in the first and second directions. At the same time, the size of the area of ​​the AC region 112 corresponding to the second silicon-based chip group 222 can also be adjusted to match the space occupied by the second silicon-based chip group 222 in the first and second directions.

[0657] In some embodiments, referring to FIG54, both the first silicon-based chipset 212 and the second silicon-based chipset 222 have multiple chip pairs. Multiple silicon-based power chips 24 are arranged adjacent to each other along a second direction, and multiple second-type diodes 25a are arranged adjacent to each other along the second direction. In other words, in this embodiment, chips of the same type are adjacent to each other and connected to corresponding conductive areas via connecting lines 26 along the first direction. This chip arrangement in this embodiment facilitates the setting of the driving connecting lines 26, and the smaller dimensions of the first silicon-based chipset 212 and the second silicon-based chipset 222 along the first direction improve the space utilization of the first silicon-based chipset 212 and the second silicon-based chipset 222 along the first direction.

[0658] In some embodiments, referring to Figures 46-48, the wide-bandgap power chip 23 includes a SiC MOSFET, and the silicon-based power chip 24 includes a Si IGBT. That is, in this embodiment, the copper layers of the SiC half-bridge and the IGBT half-bridge are electrically connected inside the power module. This reduces the commutation inductance between the SiC device and the IGBT device, shortens the commutation time, and improves efficiency.

[0659] As shown in Figure 46, the SiC MOSFET includes a source 231, a gate 232, and a drain 233. The drain 233 is located on the side of the SiC MOSFET facing the conductive metal layer 11 and is connected to the conductive region thereon through a welding or sintering process. The source 231 and the gate 232 are located on the side of the SiC MOSFET away from the conductive metal layer 11 and are used to connect to other conductive regions.

[0660] As shown in Figure 47, the Si IGBT includes an emitter 241, a gate 242, and a collector 243. The collector 243 is located at the bottom of the Si IGBT (the side of the Si IGBT facing the conductive metal layer 11) and is used to connect with the conductive region thereon by means of sintering, welding, etc. The emitter 241 and the gate 242 are located on the side of the Si IGBT away from the conductive metal layer 11 and are used to connect with other conductive regions.

[0661] As shown in Figure 48, diode 25 can be a Si FRD (fast recovery diode 25). Diode 25 includes a cathode 252 and an anode 251. The anode 251 is located at the top of diode 25 (i.e., the side of diode 25 facing away from conductive metal layer 11) and is used for electrical connection with other conductive areas. The cathode 252 is located at the bottom of diode 25 (i.e., the side of diode 25 facing conductive metal layer 11) and is connected to the conductive area thereon by sintering or welding.

[0662] In other words, the half-bridge power module 100 of this embodiment packages a SiC MOSFET and a Si IGBT in parallel. This allows the SiC MOSFET to perform the switching action using drive signals with different timings, while the Si IGBT bears most of the conduction current. This solves the problems of high switching losses and low switching frequency of IGBTs. Furthermore, a larger current can be controlled by a SiC MOSFET with a smaller current carrying capacity, thus solving the problem of high SiC cost. In this way, both the performance and cost of the half-bridge power module 100 can be balanced.

[0663] In some embodiments, referring to Figures 42-45 and Figures 57 and 58, the conductive metal layer 11 may further include two driving layer regions, which correspond to the upper bridge 21 and the lower bridge 22, respectively, and the two driving layer regions are the first driving layer region 114 and the second driving layer region 115.

[0664] The second driving layer region 114 may include: a second SiC gate driving layer 1141, a second IGBT gate driving layer 1142, a second SiC source driving layer 1143, and a second IGBT emitter driving layer 1144. The gate 232 of the SiC MOSFET of the upper bridge 21 is connected to the second SiC gate driving layer 1141 via a connection line 26, the source 231 of the SiC MOSFET of the upper bridge 21 is connected to the second SiC source driving layer 1143 via a connection line 26, the gate 242 of the Si IGBT of the upper bridge 21 is connected to the second IGBT gate driving layer 1142 via a connection line 26, and the emitter 241 of the Si IGBT of the upper bridge 21 is connected to the second IGBT emitter driving layer 1144 via a connection line 26.

[0665] The first driving layer region 115 may include: a first SiC gate driving layer 1151, a first IGBT gate driving layer 1152, a first SiC source driving layer 1153, and a first IGBT emitter driving layer 1154. The gate 232 of the SiC MOSFET of the lower bridge 22 is connected to the first SiC gate driving layer 1151 through the connection line 26. The source 231 of the SiC MOSFET of the lower bridge 22 is connected to the first SiC source driving layer 1153 through the connection line 26. The gate 242 of the Si IGBT of the lower bridge 22 is connected to the first IGBT gate driving layer 1152 through the connection line 26. The emitter 241 of the Si IGBT of the lower bridge 22 is connected to the first IGBT emitter driving layer 1154 through the connection line 26.

[0666] Thus, by setting the first driving layer region 115 and the second driving layer region 114, it is possible to facilitate the connection between each wide bandgap power chip 23, silicon-based power chip 24 and external circuits.

[0667] Optionally, driving terminals 116 are provided on the second SiC gate driving layer 1141, the second IGBT gate driving layer 1142, the second SiC source driving layer 1143, the second IGBT emitter driving layer 1144, the first SiC gate driving layer 1151, the first IGBT gate driving layer 1152, the first SiC source driving layer 1153, and the first IGBT emitter driving layer 1154. Each driving terminal 116 can be led out perpendicular to the substrate 1 to simplify the internal circuit structure of the half-bridge power module 100, reduce space occupation, and facilitate the connection of the half-bridge power module 100 with external circuits.

[0668] Optionally, referring to Figures 42, 43, and 57, the second SiC source driving layer 1143 and the second IGBT emitter driving layer 1144 are connected to form a second common copper layer 1145. In this case, the second SiC source driving layer 1143 and the second IGBT emitter driving layer 1144 can share the same driving terminal 116. This simplifies the internal structure of the half-bridge power module 100 and improves space utilization. Correspondingly, the first SiC source driving layer 1153 and the first IGBT emitter driving layer 1154 are connected to form a first common copper layer 1155. In this case, the first SiC source driving layer 1153 and the first IGBT emitter driving layer 1154 can share the same driving terminal 116. This also simplifies the internal structure of the half-bridge power module 100 and improves space utilization.

[0669] Optionally, referring to Figures 42-45, the second driving layer region 114 can be disposed along the second side 110a, and at least a portion of the structure of the DC positive region 111 is located on the side of the second driving layer region 114 away from the second side 110a along the second direction. For example, the DC positive region 111 can be entirely located on the side of the second driving layer region 114 away from the second side 110a along the second direction; or, the DC positive region 111 can partially surround the second driving layer region 114, in which case a portion of the DC positive region 111 is located on the side of the second driving layer region 114 away from the second side 110a along the second direction, and another portion is disposed along the second side 110a and arranged side-by-side with the second driving layer region 114 along the first direction. In this way, the distance between the wide bandgap power chip 23 and the silicon-based power chip 24 in the DC positive region 111 and the second driving layer region 114 can be shortened as much as possible, thereby shortening the length of the connection lines 26 of each chip in the upper bridge 21, which is beneficial for reducing parasitic inductance.

[0670] Optionally, in conjunction with Figures 42-45, the AC region 112 at least partially surrounds the first driving layer region 115. This can minimize the distance between the wide bandgap power chip 23 and the silicon-based power chip 24 in the AC region 112 and the first driving layer region 115, thereby shortening the length of the connection lines 26 of each chip in the lower bridge 22 and reducing parasitic inductance.

[0671] Optionally, in conjunction with Figures 44 and 45, the second SiC gate driving layer 1141 and the second SiC source driving layer 1143 form a third sub-layer group, and the second IGBT gate driving layer 1142 and the second IGBT emitter driving layer 1144 form a fourth sub-layer group. The third and fourth sub-layer groups can be arranged separately. For example, both the third and fourth sub-layer groups can be arranged along the first side 110a and spaced apart along the second direction. The third sub-layer group is arranged adjacent to the multiple wide bandgap power chips 23 of the first wide bandgap chip group 211, and the fourth sub-layer group is arranged opposite or staggered to the first silicon-based chip group 212 along the first direction.

[0672] Optionally, referring to Figures 44 and 45, the first SiC gate driving layer 1151 and the first SiC source driving layer 1153 form a first sub-layer group, and the first IGBT gate driving layer 1152 and the first IGBT emitter driving layer 1154 form a second sub-layer group. The first and second sub-layer groups can be arranged separately. For example, the first sub-layer group is disposed between the first wide bandgap chip group 211 and the second wide bandgap chip group 221, or the AC region 112 surrounds the first sub-layer group, and the first sub-layer group is arranged adjacent to a plurality of wide bandgap power chips 23 of the second wide bandgap chip group 221. The second sub-layer group can be arranged opposite to or staggered from the second silicon-based chip group 222 along a first direction.

[0673] Of course, this application is not limited to this. The layout of the second driving layer region 114 and the first driving layer region 115 can be reasonably set according to the layout of the upper bridge 21 and the lower bridge 22 in order to minimize the transmission path of each driving signal, reduce parasitic inductance, improve efficiency, and facilitate connection with external circuits.

[0674] In some embodiments, the second SiC source drive layer 1143 is provided with a plurality of drive resistors corresponding one-to-one with and connected to the plurality of wide bandgap power chips 23 in the first wide bandgap chipset 211; the first SiC source drive layer 1153 is provided with a plurality of drive resistors corresponding one-to-one with and connected to the plurality of wide bandgap power chips 23 in the second wide bandgap chipset 221. The drive resistors can connect the gate 232 of the corresponding wide bandgap power chip 23, such as a SiC MOSFET, to the copper layer on which it is located. By setting the drive resistors, the gate current 232 of the SiC MOSFET can be limited, ensuring the switching speed and performance of the SiC MOSFET. In addition, the drive circuit can be protected from damage by overcurrent and overvoltage.

[0675] Optionally, the multiple driving resistors on the second SiC source driving layer 1143 can be connected in series or in parallel as needed, and the multiple driving resistors on the first SiC source driving layer 1153 can be connected in series or in parallel as needed.

[0676] Understandably, since the second SiC source drive layer 1143 is located on the side of the second SiC source drive layer 1143 closer to the DC positive region 111, and the first SiC source drive layer 1153 is located on the side of the first SiC source drive layer 1153 closer to the AC region 112, the driving resistors are brought closer to the corresponding SiC MOSFETs, minimizing the resistance and capacitance of the drive signal transmission, which is beneficial to improving the system's response speed and stability.

[0677] Referring to Figure 61, the full-bridge power module 300 of this embodiment may include the half-bridge power module 100 described in the above embodiment. Specifically, there may be three half-bridge power modules 100, which are connected to the same heat sink to form a three-phase full-bridge power module 300. Each half-bridge power module 100 corresponds to one single phase. For example, the three half-bridge power modules 100 include a first half-bridge power module 100, a second half-bridge power module 100, and a third half-bridge power module 100. The first half-bridge power module 100 corresponds to the U phase, the second half-bridge power module 100 corresponds to the V phase, and the third half-bridge power module 100 corresponds to the W phase. The first half-bridge power module 100, the second half-bridge power module 100, and the third half-bridge power module 100 may be arranged sequentially, or their order may be adjusted as needed.

[0678] In addition, the full-bridge power module 300 may also include a heat sink 200, and the three half-bridge power modules 100 may all be mounted on the same heat sink 200.

[0679] The full-bridge power module 300 according to the embodiments of this application is composed of three half-bridge power modules 100 as described in the above embodiments. Since each half-bridge power module 100 is a plurality of parallel half-bridge circuits formed by wide-bandgap power chips 23 and silicon-based power chips 24, the current specification of the full-bridge power module 300 is greatly amplified, which can better convert DC power into AC power for use by electrical devices. It has stronger electrical performance and is more suitable for use as an automotive-grade power module.

[0680] The electrical equipment in this embodiment can be a new energy vehicle or other types of electrical equipment. The electrical equipment may include a power module, which may include the half-bridge power module 100 in the first aspect embodiment above, and / or the full-bridge power module 300 in the second aspect embodiment above.

[0681] Specifically, the electrical equipment also includes an energy storage device and an electrical device. The energy storage device can be a battery pack, and the electrical device can be a motor, such as a three-phase AC motor. A power module is located between the energy storage device and the electrical device, which can convert the DC power generated by the energy storage device into AC power for the use of the electrical device.

[0682] The electrical equipment may be equipped with only a half-bridge power module 100, or only a full-bridge power module 300, or the half-bridge power module 100 and the full-bridge power module 300 may be combined as needed.

[0683] The electrical equipment in this application embodiment, by setting a power module, can convert the direct current generated by the energy storage device into alternating current to power the electrical equipment, such as the electric motor, thereby providing power for the vehicle's movement. Furthermore, since the power module adopts the half-bridge power module 100 and / or the full-bridge power module 300 in the above embodiment, the current specification is higher, which can better perform AC-DC conversion and make the performance more reliable.

[0684] In various fields such as automobiles and power systems, reducing power losses in power conversion devices such as inverters and frequency converters is crucial, and power semiconductor devices in these devices play a vital role. However, the performance of traditional silicon-based power semiconductor devices is insufficient to meet current demands for power switching devices in terms of blocking voltage, on-state current, operating frequency, high temperature, and high efficiency.

[0685] Silicon-based fully controllable power semiconductor devices, represented by silicon-insulated-gate bipolar transistors (Si IGBTs), possess excellent performance characteristics such as simple control circuits, high voltage resistance, and high current handling capacity, and are widely used in power conversion devices such as inverters and frequency converters. However, when silicon-based fully controllable power semiconductor devices, represented by Si IGBTs, turn off, the collector current decays slowly, i.e., a significant tail current. This tail current is amplified by switching losses, especially when used as a high-frequency switch.

[0686] Wide bandgap semiconductor materials, such as silicon carbide, possess excellent physical properties including a large bandgap, high saturated electron drift rate, and high thermal conductivity. These properties can significantly reduce losses in power conversion devices such as inverters and frequency converters, thereby improving conversion efficiency. However, wide bandgap semiconductor power devices, represented by silicon carbide, are relatively expensive.

[0687] Therefore, wide-bandgap semiconductor power devices and silicon-based fully controllable power semiconductor devices can be connected in parallel to form a half-bridge power module. The wide-bandgap semiconductor power devices control the switching of the half-bridge power module, while the silicon-based fully controllable power semiconductor devices bear the main conduction current. This combines the advantages of the two types of devices to reduce switching losses and costs.

[0688] Currently, a half-bridge power module is mainly composed of multiple different substrates (e.g., ceramic substrates). Different substrates are used to carry different devices. For example, the first substrate carries a wide-bandgap semiconductor power device for the upper bridge, the second substrate carries a silicon-based fully controllable power semiconductor device for the upper bridge, the third substrate carries a wide-bandgap semiconductor power device for the lower bridge, and the fourth substrate carries a silicon-based fully controllable power semiconductor device for the lower bridge. These different substrates need to be interconnected to form the half-bridge power module, which results in numerous manufacturing steps and low space utilization.

[0689] To address this, this application proposes a half-bridge power module. A DC positive region, a DC negative region, and an AC region are formed on a substrate. An upper-bridge chipset is formed on the DC positive region, and a lower-bridge chipset is formed on the AC region, thereby reducing manufacturing processes and improving space utilization. Furthermore, the wide-bandgap chipsets in both the upper and lower-bridge chipsets are arranged along a second direction. Both the first and second wide-bandgap chipsets include multiple wide-bandgap power chips arranged along the second direction, forming a more regular arrangement and further improving space utilization.

[0690] The technical solutions of this application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0691] Figure 62 shows a schematic diagram of a half-bridge power module according to an embodiment of this application. As shown in Figure 62, the half-bridge power module of this embodiment may include:

[0692] A substrate 20; a DC positive region 21, a DC negative region 23, and an AC region 22 located on the substrate 20; and an upper-bridge chip group 31 located on the DC positive region 21 and a lower-bridge chip group 32 located on the AC region 22. The upper-bridge chip group 31 includes a first wide-bandgap chip group 301, and the lower-bridge chip group 32 includes a second wide-bandgap chip group 303. The first wide-bandgap chip group 301 is connected to the AC region 22, and the second wide-bandgap chip group 303 is connected to the DC negative region 23. The first wide-bandgap chip group 301 and the second wide-bandgap chip group 303 are arranged along a second direction, and both the first wide-bandgap chip group 301 and the second wide-bandgap chip group 303 include a plurality of wide-bandgap power chips 11 arranged along the second direction.

[0693] In this embodiment, substrate 20 is used to support the interconnect layer and the chipset. By forming the interconnect layer and the chipset on a single substrate, the problem of excessive manufacturing processes caused by the need for interconnection between multiple substrates is solved, reducing the number of manufacturing processes. Furthermore, forming the chipset and the interconnect layer on a single substrate allows for improved space utilization by rationally positioning the chipset and the interconnect layer on the substrate. In addition, in this embodiment, the wide bandgap chipset in the upper bridge chipset 31 and the wide bandgap chipset in the lower bridge chipset 32 ​​are arranged along a second direction. Both the first wide bandgap chipset 301 and the second wide bandgap chipset 303 include multiple wide bandgap power chips 11 arranged in the second direction, forming a relatively regular arrangement, further improving space utilization.

[0694] For example, substrate 20 may include a ceramic substrate, such as an alumina substrate, a silicon nitride substrate, a zirconia substrate, etc.

[0695] In some embodiments, as shown in Figures 63 and 64, the upper bridge chipset 31 also includes a first silicon-based chipset 302, which controls the upper bridge chipset 31 to be turned on or off via a first wide bandgap chipset 301 and the first silicon-based chipset 302. The lower bridge chipset 32 ​​also includes a second silicon-based chipset 304, which controls the lower bridge chipset 32 ​​to be turned on or off via a second wide bandgap chipset 303 and the second silicon-based chipset 304.

[0696] Power device losses are categorized into switching losses and conduction losses. Switching losses are the losses incurred during the instant the power device switches on, while conduction losses are the losses that occur over a prolonged period after the device completes the switching process. Switching losses further include turn-on losses and turn-off losses. Turn-on losses are the losses incurred during the instant the power device turns on, and turn-off losses are the losses incurred during the instant the power device turns off. Wide-bandgap chipsets handle the switching action and bear the switching losses, while silicon-based chipsets handle the conduction current. Because wide-bandgap power chips have lower switching losses and silicon-based power chips have lower costs, the goal of reducing switching losses and costs can be achieved.

[0697] For example, the first wide bandgap chipset 301 and the first silicon-based chipset 302 are located on the DC positive region 21, and the DC positive region 21 can be used to connect to the positive terminal of the power supply, thereby allowing the first wide bandgap chipset 301 and the first silicon-based chipset 302 to be connected to the positive terminal of the power supply. The second wide bandgap chipset 303 and the second silicon-based chipset 304 are connected to the DC negative region 23, and the DC negative region 23 can be used to connect to the negative terminal of the power supply, thereby allowing the lower bridge chipset 32 ​​to be connected to the negative terminal of the power supply; the first wide bandgap chipset 301 and the first silicon-based chipset 302 are connected to the AC region 22, and the second wide bandgap chipset 303 and the second silicon-based chipset 304 are located on the AC region 22, and the AC region 22 is used to connect to the load, thereby allowing the upper bridge chipset 31 and the lower bridge chipset 32 ​​to be connected to the load.

[0698] For example, the second wide bandgap chipset 303 and the second silicon-based chipset 304 can be connected to the DC negative region 23 by bonding wires, and the first wide bandgap chipset 301 and the first silicon-based chipset 302 can be connected to the AC region 22 by bonding wires, or other connecting wires.

[0699] In practical applications, at least one of the DC positive region 21, DC negative region 23 and AC region 22 is a copper layer. For example, the DC positive region 21 can be a positive DC copper layer, the DC negative region 23 can be a negative DC copper layer, and the AC region 22 can be an AC copper layer.

[0700] Considering that the parallel connection of power devices can share the power, enabling the device to withstand greater power and output greater current, the first wide bandgap chipset 301 and the second wide bandgap chipset 303 include a plurality of wide bandgap power chips 11 arranged in the second direction.

[0701] In some embodiments, the plurality of wide bandgap power chips 11 in the first wide bandgap chipset 301 are connected in parallel. Specifically, the plurality of wide bandgap power chips 11 in the second wide bandgap chipset 303 are all located on the AC region 23 and connected to the DC negative region 23, thereby realizing the parallel connection of the plurality of wide bandgap power chips 11 in the second wide bandgap chipset 303. For example, each wide bandgap power chip 11 in the second wide bandgap chipset 303 can be connected to the DC negative region 23 via a bonding wire.

[0702] Multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 301 are connected in parallel. Specifically, the multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 303 are located on the DC positive region 21 and connected to the AC region 22, thereby realizing the parallel connection of the multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 301. For example, each wide-bandgap power chip 11 in the first wide-bandgap chipset 303 can be connected to the AC region 22 via bonding wires.

[0703] Furthermore, the second wide bandgap chipset 303 is connected in series with the wide bandgap power chips 11 in the first wide bandgap chipset 301. The corresponding two wide bandgap power chips 11 can form a half-bridge circuit. Moreover, since multiple half-bridge circuits are connected in parallel, a half-bridge circuit with a current specification amplification of N times (the number of half-bridge circuits is N) can be formed, which is beneficial to improving the power level of the half-bridge power module.

[0704] In practical applications, wide bandgap power chips can include silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs) or gallium nitride high electron mobility transistors (GaN HEMTs).

[0705] Figure 65(A) shows a schematic diagram of the structure of a wide bandgap power chip 11. The surface electrodes of the wide bandgap power chip 11 include a source 111, a gate 112, and a drain 113 located at the bottom. Correspondingly, the drain 113 of the wide bandgap power chip 11 in the second wide bandgap chip group 303 is attached to the AC region 22, and the source 111 of the wide bandgap power chip 11 in the second wide bandgap chip group 303 is connected to the DC negative region 23. The drain of the wide bandgap power chip 11 in the first wide bandgap chip group 301 is attached to the DC positive region 21, and the source of the wide bandgap power chip 11 in the first wide bandgap chip group 301 is connected to the AC region 22.

[0706] In some embodiments, the first silicon-based chipset 302 includes a plurality of silicon-based power chips 12, thereby enabling the upper bridge chipset 31 to output a larger current. Specifically, the plurality of silicon-based power chips 12 in the first silicon-based chipset 302 are connected in parallel. All of the plurality of silicon-based power chips 12 in the first silicon-based chipset 302 are located on the DC positive region 21, and are connected to the AC region 22, thus realizing the parallel connection of the plurality of silicon-based power chips 12 in the first silicon-based chipset 302. For example, the plurality of silicon-based power chips 12 in the first silicon-based chipset 302 can be connected to the AC region 22 via bonding wires.

[0707] The second silicon-based chipset 304 includes multiple silicon-based power chips 12, enabling the lower-bridge chipset 32 ​​to output a larger current. Specifically, the multiple silicon-based power chips 12 in the second silicon-based chipset 304 are connected in parallel. All of the multiple silicon-based power chips 12 in the second silicon-based chipset 304 are located on the AC region 22, and are connected to the DC negative terminal region 23, thus achieving parallel connection of the multiple silicon-based power chips 12 in the second silicon-based chipset 304. For example, the multiple silicon-based power chips 12 in the second silicon-based chipset 304 can be connected to the DC negative terminal region 23 via bonding wires.

[0708] Furthermore, the silicon-based power chip 12 in each of the first silicon-based chipsets 302 is connected in series with the silicon-based power chip 12 in the second silicon-based chipset 304 to form a half-bridge structure.

[0709] In some embodiments, considering that the dynamic current sharing of the wide-bandgap power chips 11 in the second wide-bandgap chipset 303 is mainly affected by the current path, when the half-bridge power module includes a second DC connection terminal 42 located on the DC negative region 23, the current path length between each wide-bandgap power chip 11 in the second wide-bandgap chipset 303 and the second DC connection terminal 42 is the same, thereby enabling the multiple wide-bandgap power chips 11 in the second wide-bandgap chipset 303 to achieve a current sharing effect. The second DC connection terminal 42 is used to connect to external circuits, such as connecting to the negative terminal of a power supply.

[0710] In other embodiments, the first wide bandgap chipset 301 includes a plurality of wide bandgap power chips 11, and the half-bridge power module includes an AC connection terminal 43. The current path length between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection terminal 43 is the same, so that the wide bandgap power chips 11 in the first wide bandgap chipset 301 achieve a current sharing effect.

[0711] In some other embodiments, the half-bridge power module includes a first DC connection terminal 41 located on the DC positive region 21. The current path length between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the first DC connection terminal 41 is the same, further improving the current sharing effect of the wide bandgap power chips 11 in the first wide bandgap chipset 301.

[0712] It should be noted that the second DC connection terminal 42 and the AC connection terminal 43 constitute a single area. The second DC connection terminal 42 is the connection area for each wide-bandgap power chip 11 in the second wide-bandgap chipset 301, and the AC connection terminal 43 is the connection area for each wide-bandgap power chip 11 in the first wide-bandgap chipset 301. The size and length of the second DC connection terminal 42 and the AC connection terminal 43 will affect the current path length. The current path length between each wide-bandgap power chip 11 in the second wide-bandgap chipset 303 and the second DC connection terminal 42 is the same. This can mean that the shortest current path length between the source of each wide-bandgap power chip 11 in the second wide-bandgap chipset 303 and the second DC connection terminal 42 is the same. This "same" can be approximately the same; for example, the difference between the current path lengths of any two wide-bandgap power chips 11 in the second wide-bandgap chipset 303 and the second DC connection terminal 42 is within a preset difference range. The current path length between each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 and the AC connection terminal 42 is the same. This can mean that the shortest current path length between each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 and the AC connection terminal 43 is the same. For example, the difference between the current path lengths between any two wide-bandgap power chips 11 in the first wide-bandgap chipset 301 and the AC connection terminal 43 is within a preset difference range. The preset difference range can be determined according to the actual situation and is not limited here.

[0713] Similarly, the first DC connection terminal 41 is a region that is the connection area for each wide-bandgap power chip 11 in the first wide-bandgap chipset 301. The current path length between each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 and the first DC connection terminal 41 is the same, which can mean that the shortest current path length between the drain of each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 and the first DC connection terminal 41 is the same. This "same" can be approximately the same; for example, the difference between the current path lengths of any two wide-bandgap power chips 11 in the first wide-bandgap chipset 301 and the first DC connection terminal 41 is within a preset difference range.

[0714] As one implementation, the DC negative pole region 23 is also connected to a second DC connection terminal, which is led out along the first direction to connect to an external load.

[0715] As one implementation, the DC positive region 21 is also connected to a first DC connection terminal, which is led out in a first direction to connect to an external power source.

[0716] As one implementation, the AC zone 22 is also provided with an AC connection terminal, which extends in a first direction to connect to an external power source.

[0717] It is understandable that when multiple wide-bandgap power chips 11 are arranged in one direction, and the current direction after the multiple wide-bandgap power chips 11 converge is perpendicular or nearly perpendicular to the arrangement direction of the multiple wide-bandgap power chips 11, as shown in Figure 66(A), each wide-bandgap power chip 11 has a current path of approximately the same length, that is, it has a current path length of approximately the same, thus achieving good dynamic current sharing performance. When multiple wide-bandgap power chips 11 are arranged in one direction, and the current direction after the multiple wide-bandgap power chips 11 converge is parallel to the arrangement direction of the multiple wide-bandgap power chips 11, as shown in Figure 66(B), each wide-bandgap power chip 11 has a current path of different length, that is, it has a current path length of different length, which will cause dynamic current unevenness problems.

[0718] Therefore, in some examples, the plurality of wide bandgap power chips 11 in the second wide bandgap chipset 303 are arranged along the second direction so that the current path length between the plurality of wide bandgap power chips 11 in the second wide bandgap chipset 303 and the second DC connection terminal 42 is the same.

[0719] In other examples, multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 301 are arranged along the second direction to make the current path of each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 as similar as possible, thereby improving the current sharing effect of the first wide-bandgap power chipset 301.

[0720] In some examples, the second silicon-based chipset 304 may also include multiple diode chips 13, with a one-to-one correspondence between the silicon-based power chip 12 and the diode chip 13. Specifically, each diode chip 13 is connected in parallel with one silicon-based power chip 12 in the second silicon-based chipset 304 to undertake reverse current freewheeling, thereby improving the overall reverse current freewheeling capability of the module.

[0721] In other examples, the first silicon-based chipset 302 may also include multiple diode chips 13, with a one-to-one correspondence between the silicon-based power chip 12 and the diode chip 13. Specifically, each diode chip 13 is connected in parallel with one silicon-based power chip 12 in the first silicon-based chipset 302 to undertake reverse current flow and improve the overall reverse current flow capability of the module.

[0722] Furthermore, the multiple diode chips 13 in the first silicon-based chipset 302 are connected in series with the multiple diode chips in the second silicon-based chipset 304, respectively, to undertake reverse freewheeling current in the upper bridge and the lower bridge.

[0723] In practical applications, the silicon-based power chip 12 may include a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field effect transistor (Si MOSFET).

[0724] The diode chip 13 can be a silicon fast recovery diode (Si RFD) or a silicon carbide Schottky barrier diode (SiC SBD).

[0725] Figure 65(B) shows a schematic diagram of a silicon-based power chip. The surface electrodes of the silicon-based power chip 12 include an emitter 121, a base 122, and a collector 123 located at the bottom. Correspondingly, the collector of the silicon-based power chip 12 in the second silicon-based chip group 304 is attached to the AC region 22, and the emitter of the silicon-based power chip 12 in the second silicon-based chip group 304 is connected to the DC negative region 23. The collector of the silicon-based power chip 12 in the first silicon-based chip group 302 is attached to the DC positive region 21, and the emitter of the silicon-based power chip 12 in the first silicon-based chip group 302 is connected to the AC region 22.

[0726] Figure 65(C) shows a schematic diagram of a diode chip structure. The diode chip 13 includes an anode 131 at the top and a cathode 132 at the bottom. Correspondingly, the cathode of the diode chip 13 in the second silicon-based chip group 304 is bonded to the AC region 22, and the anode of the diode chip 13 in the second silicon-based chip group 304 is bonded to the DC negative region 23. The cathode of the diode chip 13 in the first silicon-based chip group 302 is bonded to the DC positive region 21, and the anode of the diode chip 13 in the first silicon-based chip group 302 is bonded to the AC region 22.

[0727] To better understand the impact of the DC connection location on the commutation circuit of the wide bandgap power chip, the following explanation uses the equivalent circuit of the half-bridge power module considering parasitic inductance, as shown in Figure 67. The wide bandgap power chip 11 turns on first, at which point the voltage drops, and the wide bandgap power chip 11 carries the entire current. Then, the silicon-based power chip 12 turns on, and the wide bandgap power chip 11 and the silicon-based power chip 12 commutate, ultimately each carrying a portion of the current. During the turn-off process, the wide bandgap power chip 11 turns off first. At this time, the silicon-based power chip 12 and the wide bandgap power chip 11 commutate, and after the wide bandgap power chip 11 carries the entire current, it turns off, at which point the voltage rises, and a turn-off voltage spike appears.

[0728] Because the wide-bandgap power chip 11 has a faster switching speed than the silicon-based power chip 12, the voltage spike generated by the wide-bandgap power chip 11 under the same inductance is much higher than that generated by the silicon-based power chip 12. Therefore, the turn-off spike caused by parasitic inductance in the switching commutation circuit of the wide-bandgap power chip 11 is more severe. Reducing the commutation circuit length of the wide-bandgap power chip 11 is the main problem.

[0729] Therefore, in some examples, on the DC negative region 23, the second DC connection terminal 42 is positioned close to the second wide bandgap chipset 303, that is, on the side of the second wide bandgap chipset 303 away from the second silicon-based chipset 304, so that the second DC connection terminal 42 is close to the second wide bandgap chipset 303, reducing the commutation loop length of the second wide bandgap chipset 303, reducing the parasitic inductance in the commutation loop, and thus reducing the voltage turn-off spike generated by the wide bandgap power chip 11.

[0730] In other examples, the half-bridge power module includes a first DC connection terminal 41 located on the DC positive region 21 and on the side of the first wide bandgap chipset 301 away from the first silicon-based chipset 302, thereby reducing the commutation loop length of the first wide bandgap chipset 301, reducing the parasitic inductance in the commutation loop, and thus reducing the voltage turn-off spike generated by the wide bandgap power chip 11.

[0731] In the above examples, the arrangement of the plurality of wide-bandgap power chips 11 in the first wide-bandgap chipset 301 and the plurality of wide-bandgap power chips 11 in the second wide-bandgap chipset 303 includes at least one of the following:

[0732] Each wide bandgap power chip 11 is aligned in the second direction; adjacent wide bandgap power chips 11 are staggered in the first direction.

[0733] Each wide-bandgap power chip is staggered in the first direction;

[0734] The first direction and the second direction are two mutually perpendicular directions on a plane.

[0735] As shown in Figure 68(A), each wide bandgap power chip 11 is arranged sequentially and neatly along the second direction, with bonding wires connected to the corresponding interconnect layer along the first direction. For example, when multiple wide bandgap power chips 11 in the first wide bandgap chip group 301 are arranged sequentially and neatly along the second direction, the bonding wires of each wide bandgap power chip 11 are connected to the AC region 22 along the first direction; similarly, when multiple wide bandgap power chips 11 in the second wide bandgap chip group 303 are arranged sequentially and neatly along the second direction, the bonding wires of each wide bandgap power chip 11 are connected to the AC region 22 along the first direction. This arrangement is more compact and helps to improve space utilization.

[0736] As shown in Figure 68(B), each wide bandgap power chip 11 is arranged sequentially in the second direction, and adjacent wide bandgap power chips 11 are staggered in the first direction. Bonding wires are connected to the corresponding interconnecting layer along the first direction. This arrangement is a heat dissipation optimized arrangement, which can further reduce thermal coupling and improve heat dissipation performance.

[0737] As shown in Figure 68(C), each wide bandgap power chip 11 is arranged sequentially in the second direction, and each wide bandgap power chip 11 is staggered in the first direction, with bonding wires connected to the corresponding interconnect layer along the first direction. This arrangement is optimized for current sharing and heat dissipation. It can adjust the source current path of different wide bandgap power chips 11, improve current sharing performance, and at the same time reduce thermal coupling and improve heat dissipation performance.

[0738] In practical applications, different wide-bandgap power chip arrangement methods can be flexibly selected according to requirements to meet different performance needs.

[0739] For example, as shown in Figure 69, when multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 301 are arranged in the second direction, each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 can be staggered in the first direction to improve the current sharing performance of the first wide-bandgap chipset 301 and to have better heat dissipation performance. When multiple wide-bandgap power chips 11 in the second wide-bandgap chipset 303 are arranged in the second direction, adjacent wide-bandgap power chips 11 in the second wide-bandgap chipset 303 can be staggered in the first direction to give the second wide-bandgap chipset 303 better heat dissipation performance.

[0740] In some embodiments, as shown in FIG64 and FIG70, the arrangement of the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the first silicon-based chipset 302 and the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the second silicon-based chipset 304 may include at least one of the following;

[0741] Multiple silicon-based power chips 12 and multiple diode chips 13 are arranged in a cross pattern in the first direction;

[0742] The first chip assembly and the second chip assembly are arranged in a first direction. The first chip assembly includes a plurality of silicon-based power chips 12 arranged in the first direction, and the second chip assembly includes a plurality of diode chips arranged in the first direction.

[0743] Multiple third chip assemblies are arranged in the first direction, and the third chip assemblies include silicon-based power chips 12 and diode chips 13 arranged in the second direction;

[0744] Multiple fourth chip combinations and multiple fifth chip combinations are arranged in a cross pattern in a first direction. The fourth chip combinations and fifth chip combinations include silicon-based power chips 12 and diode chips 13 arranged in a second direction. In the fourth chip combinations and fifth chip combinations, the silicon-based power chips 12 and diode chips 13 are arranged in opposite directions.

[0745] The first direction and the second direction are two mutually perpendicular directions on a plane.

[0746] As shown in Figure 70(A), in the second chip assembly, multiple silicon-based power chips 12 and multiple diode chips 13 are arranged in a crisscross pattern in the first direction, with bonding wires connected to the corresponding interconnect layers along the second direction. For example, in the first silicon-based chip assembly 302, the bonding wires of the silicon-based power chips 12 and diode chips 13 are connected to the AC region 22 along the second direction; similarly, in the second silicon-based chip assembly 304, the bonding wires of the silicon-based power chips 12 and diode chips 13 are connected to the DC negative electrode region 23 along the second direction. This arrangement provides high heat dissipation performance and a smaller dimension along the second direction.

[0747] As shown in Figure 71(B), the first chip assembly and the second chip assembly are arranged sequentially in the first direction. The first chip assembly includes a plurality of silicon-based power chips 12 arranged sequentially in the first direction, and the second chip assembly includes a plurality of diode chips 13 arranged sequentially in the first direction. In this arrangement, chips of the same type are adjacent to each other, and the bonding wires are connected to the corresponding connection layers along the second direction, which facilitates the connection of the bonding wires and results in a smaller size along the second direction.

[0748] As shown in Figure 71(C), multiple third chip combinations are arranged sequentially in the first direction, and the second chip combination includes silicon-based power chips 12 and diode chips 13 arranged sequentially in the second direction. In this arrangement, a silicon-based power chip 12 and a diode chip 13 form a pair, and multiple pairs of chips are arranged along the first direction, so that chips of the same type are adjacent along the first direction. The bonding wires are connected to the corresponding connection layers along the second direction. The size along the first direction is small, and it is convenient to drive the bonding wire connection.

[0749] As shown in Figure 71(D), multiple fourth chip combinations and multiple fifth chip combinations are arranged alternately in the first direction. The combination of silicon-based power chips 12 and diode chips 13 in the fourth chip combination differs from that in the fifth chip combination. Multiple pairs of chips are arranged along the wide bandgap power chip 11, ensuring that chips of the same type are not adjacent to each other. Bonding lines are connected to the corresponding interconnect layers along the second direction. This arrangement results in a smaller dimension along the first direction and better heat dissipation.

[0750] In practical applications, different arrangements of silicon-based power chips 12 and diode chips 13 can be flexibly selected according to requirements. For example, due to the slower switching speed of silicon-based power chips 12, the impact of parasitic inductance is relatively small. However, due to the lower thermal conductivity and larger size of silicon-based power chips 12, the layout can be mainly considered from the perspectives of heat dissipation and size.

[0751] As one implementation, as shown in Figures 63 and 64, the AC region 22 may include two parts, a first part and a second part connected to each other. The first part extends in a first direction and the second part extends in a second direction. At this time, the first wide bandgap chip group 301 and the first silicon-based chip group 302 are located on both sides of the second part, thereby reducing the length of the bonding line between the first wide bandgap chip group 301 and the AC region 22.

[0752] In some embodiments, as shown in FIG71, the DC positive region 21 includes a first connection layer 211 and a second connection layer 212 that are electrically connected to each other. A first wide bandgap chipset 301 is located on the first connection layer 211, and a first silicon-based chipset 302 is located on the second connection layer 312 to suit different scenario requirements.

[0753] In some examples, a first DC connection terminal 41 is formed on both the first connection layer 211 and the second connection layer 212, thereby enabling the first wide bandgap chip group 301 on the first connection layer 211 and the first silicon-based chip group 302 on the second connection layer 212 to receive external voltages, such as positive voltage. A second DC connection terminal 42 is formed on the DC negative terminal region 23, thereby enabling the second wide bandgap chip group 303 and the second silicon-based chip group 304 on the AC region 22 to receive external voltages, such as negative voltage.

[0754] As one implementation, as shown in FIG71, a recess is formed between the first connection layer 211 and the second connection layer 212 to accommodate a portion of the protruding structure of the AC region 22. At least a portion of the protruding structure is spaced apart from the DC positive region 21 for electrically connecting multiple wide bandgap power chips 11 in the first wide bandgap chipset 301, thereby reducing the length of the bonding line between the second wide bandgap chipset 303 and the second silicon-based chipset 304 and the DC negative region 23.

[0755] For example, the DC negative region 23 can be located between the first connection layer 211 and the second connection layer 212, that is, the first connection layer 211 and the second connection layer 212 are located on both sides of the DC negative region 23, and the DC negative region 23 extends in the second direction. At this time, the second wide bandgap chip group 303 and the second silicon-based chip group 304 are located on both sides of the DC negative region 23, thereby reducing the length of the bonding line between the second wide bandgap chip group 303 and the second silicon-based chip group 304 and the DC negative region 23.

[0756] As shown in Figure 71, a first portion of the AC region 22 extends between the first interconnect layer 211 and the DC negative region 23, thereby reducing the length of the bonding wire between the first wide bandgap chipset 301 and the AC region 22. A second portion of the AC region 22 extends between the DC negative region 23 and the second interconnect layer 212 to reduce the length of the bonding wire between the first silicon-based chipset 302 and the AC region 22.

[0757] In some examples, as shown in Figure 71, the first wide bandgap power chip 301 and the second wide bandgap chip group 302 both include multiple wide bandgap power chips 11, each wide bandgap power chip 11 is arranged along the second direction to form a more regular arrangement and improve space utilization.

[0758] As one implementation, the arrangement of the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the first silicon-based chipset 302, and the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the second silicon-based chipset 304, can each include at least one of the following:

[0759] Multiple silicon-based power chips 12 and multiple diode chips 13 are arranged in a crisscross pattern in a second direction; a first chip assembly and a second chip assembly are arranged in a second direction, the first chip assembly including multiple silicon-based power chips 12 arranged in a second direction, and the second chip assembly including multiple diode chips 13 arranged in a second direction; multiple third chip assemblies are arranged in a second direction, the third chip assemblies including silicon-based power chips 12 and diode chips 13 arranged in a first direction; multiple fourth chip assemblies and multiple fifth chip assemblies are arranged in a crisscross pattern in a second direction, the fourth chip assemblies and the fifth chip assemblies including silicon-based power chips 12 and diode chips 13 arranged in a first direction, and in the fourth chip assemblies and the fifth chip assemblies, the silicon-based power chips 12 and diode chips 13 are arranged in opposite directions; wherein, the first direction and the second direction are two mutually perpendicular directions on a plane.

[0760] In some embodiments, as shown in FIG. 64 and FIG. 72(B), the half-bridge power module includes an upper bridge driving layer 24 located on the substrate 20, the upper bridge driving layer 24 including a first gate driving layer 241 and a first source driving layer 243. For example, the first gate driving layer 241 and the first source driving layer 243 may be copper layers.

[0761] The gate of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 is connected to the first gate driving layer 241, and the source of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 is connected to the first source driving layer 243. This allows control of the voltage difference between the gate and source of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301, thereby controlling whether the wide-bandgap power chip 11 is in an on or off state. For example, the gate of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 is connected to the first gate driving layer 241 via a bonding wire, and the source of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 is connected to the first source driving layer 243 via a bonding wire.

[0762] In some embodiments, the upper bridge driving layer 24 further includes a second gate driving layer 242 and a first emitter driving layer 244. For example, the second gate driving layer 242 and the first emitter driving layer 244 may be copper layers.

[0763] The base of the silicon-based power chip 12 in the first silicon-based chipset 302 is connected to the second gate driving layer 242, and the emitter of the silicon-based power chip 12 in the first silicon-based chipset 302 is connected to the first emitter driving layer 244. This allows control of the voltage difference between the base and emitter of the silicon-based power chip 12 in the first silicon-based chipset 302, thereby controlling whether the silicon-based power chip 12 in the first silicon-based chipset 302 is in an on or off state. For example, the base of the silicon-based power chip 12 in the first silicon-based chipset 302 is connected to the second gate driving layer 242 via a bonding wire, and the emitter of the silicon-based power chip 12 in the first silicon-based chipset 302 is connected to the first emitter driving layer 244 via a bonding wire. For example, when multiple wide bandgap power chips 11 in the first wide bandgap chipset 301 are arranged in the second direction, and each wide bandgap power chip 11 in the first wide bandgap chipset 301 is staggered in the first direction, the first gate driving layer 241 and the first source driving layer 243 can be disposed on the side of the first wide bandgap chipset 301 near the first DC connection terminal 41, thereby shortening the bonding line between the first wide bandgap chipset 301 and the driving layer, as well as shortening the bonding line between the first wide bandgap chipset 301 and the AC region 22.

[0764] As shown in Figures 64 and 72(A), the first source driving layer 243 and the first emitter driving layer 244 can be the same driving layer, which shortens the commutation loop between the wide bandgap power chip 11 and the silicon-based power chip 12 in the hybrid module, reduces the parasitic inductance between the wide bandgap power chip 11 and the silicon-based power chip 12, and reduces the commutation time.

[0765] In some examples, as shown in Figures 64 and 72, a first gate driving terminal 441 is formed in the first gate driving layer 241, a second gate driving layer 242 terminal is formed in the second gate driving layer 242, a first source driving terminal 443 is formed in the first source driving layer 243, and a first emitter driving terminal 444 is formed in the first emitter driving layer 244. External circuitry is connected via the first gate driving terminal 441 and the first source driving terminal 443, enabling the gate and source of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 to receive external voltage, thereby controlling the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 to be in an on or off state. Similarly, external circuitry is connected via the second gate driving terminal 442 and the first emitter driving terminal 444, enabling the base and emitter of the silicon-based power chip 12 in the first silicon-based chipset 302 to receive external voltage, thereby controlling the silicon-based power chip 12 in the first silicon-based chipset 302 to be in an on or off state.

[0766] For example, when the first source driving layer 243 and the first emitter driving layer 244 are the same driving layer, the first source driving terminal 443 and the first emitter driving terminal 444 are the same driving terminal.

[0767] In one implementation, at least one of the first gate driving terminal 441, the second gate driving terminal 442, the first source driving terminal 443, and the first emitter driving terminal 444 is led out perpendicular to the substrate 20.

[0768] In other embodiments, as shown in Figures 64 and 72, the half-bridge power module includes a lower bridge driving layer 25, which includes a third gate driving layer 251 and a second source driving layer 253. For example, the third gate driving layer 251 and the second source driving layer 253 are copper layers.

[0769] The gate of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 is connected to the third gate driving layer 251, and the source of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 is connected to the second source driving layer 253. This allows control of the voltage difference between the gate and source of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303, thereby controlling whether the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 is in an on or off state. For example, the gate of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 is connected to the third gate driving layer 251 via a bonding wire, and the source of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 is connected to the second source driving layer 253 via a bonding wire.

[0770] In other embodiments, the lower bridge driving layer 25 further includes a fourth gate driving layer 252 and a second emitter driving layer 254. For example, the fourth gate driving layer 252 and the second emitter driving layer 254 are copper layers. The base of the silicon-based power chip 12 in the second silicon-based chipset 304 is connected to the fourth gate driving layer 252, and the emitter of the silicon-based power chip 12 in the second silicon-based chipset 304 is connected to the second emitter driving layer 254, so that the voltage difference between the base and emitter of the silicon-based power chip 12 in the second silicon-based chipset 304 can be controlled, thereby controlling the silicon-based power chip 12 in the second silicon-based chipset 304 to be in an on or off state. For example, the base of the silicon-based power chip 12 in the second silicon-based chipset 304 is connected to the fourth gate driving layer 252 via a bonding wire, and the emitter of the silicon-based power chip 12 in the second silicon-based chipset 304 is connected to the second emitter driving layer 254 via a bonding wire.

[0771] For example, when multiple wide bandgap power chips 11 in the second wide bandgap chipset 303 are arranged in the second direction, and adjacent wide bandgap power chips 11 in the first wide bandgap chipset 301 are staggered in the first direction, the third gate driving layer 251 and the second source driving layer 253 can be disposed on one side of the second wide bandgap chipset 303 from the second DC connection terminal 42, thereby shortening the bonding line between the second wide bandgap chipset 303 and the driving layer, as well as shortening the bonding line between the second wide bandgap chipset 303 and the DC negative electrode region 23.

[0772] As shown in Figures 64 and 72(A), the second source driving layer 253 and the second emitter driving layer 254 can be the same driving layer, which further shortens the commutation loop between the wide bandgap power chip 11 and the silicon-based power chip 12 in the hybrid module, reduces the parasitic inductance between the wide bandgap power chip 11 and the silicon-based power chip 12, and reduces the commutation time.

[0773] In some examples, a third gate driving terminal 451 is formed in the third gate driving layer 251, a fourth gate driving terminal 452 is formed in the fourth gate driving layer 252, a second source driving terminal 453 is formed in the second source driving layer 253, and a second emitter driving terminal 454 is formed in the second emitter driving layer 254. External circuitry is connected via the third gate driving terminal 451 and the second source driving terminal 453, enabling the gate and source of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 to receive external voltage, thereby controlling the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 to be in an on or off state. Similarly, external circuitry is connected via the fourth gate driving terminal 452 and the second emitter driving terminal 454, enabling the base and emitter of the silicon-based power chip 12 in the second silicon-based chipset 304 to receive external voltage, thereby controlling the silicon-based power chip 12 in the second silicon-based chipset 304 to be in an on or off state.

[0774] For example, when the second source driving layer 253 and the second emitter driving layer 254 are the same driving layer, the second source driving terminal 453 and the second emitter driving terminal 454 are the same driving terminal.

[0775] In one implementation, at least one of the third gate driving terminal 451, the fourth gate driving terminal 452, the second source driving terminal 453, and the second emitter driving terminal 454 is led out perpendicular to the substrate 20.

[0776] In some embodiments, as shown in FIG64, at least a portion of the structure of the AC region 22 is spaced and embedded in the DC positive region 21 to connect the wide bandgap power chip 11 in the first wide bandgap chipset 301, thereby shortening the connection line between the wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC region 22. Spaced embedding means that at least a portion of the structure of the AC region 22 embedded in the DC positive region 21 is non-contact and spaced from the DC positive region 21, avoiding short circuits. As one implementation, as shown in FIG64, the upper bridge driving layer 24 is located on the substrate 20 and between at least a portion of the structure of the AC region 22 embedded in the DC positive region 21 and a portion of the structure of the DC positive region 21, for example, between the first wide bandgap chipset 301 and the first silicon-based chipset 302, thereby reducing the length of the bonding lines between the first wide bandgap chipset 301 and the first silicon-based chipset 302 and the upper bridge driving layer 24.

[0777] The lower bridge driving layer 25 is located on the substrate 20, between the second wide bandgap chip group 303 and the second silicon-based chip group 304, thereby reducing the length of the bonding line between the second wide bandgap chip group 303, the second silicon-based chip group 304 and the lower bridge driving layer 25.

[0778] As one implementation, at least a portion of the AC region 22 embedded in the DC positive region 21 includes an AC connection terminal 43, where the current path length between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection terminal 43 is the same, thereby shortening the current path length between the wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection terminal 43, while improving the current sharing effect of the wide bandgap power chips 11 in the first wide bandgap chipset 301.

[0779] In some examples, as shown in Figure 73, the half-bridge power module includes two interconnected first source drive layers 243, with a plurality of drive resistors 5 formed in at least one first source drive layer 243. The first end of each drive resistor 5 is interconnected and connected to a first gate drive layer 241, and the second end of each drive resistor 5 is connected to the gate of a first chip in a first chipset. The drive resistors 5 can control the switching speed of the first wide bandgap chipset 301, thereby improving the dynamic current sharing performance of the upper bridge. The number of drive resistors 5 can be the same as or different from the number of wide bandgap power chips 11 in the first wide bandgap chipset 301. For example, the two first source drive layers 243 can be connected by bonding wires.

[0780] In other examples, the half-bridge power module includes two interconnected second source drive layers 253, with at least one second source drive layer 253 having a plurality of drive resistors formed thereon. The first end of each drive resistor is interconnected and connected to a third gate drive layer 251; the second end of each drive resistor is connected to the gate of a wide-bandgap power chip 11 in the second wide-bandgap chipset 301. The drive resistors can control the switching speed of the second wide-bandgap chipset 303, thereby improving the dynamic current sharing effect of the lower bridge. The number of drive resistors can be the same as or different from the number of wide-bandgap power chips 11 in the second wide-bandgap chipset 303. For example, the two second source drive layers 253 can be connected by bonding wires.

[0781] The above describes the half-bridge power module provided in this application. This application also provides a multiphase full-bridge hybrid module, including at least two of the above-described half-bridge power modules.

[0782] As shown in Figure 74, three half-bridge power modules are connected together to form a three-phase full-bridge hybrid module. For example, the three half-bridge power modules can be connected on the same heat sink 6.

[0783] Figures 75-77 show schematic diagrams of a hybrid power module according to an embodiment of this application. Referring to Figures 75-77, the hybrid power module of this embodiment may include: a substrate 20; a DC positive region 21 and an AC region 22 located on the substrate 20, wherein the AC region 22 includes a first AC region 221 and a second AC region 222 separated on both sides of the DC positive region 21; an upper bridge chipset 31 disposed on the DC positive region 21; a lower bridge chipset 32, wherein a portion of the chips in the lower bridge chipset 32 ​​are disposed in the first AC region 221, and another portion of the chips are disposed in the second AC region 222; the chips in the upper bridge chipset 31 are electrically connected to the AC region 22.

[0784] In this embodiment, substrate 20 is used to support the interconnect layer and the chipset. By forming the interconnect layer and chipset on a single substrate, the problem of excessive manufacturing processes caused by the need for interconnection between multiple substrates is solved, reducing the number of manufacturing processes. Furthermore, forming the chipset and interconnect layer on a single substrate allows for improved space utilization through the rational placement of the chipset and interconnect layer on the substrate. It also includes an upper-bridge chipset and a lower-bridge chipset, which can address switching losses and cost issues. In addition, the lower-bridge chipset includes multiple chips, enabling better expansion of power levels.

[0785] For example, substrate 20 may include a ceramic substrate, such as an alumina substrate, a silicon nitride substrate, a zirconia substrate, etc.

[0786] It should be noted that the upper bridge chipset 31, the lower bridge chipset 32, and the connection layer in the hybrid power module constitute a half-bridge structure. The half-bridge structure is connected to the power supply and the load, and can convert DC power into AC power for the load.

[0787] In some embodiments, the DC positive region 21 is disposed between the first AC region 221 and the second AC region 222. The first AC region 221 and the second AC region 222 are electrically connected by leads or terminals to facilitate the connection between the chipset and the AC region, thereby shortening the length of the connection line, etc.

[0788] In some embodiments, the lower bridge chipset 32 ​​includes a second wide bandgap chipset 312, which can bear the switching losses, thereby achieving the purpose of reducing switching losses.

[0789] In some examples, the downbridge chipset 32 ​​also includes a second silicon-based chipset 322 disposed on the second AC area 222. The downbridge chipset 32 ​​is controlled to be turned on or off by the second silicon-based chipset 322 and the second wide bandgap chipset 312.

[0790] Power device losses are categorized into switching losses and conduction losses. Switching losses are the losses incurred during the instant the power device switches on, while conduction losses are the losses that occur over a prolonged period after the device completes the switching process. Switching losses further include turn-on losses and turn-off losses. Turn-on losses are the losses incurred during the instant the power device turns on, and turn-off losses are the losses incurred during the instant the power device turns off. Wide-bandgap chipsets handle the switching action and bear the switching losses, while silicon-based chipsets handle the conduction current. Because wide-bandgap power chips have lower switching losses and silicon-based power chips have lower costs, the goal of reducing switching losses and costs can be achieved.

[0791] In other examples, the upper bridge chipset 31 includes a first wide bandgap chipset 311, which can absorb switching losses, thereby reducing switching losses. Furthermore, the first wide bandgap chipset 311 and the second wide bandgap chipset 312 are arranged along a first direction to improve space utilization. In addition, both the first wide bandgap chipset 311 and the second wide bandgap chipset 312 include multiple wide bandgap power chips arranged along a second direction, enabling the upper bridge chipset 31 and the lower bridge chipset 32 ​​to handle greater power and output greater current. For example, the first and second directions are two perpendicular directions on a plane.

[0792] As one implementation, the wide bandgap power chips 11 in the second wide bandgap chipset 312 and the first wide bandgap chipset 311 are connected in series one-to-one. The two corresponding wide bandgap power chips 11 can form a half-bridge circuit. Furthermore, since multiple half-bridge circuits are connected in parallel, a half-bridge circuit with a current specification amplified by N times (the number of half-bridge circuits is N) can be formed, which is beneficial to improving the power level of the half-bridge power module.

[0793] In some other examples, the upper bridge chipset 31 also includes a first silicon-based chipset 321, which, along with the first wide bandgap chipset 311, controls the upper bridge chipset 31 to be turned on or off. The first silicon-based chipset 321 can handle the conduction current and is low-cost, thus reducing costs. The first wide bandgap chipset 311 handles switching losses, thereby reducing switching losses and costs.

[0794] Furthermore, the chips in the first silicon-based chipset 321 are connected in series with the chips in the second silicon-based chipset 322 to form a half-bridge structure.

[0795] In some embodiments, the first AC region 221 includ...

Claims

1. A half-bridge power module, characterized in that, include: The substrate is provided with a conductive metal layer, the conductive metal layer including a DC positive electrode region and an AC region; The circuit unit includes an upper bridge and a lower bridge. The upper bridge is located in the DC positive region, and the lower bridge is located in the AC region. The upper bridge includes a first wide bandgap chipset, and the lower bridge includes a second wide bandgap chipset.

2. The half-bridge power module according to claim 1, characterized in that, Both the first wide bandgap chipset and the second wide bandgap chipset include multiple wide bandgap power chips.

3. The half-bridge power module according to claim 2, characterized in that, The upper bridge further includes a first silicon-based chipset, and the lower bridge further includes a second silicon-based chipset. At least one of the first silicon-based chipset and the second silicon-based chipset includes at least one of the silicon-based power chips.

4. The half-bridge power module according to any one of claims 1 to 3, characterized in that, The first wide bandgap chipset and the second wide bandgap chipset are arranged along a first direction, and both the first wide bandgap chipset and the second wide bandgap chipset include a plurality of wide bandgap power chips arranged along a second direction.

5. The half-bridge power module according to any one of claims 1 to 4, characterized in that, The multiple wide-bandgap power chips in the second wide-bandgap chipset correspond one-to-one with and are electrically connected to the multiple wide-bandgap power chips in the first wide-bandgap chipset to form a half-bridge circuit, and the multiple wide-bandgap power chips in the first wide-bandgap chipset are connected in parallel with each other.

6. The half-bridge power module according to any one of claims 1 to 5, characterized in that, At least a portion of the structure of the DC positive region and the AC region extends along the second direction, the first wide bandgap chip group is disposed in the portion of the DC positive region extending along the second direction, and the second wide bandgap chip group is disposed in the portion of the AC region extending along the second direction.

7. The half-bridge power module according to any one of claims 1 to 6, characterized in that, The conductive metal layer further includes a DC negative electrode region, at least a portion of which extends along the second direction.

8. The half-bridge power module according to claim 7, characterized in that, The DC positive region, the AC region, and the DC negative region are arranged sequentially along the first direction.

9. The half-bridge power module according to any one of claims 1 to 8, characterized in that, The multiple wide-bandgap power chips in the first wide-bandgap chipset are all connected to the AC area via a first connection line.

10. The half-bridge power module according to any one of claims 1 to 9, characterized in that, The conductive metal layer includes a DC negative electrode region, and multiple wide bandgap power chips in the second wide bandgap chipset are connected to the DC negative electrode region via a second connection line.

11. The half-bridge power module according to any one of claims 1 to 10, characterized in that, A plurality of wide-bandgap power chips in at least one of the first wide-bandgap chipset and the second wide-bandgap chipset are arranged in parallel in the first direction.

12. The half-bridge power module according to any one of claims 1 to 11, characterized in that, The conductive metal layer includes a DC negative electrode region, a DC positive electrode region is provided with a DC positive terminal, a DC negative electrode region is provided with a DC negative terminal, and an AC region is provided with an AC terminal.

13. The half-bridge power module according to claim 12, characterized in that, The DC positive terminal and the DC negative terminal are located on the same side of the DC positive region and the DC negative region along the second direction, respectively, and the AC terminal is located on the other side of the AC region along the second direction.

14. The half-bridge power module according to any one of claims 1 to 10, characterized in that, In the second wide bandgap chipset, any two adjacent wide bandgap power chips are staggered along the first direction.

15. The half-bridge power module according to claim 14, characterized in that, In the second wide bandgap chipset, multiple wide bandgap power chips are arranged opposite to the DC negative electrode region along the first direction.

16. The half-bridge power module according to claim 14, characterized in that, Along the second direction and away from the DC negative terminal, the distance between the plurality of wide bandgap power chips in the second wide bandgap chipset and the DC negative terminal region decreases sequentially.

17. The half-bridge power module according to claim 12, characterized in that, In the second direction of the DC positive terminal region, the first wide bandgap chip group is disposed between the first silicon-based chip group and the DC positive terminal.

18. The half-bridge power module according to claim 17, characterized in that, In the second direction of the AC area, the second wide bandgap chipset is disposed between the second silicon-based chipset and the AC terminal.

19. The half-bridge power module according to claim 4, characterized in that, Both the first silicon-based chipset and the second silicon-based chipset include at least one diode, which forms a chip pair with other silicon-based power chips within the chipset.

20. The half-bridge power module according to claim 19, characterized in that, The diode has the same substrate material as the silicon-based power chip.

21. The half-bridge power module according to claim 19, characterized in that, Both the first silicon-based chipset and the second silicon-based chipset have multiple chip pairs, and the multiple chip pairs are arranged along the second direction.

22. The half-bridge power module according to claim 19, characterized in that, The silicon-based power chip and diode in each chip pair are arranged along the first direction or the second direction.

23. The half-bridge power module according to claim 19, characterized in that, The silicon-based power chips and diodes in the multiple chip pairs are arranged in the same or opposite directions.

24. The half-bridge power module according to claim 22, characterized in that, Both the first silicon-based chipset and the second silicon-based chipset have multiple chip pairs, wherein the multiple silicon-based power chips are arranged adjacent to each other along the second direction, and the multiple diodes are arranged adjacent to each other along the second direction. Furthermore, the plurality of silicon-based power chips and the diodes are arranged along the second direction.

25. The half-bridge power module according to claim 4, characterized in that, The conductive metal layer further includes: The first driving layer group includes: a first SiC gate driving layer, a first IGBT gate driving layer, a first SiC source driving layer, and a first IGBT emitter driving layer. The gate of the SiC MOSFET of the upper bridge is connected to the first SiC gate driving layer, the source of the SiC MOSFET of the upper bridge is connected to the first SiC source driving layer, the gate of the Si IGBT of the upper bridge is connected to the first IGBT gate driving layer, and the emitter of the Si IGBT of the upper bridge is connected to the first IGBT emitter driving layer.

26. The half-bridge power module according to claim 25, characterized in that, The first SiC source driving layer and the first IGBT emitter driving layer are connected to form a first common copper layer.

27. The half-bridge power module according to claim 25, characterized in that, The first SiC source drive layer is provided with a plurality of drive resistors that correspond one-to-one with and are connected to the plurality of wide bandgap power chips in the first wide bandgap chipset.

28. The half-bridge power module according to claim 25, characterized in that, The conductive metal layer further includes: The second driving layer group includes: a second SiC gate driving layer, a second IGBT gate driving layer, a second SiC source driving layer, and a second IGBT emitter driving layer. The gate of the SiC MOSFET of the lower bridge is connected to the second SiC gate driving layer, the source of the SiC MOSFET of the lower bridge is connected to the second SiC source driving layer, the gate of the Si IGBT of the lower bridge is connected to the second IGBT gate driving layer, and the emitter of the Si IGBT of the lower bridge is connected to the second IGBT emitter driving layer.

29. The half-bridge power module according to claim 28, characterized in that, The second SiC source drive layer and the second IGBT emitter drive layer are connected to form a second common copper layer.

30. The half-bridge power module according to claim 28, characterized in that, The second SiC source drive layer is provided with a plurality of drive resistors that correspond one-to-one with and are connected to the plurality of wide bandgap power chips in the second wide bandgap chipset.

31. The half-bridge power module according to claim 28, characterized in that, The conductive metal layer includes a first side and a second side that are opposite to each other along the first direction. The first driving layer group is disposed along the first side, and at least a portion of the structure of the DC positive pole region is located on the side of the first driving layer group away from the first side along the first direction.

32. The half-bridge power module according to claim 31, characterized in that, The second driving layer group is located on one side of the DC negative pole region along the second direction toward the second side, or the AC region at least partially surrounds the second driving layer group.

33. The half-bridge power module according to any one of claims 1 to 3, characterized in that, The conductive metal layer includes a first driving layer region; At least a portion of the first driver layer region is disposed between the first wide bandgap chipset and the second wide bandgap chipset.

34. The half-bridge power module according to claim 33, characterized in that, The first driving layer region is used to form an electrical connection with the second wide bandgap chipset.

35. The half-bridge power module according to any one of claims 1 to 3 or claim 34, characterized in that, Both the first wide bandgap chipset and the second wide bandgap chipset include a plurality of wide bandgap power chips arranged along a first direction, and the first wide bandgap chipset and the second wide bandgap chipset are arranged along a second direction.

36. The half-bridge power module according to claim 35, characterized in that, Multiple wide-bandgap power chips in the first wide-bandgap chipset are connected in series one-to-one with multiple wide-bandgap power chips in the first wide-bandgap chipset to form a half-bridge circuit, and multiple wide-bandgap power chips in the first wide-bandgap chipset are connected in parallel with each other.

37. The half-bridge power module according to claim 35, characterized in that, At least a portion of the structure of the DC positive region and the AC region extends along the first direction and is arranged along the second direction. The first wide bandgap chip group is disposed in the portion of the DC positive region extending along the first direction, and the second wide bandgap chip group is disposed in the portion of the AC region extending along the first direction.

38. The half-bridge power module according to claim 37, characterized in that, The conductive metal layer further includes a DC negative electrode region, at least a portion of which extends along the first direction.

39. The half-bridge power module according to claim 38, characterized in that, The plurality of wide-bandgap power chips in the first wide-bandgap chipset are electrically connected to the AC region, and the plurality of wide-bandgap power chips in the second wide-bandgap chipset are electrically connected to the DC negative region.

40. The half-bridge power module according to claim 35, characterized in that, The outer contour of the conductive metal layer includes a first side and a second side opposite to each other along the first direction, and a third side and a fourth side opposite to each other along the second direction. The DC positive region includes a first positive transmission region, which extends along the second direction and is disposed along the first side, and the first silicon-based chip group is disposed in the first positive transmission region.

41. The half-bridge power module according to claim 40, characterized in that, The DC positive region further includes a second positive transmission region, which extends along the first direction and is interspersed with the AC region at intervals. The first wide bandgap chip group is located in the second positive transmission region.

42. The half-bridge power module according to claim 41, characterized in that, The DC negative pole region includes a first negative pole transmission region and a second negative pole transmission region. The first negative pole transmission region is disposed along the third side, and the second negative pole transmission region is disposed along the second side.

43. The half-bridge power module according to claim 42, characterized in that, The AC region includes a first AC region, which extends along the first direction and is located between the second positive transmission region and the first negative transmission region, and the second wide bandgap chipset is disposed in the first AC region.

44. The half-bridge power module according to claim 43, characterized in that, The AC region also includes a second AC region, which is located between the second positive electrode transmission region and the second negative electrode transmission region, and the second silicon-based chip assembly is disposed in the second AC region.

45. The half-bridge power module according to claim 44, characterized in that, A recessed area is provided between the first AC area and the second AC area to accommodate the second positive electrode transmission area extending along the first direction.

46. ​​The half-bridge power module according to claim 45, characterized in that, The half-bridge power module also includes a DC positive terminal, which is located in the first positive transmission area.

47. The half-bridge power module according to claim 46, characterized in that, The DC positive terminal is led out from the third side.

48. The half-bridge power module according to claim 46, characterized in that, The half-bridge power module also includes a DC negative terminal, which is located in the first negative transmission area.

49. The half-bridge power module according to claim 48, characterized in that, The DC negative terminal is led out from the third side.

50. The half-bridge power module according to claim 48, characterized in that, The half-bridge power module also includes an AC terminal, which is located in the second AC area.

51. The half-bridge power module according to claim 50, characterized in that, The AC terminal is led out from the fourth side.

52. The half-bridge power module according to claim 48, characterized in that, The DC negative terminal is positioned opposite to the second wide bandgap chipset along the second direction.

53. The half-bridge power module according to claim 44, characterized in that, The multiple wide-bandgap power chips in the first wide-bandgap chipset are all connected to the first AC area via a first connection line.

54. The half-bridge power module according to claim 53, characterized in that, The multiple wide-bandgap power chips in the second wide-bandgap chipset are all connected to the first negative transmission area via a second connection line.

55. The half-bridge power module according to claim 36, characterized in that, The plurality of wide bandgap power chips in at least one of the first wide bandgap chipset and the second wide bandgap chipset are arranged flush in the second direction.

56. The half-bridge power module according to claim 36, characterized in that, The first wide bandgap chipset and the second wide bandgap chipset are at least one group of multiple wide bandgap power chips, and any two adjacent wide bandgap power chips are staggered along the second direction.

57. The half-bridge power module according to claim 40, characterized in that, Along the second direction of the DC positive region, the first wide bandgap chip group is disposed near the third side, and the first silicon-based chip group is disposed near the fourth side.

58. The half-bridge power module according to claim 44, characterized in that, Along the second direction of the communication area, the second wide bandgap chipset is disposed near the third side, and the second silicon-based chipset is disposed near the fourth side.

59. The half-bridge power module according to claim 33, characterized in that, The first wide bandgap chipset and the second wide bandgap chipset also include a first type of diode. The first type of diode of the first wide bandgap chipset is connected in series with the first type of diode of the second wide bandgap chipset, and the first type of diode is connected in parallel with the wide bandgap power chip in the same group.

60. The half-bridge power module according to claim 59, characterized in that, The first type of diode has the same substrate material as the wide bandgap power chip.

61. The half-bridge power module according to claim 35, characterized in that, Both the first silicon-based chipset and the second silicon-based chipset include at least one second type diode. The second type diode of the first silicon-based chipset is connected in series with the second type diode of the second silicon-based chipset, and the second type diode is connected in parallel with the silicon-based chip in the same group.

62. The half-bridge power module according to claim 61, characterized in that, The silicon-based power chip and the second type of diode in the silicon-based chipset are connected in parallel to form a chip pair.

63. The half-bridge power module according to claim 61, characterized in that, The second type of diode has the same substrate material as the silicon-based power chip.

64. The half-bridge power module according to claim 62, characterized in that, Both the first silicon-based chipset and the second silicon-based chipset contain multiple chip pairs, and the multiple chip pairs are arranged along the second direction.

65. The half-bridge power module according to claim 64, characterized in that, The silicon-based power chip and the second type of diode in each chip pair are arranged along the first direction or the second direction.

66. The half-bridge power module according to claim 64, characterized in that, The silicon-based power chips and second-type diodes in the multiple chip pairs are arranged in the same or opposite directions.

67. The half-bridge power module according to claim 61, characterized in that, The first silicon-based chip group and the second silicon-based chip group each contain multiple chip pairs, wherein multiple silicon-based power chips are arranged adjacently along the second direction, multiple second-type diodes are arranged adjacently along the second direction, and multiple silicon-based power chips and second-type diodes are arranged along the second direction.

68. The half-bridge power module according to any one of claims 33-67, characterized in that, The wide bandgap power chip includes SiC MOSFET, and the silicon-based power chip includes Si IGBT.

69. The half-bridge power module according to claim 68, characterized in that, The first driving layer region includes: a first SiC gate driving layer and a first SiC source driving layer. The gate of the SiC MOSFET of the lower bridge is connected to the first SiC gate driving layer, and the source of the SiC MOSFET of the lower bridge is connected to the first SiC source driving layer.

70. The half-bridge power module according to claim 69, characterized in that, The first SiC gate driving layer and the first SiC source driving layer are disposed between the first wide bandgap chipset and the second wide bandgap chipset.

71. The half-bridge power module according to claim 69, characterized in that, The first driving layer region further includes: a first IGBT gate driving layer and a first IGBT emitter driving layer, wherein the gate of the Si IGBT of the lower bridge is connected to the first IGBT gate driving layer, and the emitter of the Si IGBT of the lower bridge is connected to the first IGBT emitter driving layer.

72. The half-bridge power module according to claim 71, characterized in that, The first IGBT gate driving layer and the first IGBT emitter driving layer are disposed on the second side.

73. The half-bridge power module according to claim 69, characterized in that, The conductive metal layer further includes a second driving layer region, which is located close to the first wide bandgap chipset.

74. The half-bridge power module according to claim 73, characterized in that, At least a portion of the second driving layer region is disposed between the DC positive region and the AC region.

75. The half-bridge power module according to claim 73, characterized in that, The second driving layer region includes: a second SiC gate driving layer and a second SiC source driving layer, wherein the gate of the SiC MOSFET of the upper bridge is connected to the second SiC gate driving layer, and the source of the SiC MOSFET of the upper bridge is connected to the second SiC source driving layer.

76. The half-bridge power module according to claim 75, characterized in that, The second SiC gate driving layer and the second IGBT gate driving layer are disposed between the DC positive region and the AC region.

77. The half-bridge power module according to claim 74, characterized in that, The second driving layer region further includes: a second IGBT gate driving layer and a second IGBT emitter driving layer, wherein the gate of the Si IGBT of the upper bridge is connected to the second IGBT gate driving layer, and the emitter of the Si IGBT of the upper bridge is connected to the second IGBT emitter driving layer.

78. The half-bridge power module according to claim 76, characterized in that, The second IGBT gate driving layer and the second IGBT emitter driving layer are disposed on the second side.

79. The half-bridge power module according to claim 71 or 77, characterized in that, The first SiC source driving layer 1153 and the first IGBT emitter driving layer 1154 are connected to form a first common copper layer; or... The second SiC source driving layer 1143 and the second IGBT emitter driving layer 1144 are connected to form The second common copper layer is 1145.

80. The half-bridge power module according to any one of claims 1 to 3, characterized in that, The first wide bandgap chip group and the second wide bandgap chip group are arranged along a first direction. Both the first wide bandgap chip group and the second wide bandgap chip group include multiple wide bandgap power chips. Multiple wide bandgap power chips in one group of the first wide bandgap chip group and the second wide bandgap chip group are arranged along the first direction, and multiple wide bandgap power chips in the other group are arranged along a second direction.

81. The half-bridge power module according to claim 80, characterized in that, The conductive metal layer includes a first driving layer region, which is disposed near the second wide bandgap chipset of the lower bridge.

82. The half-bridge power module according to claim 81, characterized in that, The first driving layer area is disposed within the AC area and is insulated from and separated from the AC area.

83. The half-bridge power module according to claim 81, characterized in that, The first driving layer is spaced between the AC region and the DC positive region.

84. The half-bridge power module according to claim 80, characterized in that, The wide bandgap power chips in the second wide bandgap chipset are connected in series one-to-one with the wide bandgap power chips in the first wide bandgap chipset to form a half-bridge circuit, and the multiple wide bandgap power chips in the first wide bandgap chipset are connected in parallel with each other.

85. The half-bridge power module according to claim 80, characterized in that, The plurality of wide bandgap power chips in the first wide bandgap chipset are arranged along the second direction, and the plurality of wide bandgap power chips in the second wide bandgap chipset are arranged along the first direction.

86. The half-bridge power module according to claim 80, characterized in that, The multiple wide-bandgap power chips in the first wide-bandgap chipset are all electrically connected to the AC area.

87. The half-bridge power module according to claim 80, characterized in that, The conductive metal layer also includes a DC negative electrode region, and multiple wide bandgap power chips in the second wide bandgap chipset are electrically connected to the DC negative electrode region.

88. The half-bridge power module according to claim 80, characterized in that, At least a portion of the structure of the DC positive region extends along the second direction, and the first wide bandgap chip group is disposed in the portion of the DC positive region extending along the second direction.

89. The half-bridge power module according to claim 80, characterized in that, At least a portion of the structure of the communication area extends along the first direction, and the second wide bandgap chipset is disposed in the portion of the communication area extending along the first direction.

90. The half-bridge power module according to claim 80, characterized in that, The outer contour of the conductive metal layer includes a first side and a second side opposite to each other along the first direction, and a third side and a fourth side opposite to each other along the second direction; at least a portion of the structure of the DC positive electrode region is disposed along the first side.

91. The half-bridge power module according to claim 90, characterized in that, The upper bridge includes a first silicon-based chipset, and the first wide bandgap chipset and the first silicon-based chipset are arranged side by side along a second direction of the first side.

92. The half-bridge power module according to claim 90, characterized in that, The conductive metal layer further includes a DC negative electrode region, at least a portion of which is disposed along the second side.

93. The half-bridge power module according to claim 92, characterized in that, The DC negative pole region includes a first negative pole transmission region and a second negative pole transmission region. The first negative pole transmission region is disposed along the third side, and the second negative pole transmission region is disposed along the second side.

94. The half-bridge power module according to claim 93, characterized in that, The lower bridge also includes a second silicon-based chipset, and the second wide-bandgap chipset and the second silicon-based chipset are disposed in the AC area.

95. The half-bridge power module according to claim 94, characterized in that, The AC region is located within the space enclosed by the DC positive region, the first negative transmission region, and the second negative transmission region. The second wide bandgap chipset and the second silicon-based chipset are arranged side by side in the AC region along the second direction.

96. The half-bridge power module according to claim 90, characterized in that, The half-bridge power module also includes a DC positive terminal, which is electrically connected to the DC positive region.

97. The half-bridge power module according to claim 96, characterized in that, The DC positive terminal is led out from the third side.

98. The half-bridge power module according to claim 90, characterized in that, The half-bridge power module also includes a DC negative terminal, which is electrically connected to the first negative transmission area.

99. The half-bridge power module according to claim 90, characterized in that, The DC negative terminal is led out from the third side.

100. The half-bridge power module according to claim 90, characterized in that, The half-bridge power module also includes an AC terminal, which is electrically connected to the AC zone.

101. The half-bridge power module according to claim 100, characterized in that, The AC terminal is led out from the fourth side.

102. The half-bridge power module according to claim 96, characterized in that, In the DC positive region, the first wide bandgap chipset is positioned close to the DC positive terminal.

103. The half-bridge power module according to claim 98, characterized in that, In the AC region, the second wide-bandgap chipset is positioned close to the DC negative terminal.

104. The half-bridge power module according to claim 102, characterized in that, The DC negative terminal and the second wide bandgap chip group are arranged at a distance from each other along the second direction.

105. The half-bridge power module according to claim 80, characterized in that, The plurality of wide bandgap power chips in the first wide bandgap chipset are arranged flush in the first direction.

106. The half-bridge power module according to claim 80, characterized in that, In the first wide bandgap chipset, any two adjacent wide bandgap power chips are staggered along the first direction.

107. The half-bridge power module according to claim 80, characterized in that, The plurality of wide bandgap power chips in the second wide bandgap chipset are aligned in the second direction.

108. The half-bridge power module according to claim 80, characterized in that, In the second wide bandgap chipset, any two adjacent wide bandgap power chips are staggered along the second direction.

109. The half-bridge power module according to claim 80, characterized in that, The first wide bandgap chipset and the second wide bandgap chipset are also provided with first type diodes. The first type diodes of the first wide bandgap chipset are connected in series with the first type diodes of the second wide bandgap chipset and in parallel with the wide bandgap power chips in the group.

110. The half-bridge power module according to claim 109, characterized in that, The first type of diode has the same substrate material as the wide bandgap power chip.

111. The half-bridge power module according to claim 80, characterized in that, Both the first silicon-based chipset and the second silicon-based chipset include at least one second-type diode. The second-type diodes of the first silicon-based chipset are connected in series with the second-type diodes of the second silicon-based chipset, and the silicon-based power chips and second-type diodes within the same group are connected in parallel.

112. The half-bridge power module according to claim 111, characterized in that, The second type of diode has the same substrate material as the silicon-based power chip.

113. The half-bridge power module according to claim 111, characterized in that, The silicon-based power chip and the second type of diode in the first silicon-based chipset and the second silicon-based chipset form a chip pair.

114. The half-bridge power module according to claim 113, characterized in that, Both the first silicon-based chipset and the second silicon-based chipset have multiple chip pairs, and the multiple chip pairs are arranged along the second direction.

115. The half-bridge power module according to claim 113, characterized in that, The silicon-based power chip and the second type of diode in each chip pair are arranged along the first direction or the second direction.

116. The half-bridge power module according to claim 113, characterized in that, The silicon-based power chips and second-type diodes in the multiple chip pairs are arranged in the same or opposite directions.

117. The half-bridge power module according to claim 113, characterized in that, The first silicon-based chipset and the second silicon-based chipset each have multiple chip pairs, wherein the multiple silicon-based power chips are arranged adjacent to each other along the second direction, the multiple second-type diodes are arranged adjacent to each other along the second direction, and the multiple silicon-based power chips and the second-type diodes are arranged along the second direction.

118. The half-bridge power module according to any one of claims 80-117, characterized in that, The upper bridge further includes a first silicon-based chipset, and the lower bridge further includes a second silicon-based chipset. Both the first and second silicon-based chipsets include at least one silicon-based power chip. The wide-bandgap power chip includes a SiC MOSFET, and the silicon-based power chip includes a Si IGBT.

119. The half-bridge power module according to claim 118, characterized in that, The first driving layer region includes a first SiC gate driving layer and a first SiC source driving layer. The gate of the SiC MOSFET of the lower bridge is connected to the first SiC gate driving layer, and the source of the SiC MOSFET of the lower bridge is connected to the first SiC source driving layer.

120. The half-bridge power module according to claim 119, characterized in that, The first driving layer region further includes: a first IGBT gate driving layer and a first IGBT emitter driving layer, wherein the gate of the Si IGBT of the lower bridge is connected to the first IGBT gate driving layer, and the emitter of the Si IGBT of the lower bridge is connected to the first IGBT emitter driving layer.

121. The half-bridge power module according to claim 120, characterized in that, The conductive metal layer further includes a second driving layer region, which includes a second SiC gate driving layer and a second SiC source driving layer. The gate of the SiC MOSFET of the upper bridge is connected to the second SiC gate driving layer, and the source of the SiC MOSFET of the upper bridge is connected to the second SiC source driving layer.

122. The half-bridge power module according to claim 121, characterized in that, The second driving layer region further includes: a second IGBT gate driving layer and a second IGBT emitter driving layer, wherein the gate of the Si IGBT of the upper bridge is connected to the second IGBT gate driving layer, and the emitter of the Si IGBT of the upper bridge is connected to the second IGBT emitter driving layer.

123. The half-bridge power module according to claim 122, characterized in that, The half-bridge power module further includes a drive terminal, wherein one or more of the first SiC gate drive layer, the first SiC source drive layer, the first IGBT gate drive layer, the first IGBT emitter drive layer, the second SiC gate drive layer, the second SiC source drive layer, the second IGBT gate drive layer, and the second IGBT emitter drive layer are led out perpendicularly to the substrate through the drive terminal.

124. The half-bridge power module according to claim 120 or 122, characterized in that, The first SiC source driving layer and the first IGBT emitter driving layer are connected to form a first common copper layer; or, the second SiC source driving layer and the second IGBT emitter driving layer are connected to form a second common copper layer.

125. A half-bridge power module, characterized in that, include substrate; The DC positive electrode region, AC region, and DC negative electrode region are located on the substrate; And an upper bridge chip set located on the DC positive region, and a lower bridge chip set on the AC region, wherein the upper bridge chip set includes a first wide bandgap chip set and the lower bridge chip set includes a second wide bandgap chip set; The first wide bandgap chipset is connected to the AC region, and the second wide bandgap chipset is connected to the DC negative region; The first wide bandgap chipset and the second wide bandgap chipset are arranged along the second direction, and both the first wide bandgap chipset and the second wide bandgap chipset include a plurality of wide bandgap power chips arranged along the second direction.

126. The half-bridge power module according to claim 125, characterized in that, The upper bridge chipset also includes a first silicon-based chipset, and the lower bridge chipset also includes a second silicon-based chipset. The silicon-based power chip in each of the first silicon-based chipset is connected in series with the silicon-based power chip in the second silicon-based chipset to form a half-bridge structure.

127. The half-bridge power module according to claim 126, characterized in that, The second wide bandgap chipset is connected in series with the wide bandgap power chips in the first wide bandgap chipset to form a half-bridge circuit, and the multiple wide bandgap power chips in the wide bandgap chipset are connected in parallel with each other.

128. The half-bridge power module according to claim 125, characterized in that, The conductive metal layer also includes a DC negative electrode region, on which a second DC connection terminal is provided. The current path length between each wide bandgap power chip of the second wide bandgap chipset and the second DC connection terminal is the same.

129. The half-bridge power module according to claim 125, characterized in that, At least a portion of the structure of the AC region is embedded within the DC positive region and is insulated from the DC positive region by a distance, so as to connect to the wide bandgap power chip in the first wide bandgap chipset.

130. The half-bridge power module according to claim 128, characterized in that, On the DC negative region, the second DC connection terminal is located close to the second wide bandgap chipset.

131. The half-bridge power module according to claim 125, characterized in that, The half-bridge power module further includes a first DC connection terminal, which is located on the DC positive region. The current path length between each wide-bandgap power chip in the first wide-bandgap chipset and the first DC connection terminal is the same.

132. The half-bridge power module according to claim 126, characterized in that, The DC positive region includes a first connection layer and a second connection layer that are electrically connected to each other. The first wide bandgap chipset is located on the first interconnect layer, and the first silicon-based chipset is located on the second interconnect layer.

133. The half-bridge power module according to claim 132, characterized in that, The first connection layer and the second connection layer are located on both sides of the DC negative electrode region.

134. The half-bridge power module according to claim 132, characterized in that, A recess is formed between the first connection layer and the second connection layer to accommodate at least a portion of the protruding structure of the AC region. The protruding at least a portion of the structure is spaced apart from the DC positive region and is used to electrically connect multiple wide bandgap power chips in the first wide bandgap chipset.

135. The half-bridge power module according to any one of claims 125-134, characterized in that, The arrangement of the multiple wide-bandgap power chips includes at least one of the following: Each of the wide bandgap power chips is flush-mounted in the second direction; Two adjacent wide-bandgap power chips are staggered in the first direction; Each of the wide bandgap power chips is staggered in the first direction; The first direction and the second direction are two mutually perpendicular directions on a plane.

136. The half-bridge power module according to claim 126, characterized in that, The first silicon-based chipset also includes multiple diode chips.

137. The half-bridge power module according to claim 136, characterized in that, The second silicon-based chipset also includes multiple diode chips.

138. The half-bridge power module according to claim 137, characterized in that, Each of the multiple diode chips in the first silicon-based chipset is connected in series with multiple diode chips in the second silicon-based chipset.

139. The half-bridge power module according to claim 137, characterized in that, The arrangement of the plurality of silicon-based power chips and the plurality of diode chips within any one of the silicon-based chipsets includes at least one of the following: The silicon-based power chip and the diode chip are arranged crosswise in a first direction; A first chip assembly and a second chip assembly are arranged in the first direction, the first chip assembly including a plurality of silicon-based power chips arranged in the first direction, and the second chip assembly including a plurality of diode chips arranged in the first direction. Multiple third chip assemblies are arranged in the first direction, and the third chip assemblies are included in the second direction. The silicon-based power chip and the diode chip arranged upwards; Multiple fourth chip combinations and multiple fifth chip combinations are arranged in a crisscrossing manner in the first direction. The fourth chip combinations and the fifth chip combinations include silicon-based power chips and diode chips arranged in the second direction, and the silicon-based power chips and the diode chips in the fourth chip combinations and the fifth chip combinations are arranged in opposite directions. Wherein, the first direction and the second direction are two mutually perpendicular directions on a plane.

140. The half-bridge power module according to claim 137, characterized in that, The arrangement of the plurality of silicon-based power chips and the plurality of diode chips within any one of the silicon-based chipsets includes at least one of the following: The silicon-based power chip and the diode chip are arranged in a cross pattern in the second direction; A first chip assembly and a second chip assembly are arranged in the second direction, the first chip assembly including a plurality of silicon-based power chips arranged in the second direction, and the second chip assembly including a plurality of diode chips arranged in the second direction; Multiple third chip combinations are arranged in the second direction, the third chip combinations including the silicon-based power chip and the diode chip arranged in the first direction; Multiple fourth chip combinations and multiple fifth chip combinations are arranged in a cross pattern in the second direction. The fourth chip combinations and the fifth chip combinations include the silicon-based power chip and the diode chip arranged in the first direction, and the silicon-based power chip and the diode chip are arranged in opposite directions in the fourth chip combinations and the fifth chip combinations.

141. The half-bridge power module according to claim 136, characterized in that, The half-bridge power module includes: An upper bridge driving layer located on the substrate, the upper bridge driving layer including a first gate driving layer and a first source driving layer; The gate of each wide bandgap power chip in the first wide bandgap chipset is connected to the first gate driving layer, and the source of each wide bandgap power chip in the first wide bandgap chipset is connected to the first source driving layer.

142. The half-bridge power module according to claim 141, characterized in that, The upper bridge driving layer further includes a second gate driving layer and a first emitter driving layer, wherein the base of each silicon-based power chip in the first silicon-based chip group is connected to the second gate driving layer, and the emitter of each silicon-based power chip in the first silicon-based chip group is connected to the first emitter driving layer.

143. The half-bridge power module according to claim 137, characterized in that, The half-bridge power module includes: A lower bridge driving layer located on the substrate, the lower bridge driving layer including a third gate driving layer and a second source driving layer; The gate of each wide bandgap power chip in the second wide bandgap chipset is connected to the third gate driving layer, and the source of each wide bandgap power chip in the second wide bandgap chipset is connected to the second source driving layer.

144. The half-bridge power module according to claim 143, characterized in that, The lower bridge driving layer further includes a fourth gate driving layer and a second emitter driving layer. The base of each silicon-based power chip in the second silicon-based chipset is connected to the fourth gate driving layer, and the emitter of each silicon-based power chip in the second silicon-based chipset is connected to the second emitter driving layer.

145. The half-bridge power module according to claim 142, characterized in that, The first source driving layer and the first emitter driving layer are the same driving layer.

146. The half-bridge power module according to claim 142, characterized in that, The half-bridge power module includes: The first gate driving terminal disposed in the first gate driving layer, and the first gate driving terminal disposed in the second gate driving layer The second gate driving terminal, the first source driving terminal disposed in the first source driving layer, and the first emitter driving terminal disposed in the first emitter driving layer.

147. The half-bridge power module according to claim 146, characterized in that, At least one of the first gate driving terminal, the second gate driving terminal, the first source driving terminal, and the first emitter driving terminal is led out perpendicularly to the substrate.

148. The half-bridge power module according to claim 144, characterized in that, The second source driving layer and the second emitter driving layer are the same driving layer.

149. The half-bridge power module according to claim 144, characterized in that, The half-bridge power module includes: The third gate driving terminal is disposed in the third gate driving layer, the fourth gate driving terminal is disposed in the fourth gate driving layer, the second source driving terminal is disposed in the second source driving layer, and the second emitter driving terminal is disposed in the second emitter driving layer.

150. The half-bridge power module according to claim 149, characterized in that, At least one of the third gate driving terminal, the fourth gate driving terminal, the second source driving terminal, and the second emitter driving terminal is led out perpendicularly to the substrate.

151. The half-bridge power module according to claim 141, characterized in that, The half-bridge power module includes: Two interconnected first source driving layers, at least one of the source driving layers having a plurality of driving resistors; The first end of each of the driving resistors is interconnected and connected to the first gate driving layer, and the second end of each of the driving resistors is connected to the gate of one of the first wide bandgap power chips in the first wide bandgap chipset.

152. The half-bridge power module according to claim 143, characterized in that, The half-bridge power module includes: Two interconnected second source driving layers, each having multiple driving resistors; the first end of each driving resistor is interconnected and connected to the third gate driving layer, and the second end of each driving resistor is connected to the gate of one of the wide bandgap power chips in the second wide bandgap chipset.

153. The half-bridge power module according to claim 129, characterized in that, At least a portion of the structure of the AC region embedded in the DC positive region includes an AC connection terminal, and the current path length between each wide bandgap power chip in the first wide bandgap chipset and the AC connection terminal is the same.

154. The half-bridge power module according to claim 125, characterized in that, The DC negative pole area is also connected to a second DC connection terminal, which is led out along the first direction.

155. The half-bridge power module according to claim 125, characterized in that, The DC positive region is also connected to a first DC connection terminal, which is led out along a first direction.

156. The half-bridge power module according to claim 125, characterized in that, The AC area is also connected to an AC connection terminal, which is led out along a first direction.

157. The half-bridge power module according to any one of claims 125-156, characterized in that, At least one of the DC positive region, the DC negative region, and the AC region is a copper layer.

158. The half-bridge power module according to any one of claims 125-156, characterized in that, The wide bandgap power chip includes silicon carbide metal-oxide-semiconductor field-effect transistors or gallium nitride high electron mobility transistors.

159. The half-bridge power module according to claims 126-158, characterized in that, The silicon-based power chip includes a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field-effect transistor. Diode chips include silicon fast recovery diode chips or silicon carbide Schottky diode chips.

160. A half-bridge power module, characterized in that, include: substrate; The DC positive region and AC region are located on the substrate. The AC zone includes a first AC zone and a second AC zone, which are separated and disposed on both sides of the DC positive pole zone; The upper bridge chip group is disposed on the DC positive region; A lower-bridge chipset, wherein a portion of the chips in the lower-bridge chipset are disposed in a first AC area, and another portion of the chips are disposed in a second AC area; The chips within the upper bridge chipset are electrically connected to the AC area.

161. The half-bridge power module according to claim 160, characterized in that, The DC positive region is located between the first AC region and the second AC region, and the first AC region and the second AC region are electrically connected by leads or terminals.

162. The half-bridge power module according to claim 160, characterized in that, The lower bridge chipset includes a second wide bandgap chipset, and the chips in the upper bridge chipset are electrically connected to the first AC region. The second wide bandgap chipset is disposed in the first AC region.

163. The half-bridge power module according to claim 162, characterized in that, The downbridge chipset also includes a second silicon-based chipset, which is disposed in the second AC area.

164. The half-bridge power module according to claim 163, characterized in that, The upper bridge chipset includes a first wide bandgap chipset, and the first wide bandgap chipset and the second wide bandgap chipset are arranged along a first direction. Both the first wide bandgap chipset and the second wide bandgap chipset include a plurality of wide bandgap power chips arranged along a second direction.

165. The half-bridge power module according to claim 164, characterized in that, The second wide bandgap chipset is connected in series with the wide bandgap power chips in the first wide bandgap chipset.

166. The half-bridge power module according to claim 164, characterized in that, The upper bridge chipset also includes a first silicon-based chipset, wherein the chips in the first silicon-based chipset are connected in series with the chips in the second silicon-based chipset in a one-to-one correspondence.

167. The half-bridge power module according to claim 164, characterized in that, The first AC region includes a first AC connection terminal, and the current path length between each wide bandgap power chip in the first wide bandgap chipset and the first AC connection terminal is the same.

168. The half-bridge power module according to claim 162, characterized in that, The half-bridge power module also includes a DC negative region, and the second wide bandgap chipset is electrically connected to the DC negative region.

169. The half-bridge power module according to claim 168, characterized in that, The half-bridge power module includes a second DC connection terminal located on the DC negative region; the current path length between each wide bandgap power chip in the second wide bandgap chipset and the second DC connection terminal is the same.

170. The half-bridge power module according to claim 160, characterized in that, The bridge chipset includes: The first silicon-based chip group and the first wide bandgap chip group are arranged along a first direction on the DC positive electrode region.

171. The half-bridge power module according to claim 163, characterized in that, The lower bridge chipset also includes: The second silicon-based chipset and the second wide-bandgap chipset are arranged in a first direction.

172. The half-bridge power module according to claim 169, characterized in that, On the DC negative region, the second DC connection terminal is located close to the second wide bandgap chipset.

173. The half-bridge power module according to claim 166, characterized in that, The first silicon-based chipset includes multiple silicon-based power chips and multiple diode chips, with each silicon-based power chip and each diode chip connected in parallel in a one-to-one correspondence.

174. The half-bridge power module according to claim 163, characterized in that, The second silicon-based chipset includes multiple silicon-based power chips and multiple diode chips, with each silicon-based power chip and each diode chip connected in parallel in a one-to-one correspondence.

175. The half-bridge power module according to claim 168, characterized in that, The DC negative electrode region includes a first DC negative electrode connection layer and a second DC negative electrode connection layer, which are connected together.

176. The half-bridge power module according to claim 175, characterized in that, The first AC region, the DC positive region, and the second AC region are disposed between the first DC negative connection layer and the second DC negative connection layer.

177. The half-bridge power module according to claim 176, characterized in that, The first AC region is disposed close to the first DC negative electrode connection layer in the first direction, and the second AC region is disposed close to the second DC negative electrode connection layer in the first direction.

178. The half-bridge power module according to claim 176, characterized in that, The first DC negative electrode connection layer and the second DC negative electrode connection layer enclose the first AC region, the DC positive electrode region and the second AC region.

179. The half-bridge power module according to claim 176, characterized in that, The second DC negative electrode connection layer is disposed at least partially close to the DC positive electrode region.

180. The half-bridge power module according to claim 179, characterized in that, The current direction of the second DC negative electrode connection layer is opposite to the current direction of the DC positive electrode region.

181. The half-bridge power module according to claim 166, characterized in that, The second AC area includes a second AC connection terminal, and the chip of the first silicon-based chipset is connected to the second AC connection terminal.

182. The half-bridge power module according to claim 166, characterized in that, In the second AC area, the second AC connection terminal is positioned close to the first silicon-based chipset.

183. The half-bridge power module according to claim 175, characterized in that, The half-bridge power module includes two first DC terminals, which are located on the first DC negative terminal connection layer and the second DC negative terminal connection layer, respectively.

184. The half-bridge power module according to claim 164, characterized in that, The arrangement of the multiple wide-bandgap power chips includes at least one of the following: Each of the wide bandgap power chips is flush in the second direction; Two adjacent wide-bandgap power chips are staggered in the first direction; Wherein, the first direction and the second direction are two mutually perpendicular directions on a plane.

185. The half-bridge power module according to claim 173, characterized in that, silicon-based chipsets include: The arrangement of multiple silicon-based power chips and multiple diode chips includes at least one of the following: A first chip assembly, a second chip assembly, and a third chip assembly are arranged sequentially in a second direction. The first chip assembly includes at least one silicon-based power chip arranged sequentially in the second direction. The second chip assembly includes at least one diode chip arranged sequentially in the second direction. The third chip assembly includes at least one silicon-based power chip arranged sequentially in the second direction. A fourth chip assembly, a fifth chip assembly, and a sixth chip assembly are arranged sequentially in the second direction. The fourth chip assembly includes at least one diode chip arranged sequentially in the second direction. The fifth chip assembly includes at least one silicon-based power chip arranged sequentially in the second direction. The sixth chip assembly includes at least one diode chip arranged sequentially in the second direction. Multiple silicon-based power chips and multiple diode chips are arranged in a crisscross pattern in the second direction; and, Wherein, the first direction and the second direction are two mutually perpendicular directions on a plane.

186. The half-bridge power module according to claim 166, characterized in that, The half-bridge power module includes: A first gate driving layer and a first source driving layer are located on the substrate; The gate of each wide bandgap power chip in the first wide bandgap chipset is connected to the first gate driving layer, and the source of each wide bandgap power chip in the first wide bandgap chipset is connected to the first source driving layer.

187. The half-bridge power module according to claim 166, characterized in that, The half-bridge power module includes: A second gate driving layer and a first emitter driving layer are located on the substrate; the base of each silicon-based power chip in the first silicon-based chip group is connected to the second gate driving layer, and the emitter of each silicon-based power chip in the first silicon-based chip group is connected to the first emitter driving layer.

188. The half-bridge power module according to claim 166, characterized in that, The half-bridge power module includes: The third gate driving layer and the second source driving layer located on the substrate The gate of each wide bandgap power chip in the second wide bandgap chipset is connected to the third gate driving layer, and the source of each wide bandgap power chip in the second wide bandgap chipset is connected to the second source driving layer.

189. The half-bridge power module according to claim 166, characterized in that, The half-bridge power module includes: A fourth gate driving layer and a second emitter driving layer are located on the substrate; the base of each silicon-based power chip in the second silicon-based chip group is connected to the fourth gate driving layer, and the emitter of each silicon-based power chip in the second silicon-based chip group is connected to the second emitter driving layer.

190. The half-bridge power module according to claim 186, characterized in that, The half-bridge power module includes: A first gate driving terminal and a first source driving terminal are disposed in the first gate driving layer.

191. The half-bridge power module according to claim 187, characterized in that, The half-bridge power module includes: A second gate driving terminal is disposed in the second gate driving layer and a first emitter driving terminal is disposed in the first emitter driving layer.

192. The half-bridge power module according to claim 188, characterized in that, The half-bridge power module includes: The third gate driving terminal is disposed in the third gate driving layer and the second source driving terminal is disposed in the second source driving layer.

193. The half-bridge power module according to claim 189, characterized in that, The half-bridge power module includes: The fourth gate driving terminal is disposed in the fourth gate driving layer and the second emitter driving terminal is disposed in the second emitter driving layer.

194. The half-bridge power module according to any one of claims 168-193, characterized in that, At least one of the DC positive region, the DC negative region, and the AC region is a copper layer.

195. The half-bridge power module according to any one of claims 164-193, characterized in that, The wide bandgap power chip includes silicon carbide metal-oxide-semiconductor field-effect transistors or gallium nitride high electron mobility transistors.

196. The half-bridge power module according to claim 173 or 174, characterized in that, The silicon-based power chip includes a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field-effect transistor. The diode chip includes a silicon fast recovery diode chip or a silicon carbide Schottky diode chip.

197. A half-bridge power module, characterized in that, include: substrate; A circuit unit is disposed on the substrate. The circuit unit includes an upper bridge and a lower bridge, both of which include various power components. These power components include wide-bandgap power chips, silicon-based power chips, and diodes. Specifically, there are multiple wide-bandgap power chips, and at least one silicon-based power chip and one diode. In the arrangement of the wide bandgap power chip, the silicon-based power chip, and the diode, any two adjacent power elements are power elements of different types.

198. The half-bridge power module according to claim 197, characterized in that, The power elements of the lower bridge are electrically connected to the power elements of the same type in the upper bridge to form a half-bridge circuit, and the various power elements in the upper bridge are connected in parallel with each other.

199. The half-bridge power module according to claim 197, characterized in that, The substrate is provided with a conductive metal layer, which includes a DC positive electrode region, an AC region and a DC negative electrode region. The upper bridge is located in the DC positive region, and all of the power elements of the upper bridge are electrically connected to the AC region. The lower bridge is located in the AC region, and all of the power components of the lower bridge are electrically connected to the DC negative region.

200. The half-bridge power module according to claim 199, characterized in that, At least a portion of the structure of each of the DC positive region, the AC region, and the DC negative region extends along a second direction and is arranged along a first direction, which is perpendicular to the second direction.

201. The half-bridge power module according to claim 200, characterized in that, The power elements in the upper bridge are arranged in at least one row.

202. The half-bridge power module according to claim 201, characterized in that, The power elements in the upper bridge are arranged in multiple rows.

203. The half-bridge power module according to claim 202, characterized in that, When the multiple power elements in the upper bridge are arranged in multiple rows, the multiple rows are arranged along the first direction.

204. The half-bridge power module according to claim 201, characterized in that, The power elements in the lower bridge are arranged in at least one row.

205. The half-bridge power module according to claim 204, characterized in that, The power elements in the lower bridge are arranged in multiple rows.

206. The half-bridge power module according to claim 205, characterized in that, When the multiple power elements in the lower bridge are arranged in multiple rows, the multiple rows are arranged along the first direction.

207. The half-bridge power module according to claim 204, characterized in that, Each row includes several of the power elements arranged along the second direction.

208. The half-bridge power module according to claim 207, characterized in that, Power components of the same type are placed in the same row.

209. The half-bridge power module according to claim 197, characterized in that, The power components in the upper bridge and the lower bridge are arranged in the same way.

210. The half-bridge power module according to claim 197, characterized in that, The power components in the upper bridge and the lower bridge are arranged differently.

211. The half-bridge power module according to claim 209, characterized in that, The two power elements in the upper bridge and the lower bridge that are opposite each other along the first direction are of different types.

212. The half-bridge power module according to claim 210, characterized in that, The two power elements in the upper bridge and the lower bridge that are opposite each other along the first direction are of the same type.

213. The half-bridge power module according to claim 199, characterized in that, The half-bridge power module also includes a DC positive terminal, which is located within the DC positive region and is led out from a direction perpendicular to the substrate, or from the side of the DC positive region.

214. The half-bridge power module according to claim 213, characterized in that, The half-bridge power module also includes a DC negative terminal, which is located within the DC negative region and is led out from a direction perpendicular to the substrate, or from the side of the DC negative region.

215. The half-bridge power module according to claim 214, characterized in that, The half-bridge power module also includes an AC terminal, which is located within the AC region and extends out from a direction perpendicular to the substrate, or from the side of the AC region.

216. The half-bridge power module according to claim 215, characterized in that, The DC positive terminal and the DC negative terminal are located on the same side of the substrate along the first direction, and the AC terminal is located on the side of the substrate opposite to the DC positive terminal along the first direction.

217. The half-bridge power module according to claim 216, characterized in that, When the multiple power elements in the upper bridge and the lower bridge are all divided into multiple rows arranged along the first direction The row containing the wide bandgap power chip is closer to the DC positive terminal and the DC negative terminal along the first direction.

218. The half-bridge power module according to claim 217, characterized in that, The outer contour of the conductive metal layer includes a first side and a second side opposite to each other along the first direction, and a third side and a fourth side opposite to each other along the second direction. The DC positive region includes a first transmission region that extends along the second direction, and the upper bridge is located in the first transmission region.

219. The half-bridge power module according to claim 218, characterized in that, The DC negative electrode region is arranged along the second side and is opposite to and spaced from the first transmission region along the first direction, and the DC negative terminal is led out from the second side.

220. The half-bridge power module according to claim 219, characterized in that, The AC region includes a first AC region, which is located between the first transmission region and the DC negative region, and the lower bridge is located in the first AC region.

221. The half-bridge power module according to claim 220, characterized in that, The DC positive region further includes a second transmission region and a third transmission region. The second transmission region is disposed along the third side, and the third transmission region is disposed along the fourth side. Both the second and third transmission regions extend to the second side along the first direction. The first AC region and the DC negative region are located between the second transmission region and the third transmission region, and the DC positive terminal is disposed on at least one of the second transmission region and the third transmission region.

222. The half-bridge power module according to claim 221, characterized in that, The DC positive terminal is led out from the second side of the conductive metal layer.

223. The half-bridge power module according to claim 222, characterized in that, The second transmission area and the third transmission area each have an extension portion extending along the second side at one end away from the first transmission area along the first direction. There are two DC positive terminals, which are respectively located on the second transmission area and the extension of the third transmission area, and the DC negative terminal is located between the two DC positive terminals.

224. The half-bridge power module according to claim 220, characterized in that, The communication area further includes a second communication area, which is located on the side of the first transmission area facing the first side. The second AC area is disposed along the first side and is connected to the first AC area via a connecting line, and the AC terminal is disposed in the second AC area.

225. The half-bridge power module according to claim 224, characterized in that, The second communication area also includes: the main AC area and the connection area. The AC main area is arranged along the first side, and there are two connection areas. The two connection areas are respectively located on both sides of the first transmission area along the second direction. The first end of each connection area is connected to the AC main area, and the second end extends towards the direction close to the first AC area. The second end is connected to the first AC area through a connection line.

226. The half-bridge power module according to any one of claims 197-225, characterized in that, The wide bandgap power chip includes SiC MOSFETs, and the silicon-based power chip includes Si IGBTs.

227. The half-bridge power module according to claim 226, characterized in that, The substrate has a conductive metal layer, and the conductive metal layer further includes: The first driving layer group includes: a first SiC gate driving layer, a first IGBT gate driving layer, a first SiC source driving layer, and a first IGBT emitter driving layer. The gate of the SiC MOSFET of the upper bridge is connected to the first SiC gate driving layer, the source of the SiC MOSFET of the upper bridge is connected to the first SiC source driving layer, the gate of the Si IGBT of the upper bridge is connected to the first IGBT gate driving layer, and the emitter of the Si IGBT of the upper bridge is connected to the first IGBT emitter driving layer.

228. The half-bridge power module according to claim 227, characterized in that, The conductive metal layer further includes a second driving layer group, comprising a second SiC gate driving layer, a second IGBT gate driving layer, a second SiC source driving layer, and a second IGBT emitter driving layer. The gate of the SiC MOSFET in the lower bridge is connected to the second SiC gate driving layer, the source of the SiC MOSFET in the lower bridge is connected to the second SiC source driving layer, the gate of the Si IGBT in the lower bridge is connected to the second IGBT gate driving layer, and the emitter of the Si IGBT in the lower bridge is connected to the second IGBT emitter driving layer.

229. The half-bridge power module according to claim 228, characterized in that, The first SiC source driving layer and the first IGBT emitter driving layer are connected to form a first common copper layer.

230. The half-bridge power module according to claim 228, characterized in that, The second SiC source drive layer and the second IGBT emitter drive layer are connected to form a second common copper layer.

231. The half-bridge power module according to claim 228, characterized in that, There are multiple first driving layer groups, and each first driving layer group is used to connect at least one of the SiC MOSFETs and at least one of the Si IGBTs in the upper bridge.

232. The half-bridge power module according to claim 228, characterized in that, There are multiple second driving layer groups, and each second driving layer group is used to connect at least one of the SiC MOSFETs and one of the Si IGBTs in the lower bridge.

233. A half-bridge power module, characterized in that, include: Base plate; A first substrate and a second substrate are arranged side-by-side and spaced apart along a first direction on the base plate. The first substrate is provided with a first half-bridge unit, which includes a plurality of wide bandgap power chips. The second substrate is provided with a second half-bridge unit, which includes a plurality of silicon-based power chips. The first substrate and the second substrate are electrically connected.

234. The half-bridge power module according to claim 233, characterized in that, The half-bridge power module also includes a DC positive terminal, a DC negative terminal, and an AC terminal, wherein the DC positive terminal and the DC negative terminal are located on the same substrate.

235. The half-bridge power module according to claim 234, characterized in that, The DC positive terminal and the DC negative terminal are disposed on the first substrate.

236. The half-bridge power module according to claim 234, characterized in that, Both the DC positive terminal and the DC negative terminal are located on different substrates from the AC terminal.

237. The half-bridge power module according to claim 234, characterized in that, The first substrate has a first conductive metal layer. The first conductive metal layer includes a first DC positive electrode region, and the DC positive terminal is disposed in the first DC positive electrode region.

238. The half-bridge power module according to claim 237, characterized in that, The first conductive metal layer further includes a first DC negative electrode region, wherein the DC negative terminal is disposed in the first DC negative electrode region.

239. The half-bridge power module according to claim 238, characterized in that, The first conductive metal layer further includes a first AC region, and the first half-bridge unit includes a first upper bridge chip group and a first lower bridge chip group. The first upper bridge chip group is located in the first DC positive region, and the first lower bridge chip group... The chip group is located in the first AC area, and both the first upper bridge chip group and the first lower bridge chip group include a plurality of the wide bandgap power chips.

240. The half-bridge power module according to claim 239, characterized in that, The first upper-bridge chipset and the first lower-bridge chipset are arranged along the second direction.

241. The half-bridge power module according to claim 240, characterized in that, The wide bandgap power chips in the first upper-bridge chipset and the first lower-bridge chipset are arranged along the first direction.

242. The half-bridge power module according to claim 239, characterized in that, Several wide-bandgap power chips in the first upper-bridge chipset are connected to the first AC area via a first connection line. Several wide-bandgap power chips in the first lower-bridge chipset are connected to the first DC negative electrode region via a second connection line.

243. The half-bridge power module according to claim 239, characterized in that, At least a portion of each of the first DC positive region, the first AC region, and the first DC negative region extends along the first direction and is arranged along the second direction.

244. The half-bridge power module according to claim 239, characterized in that, The first upper-bridge chipset and the first lower-bridge chipset also include a first type of diode, which is arranged along a first direction with the wide-bandgap power chip.

245. The half-bridge power module according to claim 244, characterized in that, The first type of diode in the first upper bridge chipset is connected in series with the first type of diode in the first lower bridge chipset, and the first type of diode is connected in parallel with the wide bandgap power chip in the same chipset.

246. The half-bridge power module according to claim 244, characterized in that, The first type of diode uses the same substrate material as the wide bandgap power chip.

247. The half-bridge power module according to claim 244, characterized in that, The first type of diode is a wide-bandgap substrate Schottky diode.

248. The half-bridge power module according to claim 244, characterized in that, The diodes and the wide-bandgap power chip are arranged alternately along the first direction.

249. The half-bridge power module according to claim 239, characterized in that, The second substrate has a second conductive metal layer. The second conductive metal layer includes a second DC positive electrode region, and the first DC positive electrode region is electrically connected to the second DC positive electrode region.

250. The half-bridge power module according to claim 249, characterized in that, The second conductive metal layer further includes a second DC negative electrode region, and the first DC negative electrode region is electrically connected to the second DC negative electrode region.

251. The half-bridge power module according to claim 250, characterized in that, The second conductive metal layer further includes a second AC region, and the first AC region is electrically connected to the second AC region.

252. The half-bridge power module according to claim 251, characterized in that, The AC terminal is located in the second AC area.

253. The half-bridge power module according to claim 252, characterized in that, The second half-bridge unit includes a second upper bridge chip group and a second lower bridge chip group. The second upper bridge chip group is located in the second DC positive region, and the second lower bridge chip group is located in the second AC region. Both the second upper bridge chip group and the second lower bridge chip group include a plurality of the silicon-based power chips.

254. The half-bridge power module according to claim 253, characterized in that, The second upper bridge chip group and the second lower bridge chip group are arranged along the second direction.

255. The half-bridge power module according to claim 254, characterized in that, Both the second upper bridge chip group and the second lower bridge chip group include a plurality of silicon-based power chips arranged along the first direction.

256. The half-bridge power module according to claim 253, characterized in that, Several silicon-based power chips in the second upper bridge chipset are connected to the first upper bridge chipset via a third connection line. In the second AC region, several silicon-based power chips in the second lower bridge chipset are connected to the second DC negative region via a fourth connection line.

257. The half-bridge power module according to claim 251, characterized in that, At least a portion of each of the second DC positive region, the second AC region, and the second DC negative region extends along the first direction and is arranged along the second direction.

258. The half-bridge power module according to claim 251, characterized in that, The first DC positive region and the second DC positive region are arranged opposite to each other along the first direction.

259. The half-bridge power module according to claim 251, characterized in that, The first DC negative region and the second DC negative region are arranged opposite to each other along the first direction.

260. The half-bridge power module according to claim 251, characterized in that, The first communication area and the second communication area are arranged opposite each other along the first direction.

261. The half-bridge power module according to claim 253, characterized in that, The second upper bridge chip group and the second lower bridge chip group also include a second type of diode, which is arranged along the first direction with the silicon-based power chip.

262. The half-bridge power module according to claim 261, characterized in that, The second type of diode in the second upper bridge chip group is connected in series with the second type of diode in the second lower bridge chip group, and the second type of diode is connected in parallel with the silicon-based power chip in the same chip group.

263. The half-bridge power module according to claim 261, characterized in that, The second type of diode uses the same substrate material as the silicon-based power chip.

264. The half-bridge power module according to claim 261, characterized in that, The second type of diode is a silicon substrate fast recovery diode.

265. The half-bridge power module according to claim 261, characterized in that, The second type of diode and the silicon-based power chip are arranged alternately along the first direction.

266. The half-bridge power module according to any one of claims 237-265, characterized in that, The wide bandgap power chip includes SiC MOSFETs, and the silicon-based power chip includes Si IGBTs.

267. The half-bridge power module according to claim 266, characterized in that, The first conductive metal layer further includes: The first SiC driving layer group includes: a first SiC gate driving layer and a first SiC source driving layer, wherein the gate of the SiC MOSFET of the first upper bridge chip group is electrically connected to the first SiC gate driving layer, and the source of the SiC MOSFET of the first upper bridge chip group is electrically connected to the first SiC source driving layer.

268. The half-bridge power module according to claim 267, characterized in that, The first conductive metal layer further includes: The second SiC driving layer group includes: a second SiC gate driving layer and a second SiC source driving layer. The gate of the SiC MOSFET of the first lower bridge chip group is electrically connected to the second SiC gate driving layer, and the source of the SiC MOSFET of the first lower bridge chip group is electrically connected to the second SiC source driving layer.

269. The half-bridge power module according to claim 266, characterized in that, The second conductive metal layer also includes: The first IGBT driving layer group includes: a first IGBT gate driving layer and a first IGBT emitter driving layer. The gate of the Si IGBT in the second upper bridge chip group is electrically connected to the first IGBT gate driving layer, and the emitter of the Si IGBT in the second upper bridge chip group is electrically connected to the first IGBT emitter driving layer.

270. The half-bridge power module according to claim 269, characterized in that, The second conductive metal layer further includes: The second IGBT driving layer group includes: a second IGBT gate driving layer and a second IGBT emitter driving layer, wherein the gate of the Si IGBT in the second lower bridge chip group is electrically connected to the second IGBT gate driving layer, and the emitter of the Si IGBT in the second lower bridge chip group is electrically connected to the second IGBT emitter driving layer.

271. The half-bridge power module according to claim 268, characterized in that, The base plate includes a first side and a second side opposite to each other along a second direction, and a third side and a fourth side opposite to each other along the first direction; The first SiC driving layer group is located on the side of the first DC positive electrode region facing the first side.

272. The half-bridge power module according to claim 271, characterized in that, The second SiC driving layer group is located on the side of the first DC negative electrode region facing the second side.

273. The half-bridge power module according to claim 270, characterized in that, The first IGBT drive layer group is located on the side of the second DC positive region facing the first side.

274. The half-bridge power module according to claim 273, characterized in that, The second IGBT drive layer group is located on the side of the second DC negative electrode region facing the second side.

275. The half-bridge power module according to claim 233, characterized in that, The wide bandgap power chip is connected to the first substrate using a first connection process, which is either a sintering process or a welding process.

276. The half-bridge power module according to claim 275, characterized in that, The silicon-based power chip is connected to the second substrate using a second connection process, which is either a sintering process or a welding process.

277. The half-bridge power module according to claim 276, characterized in that, One of the first connection process and the second connection process is a sintering process, and the other is a welding process.

278. The half-bridge power module according to claim 276, characterized in that, Both the first and second joining processes are sintering processes, or both the first and second joining processes are welding processes. Furthermore, the process parameters of the first connection process are different from those of the second connection process, and the process parameters include: process temperature and process duration.

279. A method for manufacturing a half-bridge power module, used to manufacture the half-bridge power module according to any one of claims 233-278, characterized in that, Includes the following steps: The wide-bandgap power chip is fixed to the first substrate, and the silicon-based power chip is fixed to the second substrate. The wide-bandgap power chip is bonded to the first substrate via interconnecting wires, and the silicon-based power chip is bonded to the second substrate via interconnecting wires. Electrical tests were performed on the first half-bridge unit formed by the wide bandgap power chip and the second half-bridge unit formed by the silicon-based power chip, respectively. The first substrate and the second substrate, which have passed the electrical test, are respectively fixed to the base plate; The first substrate and the second substrate are connected by a connecting line; Install housing and connection terminals.

280. The method for manufacturing a half-bridge power module according to claim 279, characterized in that, The steps of fixing the wide-bandgap power chip to the first substrate and fixing the silicon-based power chip to the second substrate include: The wide bandgap power chip is fixed to the first substrate using a first connection process, and the silicon-based power chip is fixed to the second substrate using a second connection process. The first connection process is one of sintering and welding. The second joining process is either sintering or welding.

281. The method for manufacturing a half-bridge power module according to claim 280, characterized in that, One of the first connection process and the second connection process is a sintering process, and the other is a welding process.

282. The method for manufacturing a half-bridge power module according to claim 280, characterized in that, Both the first and second joining processes are sintering processes, or both the first and second joining processes are welding processes. Furthermore, the process parameters of the first connection process are different from those of the second connection process, and the process parameters include: process temperature and process duration.

283. The method for manufacturing a half-bridge power module according to claim 279, characterized in that, The step of fixing the first substrate and the second substrate, which have passed the electrical test, to the base plate includes: Both the first substrate and the second substrate are soldered to the base plate.

284. A full-bridge power module, characterized in that, include: The half-bridge power module according to any one of claims 1-278, wherein there are three half-bridge power modules, the three half-bridge power modules are connected to the same heat dissipation base plate and form a three-phase full-bridge power module, and each half-bridge power module corresponds to one of the single phases.

285. An electrical appliance, characterized in that, The power module includes a half-bridge power module as described in any one of claims 1-278, and / or a full-bridge power module as described in claim 284.

286. A control circuit for a switch, characterized in that, The signal input terminal of the control circuit is used to receive modulation signals and control signals; The signal output terminal of the control circuit is connected to the switch. The control circuit is used to process the modulation signal based on the control signal and output a drive signal; wherein the drive signal is used to drive the switch.

287. The control circuit according to claim 286, characterized in that, The control circuit includes: A delay module, connected to the signal input terminal, is used to delay the modulation signal based on the control signal and output the drive signal.

288. The control circuit according to claim 287, characterized in that, The delay module includes: The charging and discharging module receives the modulation signal and responds to the modulation signal to charge and discharge, thereby changing its own output; A comparison module, connected to the charging / discharging module, is used to receive the control signal and output the drive signal based on the comparison result between the output of the charging / discharging module and the control signal.

289. The control circuit according to claim 288, characterized in that, The charging and discharging module includes: a first resistor and a first capacitor; One end of the first resistor receives the modulation signal, and the other end is connected to the non-inverting input of the comparison module and one end of the first capacitor; The other end of the first capacitor is grounded.

290. The control circuit according to claim 288, characterized in that, The control circuit also includes: The driving module is connected to the output terminal of the delay module and the switch, and is used to shape the driving signal and output the shaped driving signal.

291. The control circuit according to claim 290, characterized in that, The driving module includes: The second push-pull circuit, connected to the delay module, is used to adjust the amplitude of the drive signal.

292. The control circuit according to claim 290, characterized in that, The control circuit also includes: An isolation module, connected between the delay module and the switch, is used to electrically isolate signals on both sides of the isolation module.

293. The control circuit according to claim 290, characterized in that, The control circuit also includes: a Schmitt trigger, The input of the Schmitt trigger is connected to the delay module, and the output is connected to the drive module.

294. The control circuit according to claim 287, characterized in that, The control circuit also includes: The shaping module is connected to the input terminal of the delay module and receives the modulation signal. It is used to shape the modulation signal and output the shaped modulation signal to the delay module.

295. The control circuit according to claim 294, characterized in that, The shaping module includes: a first push-pull circuit. The input terminal of the first push-pull circuit receives the modulation signal, and the output terminal is connected to the input terminal of the delay module to adjust the amplitude of the modulation signal.

296. The control circuit according to claim 295, characterized in that, The first push-pull circuit includes: a first transistor, a second transistor, and a third resistor; One end of the first transistor receives a first reference voltage, and the other end of the first transistor is connected to one end of the second transistor and one end of the third resistor. The control terminal of the first transistor receives the modulation signal. The other end of the second transistor receives a second reference voltage, and the control terminal of the second transistor is connected to the control terminal of the first transistor; the other end of the third resistor is connected to the delay module.

297. The control circuit according to claim 292, characterized in that, The switch is a hybrid switch, which includes a first switch and a second switch; the control signal includes a first control signal and a second control signal. The control circuit is used to process the modulation signal based on the first control signal and the second control signal, and output the first driving signal and the second driving signal. Wherein, the first driving signal is used to drive the first switch, and the second driving signal is used to drive the second switch.

298. The control circuit according to claim 297, characterized in that, The signal input terminal includes a first input terminal, a second input terminal, and a third input terminal; The first input terminal is used to receive the first control signal, the second input terminal is used to receive the second control signal, and the third input terminal is used to receive the modulation signal.

299. The control circuit according to claim 298, characterized in that, The delay module includes: A first delay module is connected to the first input terminal and the third input terminal, and is used to delay the modulation signal based on the first control signal and output a first drive signal. The second delay module is connected to the second input terminal and the third input terminal, and is used to delay the modulation signal based on the second control signal and output the second drive signal.

300. The control circuit according to claim 299, characterized in that, The charging and discharging module includes: a first charging and discharging module and a second charging and discharging module; The first charging / discharging module and the second charging / discharging module are used to receive the modulation signal and charge / discharge in response to the modulation signal to change their own output.

301. The control circuit according to claim 300, characterized in that, The comparison module includes: A first comparison module, connected to the first charge / discharge module, is used to receive the first control signal and output the first drive signal based on the comparison result between the output of the first charge / discharge module and the first control signal. The second comparison module, connected to the second charge / discharge module, is used to receive the second control signal and output the second drive signal based on the comparison result between the output of the second charge / discharge module and the second control signal.

302. The control circuit according to claim 301, characterized in that, The first comparison module and / or the second comparison module include: The comparator has its non-inverting input connected to the charging / discharging module under the delay module, its inverting input receiving the corresponding control signal, and its output connected to the corresponding switch.

303. The control circuit according to claim 301, characterized in that, The charging rate and / or discharging rate of the first charging / discharging module are different from those of the second charging / discharging module.

304. The control circuit according to claim 303, characterized in that, The charging rate of the first charging / discharging module is greater than the charging rate of the second charging / discharging module.

305. The control circuit according to claim 304, characterized in that, The discharge rate of the first charge / discharge module is less than the discharge rate of the second charge / discharge module.

306. The control circuit according to claim 301, characterized in that, The first charging / discharging module and / or the second charging / discharging module include: a first resistor and a first capacitor; One end of the first resistor is connected to the third input terminal, and the other end is connected to the non-inverting input terminal of the comparison module under the delay module and one end of the first capacitor; The other end of the first capacitor is grounded.

307. The control circuit according to claim 306, characterized in that, The first charging and discharging module further includes: a first diode, The positive terminal of the first diode is connected to one end of the first resistor under the first charging and discharging module, and the negative terminal of the first diode is connected to one end of the first capacitor under the first charging and discharging module.

308. The control circuit according to claim 307, characterized in that, The second charge / discharge module also includes: a second diode, The negative terminal of the second diode is connected to one end of the first resistor under the second charging / discharging module, and the positive terminal of the second diode is connected to one end of the second capacitor.

309. The control circuit according to claim 299, characterized in that, The driving module includes a first driving module and a second driving module. The first driving module is connected to the first delay module and the first switch, and is used to shape the first driving signal and output the shaped first driving signal. The second driving module is connected to the second delay module and the second switch, and is used to shape the second driving signal and output the shaped second driving signal.

310. The control circuit according to claim 309, characterized in that, The isolation module includes a first isolation module and a second isolation module. The input terminal of the first isolation module is connected to the first delay module, and the output terminal is connected to the first drive module, which is used to electrically isolate the signals at the input and output terminals of the first isolation module. The input terminal of the second isolation module is connected to the second delay module, and the output terminal is connected to the second drive module, which is used to electrically isolate the signals at the input and output terminals of the second isolation module.

311. The control circuit according to claim 310, characterized in that, The first isolation module and / or the second isolation module include: Optocoupler U5, the primary input terminal of which is connected to the output terminal of the corresponding delay unit, and the primary output terminal is grounded; the secondary input terminal of optocoupler U5 is connected to the corresponding switch, and the secondary output terminal is grounded.

312. The control circuit according to any one of claims 286 to 311, characterized in that, The control circuit is integrated and fabricated on the substrate.

313. A switch module, characterized in that, include: The control circuit and switch as described in any one of claims 286-312.

314. The switching module according to claim 313, characterized in that, The switch is a hybrid switch, which includes a first switch and a second switch.

315. The switching module according to claim 314, characterized in that, The first switch is a wide bandgap semiconductor switch, and the second switch is a silicon-based switch.

316. A switching system, characterized in that, include: Controller, switch, and control circuit as described in any one of claims 1-311; The switch is connected to the output terminal of the control circuit; The controller is connected to the control circuit and is used to provide the modulation signal and control signal corresponding to the control circuit.

317. The switching system according to claim 316, characterized in that, The number of switches and control circuits are both multiple, and the multiple switches are connected to form a bridge circuit.

318. The switching system according to claim 317, characterized in that, The bridge circuit is a three-phase full-bridge circuit.

319. The switching system according to claim 318, characterized in that, Different switches correspond to different modulation signals, while different switches correspond to the same control signal. Alternatively, different switches correspond to different modulation signals, and switches under different phases correspond to different control signals.

320. A method for controlling a switch, characterized in that, The method includes: Receive modulation signals and control signals; The modulation signal is controlled based on the control signal to output a drive signal; The driving signal is used to drive the switch.

321. A method for driving a switch, characterized in that, Applied to the switching system as described in any one of claims 316 to 319, the method comprises: The controller acquires the signal parameters of the drive signal; the signal parameters characterize the timing of the drive signal; The controller outputs modulation signals and control signals according to the signal parameters.

322. The method according to claim 321, characterized in that, The switch is a hybrid switch, which includes a first switch and a second switch; the driving signal includes a first driving signal for driving the first switch and a second driving signal for driving the second switch. The rising flip time of the first driving signal is earlier than the rising flip time of the second driving signal, and the falling flip time of the first driving signal is later than the falling flip time of the second driving signal.

323. The method according to claim 322, characterized in that, The signal parameters include a turn-on delay parameter and a turn-off delay parameter. The turn-on delay parameter represents the duration between the rising and falling transition times of the first driving signal and the second driving signal, and the turn-off delay parameter represents the duration between the falling and falling transition times of the first driving signal and the second driving signal. The control signal includes a first control signal and a second control signal; The controller outputs a modulation signal and the control signal based on the signal parameters, including: The second control signal is adjusted according to the conduction delay parameter; the magnitude of the second control signal is positively correlated with the magnitude of the conduction delay parameter. The first control signal is adjusted according to the shutdown delay parameter; the magnitude of the first control signal is positively correlated with the magnitude of the shutdown delay parameter.

324. A method for driving a hybrid switch, characterized in that, The hybrid switch is applied in an inverter circuit, and the hybrid switch includes a first switch and a second switch; the method includes: The current value of the first current at the AC terminal of the hybrid switch is detected; The driving mode of the hybrid switch is changed according to the current value of the first current and the first switching current value; the switching loss ratio is different under different driving modes; wherein, the switching loss ratio under the driving mode is the ratio of the loss of the first switch and the loss of the second switch under the driving mode.

325. The method according to claim 324, characterized in that, The conduction duration and / or switching frequency of the first switch and the second switch are different under different driving modes, so that the loss ratio of the first switch and the second switch is different under different driving modes.

326. The method according to claim 325, characterized in that, The driving modes include a first driving mode and a second driving mode; The switching loss ratio in the first driving mode is greater than that in the second driving mode.

327. The method according to claim 326, characterized in that, The conduction duration and / or number of switching cycles of the first switch in the first driving mode are greater than the conduction duration and / or number of switching cycles of the first switch in the second driving mode. The conduction duration and / or number of switching cycles of the second switch in the first driving mode are less than the conduction duration and / or number of switching cycles of the second switch in the second driving mode.

328. The method according to claim 326, characterized in that, In the first driving mode, the loss ratio of the first switch to the second switch is greater than one; in the second driving mode, the loss ratio of the first switch to the second switch is less than one.

329. The method according to claim 328, characterized in that, In the first driving mode, the conduction duration and / or number of switching operations of the first switch are greater than those of the second switch. On-time duration and / or number of on / off cycles; In the second driving mode, the conduction duration and / or number of switching cycles of the first switch are less than the conduction duration and / or number of switching cycles of the second switch.

330. The method according to claim 329, characterized in that, Under the first driving mode, the first switch is turned on earlier than the second switch, and the first switch is turned off later than the second switch.

331. The method according to claim 329, characterized in that, Under the second driving mode, the first switch is turned on later than the second switch, the first switch is turned off later than the second switch, and the on-time of the first switch is less than the on-time of the second switch.

332. The method according to claim 326, characterized in that, The method further includes: Based on the switching current value corresponding to each mode group, the switching current value corresponding to the first mode group is obtained as the first switching current value; the first mode group includes the first driving mode and the second driving mode.

333. The method according to claim 332, characterized in that, The step of changing the driving mode of the hybrid switch based on the current value of the first current and the first switching current value includes: If the current value of the first current does not reach the first switching current value, then switch to the first driving mode; If the current value of the first current reaches the first switching current value, then switch to the second driving mode.

334. The method according to claim 332, characterized in that, The method further includes: Based on the limiting current value corresponding to each mode group, the first limiting current value corresponding to the first mode group is obtained; The amplitude of the first current is controlled to not exceed the first limit current value.

335. The method according to claim 334, characterized in that, If the amplitude of the first current is equal to the first limit current value, then both the first switch and the second switch will reach their respective limit temperatures.

336. The method according to claim 335, characterized in that, The method further includes: According to the first driving mode and the second driving mode, the hybrid switch is driven based on the switching current value, and the switching current value and the amplitude of the first current are adjusted until both the first switch and the second switch reach their own limit temperature. The amplitude of the current first current is used as the first limit current value, and the current switching current value is used as the first switching current value.

337. The method according to claim 336, characterized in that, The adjustment of the switching current value and the amplitude of the first current until both the first and second switches reach their own limit temperatures includes: Obtain the amplitude of the first current that causes the first switch to reach its own limit temperature under the first driving mode. According to the first driving mode and the second driving mode, the hybrid switch is driven based on the current switching current value, and the switching current value and the amplitude of the first current are adjusted according to the adjustment strategy until both the first switch and the second switch reach their own limit temperature. The adjustment strategy includes: if the first switch or the second switch reaches its own limit temperature, then keep the current amplitude of the first current unchanged and adjust the switching current value; if the temperature difference between the two switches is the limit temperature difference, then keep the current switching current value unchanged and adjust the amplitude of the first current; wherein the limit temperature difference is the difference between the limit temperature of the first switch and the limit temperature of the second switch.

338. The method according to claim 337, characterized in that, If the first switch or the second switch reaches its limit temperature, the current amplitude of the first current is kept constant, and the switching current value is adjusted, including: If the first switch reaches its own limit temperature, then keep the current amplitude of the first current unchanged and reduce the switching current value. If the second switch reaches its own limit temperature, the amplitude of the first current remains unchanged, and the switching current value is increased.

339. The method according to claim 337, characterized in that, The step of obtaining the amplitude of the first current that causes the first switch to reach its limit temperature under the first driving mode includes: Set the switching current value to be equal to the current amplitude of the first current; Increase the amplitude of the first current until the first switch reaches its limit temperature.

340. The method according to any one of claims 324-339, characterized in that, The first switch is a wide bandgap semiconductor switch, and the second switch is a silicon-based switch.

341. The method according to any one of claims 324-339, characterized in that, The inverter circuit is a half-bridge circuit.

342. A driving device for a hybrid switch, characterized in that, The hybrid switch includes a first switch and a second switch; the device includes: The detection module is used to detect the current value of the first current at the AC terminal of the hybrid switch; The processing module is used to change the driving mode of the hybrid switch according to the current value of the first current and the first switching current value; the switching loss ratio is different under different driving modes; wherein, the switching loss ratio under the driving mode is the ratio of the loss of the first switch and the loss of the second switch under the driving mode.

345. A control circuit for a hybrid switch, characterized in that, A driving method for performing a hybrid switch as described in any one of claims 324-341.

346. A hybrid switching system, characterized in that, include: A hybrid switch and the control circuit as described in claim 345.

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