A control device and control method of bootstrap driving

Abstract

The application provides a bootstrap driving control device and a control method. The device comprises a full-bridge circuit and a bootstrap driving circuit. The full-bridge circuit comprises first to fourth MOS transistors and first to fourth diodes. The bootstrap driving circuit comprises a bootstrap driving module, first and second bootstrap capacitors and a fifth diode. The bootstrap driving module is used to load the voltage of the first and second bootstrap capacitors to the gate of the second MOS transistor when the first MOS transistor changes from on to off and the fourth MOS transistor changes from on to off, and is also used to load the first power supply voltage and the voltage of the first bootstrap capacitor to the gate of the first MOS transistor when the second MOS transistor changes from on to off and the third MOS transistor changes from on to off. The bootstrap driving circuit is used to control the third and fourth MOS transistors to be continuously turned on in the respective working half cycles, so as to realize sufficient charging of the bootstrap capacitors, and to realize smooth turning on of the first and second MOS transistors when the full-bridge circuit enters a light load mode.

Description

Technical Field

[0001] This application relates to the field of electronic power technology, and in particular to a bootstrap-driven control device and control method. Background Technology

[0002] LLC boost circuits are a commonly used circuit structure in this field, such as... Figure 1 As shown. In the primary side of an LLC boost converter, either a half-bridge or a full-bridge structure can be used. For example... Figure 1 The MOS transistors PWM2A, PWM2B, PWM32A, and PWM3B shown constitute a full-bridge structure.

[0003] For a MOS transistor to conduct, its gate voltage must be greater than its threshold voltage (Vth). Figure 1 In the primary-side full-bridge circuit of the LLC boost circuit shown, for the upper transistor, namely the upper MOS transistors PWM2A and PWM3B, in order to turn it on, its gate voltage needs to be greater than the sum of its drain voltage and threshold voltage.

[0004] To meet the requirements for power-on of the upper tube, existing technologies use a bootstrap circuit. Figure 2 This describes the application of turning on the upper transistor in a typical existing bootstrap circuit. For ease of explanation, in... Figure 2 The diagram shows a half-bridge structure; the full-bridge structure is similar. The drive module controls the successive on / off states of MOS transistors M1 and M2. To enable the conduction of M1, a bootstrap capacitor C is required. VCC is applied to the gate of M1 via the drive module during the transition of M2 from on to off. VCC is actually the drain voltage of M1. As mentioned earlier, for M1 to conduct, its gate voltage must be greater than the sum of its drain voltage and threshold voltage (Vth), i.e., M1's gate voltage Vgm1 > VCC + Vth. Figure 2 In the circuit diagram, when M1 is off and M2 is on, the drain and source of M2 act as a single wire. At this time, VDD forms a loop through diode D, bootstrap capacitor C, M2, and ground, charging the bootstrap capacitor C. When M1 needs to change from off to on, M2 is off, and the drive circuit applies VCC to the gate of M1. Because M2 is off, the bootstrap capacitor C discharges, causing diode D to reverse-biased and cut off. The voltage discharged by the bootstrap capacitor C is also applied to the gate of M1 through the drive circuit, resulting in a voltage of VCC + V on the gate of M1. 自举电容 As long as V 自举电容 If the voltage is greater than the threshold voltage Vth, M1 will be turned on.

[0005] Therefore, the voltage across the bootstrap capacitor C determines whether M1 can conduct. If the bootstrap capacitor C is not sufficiently charged, M1 may not be able to conduct. In the primary circuit of the LLC, as shown... Figure 3 When entering light-load mode, the gain characteristics must allow the LLC primary-side circuit to enter a small duty cycle mode, meaning it drives for a period of time and then stops for a period of time. This type of drive, due to its small duty cycle, for example... Figure 3 In the process, the conduction time of M2 is the same as that of M1. Within one cycle, the conduction time of M2 is very short, and it may even be without drive for a long time. During the conduction period of M2, the time for VDD to charge the bootstrap capacitor C through diode D is also very short, resulting in insufficient charge of bootstrap capacitor C. Therefore, when the upper transistor M1 is turned on again, it will not be able to conduct due to insufficient voltage applied to the gate. Summary of the Invention

[0006] To address the problem of insufficient charging capacity of bootstrap capacitors in existing technologies, this application provides a control device and method for bootstrap driving. This application provides a control device for bootstrap driving, comprising:

[0007] A full-bridge circuit and a bootstrap driving circuit are provided. The full-bridge circuit includes a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The source of the first MOS transistor Q1 and the drain of the third MOS transistor Q3 are connected together to form the first bridge arm A of the full-bridge circuit. The source of the second MOS transistor Q2 and the drain of the fourth MOS transistor Q4 are connected together to form the second bridge arm B of the full-bridge circuit. A load is connected between the first bridge arm A and the second bridge arm B. The drain of the first MOS transistor Q1 and the drain of the second MOS transistor Q2 are connected together and connected to the first power supply voltage VCC. The drain of the third MOS transistor Q3 and the drain of the fourth MOS transistor Q4 are connected together and grounded. The two ends of the full-bridge capacitor (C10) are connected between the first power supply voltage VCC and ground.

[0008] The bootstrap driving circuit includes a bootstrap driving module 10, a first bootstrap capacitor C1, a second bootstrap capacitor C2, and a fifth diode D5. The first terminal of the first bootstrap capacitor C1, the first terminal of the second bootstrap capacitor C2, and the bootstrap driving module 10 are connected together and to the cathode of the fifth diode; the anode of the fifth diode D5 is connected to the first power supply voltage VCC; the second terminal of the first bootstrap capacitor C1 is connected to the source of the first MOS transistor Q1 and serves as the first bridge arm A; the second terminal of the second bootstrap capacitor C2 is connected to the source of the second MOS transistor Q2 and serves as the second bridge arm B.

[0009] The bootstrap driving module 10 is used to apply the first power supply voltage VCC and the voltage V2 of the second bootstrap capacitor C2 to the gate of the second MOS transistor Q2 when the first MOS transistor Q1 changes from being on to being off and the fourth MOS transistor Q4 changes from being on to being off. The bootstrap driving module 10 is also used to apply the first power supply voltage VCC and the voltage V1 of the first bootstrap capacitor C1 to the gate of the first MOS transistor Q1 when the second MOS transistor Q2 changes from being on to being off and the third MOS transistor Q3 changes from being on to being off.

[0010] Optionally, the bootstrap driving module 10 includes a first driving transistor T1, a second driving transistor T2, a third driving transistor T3, a fourth driving transistor T4, and a resistor R. The gates of the first driving transistor T1, the second driving transistor T2, the third driving transistor T3, and the fourth driving transistor T4 are respectively connected to the first driving signal IN1, the second driving signal IN2, the third driving signal IN3, and the fourth driving signal IN4. The drain and source of the first driving transistor T1 are respectively connected to the first power supply voltage VCC and ground, and the gate of the first MOS transistor Q1 is connected to the source of the first driving transistor T1. The drain and source of the second driving transistor T2 are respectively connected to the first power supply voltage VCC and ground, and the gate of the second MOS transistor Q2 is connected to the second driving transistor T1. The source of transistor T2 is connected; the drain and source of the third driving transistor T3 are connected to the first power supply voltage VCC and ground, respectively, and the gate of the third MOS transistor Q3 is connected to the source of the third driving transistor T3; the drain and source of the fourth driving transistor T4 are connected to the first power supply voltage VCC and ground, respectively, and the gate of the fourth MOS transistor Q4 is connected to the source of the fourth driving transistor T4; the first end of resistor R is connected to the first end of the first bootstrap capacitor C1 and the first end of the second bootstrap capacitor C2, and the second end of resistor R is connected to the drain of the first driving transistor T1 and the drain of the second driving transistor T2.

[0011] This application also provides a control method for a bootstrap driven control device, comprising the following steps:

[0012] Step 1: During the first half of a complete working cycle of the full-bridge circuit, the bootstrap driving circuit sets the second MOS transistor Q2 and the third MOS transistor Q3 to the off state; during the time period from the first time point to the second time point, which is the starting time point of the first half of the cycle, the bootstrap driving circuit sets the first MOS transistor Q1 to the on state; and during the entire first half of the cycle, the bootstrap driving circuit sets the fourth MOS transistor Q4 to the on state.

[0013] Step 2: During the second half of a complete working cycle of the full-bridge circuit, the bootstrap driving circuit sets the first MOS transistor Q1 and the fourth MOS transistor Q4 to the off state; during the period from the third time point to the fourth time point, which is the starting time point of the second half of the cycle, the bootstrap driving circuit sets the second MOS transistor Q2 to the on state; and during the entire second half of the cycle, the bootstrap driving circuit sets the third MOS transistor Q3 to the on state.

[0014] Preferably, during the first half of a complete operating cycle of the full-bridge circuit, the second drive signal IN2 and the third drive signal IN3 in the bootstrap drive circuit are set to low level, thereby turning off the second MOS transistor Q2 and the third MOS transistor Q3; during the time period from the first time point to the second time point, which is the starting time point in the first half of the cycle, the first drive signal IN1 is set to high level; and during the entire first half of the cycle, the fourth drive signal IN4 is set to high level.

[0015] Preferably, during the second half of a complete operating cycle of the full-bridge circuit, the first drive signal IN1 and the fourth drive signal IN4 in the bootstrap drive circuit are set to low level, thereby turning off the first MOS transistor Q1 and the fourth MOS transistor Q4; during the time period from the third time point to the fourth time point, which is the starting time point of the second half of the cycle, the second drive signal IN2 is set to high level; and during the entire second half of the cycle, the third drive signal IN3 is set to high level. Attached Figure Description

[0016] Figure 1 This is a circuit diagram of an LLC boost circuit.

[0017] Figure 2 This is the schematic diagram of an existing bootstrap driver circuit.

[0018] Figure 3 This is a timing diagram of an existing bootstrap driver circuit.

[0019] Figure 4 This is a circuit diagram of the bootstrap-driven control device of the present invention.

[0020] Figure 5 This is a preferred circuit diagram of the bootstrap-driven control device of the present invention.

[0021] Figure 6 This is a timing diagram of the bootstrap-driven control device of the present invention. Detailed Implementation

[0022] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0023] This invention proposes a bootstrap driven control device, see [link to relevant documentation]. Figure 4 The circuit includes a full-bridge circuit and a bootstrap driving circuit. The full-bridge circuit includes a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The source of the first MOS transistor Q1 and the drain of the third MOS transistor Q3 are connected together to form the first bridge arm A of the full-bridge circuit. The source of the second MOS transistor Q2 and the drain of the fourth MOS transistor Q4 are connected together to form the second bridge arm B of the full-bridge circuit. A load is connected between the first bridge arm A and the second bridge arm B. The drain of the first MOS transistor Q1 and the drain of the second MOS transistor Q2 are connected together and connected to the first power supply voltage VCC. The drain of the third MOS transistor Q3 and the drain of the fourth MOS transistor Q4 are connected together and grounded. The two ends of the full-bridge capacitor (C10) are connected between the first power supply voltage VCC and ground.

[0024] The bootstrap driving circuit includes a bootstrap driving module 10, a first bootstrap capacitor C1, a second bootstrap capacitor C2, and a fifth diode D5. The first terminal of the first bootstrap capacitor C1, the first terminal of the second bootstrap capacitor C2, and the bootstrap driving module 10 are connected and connected to the negative terminal of the fifth diode; the positive terminal of the fifth diode D5 is connected to the second power supply voltage VDD; the second terminal of the first bootstrap capacitor C1 is connected to the source of the first MOS transistor Q1 and serves as the first bridge arm A; the second terminal of the second bootstrap capacitor C2 is connected to the source of the second MOS transistor Q2 and serves as the second bridge arm B.

[0025] The bootstrap driving module 10 is used to apply the first power supply voltage VCC and the voltage V2 of the second bootstrap capacitor C2 to the gate of the second MOS transistor Q2 when the first MOS transistor Q1 changes from being on to being off and the fourth MOS transistor Q4 changes from being on to being off. The bootstrap driving module 10 is also used to apply the first power supply voltage VCC and the voltage V1 of the first bootstrap capacitor C1 to the gate of the first MOS transistor Q1 when the second MOS transistor Q2 changes from being on to being off and the third MOS transistor Q3 changes from being on to being off.

[0026] Optional, see Figure 5The bootstrap driving module 10 includes a first driving transistor T1, a second driving transistor T2, a third driving transistor T3, a fourth driving transistor T4, and a resistor R. The gates of the first driving transistor T1, the second driving transistor T2, the third driving transistor T3, and the fourth driving transistor T4 are respectively connected to the first driving signal IN1, the second driving signal IN2, the third driving signal IN3, and the fourth driving signal IN4. The drain and source of the first driving transistor T1 are respectively connected to the first power supply voltage VCC and ground, and the gate of the first MOS transistor Q1 is connected to the source of the first driving transistor T1. The drain and source of the second driving transistor T2 are respectively connected to the first power supply voltage VCC and ground, and the gate of the second MOS transistor Q2 is connected to the second driving transistor T4. The source of transistor T2 is connected; the drain and source of the third driving transistor T3 are connected to the first power supply voltage VCC and ground, respectively, and the gate of the third MOS transistor Q3 is connected to the source of the third driving transistor T3; the drain and source of the fourth driving transistor T4 are connected to the first power supply voltage VCC and ground, respectively, and the gate of the fourth MOS transistor Q4 is connected to the source of the fourth driving transistor T4; the first end of resistor R is connected to the first end of the first bootstrap capacitor C1 and the first end of the second bootstrap capacitor C2, and the second end of resistor R is connected to the drain of the first driving transistor T1 and the drain of the second driving transistor T2.

[0027] This application also provides a control method for a bootstrap driven control device, see [link to relevant documentation]. Figure 4 and 6 This includes the following steps:

[0028] Step 1: During the first half of a complete operating cycle t1 to t5 of the full-bridge circuit, from t1 to t3, the bootstrap driving circuit sets the second MOS transistor Q2 and the third MOS transistor Q3 to the off state; during the time period from the first time point t1 to the second time point t2 within this first half-cycle, the bootstrap driving circuit sets the first MOS transistor Q1 to the on state; and during the entire first half-cycle t1 to t3, the bootstrap driving circuit sets the fourth MOS transistor Q4 to the on state; Figure 6 As can be seen, during the time period t1 to t2 of the first half-cycle, the first MOS transistor Q1 and the fourth MOS transistor Q4 are turned on, and the second power supply voltage VDD forms a loop with ground through the fifth diode D5, the second bootstrap capacitor C2, the second bridge arm B, the fourth MOS transistor Q4, and the second power supply voltage VDD charges the second bootstrap capacitor C2; during the time period t2 to t3 of the first half-cycle, the first MOS transistor Q1 is turned off, the fourth MOS transistor Q4 is still turned on, and the second power supply voltage VDD continues to charge the second bootstrap capacitor C2.

[0029] Step Two: During the second half of a complete operating cycle of the full-bridge circuit, from t3 to t5, the bootstrap driving circuit sets the first MOS transistor Q1 and the fourth MOS transistor Q4 to the off state. During the time period from the third time point t3 to the fourth time point t4, which serves as the starting point of this second half-cycle, the bootstrap driving circuit sets the second MOS transistor Q2 to the on state. Throughout the entire second half-cycle from t3 to t5, the bootstrap driving circuit sets the third MOS transistor Q3 to the on state. See also... Figure 6 When the second half of the cycle arrives, i.e., at time t3, the first MOS transistor Q1 and the fourth MOS transistor Q4 are turned off. The second bootstrap capacitor C2 loads the second voltage V2 onto the gate of the second MOS transistor Q2 through the bootstrap driving module 10. At the same time, the fifth diode D5 is reverse-biased and cut off, and the second power supply voltage VDD is disconnected from the bootstrap driving module 10. Moreover, the bootstrap driving module 10 also loads the first power supply voltage VCC onto the gate of the second MOS transistor Q2. At this time, the voltage VgQ2 loaded on the gate of the second MOS transistor Q2 is the sum of the first power supply voltage VCC (which is also the drain voltage VdQ2 of the second MOS transistor Q2) and the voltage V2 of the second bootstrap capacitor C2, i.e., VgQ1 = VCC + V2. As long as the charging time of the second bootstrap capacitor C2 is long enough, so that V2 > VthQ2, then VCC + V2 > VdQ2 + VthQ2 can be achieved, thereby turning on the turned-off second MOS transistor Q2.

[0030] See also Figure 6 During the second half-cycle, from t3 to t4, the second MOS transistor Q2 and the third MOS transistor Q3 are turned on. The second power supply voltage VDD forms a loop with ground through the fifth diode D5, the first bootstrap capacitor C1, the first bridge arm A, and the third MOS transistor Q3. The second power supply voltage VDD charges the first bootstrap capacitor C1. During the second half-cycle, from t4 to t5, the second MOS transistor Q2 is turned off, while the third MOS transistor Q3 remains turned on. The second power supply voltage VDD continues to charge the first bootstrap capacitor C1.

[0031] When the next complete cycle arrives, i.e. at time t5, the second MOS transistor Q2 and the third MOS transistor Q3 are turned off. The first bootstrap capacitor C1 loads the first voltage V1 onto the gate of the first MOS transistor Q1 through the bootstrap driving module 10. At the same time, the fifth diode D5 is reverse-biased and turned off. The second power supply voltage VDD is disconnected from the bootstrap driving module 10. Moreover, the bootstrap driving module 10 also loads the first power supply voltage VCC onto the gate of the first MOS transistor Q1. Similar to the previous description, the combined loading of the first voltage V1 and the first power supply voltage VCC makes the gate voltage of the first MOS transistor Q1 greater than the sum of its drain voltage and threshold voltage, thereby turning the turned-off first MOS transistor Q1 back on.

[0032] As a preferred embodiment of the present invention, see [link to previous document]. Figure 5 and 6 During the first half of a complete operating cycle of the full-bridge circuit, from t1 to t3, the second drive signal IN2 and the third drive signal IN3 in the bootstrap drive circuit are set to low level, thereby turning off the second MOS transistor Q2 and the third MOS transistor Q3. During the time period from the first time point t1 to the second time point t2 within this first half-cycle, the first drive signal IN1 is set to high level. Throughout the entire first half-cycle from t1 to t3, the fourth drive signal IN4 is set to high level. For details, see [link to relevant documentation]. Figure 5 and 6 At time t1, the first drive signal IN1 and the fourth drive signal IN4 are at high level. At this time, the first drive transistor T1 and the fourth drive transistor T4 are turned on. The voltage applied to the gate of the first MOS transistor Q1 and the gate of the fourth MOS transistor Q4 is the sum of the first power supply voltage VCC, the voltage of the first bootstrap capacitor C1, and the voltage of the second bootstrap capacitor C2. This sum of voltages triggers the first MOS transistor Q1 and the fourth MOS transistor Q4 to turn on. During the time interval t2-t3, the first drive signal IN1 is at low level and is turned off, causing the gate voltage of the first MOS transistor Q1 to drop to 0. The first MOS transistor Q1 changes from being turned on to being turned off. The fourth drive signal IN4 is still at high level, thereby maintaining the fourth drive transistor T4 on, and further maintaining the fourth MOS transistor Q4 in the on state. The second power supply voltage VDD forms a loop through the fifth diode D5, the second bootstrap capacitor C2, the second bridge arm B, the fourth MOS transistor Q4, and ground, thereby charging the second bootstrap capacitor C2.

[0033] During the second half of a full-bridge circuit's operating cycle, from t3 to t5, the first drive signal IN1 and the fourth drive signal IN4 in the bootstrap drive circuit are set to low level, thereby turning off the first MOS transistor Q1 and the fourth MOS transistor Q4. During the period from the third time point t3 to the fourth time point t4, which is the starting time point of this second half of the cycle, the second drive signal IN2 is set to high level. During the entire second half of the cycle, from t3 to t5, the third drive signal IN3 is set to high level. Specifically, at time t3, the fourth drive signal IN4 changes from high to low and is cut off, causing the gate voltage of the fourth MOS transistor Q4 to become 0 and be cut off, and the second bootstrap capacitor C2 stops charging; at this time, the second drive signal IN2 and the third drive signal IN3 change from low to high, and the second drive transistor T2 and the third drive transistor T3 are turned on; the voltage of the second bootstrap capacitor C2 is applied to the gate of the second MOS transistor Q2, and at the same time, the first power supply voltage VCC and the second power supply voltage VDD are also applied to the gate of the second MOS transistor Q2. The superposition of the voltages applied to the gate of the second MOS transistor Q2 triggers the second MOS transistor Q2 to turn on; similarly, the third MOS transistor Q3 is also turned on; during the time period from t3 to t4, on the one hand, the full-bridge circuit, due to the diagonal setting The second MOS transistor Q2 and the third MOS transistor Q3 are turned on and operate normally. On the other hand, the turn-on of the third MOS transistor Q3 causes the second power supply voltage VDD to form a loop through the fifth diode D5, the first bootstrap capacitor C1, the first bridge arm A, the third MOS transistor Q3 and ground, thereby charging the first bootstrap capacitor C1. During the time period from t4 to t5, the second drive signal IN2 is low, causing the second drive transistor T2 to be turned off, which in turn causes the second MOS transistor Q2 to be turned off. However, since the third drive signal IN3 is still high, the third MOS transistor Q3 remains on, thereby continuing to charge the first bootstrap capacitor C1. Thus, at time t5, similar to the previous process, the first MOS transistor Q1 and the fourth MOS transistor Q4 are turned on, and the next working cycle begins.

[0034] Thus, this invention utilizes a bootstrap drive circuit, which solves the problem of insufficient capacitor charge in the bootstrap drive circuit preventing the upper transistor from conducting when the full-bridge circuit enters a light-load mode by continuously conducting the lower transistor.

[0035] The technical solution of the present invention has been described above. All substitutions that do not depart from the essence of the technical solution of the present invention should be within the scope of the claims of the present invention.

Claims

1. A control device of a bootstrap drive, characterized by comprising: The application relates to a self-boosting driving control device of a full-bridge circuit. The full-bridge circuit comprises a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4; the source of the first MOS transistor Q1 is connected with the drain of the third MOS transistor Q3 and serves as a first bridge arm A of the full-bridge circuit; the source of the second MOS transistor Q2 is connected with the drain of the fourth MOS transistor Q4 and serves as a second bridge arm B of the full-bridge circuit; a load is connected between the first bridge arm A and the second bridge arm B; the drain of the first MOS transistor Q1 is connected with the drain of the second MOS transistor Q2 and connected with a first power supply voltage VCC; the drain of the third MOS transistor Q3 is connected with the drain of the fourth MOS transistor Q4 and connected with the ground; and the full-bridge capacitor (C10) is connected between the first power supply voltage VCC and the ground. The self-boosting driving circuit comprises a self-boosting driving module 10, a first self-boosting capacitor C1, a second self-boosting capacitor C2 and a fifth diode D5; the first end of the first self-boosting capacitor C1, the first end of the second self-boosting capacitor C2 and the self-boosting driving module 10 are connected and connected with the negative electrode of the fifth diode; the positive electrode of the fifth diode D5 is connected with a second power supply voltage VDD; the second end of the first self-boosting capacitor C1 is connected with the source of the first MOS transistor Q1 and serves as the first bridge arm A; and the second end of the second self-boosting capacitor C2 is connected with the source of the second MOS transistor Q2 and serves as the second bridge arm B. In the upper half cycle of a complete working cycle of the full-bridge circuit, the self-boosting driving circuit sets the fourth MOS transistor Q4 to be in a conducting state; and in the whole lower half cycle, the self-boosting driving circuit sets the third MOS transistor Q3 to be in a conducting state, so that the self-boosting capacitor is fully charged.

2. The self-boosting driving control device according to claim 1, wherein the self-boosting driving module 10 is used for loading the first power supply voltage VCC and the voltage V2 of the second self-boosting capacitor C2 to the gate of the second MOS transistor Q2 when the first MOS transistor Q1 changes from being in a conducting state to being in a cut-off state and the fourth MOS transistor Q4 changes from being in a conducting state to being in a cut-off state; and the self-boosting driving module 10 is further used for loading the first power supply voltage VCC and the voltage V1 of the first self-boosting capacitor C1 to the gate of the first MOS transistor Q1 when the second MOS transistor Q2 changes from being in a conducting state to being in a cut-off state and the third MOS transistor Q3 changes from being in a conducting state to being in a cut-off state.

3. The self-boosting driving control device according to claim 2, wherein ​ ​ The bootstrap drive module 10 comprises a first drive transistor T1, a second drive transistor T2, a third drive transistor T3, a fourth drive transistor T4 and a resistor R; wherein the gates of the first drive transistor T1, the second drive transistor T2, the third drive transistor T3 and the fourth drive transistor T4 are connected to a first drive signal IN1, a second drive signal IN2, a third drive signal IN3 and a fourth drive signal IN4 respectively; the drain and source of the first drive transistor T1 are connected to a first power supply voltage VCC and ground respectively, and the gate of a first MOS transistor Q1 is connected to the source of the first drive transistor T1; the drain and source of the second drive transistor T2 are connected to the first power supply voltage VCC and ground respectively, and the gate of a second MOS transistor Q2 is connected to the source of the second drive transistor T2; the drain and source of the third drive transistor T3 are connected to the first power supply voltage VCC and ground respectively, and the gate of a third MOS transistor Q3 is connected to the source of the third drive transistor T3; the drain and source of the fourth drive transistor T4 are connected to the first power supply voltage VCC and ground respectively, and the gate of a fourth MOS transistor Q4 is connected to the source of the fourth drive transistor T4; the first end of the resistor R is connected to the first end of a first bootstrap capacitor C1 and the first end of a second bootstrap capacitor C2, and the second end of the resistor R is connected to the drain of the first drive transistor T1 and the drain of the second drive transistor T2.

4. A control method of a control device of a bootstrap drive, characterized by, The control method comprises the following steps: Step one: in the upper half cycle of a complete working cycle of the full-bridge circuit, the bootstrap drive circuit sets the second MOS transistor Q2 and the third MOS transistor Q3 to be in the off state; in the time period from a first time point to a second time point as a starting time point in the upper half cycle, the bootstrap drive circuit sets the first MOS transistor Q1 to be in the on state, and in the entire upper half cycle, the bootstrap drive circuit sets the fourth MOS transistor Q4 to be in the on state; Step two: in the lower half cycle of a complete working cycle of the full-bridge circuit, the bootstrap drive circuit sets the first MOS transistor Q1 and the fourth MOS transistor Q4 to be in the off state; in the time period from a third time point to a fourth time point as a starting time point in the lower half cycle, the bootstrap drive circuit sets the second MOS transistor Q2 to be in the on state, and in the entire lower half cycle, the bootstrap drive circuit sets the third MOS transistor Q3 to be in the on state.

5. The control method of the control device of the bootstrap drive according to claim 4, characterized by, In the upper half cycle of a complete working cycle of the full-bridge circuit, the second drive signal IN2 and the third drive signal IN3 in the bootstrap drive circuit are set to be low, so that the second MOS transistor Q2 and the third MOS transistor Q3 are turned off; in the time period from a first time point to a second time point as a starting time point in the upper half cycle, the first drive signal IN1 is set to be high; in the entire upper half cycle, the fourth drive signal IN4 is set to be high.

6. The control method of the control device of the bootstrap drive according to claim 4, characterized by, In the second half cycle of a complete working cycle of the full-bridge circuit, the first drive signal IN1 and the fourth drive signal IN4 in the bootstrap drive circuit are set to low level, so that the first MOS transistor Q1 and the fourth MOS transistor Q4 are turned off; in the time period from the third time point to the fourth time point as the starting time point in the second half cycle, the second drive signal IN2 is set to high level; and in the whole second half cycle, the third drive signal IN3 is set to high level.

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