Memory access management method and apparatus, and electronic device

Abstract

The present application provides a memory access management method and apparatus, and an electronic device. The method provided by the present application comprises: on the basis of a memory access request or a read / write request received in a current clock cycle, counting the total number of memory blocks that need to be accessed in the current clock cycle; determining an access increment on the basis of the total number and an average value of the number of memory blocks that need to be accessed in a preset number of historical clock cycles; when the access increment is greater than a preset threshold, executing a preheating process, the preheating process comprising: taking the average value as an initial value of the number of memory blocks that need to be accessed, and increasing the number of memory blocks that need to be accessed step by step according to a preset increasing rule, until the number of increased memory blocks is greater than or equal to the total number, so as to gradually increase access intensity, causing an on-chip storage unit to complete the preheating process and enter a stable state. The memory access management method and apparatus, and the electronic device, provided in the present application can enable on-chip memory to smoothly transition to a high-load state.

Description

A memory access management method, apparatus, and electronic device Technical Field

[0001] This application claims priority to Chinese Patent Application No. 202411203375.8, filed on August 28, 2024, entitled "A Memory Access Management Method, Apparatus and Electronic Device", the entire contents of which are incorporated herein by reference.

[0002] This application relates to the field of on-chip storage technology, and in particular to a memory access management method, apparatus and electronic device. Background Technology

[0003] With the continuous advancement of integrated circuit technology, on-chip memory (SRAM) and DRAM are becoming increasingly common in modern microprocessors and system-on-chip (SoC) devices. In high-performance computing and large-scale data processing systems, the memory access load of on-chip memory units often increases suddenly, leading to system instability. Technical issues

[0004] This application provides a memory access management method, apparatus, and electronic device to enable on-chip storage units to smoothly transition to high-load states, avoiding bottlenecks or jitter caused by sudden large-scale accesses and maintaining stability.

[0005] Specifically, this application is implemented through the following technical solution:

[0006] The first aspect of this application provides a memory access management method, the method comprising:

[0007] Based on the memory access requests or read / write requests received in the current clock cycle, calculate the total number of memory blocks that need to be accessed in the current clock cycle.

[0008] The access increment corresponding to the current clock cycle is determined based on the total number and the average number of memory blocks that need to be accessed in a preset number of historical clock cycles.

[0009] When the access increment is greater than a preset threshold, a warm-up process is executed; wherein, the warm-up process includes: taking the average value as the initial value of the number of memory blocks to be accessed, increasing the number of memory blocks to be accessed step by step according to a preset increment rule, until the number of memory blocks after the increase is greater than or equal to the total number, so as to gradually increase the access intensity, so that the on-chip storage unit completes the warm-up process and enters a stable state.

[0010] A second aspect of this application provides a memory access management device, the device comprising a counting module, a register group, a comparison unit, and a controller; wherein...

[0011] The counting module is used to count the total number of memory blocks that need to be accessed in the current clock cycle based on the memory access requests received in the current clock cycle.

[0012] The register group is used to store the number of memory blocks that need to be accessed in historical clock cycles;

[0013] The comparison unit is used to determine the access increment corresponding to the current clock cycle based on the total number and the average number of memory blocks that need to be accessed in a preset number of historical clock cycles.

[0014] The controller is equipped with a state machine; the controller is used to control the state machine to enter a preheating state when the access increment is greater than the preset threshold; wherein, the controller executes a preheating process in the preheating state; the preheating process includes: taking the average value as the initial value of the number of memory blocks to be accessed, and gradually increasing the number of memory blocks to be accessed according to a preset increment rule until the number of memory blocks after the increase is greater than or equal to the total number, so as to gradually increase the access intensity, so that the on-chip storage unit completes the preheating process and enters a stable state.

[0015] A third aspect of this application provides an electronic device, which includes any of the memory access management devices provided in the second aspect of this application.

[0016] The memory access management method, apparatus, and electronic device provided in this application determine the access increment corresponding to the current clock cycle by statistically analyzing the total number of memory blocks that need to be accessed in the current clock cycle and the average number of memory blocks that need to be accessed in a preset number of historical clock cycles. When the access increment is greater than a preset threshold, a warm-up process is initiated. In the warm-up process, by gradually increasing the number of memory blocks that need to be accessed, rather than by a sudden large number of accesses, the on-chip storage unit can transition to a high-load state more smoothly, thereby avoiding bottlenecks or jitter caused by a sudden large number of accesses and maintaining stability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 is a flowchart of a first embodiment of the memory access management method provided in this application;

[0019] Figure 2 is a flowchart of Embodiment 2 of the memory access management method provided in this application;

[0020] Figure 3 is a flowchart of a third embodiment of the memory access management method provided in this application;

[0021] Figure 4 is a structural schematic diagram of a first embodiment of the memory access management device provided in this application;

[0022] Figure 5 is a schematic diagram of the state transition of a state machine according to an exemplary embodiment of this application;

[0023] Figure 6 is a schematic diagram of a memory access management device illustrated in an exemplary embodiment of this application;

[0024] Figure 7 is a structural schematic diagram of Embodiment 2 of the memory access management device provided in this application;

[0025] Figure 8 is a schematic diagram of a merging unit shown in an exemplary embodiment of this application;

[0026] Figure 9 is a schematic diagram of an electronic device illustrated in an exemplary embodiment of this application. Embodiments of the present invention

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0028] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0029] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0030] The following specific embodiments are given to illustrate the technical solution of this application in detail.

[0031] Figure 1 is a flowchart of an embodiment of the memory access management method provided in this application. Referring to Figure 1, the method provided in this embodiment may include:

[0032] S101. Based on the memory access requests or read / write requests received in the current clock cycle, calculate the total number of memory blocks that need to be accessed in the current clock cycle.

[0033] The memory access management method provided in this application is applied to a memory access management device in an electronic device equipped with on-chip storage units. Here, on-chip storage units refer to storage units integrated on a chip. Furthermore, the memory access management method provided in this application is used to manage the access behavior of other functional modules in the electronic device to memory blocks in the on-chip storage units.

[0034] It should be noted that the on-chip storage unit includes multiple memory blocks. Furthermore, the number and size of the memory blocks contained in the on-chip storage unit are set according to actual needs, and are not limited in this embodiment.

[0035] Furthermore, after the on-chip memory unit is divided into fixed-size memory blocks, the electronic device records the mapping relationship between address ranges and memory block identifiers. For example, in one possible implementation, the on-chip memory unit is divided into 64 memory blocks, each memory block being 16 bits in size. The address range of memory block 1 is 0-16 bits, the address range of memory block 2 is 16-32 bits, and so on.

[0036] Specifically, memory access requests or read / write requests originate from other functional modules within the electronic device. It's important to note that memory access requests and read / write requests are two different types of requests. A memory access request is a request indicating access to a specific memory block. This request carries a memory access bitmap, which marks which memory blocks need to be accessed. The corresponding processing method involves parsing the memory access bitmap and determining whether to access the corresponding memory block based on the value of each bit. Conversely, a read / write request is a request to perform a specific read or write operation. It carries information such as the operation type, starting address, and data length. The corresponding processing method involves determining the specific memory block range based on the starting address and data length, and then performing the read or write operation.

[0037] It should be noted that the memory access bitmap consists of a series of bits, each corresponding to a memory block in the on-chip storage unit. The value of each bit indicates whether the corresponding memory block needs to be accessed (each bit has a value of 0 or 1, where 0 indicates that the corresponding memory block does not need to be accessed, and 1 indicates that the corresponding memory block needs to be accessed). For example, in one possible implementation, the on-chip storage unit includes four memory blocks, and the memory access bitmap carried in a memory access request is 1010. This memory access request indicates that the first and third memory blocks need to be accessed.

[0038] Furthermore, when the received request is a read / write request, for each read / write request, it needs to be converted into a memory access request first, and then the total number of memory blocks that need to be accessed in the current clock cycle is calculated based on the memory access request. When the received request is a memory access request, the total number of memory blocks that need to be accessed in the current clock cycle is calculated directly based on that memory access request.

[0039] Optionally, in one possible implementation, the step of converting a read / write request into a memory access request may include:

[0040] (1) Determine the range of addresses to be accessed based on the starting address and data length in the read / write request.

[0041] It should be noted that the starting address and data length in the read and write requests from each functional module are set by each functional module according to actual needs, and are not limited in this embodiment.

[0042] In practice, when determining the address range to be accessed, the end address can be determined first based on the start address and data length. Then, the continuous region from the start address to the end address can be defined as the address range to be accessed. The end address can be determined using the following formula:

[0043] End address = Start address + Data length - 1

[0044] Combining the previous examples, for instance, in one embodiment, the starting address of the read / write request is 0 bits and the data length is 33 bits, so the address range accessed by the read / write request is 0-32 bits; in another embodiment, the starting address of the read / write request is 2 bits and the data length is 33 bits, so the address range accessed by the read / write request is 2-34 bits.

[0045] (2) Determine the memory block to be accessed based on the address range and the pre-recorded mapping relationship between the address range and the memory block identifier.

[0046] In practice, the mapping relationship between address range and memory block identifier can be searched to find the mapping relationship containing the address range, and then the memory block indicated by the memory block identifier recorded in the found mapping relationship can be determined as the memory block to be accessed.

[0047] Referring to the examples above, memory block 1 ranges from 0 to 16 bits, memory block 2 ranges from 16 to 32 bits, memory block 3 ranges from 32 to 48 bits, and so on, with memory block 10 ranging from 144 to 160 bits. Further, in one embodiment, when the address range to be accessed by the read / write request is 0-32 bits, the memory blocks to be accessed by the read / write request are memory block 1 and memory block 2; in another embodiment, when the address range to be accessed by the read / write request is 2-34 bits, the memory blocks to be accessed by the read / write request are memory block 1, memory block 2, and memory block 3.

[0048] (3) Generate a memory access request based on the memory block to be accessed; wherein the memory access request carries a memory access bitmap, which is used to mark which memory blocks in the on-chip storage unit need to be accessed.

[0049] In practical implementation, a corresponding memory access bitmap can be generated first based on the memory block to be accessed, and then the memory access bitmap can be encapsulated to generate a memory access request. Specifically, when generating the corresponding memory access bitmap, a corresponding binary bitmap can be created based on the number of memory blocks included in the on-chip storage unit. Each bit of this binary bitmap identifies the state of a memory block. Further, for each memory block in the on-chip storage unit, if the memory block is the one to be accessed, the value at the corresponding position is set to 1; otherwise, the value at the corresponding position is set to 0. In this way, the memory access bitmap can be obtained.

[0050] For example, in one embodiment, assuming the on-chip storage unit is divided into 8 memory blocks (memory block 0 to memory block 7), and the memory blocks to be accessed are memory block 1, memory block 3, and memory block 5, then the generated memory access bitmap is 01010100, and the generated memory access request can be: Request ID: 1234 Timestamp: 2024-07-24 15:00:00, Memory Access Bitmap: 01010100.

[0051] It should be noted that when calculating the total number of memory blocks to be accessed in the current clock cycle based on memory access requests, we can first extract a memory access bitmap for each memory access request; then parse the extracted memory access bitmap, mapping each bit to a specific memory block to determine the memory block that the memory access request needs to access; finally, for all memory access requests, we can determine the union of the memory blocks that all memory access requests need to access, and determine the number of memory blocks contained in this union as the total number of memory blocks to be accessed in the current clock cycle (if different memory access requests need to access the same memory block, it is counted once).

[0052] Based on the above introduction, for example, in one possible implementation, three memory access requests are received in the current clock cycle. After parsing the memory access bitmap carried by each memory access request, it is determined that memory access request 1 requests to access memory blocks 2-10, memory access request 2 requests to access memory blocks 4-11, and memory access request 3 requests to access memory blocks 4-15. After taking the union, it is determined that the memory blocks to be accessed are memory blocks 2-15. Furthermore, the total number of memory blocks to be accessed in the current clock cycle is determined to be 14.

[0053] S102. Based on the total number and the average number of memory blocks that need to be accessed in a preset number of historical clock cycles, determine the access increment corresponding to the current clock cycle.

[0054] Specifically, the preset number is set according to actual needs, and is not limited in this embodiment. For example, in one possible implementation, the preset number is 5, that is, in this step, the access increment is determined based on the average number of memory blocks that need to be accessed over 5 historical clock cycles.

[0055] It should be noted that the access increment corresponding to the current clock cycle is equal to the difference between the total number of memory blocks that need to be accessed in the current clock cycle and the average number of memory blocks that need to be accessed in a preset number of historical clock cycles.

[0056] For example, in one possible implementation, the average number of memory blocks that need to be accessed over a preset number of historical clock cycles is 4, and the total number of memory blocks that need to be accessed in the current clock cycle is 20. In this case, the access increment corresponding to the current clock cycle is 16.

[0057] S103. When the access increment is greater than a preset threshold, a preheating process is executed; wherein, the preheating process includes: taking the average value as the initial value of the number of memory blocks to be accessed, increasing the number of memory blocks to be accessed step by step according to a preset increment rule, until the number of memory blocks after the increase is greater than or equal to the total number, so as to gradually increase the access intensity, so that the on-chip storage unit completes the preheating process and enters a stable state.

[0058] Specifically, the specific value of the preset threshold is set according to actual needs, and is not limited in this embodiment. For example, in one possible implementation, the preset threshold is 5.

[0059] Furthermore, the preset increment rule is set according to actual needs, and is not limited in this embodiment. For example, in one possible implementation, the preset increment rule is to add the same number of memory blocks at each level. For example, in one embodiment, 2 memory blocks are added at each level; as another example, in another possible implementation, the preset increment rule is: the number of memory blocks added at the first level is a preset value, and the number of memory blocks added at the subsequent level is 1 more than the number added at the previous level. For example, in one embodiment, 2 memory blocks are added at the first level, 3 memory blocks are added at the second level, and so on, until the number of added memory blocks is greater than or equal to the total number.

[0060] Based on the example above, the initial number of memory blocks to be accessed is 4. The default increment rule is to add 2 memory blocks at each level. After the first level, the number of memory blocks is 6. After the second level, the number of memory blocks is 8. This increment continues until the number of memory blocks after the increment is greater than or equal to the total number, thus completing the warm-up process.

[0061] It should be noted that the specific implementation process of the preheating process may include: using the average value as the number of memory blocks to be accessed, generating a memory read request, and sending the memory read request to the arbitrator for execution; increasing the number of memory blocks to be accessed according to a preset increment rule to obtain the increased number of memory blocks; using the increased number of memory blocks as the number of memory blocks to be accessed, and executing the step of generating a memory read request again, until the increased number of memory blocks is greater than or equal to the total number, thus completing the preheating process.

[0062] It should be noted that memory read requests carry a memory access bitmap. Furthermore, memory read requests only focus on the number of memory blocks that need to be accessed, not on which specific memory block is being accessed.

[0063] The method provided in this embodiment calculates the total number of memory blocks that need to be accessed in the current clock cycle, and then determines the access increment corresponding to the current clock cycle based on the total number and the average number of memory blocks that need to be accessed in a preset number of historical clock cycles. When the access increment is greater than a preset threshold, a warm-up process is initiated. In the warm-up process, by gradually increasing the number of memory blocks that need to be accessed, rather than by a sudden large number of accesses, the on-chip storage unit can transition to a high-load state more smoothly, thereby avoiding bottlenecks or jitter caused by a sudden large number of accesses and maintaining stability.

[0064] Optionally, in one possible implementation, after each increase in the number of memory blocks that need to be accessed, the method further includes:

[0065] Control the preset clock cycle for the pause.

[0066] The preset clock cycle is set according to actual needs, and is not limited in this embodiment. It is understood that the preset clock cycle required to pause remains the same each time the number of memory blocks to be accessed is increased. For example, in one possible implementation, the preset clock cycle is 1, meaning that a pause of 1 clock cycle is required each time the number of memory blocks to be accessed is increased.

[0067] The method provided in this embodiment controls the pause time by a preset clock cycle after each increase in the number of memory blocks that need to be accessed. This ensures that the on-chip storage unit has enough time to adapt to the new load after each increase in memory blocks, thereby smoothly transitioning to a high-load state and effectively preventing sudden load fluctuations, thus ensuring stability.

[0068] Figure 2 is a flowchart of a second embodiment of the memory access management method provided in this application. Referring to Figure 2, the method provided in this embodiment may include:

[0069] S201. Merge the memory access requests to obtain a merge signal.

[0070] Specifically, memory access requests can be merged using an OR operation. As mentioned earlier, each memory access request carries a memory access bitmap. In practice, for multiple memory access requests, the multiple memory access bitmaps of these requests can be merged to obtain a merged memory access bitmap. Then, a merge signal (carrying the merged memory access bitmap) is obtained based on this merged memory access bitmap.

[0071] It should be noted that, as described above, multiple memory access bitmaps contain the same number of bits, which equals the number of memory blocks contained in the on-chip storage unit. Each bit corresponds to one memory block in the on-chip storage unit. Furthermore, when merging multiple memory access bitmaps into a single merged bitmap, an OR operation can be performed on each bit to obtain its corresponding update value. Finally, after obtaining the update values ​​for all bits, the merged memory access bitmap is obtained. Specifically, when performing an OR operation on each bit, if any memory access request has a value of 1 in that bit, the resulting update value is 1; if all memory access requests have a value of 0 in that bit, the resulting update value is 0.

[0072] Referring to the previous examples, for instance, in one embodiment, assume that the on-chip memory cell contains 8 memory blocks, and there are three memory access requests in the current clock cycle. The memory access bitmap of memory access request 1 is 01010100, the memory access bitmap of memory access request 2 is 11001011, and the memory access bitmap of memory access request 3 is 01000101. After merging the three memory access bitmaps of these three memory access requests, the merged memory access bitmap is 11011111.

[0073] S202. Determine the total quantity based on the merging signal.

[0074] Referring to the previous description, the merge signal carries the merged memory access bitmap. The value of each bit in the memory access bitmap indicates whether the corresponding memory block needs to be accessed. When the value is 1, it means that the corresponding memory block needs to be accessed. In this step, the number of 1s in the merged memory access bitmap can be counted, and then the counted number can be determined as the total number.

[0075] Combining the example above, for instance, the merged memory access bitmap is 11011111, with 7 bits having a value of 1, indicating that the number of memory blocks that need to be accessed is 7, that is, the total number of memory blocks that need to be accessed in the current clock cycle is 7.

[0076] S203. Based on the total number and the average number of memory blocks that need to be accessed in a preset number of historical clock cycles, determine the access increment corresponding to the current clock cycle.

[0077] S204. Determine whether the access increment is greater than a preset threshold. If yes, proceed to step S205; otherwise, proceed to step S206.

[0078] Specifically, the implementation principles and processes of steps S203 and S204 can be found in the descriptions in the previous embodiments, and will not be repeated here.

[0079] S205, Perform the preheating process.

[0080] Specifically, the preheating process includes: using the average value as the initial value of the number of memory blocks to be accessed, and gradually increasing the number of memory blocks to be accessed according to a preset increment rule until the number of memory blocks after the increase is greater than or equal to the total number, so as to gradually increase the access intensity and enable the on-chip storage unit to complete the preheating process and enter a stable state.

[0081] Referring to the preceding description, for example, in one embodiment, the average number of memory blocks accessed over a preset number of historical clock cycles is 4, and the access increment corresponding to the current clock cycle is 16. In this case, the number of memory blocks to be accessed can be increased incrementally in the manner of 64'b1111->64'b11111->64'b111111->....... Furthermore, to further achieve a smooth transition in memory access, after each increase in the number of memory blocks to be accessed, a preset clock cycle is maintained. For example, after issuing 64'b1111, a preset clock cycle is maintained before proceeding to the next level, 64'b11111.

[0082] S206, Perform standard memory access operations.

[0083] Specifically, when performing standard memory access operations, the memory access management device directly sends the memory access requests or read / write requests received in the current clock cycle to the arbitrator for execution.

[0084] S207. After the preheating process is completed, perform a standard memory access operation.

[0085] For details regarding the execution of standard memory access operations, please refer to the previous introduction; further details will not be repeated here.

[0086] The method provided in this embodiment enters a warm-up process when the access increment exceeds a preset threshold. In the warm-up process, by gradually increasing the number of memory blocks that need to be accessed, rather than a sudden large number of accesses, the on-chip storage unit can transition to a high-load state more smoothly. This helps to avoid bottlenecks or jitter caused by a sudden large number of accesses and maintains stability. In this way, the on-chip storage unit can quickly and safely reach a stable working state before performing standard memory access operations. Then, standard memory access operations are performed only after the on-chip storage unit has reached a stable working state, which can ensure the stability of the execution when performing standard memory access operations.

[0087] Figure 3 is a flowchart of a third embodiment of the memory access management method provided in this application. Referring to Figure 3, the method provided in this embodiment, based on the above embodiments, may further include:

[0088] S301. During the preheating process, determine first state information to characterize whether the preheating process is completed, and second state information to characterize the current stage of the preheating process.

[0089] Specifically, the first status information indicates whether the on-chip storage unit has completed the warm-up process and is ready for standard memory access operations. The status of the first status information includes 1 or 0. When the status value of the first status information is 1, it indicates that the on-chip storage unit has completed the warm-up process and can perform standard memory access operations. When the status value of the first status information is 0, it indicates that the on-chip storage unit is in the process of warming up or has not completed the warm-up process and cannot perform standard memory access operations.

[0090] Specifically, during the warm-up process, the number of added memory blocks can be monitored in real time, and the first state information can be determined based on this. In practice, if the number of added memory blocks is less than a preset threshold, the warm-up process is determined to be incomplete, and the state value of the first state information is determined to be 0. If the number of added memory blocks is greater than or equal to the preset threshold, the warm-up process is determined to be complete, and the state value of the first state information is determined to be 1.

[0091] Furthermore, the second state information indicates the current warm-up stage of the on-chip memory cell. For example, in one possible implementation, when the second state information is 1, it indicates that the on-chip memory cell is in the initial stage of the warm-up process; when the second state information is 2, it indicates that the on-chip memory cell is in the middle stage of the warm-up process; when the second state information is 3, it indicates that the on-chip memory cell is in the completion stage of the warm-up process, and the on-chip memory cell has completed the warm-up process and entered a stable state.

[0092] In practice, during the warm-up process, the number of memory blocks added can be monitored in real time, and the increase percentage can be calculated based on the number of memory blocks added and the access increment (the increase percentage is equal to the percentage of the number of memory blocks added and the access increment). Furthermore, based on the increase percentage and the preset correspondence between the increase percentage and the warm-up stage, the current warm-up stage can be determined.

[0093] It should be noted that the number of preheating stages included in the preheating phase is set according to actual needs, and this embodiment does not limit this. Furthermore, the preset increase percentage and the correspondence between the preheating stages are also set according to actual needs. For example, in one possible implementation, combining the above example, the preset phase includes three stages: the start stage, the intermediate stage, and the completion stage. The preset increase percentage and the correspondence between the preheating stages are shown in Table 1.

[0094] Table 1 shows the correspondence between the preset percentage increase and the preheating stage.

[0095] Preheating phase, start phase, intermediate phase, completion phase, percentage increase: 0%-10%, greater than 10%, less than 100%, 100%.

[0096] S302. Feedback the first status information and the second status information to the status management device in the electronic device, so that the status management device can obtain the status of the memory access management device.

[0097] Specifically, the state management device can be a CPU or GPU in an electronic device; this embodiment does not limit it. Furthermore, by sending the first and second state information to the state management device, the state management device can gain a comprehensive understanding of the memory access management device's state, helping it to monitor and manage more effectively and make corresponding state management decisions.

[0098] The memory access management method provided in this embodiment determines, during the preheating process, a first state information for characterizing whether the preheating process is completed and a second state information for characterizing the current stage of the preheating process. Then, the first state information and the second state information are fed back to the state management device in the electronic device. In this way, the state management device can obtain the state of the memory access management device and realize real-time monitoring and precise control of the preheating process.

[0099] Corresponding to the aforementioned embodiment of a memory access management method, this application also provides an embodiment of a memory access management device.

[0100] Figure 4 is a schematic diagram of the structure of a memory access management device according to a first embodiment of this application. Referring to Figure 4, the device provided in this embodiment is applied in an electronic device equipped with on-chip storage. The device includes a counting module 410, a register group 420, a comparison unit 430, and a controller 440; wherein...

[0101] The counting module 410 is used to count the total number of memory blocks that need to be accessed in the current clock cycle based on the memory access requests received in the current clock cycle.

[0102] The register group 420 is used to store the number of memory blocks that need to be accessed in historical clock cycles;

[0103] The comparison unit 430 is used to determine the access increment corresponding to the current clock cycle based on the total number and the average number of memory blocks that need to be accessed in a preset number of historical clock cycles.

[0104] The controller 440 is equipped with a state machine. The controller 440 is used to control the state machine to enter a preheating state when the access increment is greater than the preset threshold. In the preheating state, the controller executes a preheating process. The preheating process includes: taking the average value as the initial value of the number of memory blocks to be accessed, and gradually increasing the number of memory blocks to be accessed according to a preset increment rule until the number of memory blocks after the increase is greater than or equal to the total number, so as to gradually increase the access intensity and enable the on-chip storage unit to complete the preheating process and enter a stable state.

[0105] Specifically, the controller 440 is equipped with a state machine. Figure 5 is a schematic diagram of the state transitions of the state machine shown in an exemplary embodiment of this application. Referring to Figure 5, the state machine includes three states: idle state, warm-up state, and working state. Further, in the idle state, the controller waits for the next memory access request or read / write request. In the idle state, the controller only performs some basic maintenance and checks until a new memory access request or read / write request is detected, at which point it leaves the idle state and enters the warm-up state or the working state. In the warm-up state, the controller executes the warm-up process. In the working state, the controller performs standard memory access operations.

[0106] Furthermore, when in an idle state, upon detecting a new memory access request or read / write request, if the access increment is not greater than a preset threshold, it directly enters the working state; if the access increment is greater than the preset threshold, it enters the warm-up state. In addition, after the warm-up state is completed, it enters the working state.

[0107] The apparatus in this embodiment can be used to execute the steps of the method embodiment shown in FIG1. ​​The specific implementation principle and process are similar and will not be described again here.

[0108] Furthermore, Figure 6 is a schematic diagram of a memory access management device illustrated in an exemplary embodiment of this application. Referring to Figure 6, the memory access management device includes a register set, the number of registers in which the register set contains a preset number, and each register is used to store the number of memory blocks that need to be accessed in one historical clock cycle. Furthermore, the preset number is set according to actual needs; in this embodiment, the specific value of the preset number is not limited. For example, in one possible implementation, the preset number may be equal to 2. n .

[0109] Furthermore, referring to Figure 6, when the preset number is 4, the number of memory blocks that need to be accessed in the four historical cycles stored in the four registers can be added together and divided by 4, that is, the register values ​​are added together, and then the result is shifted right by 2 bits to calculate the average number of memory blocks that need to be accessed in the four historical clock cycles.

[0110] It should be noted that after calculating the average number of memory blocks that need to be accessed over a preset number of historical clock cycles, in each clock cycle, the total number of memory blocks that need to be accessed in the current clock cycle is stored in the latest register position, and the existing register value is shifted to the right.

[0111] Furthermore, referring to Figure 6, it can be understood that the comparison unit can be a subtractor to determine the access increment corresponding to the current clock cycle through subtraction.

[0112] The memory access management device provided in this embodiment calculates the total number of memory blocks that need to be accessed in the current clock cycle, and then determines the access increment corresponding to the current clock cycle based on the total number and the average number of memory blocks that need to be accessed in a preset number of historical clock cycles. When the access increment is greater than a preset threshold, a warm-up process is initiated. In the warm-up process, by gradually increasing the number of memory blocks that need to be accessed, rather than by a sudden large number of accesses, the on-chip storage unit can transition to a high-load state more smoothly, avoiding bottlenecks or jitter caused by a sudden large number of accesses and maintaining stability.

[0113] Figure 7 is a schematic diagram of a second embodiment of the memory access management device provided in this application. Referring to Figure 7, the counting module 410 includes a merging unit 411 and a counting unit 412; wherein,

[0114] The merging unit 411 is used to merge the memory access requests to obtain a merging signal;

[0115] The statistical unit 412 is used to determine the total quantity based on the merging signal.

[0116] Specifically, Figure 8 is a schematic diagram of a merging unit shown in an exemplary embodiment of this application. Referring to Figure 8, the merging unit can be an OR gate, which is a basic logic gate used to implement the "OR" operation in logical operations. As described above, its function is to perform an "OR" operation on the bits contained in multiple memory access bitmaps. When any memory access request has a value of 1 in that bit, the output is 1; when all memory access requests have a value of 0 in that bit, the output is 0.

[0117] Optionally, in one possible implementation, the controller 440 is further configured to control a pause preset clock cycle after each increase in the number of memory blocks that need to be accessed.

[0118] Optionally, the controller 440 is further configured to control the state machine to enter a working state when the access increment is not greater than the preset threshold, wherein when the state machine is in the working state, the controller performs standard memory access operations.

[0119] This application also provides an electronic device that includes any of the memory access management devices provided in the second aspect of this application.

[0120] Figure 9 is a schematic diagram of an electronic device according to an exemplary embodiment of this application. Referring to Figure 9, the electronic device provided in this embodiment includes multiple functional modules, a memory access management device, an arbitrator, and an on-chip storage unit; the on-chip storage unit is divided into multiple memory blocks; wherein,

[0121] Multiple functional modules are used to send memory access requests and read / write requests to the memory access management device;

[0122] A memory access management device for performing access management;

[0123] An arbitrator is used to receive and execute memory read requests from a memory access management device, or to receive and execute memory access requests or read / write requests from a memory access management device.

[0124] Each memory block is used to store data.

[0125] Referring to the foregoing description, the memory access management device performs access management as described in any of the memory access management methods provided in the first aspect of this application. During the warm-up process, the memory access management device sends memory read requests to the arbitrator level by level, with the number of memory blocks to be accessed increasing progressively with each level of the memory read request, in order to complete the warm-up process and bring the on-chip storage units to a stable state. Furthermore, when performing standard memory access operations, the memory access management device directly sends memory access requests or read / write requests from functional modules to the arbitrator for execution.

[0126] The electronic device provided in this embodiment enables the on-chip storage unit to smoothly transition to a high-load state, avoiding bottlenecks or jitter caused by a sudden large number of accesses and maintaining stability.

[0127] Furthermore, referring to Figure 9, the electronic device also includes a state management device, which can send a preset clock cycle set by the user to the memory access management device, and further receive first state information and second state information from the memory access management device.

[0128] The specific implementation process of the functions and roles of each unit in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0129] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0130] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A memory access management method, characterized in that, The method is applied to a memory access management device in an electronic device equipped with on-chip storage units, and the method includes: Based on the memory access requests or read / write requests received in the current clock cycle, calculate the total number of memory blocks that need to be accessed in the current clock cycle. The access increment corresponding to the current clock cycle is determined based on the total number and the average number of memory blocks that need to be accessed in a preset number of historical clock cycles. When the access increment is greater than a preset threshold, a warm-up process is executed; wherein, the warm-up process includes: taking the average value as the initial value of the number of memory blocks to be accessed, increasing the number of memory blocks to be accessed step by step according to a preset increment rule, until the number of memory blocks after the increase is greater than or equal to the total number, so as to gradually increase the access intensity, so that the on-chip storage unit completes the warm-up process and enters a stable state.

2. The method according to claim 1, characterized in that, Each time the number of memory blocks that need to be accessed is increased, the method further includes: Control the preset clock cycle for the pause.

3. The method according to claim 1, characterized in that, The step of calculating the total number of memory blocks that need to be accessed in the current clock cycle based on the read and write requests received in the current clock cycle includes: For each read / write request, the read / write request is converted into a memory access request; Based on the memory access request, count the total number of memory blocks that need to be accessed within the current clock cycle.

4. The method according to claim 1 or 3, characterized in that, The step of calculating the total number of memory blocks that need to be accessed in the current clock cycle based on the memory access requests received in the current clock cycle includes: The memory access requests are merged to obtain a merge signal; The total quantity is determined based on the merging signal.

5. The method according to claim 1, characterized in that, The method further includes: When the access increment is not greater than a preset threshold, a standard memory access operation is performed.

6. The method according to claim 1, characterized in that, After the preheating process is completed, the method further includes: Perform standard memory access operations.

7. The method according to claim 1, characterized in that, The method further includes: During the preheating process, first state information is determined to characterize whether the preheating process is complete, and second state information is determined to characterize the current stage of the preheating process. The first status information and the second status information are fed back to the status management device in the electronic device, so that the status management device can obtain the status of the memory access management device.

8. A memory access management device, characterized in that, The memory access management device is used in electronic devices equipped with on-chip storage. The memory access management device includes a counting module, a register set, a comparison unit, and a controller; wherein, The counting module is used to count the total number of memory blocks that need to be accessed in the current clock cycle based on the memory access requests received in the current clock cycle. The register group is used to store the number of memory blocks that need to be accessed in historical clock cycles; The comparison unit is used to determine the access increment corresponding to the current clock cycle based on the total number and the average number of memory blocks that need to be accessed in a preset number of historical clock cycles. The controller is equipped with a state machine; the controller is used to control the state machine to enter a preheating state when the access increment is greater than the preset threshold; wherein, the controller executes a preheating process in the preheating state; the preheating process includes: taking the average value as the initial value of the number of memory blocks to be accessed, and gradually increasing the number of memory blocks to be accessed according to a preset increment rule until the number of memory blocks after the increase is greater than or equal to the total number, so as to gradually increase the access intensity, so that the on-chip storage unit completes the preheating process and enters a stable state.

9. The apparatus according to claim 8, characterized in that, The counting module includes a merging unit and a statistical unit; wherein... The merging unit is used to merge the memory access requests to obtain a merge signal; The statistical unit is used to determine the total quantity based on the merged signal.

10. The apparatus according to claim 8, characterized in that, The controller is also configured to control the pause for a preset clock cycle after each increase in the number of memory blocks that need to be accessed.

11. An electronic device, characterized in that, The electronic device includes the memory access management device according to any one of claims 8-10.

Images