Wear leveling method and memory storage device

Abstract

The present invention provides a wear leveling method and a memory storage device. The wear leveling method is applied to a rewritable non-volatile memory module. The rewritable non-volatile memory module comprises a plurality of physical erasing units. The wear leveling method comprises: on the basis of erase counts and a duration since the last write of each of the plurality of physical erasing units, determining whether each of the plurality of physical erasing units satisfies preset conditions; if a current physical erasing unit satisfying the preset conditions is present among the plurality of physical erasing units, determining whether the current physical erasing unit is fully written; and if the current physical erasing unit is not fully written, performing a first wear leveling operation on the current physical erasing unit, and if the current physical erasing unit is fully written, performing a second wear leveling operation on the current physical erasing unit.

Description

Wear leveling method and memory storage device Technical Field

[0001] This invention relates to the field of storage management technology, and more particularly to a wear leveling method and a memory storage device. Background Technology

[0002] The rapid growth of smartphones, tablets, and personal computers in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the various portable multimedia devices exemplified above due to their characteristics such as data non-volatility, low power consumption, small size, and lack of mechanical structure.

[0003] Conventional wear leveling methods involve moving data to physical erase units with higher erase counts, thereby enabling the use of physical erase units with lower erase counts and averaging the usage frequency of physical erase units in a rewritable non-volatile memory module. To better adapt to actual usage scenarios and more effectively extend the lifespan of memory storage devices, refining wear leveling strategies is a crucial technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0004] Exemplary embodiments of the present invention provide a wear leveling method and a memory storage device, which can improve the lifespan and data stability of the memory storage device.

[0005] An exemplary embodiment of the present invention provides a wear leveling method for a rewritable non-volatile memory module, the rewritable non-volatile memory module including a plurality of physical erase units, the wear leveling method including: determining whether each of the plurality of physical erase units meets a preset condition based on the number of erases and the write time of each of the plurality of physical erase units; if there is a current physical erase unit among the plurality of physical erase units that meets the preset condition, determining whether the current physical erase unit is full; if the current physical erase unit is not full, performing a first wear leveling operation on the current physical erase unit; if the current physical erase unit is full, performing a second wear leveling operation on the current physical erase unit.

[0006] In an exemplary embodiment of the present invention, if the current entity erase unit is not full, the wear leveling method further includes: determining whether the current entity erase unit stores valid data; if the current entity erase unit stores valid data, performing a first wear leveling operation on the current entity erase unit; if the current entity erase unit does not store valid data, associating the current entity erase unit with an idle pool.

[0007] In an exemplary embodiment of the present invention, the step of determining whether each of the plurality of entity erasure units meets the preset condition based on the erasure count and the write time of each of the plurality of entity erasure units includes: determining whether the difference between the erasure count and the average erasure count of each of the plurality of entity erasure units is greater than a preset threshold; if there is at least one entity erasure unit among the plurality of entity erasure units whose difference is greater than the preset threshold, determining whether the write time of each of the at least one entity erasure unit is greater than a preset time threshold; and if there is a current entity erasure unit among the at least one entity erasure unit whose write time is greater than the preset time threshold, determining that the current entity erasure unit meets the preset condition.

[0008] In an exemplary embodiment of the present invention, the step of performing the first wear leveling operation includes: selecting the physical erase unit with the highest number of erases from the idle pool as the first target physical erase unit; and transferring all data of the current physical erase unit to the first target physical erase unit.

[0009] In an exemplary embodiment of the present invention, the step of performing the first wear leveling operation includes: determining whether there is a first target entity erasure unit that is not fully written; and if there is no first target entity erasure unit that is not fully written, selecting the entity erasure unit with the highest number of erasures from the idle pool as the first target entity erasure unit, and moving all data in the current entity erasure unit to the first target entity erasure unit.

[0010] In an exemplary embodiment of the present invention, the step of performing the first wear leveling operation includes: if there is a first target entity erasure unit that is not fully written, determining whether the remaining capacity of the first target entity erasure unit that is not fully written is sufficient to store all the data in the current entity erasure unit; if yes, moving all the data in the current entity erasure unit to the first target entity erasure unit that is not fully written; and if no, selecting the entity erasure unit with the highest number of erasures from the idle pool as the first target entity erasure unit, and moving all the data in the current entity erasure unit to the first target entity erasure unit.

[0011] In an exemplary embodiment of the present invention, the step of performing the second wear leveling operation includes: determining whether there is a second target entity erasure unit that is not fully written; and if there is no second target entity erasure unit that is not fully written, selecting the entity erasure unit with the highest number of erasures from the idle pool as the second target entity erasure unit, and transferring the valid data in the current entity erasure unit to the second target entity erasure unit.

[0012] In an exemplary embodiment of the present invention, the step of performing the second wear leveling operation includes: if there is an unfilled second target entity erasure unit, determining whether the remaining capacity of the unfilled second target entity erasure unit is sufficient to store the valid data in the current entity erasure unit; if yes, moving the valid data in the current entity erasure unit to the unfilled second target entity erasure unit; and if no, selecting the entity erasure unit with the highest erasure count from the idle pool as the second target entity erasure unit, and sequentially moving the valid data in the current entity erasure unit to the unfilled second target entity erasure unit and the second target entity erasure unit.

[0013] In an exemplary embodiment of the present invention, the wear leveling method further includes: obtaining a plurality of erasure counts for the plurality of entity erasure units; and calculating the average erasure count based on the plurality of erasure counts.

[0014] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The connection interface unit is used to couple to a host system. The rewritable non-volatile memory module includes a plurality of physical erase units. The memory control circuit unit is used to determine whether each of the plurality of physical erase units meets a preset condition based on the number of erases and the write time of each of the plurality of physical erase units. If there is a current physical erase unit among the plurality of physical erase units that meets the preset condition, the memory control circuit unit is further used to determine whether the current physical erase unit is full. If the current physical erase unit is not full, the memory control circuit unit is further used to perform a first wear leveling operation on the current physical erase unit. If the current physical erase unit is full, the memory control circuit unit is further used to perform a second wear leveling operation on the current physical erase unit.

[0015] In an exemplary embodiment of the present invention, if the current entity erase unit is not full, the memory control circuit unit is further configured to determine whether the current entity erase unit stores valid data; if the current entity erase unit stores valid data, a first wear leveling operation is performed on the current entity erase unit; if the current entity erase unit does not store valid data, the current entity erase unit is associated with an idle pool.

[0016] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine whether the difference between the number of erasures of each of the plurality of physical erasure units and the average number of erasures is greater than a preset threshold. If there is at least one physical erasure unit among the plurality of physical erasure units whose difference is greater than the preset threshold, the memory control circuit unit is further configured to determine whether the write time of each of the at least one physical erasure unit is greater than a preset time threshold. If there is a current physical erasure unit among the at least one physical erasure unit whose write time is greater than the preset time threshold, the memory control circuit unit is further configured to determine that the current physical erasure unit satisfies the preset condition.

[0017] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to select the entity erase unit with the highest number of erases from the idle pool as the first target entity erase unit, and to move all data of the current entity erase unit to the first target entity erase unit.

[0018] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine whether there is a first target entity erasure unit that is not fully written. If there is no first target entity erasure unit that is not fully written, the memory control circuit unit is further configured to select the entity erasure unit with the highest number of erasures from the idle pool as the first target entity erasure unit, and move all data in the current entity erasure unit to the first target entity erasure unit.

[0019] In an exemplary embodiment of the present invention, if there is a first target entity erasure unit that is not fully written, the memory control circuit unit is further configured to determine whether the remaining capacity of the first target entity erasure unit that is not fully written is sufficient to store all the data in the current entity erasure unit. If yes, the memory control circuit unit is further configured to move all the data in the current entity erasure unit to the first target entity erasure unit that is not fully written. If no, the memory control circuit unit is further configured to select the entity erasure unit with the highest number of erasures from the idle pool as the first target entity erasure unit, and move all the data in the current entity erasure unit to the first target entity erasure unit.

[0020] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine whether there is a second target entity erasure unit that is not fully written. If there is no second target entity erasure unit that is not fully written, the memory control circuit unit is further configured to select the entity erasure unit with the highest number of erasures from the idle pool as the second target entity erasure unit, and move the valid data in the current entity erasure unit to the second target entity erasure unit.

[0021] In an exemplary embodiment of the present invention, if there is an unfilled second target entity erasure unit, the memory control circuit unit is further configured to determine whether the remaining capacity of the unfilled second target entity erasure unit is sufficient to store the valid data in the current entity erasure unit. If yes, the memory control circuit unit is further configured to move the valid data in the current entity erasure unit to the unfilled second target entity erasure unit. If no, the memory control circuit unit is further configured to select the entity erasure unit with the highest number of erasures from the idle pool as the second target entity erasure unit, and sequentially move the valid data in the current entity erasure unit to the unfilled second target entity erasure unit and the second target entity erasure unit.

[0022] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to obtain a plurality of erasure counts of the plurality of physical erasure units, and calculate the average erasure count based on the plurality of erasure counts.

[0023] Based on the above, the present invention provides a wear leveling method and a memory storage device capable of performing wear leveling operations on both closed and open physical erase units to accommodate user habits. Furthermore, in the wear leveling operation on open physical erase units, by moving all data from the open physical erase unit to the target physical erase unit, the lifespan of the memory storage device can be extended while simultaneously improving data stability. Moreover, by reusing unfilled target physical erase units, storage space waste can be effectively avoided.

[0024] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0025] Figure 1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0026] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of a system and storage device according to an exemplary embodiment of the present invention;

[0028] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0029] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0030] Figure 6 is a schematic diagram of a module for managing a rewritable non-volatile memory according to an exemplary embodiment of the present invention;

[0031] Figure 7 is a schematic diagram of the storage pool and idle pool according to an exemplary embodiment of the present invention;

[0032] Figure 8 is a flowchart of a wear equalization method according to an exemplary embodiment of the present invention;

[0033] Figure 9 is a flowchart illustrating the execution of the first wear leveling operation according to an exemplary embodiment of the present invention;

[0034] Figure 10 is a schematic diagram of the storage pool and idle pool according to an exemplary embodiment of the present invention;

[0035] Figure 11 is a flowchart illustrating the execution of the first wear leveling operation according to an exemplary embodiment of the present invention;

[0036] Figure 12 is a schematic diagram of the storage pool and idle pool according to an exemplary embodiment of the present invention;

[0037] Figure 13 is a flowchart illustrating the execution of the second wear leveling operation according to an exemplary embodiment of the present invention;

[0038] Figure 14 is a schematic diagram of the storage pool and idle pool according to an exemplary embodiment of the present invention;

[0039] Figure 15 is a schematic diagram of the storage pool and idle pool according to an exemplary embodiment of the present invention;

[0040] Figure 16 is a schematic diagram of the storage pool and idle pool according to an exemplary embodiment of the present invention;

[0041] Figure 17 is a flowchart of a wear leveling method according to an exemplary embodiment of the present invention. Detailed Implementation

[0042] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0043] Figure 1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device, and I / O device according to an exemplary embodiment of the present invention.

[0044] Referring to Figures 1 and 2, the host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 can be connected to the system bus 110.

[0045] The host system 11 can be connected to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. Furthermore, the host system 11 can be connected to the I / O device 12 via the system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0046] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 can be connected to the memory storage device 10 via wired or wireless means.

[0047] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected via the system bus 110 to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0048] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include the storage device 30 and system 31 of FIG3.

[0049] Figure 3 is a schematic diagram of a system and storage device according to an exemplary embodiment of the present invention. Referring to Figure 3, the storage device 30 can be used in conjunction with the system 31 to store data. For example, the system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0050] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to Figure 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0051] The connection interface unit 41 is used to connect to the host system 11. The memory storage device 10 can communicate with the host system 11 through the connection interface unit 41. For example, the connection interface unit 41 may be compatible with the Peripheral Component Interconnect Express (PCI Express) standard, the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards.

[0052] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to control the rewritable non-volatile memory module 43. For example, the memory control circuit unit 42 can instruct the rewritable non-volatile memory module 43 to perform operations such as writing, reading, and erasing data according to instructions from the host system 11. For example, the memory control circuit unit 42 may include a flash memory controller.

[0053] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quadruple-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0054] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0055] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into lower physical programming units and upper physical programming units at least. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0056] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to Figure 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0057] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. For example, the memory management circuit 51 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0058] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. For example, the host interface 52 may be compatible with PCI Express, SATA, PATA, IEEE 1394, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transfer standards.

[0059] The memory interface 53 is connected to the memory management circuit 51. The memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. For example, the memory management circuit 51 can issue operation commands to the rewritable non-volatile memory module 43 through the memory interface 53 to instruct the rewritable non-volatile memory module 43 to perform various operations such as reading, writing or erasing data.

[0060] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0061] Error checking and correction circuit 54 is connected to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. For example, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0062] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0063] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Referring to Figure 6, the memory management circuit 51 can logically group the physical units 601(0) to 601(C) in the rewritable non-volatile memory module 43 into the memory pool 61 and the spare pool 62.

[0064] In one exemplary embodiment, an entity unit refers to an entity address or an entity programmable unit. An entity programmable unit is the basic unit for performing programmatic operations to write data. For example, an entity programmable unit may include one or more entity pages or entity sectors. In one exemplary embodiment, an entity unit may also consist of multiple contiguous or non-contiguous entity addresses. In one exemplary embodiment, an entity unit may also refer to a virtual block (VB). A virtual block may include multiple entity addresses or multiple entity programmable units. In one exemplary embodiment, a virtual block may include one or more entity erase units. An entity erase unit is the basic unit for performing erase operations to erase data. For example, an entity erase unit may include one or more entity blocks.

[0065] In one exemplary embodiment, entity units 601(0) to 601(B) in storage pool 61 are used to store user data (e.g., user data from host system 11 of FIG. 1). For example, entity units 601(0) to 601(B) in storage pool 61 can store valid data and invalid data. Furthermore, memory management circuitry 51 can logically group entity units 601(0) to 601(A) in storage pool 61 into open pool 611 and logically group entity units 601(A+1) to 601(B) in storage pool 61 into closed pool 612. For example, if an entity unit has stored data and is not full, this entity unit can be associated (or added) to open pool 611. For example, if an entity unit has stored data and is full, this entity unit can be associated (or added) to closed pool 612. In one exemplary embodiment, entity units 601(0) to 601(A) in open pool 611 are also referred to as open entity units. Entity units 601(A+1) to 601(B) in closed pool 612 are also referred to as closed entity units. For example, open pool 611 may include multiple open entity erasure units, wherein each open entity erasure unit may include one or more open entity blocks. For example, closed pool 612 may include multiple closed entity erasure units, wherein each closed entity erasure unit may include one or more closed entity blocks.

[0066] In one exemplary embodiment, entity units 601(B+1) to 601(C) in the idle pool 62 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to the idle area 62. Furthermore, entity units (or entity units that do not store valid data) in the idle pool 62 may be erased. When new data is written, one or more entity units may be retrieved from the idle pool 62 to store this new data.

[0067] In one exemplary embodiment, the memory management circuit 51 may configure logic units 602(0) to 602(D) to map physical units 601(0) to 601(B) in the memory area 61. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programmable unit or consist of multiple consecutive or non-consecutive logical addresses.

[0068] In one exemplary embodiment, the memory management circuit 51 may record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0069] Figure 7 is a schematic diagram of the storage pool and idle pool according to an exemplary embodiment of the present invention. Referring to Figure 7, in an exemplary embodiment, the memory management circuit 51 can logically group the physical erase units in the rewritable non-volatile memory module 43 into the idle pool 72 and the open pool 711 and closed pool 712 of the storage pool 71.

[0070] First, in the first phase, the idle pool 72 includes, but is not limited to, physical erase units B7-B9; the open pool 711 includes, but is not limited to, physical erase units B1-B3; and the closed pool 712 includes, but is not limited to, physical erase units B4-B6. Next, in the second phase, physical erase units B2 and B3, which originally belonged to the open pool 711 in the first phase, can be filled and associated with the closed pool 722, while physical erase unit B1 is not accessed by the host system 11 and remains associated with the open pool 711 in the second phase. Additionally, physical erase units B7 and B8, which originally belonged to the idle pool 72 in the first phase, can be associated with the open pool 711 in the second phase. Finally, after a relatively long period, the third phase begins.

[0071] As shown in Figure 7, since the user no longer uses physical erase unit B1 and physical erase unit B1 associated with open pool 711 does not participate in the wear leveling operation, during the second to third stages, physical erase unit B1 is not filled and remains in open pool 711, while the erase count of other physical erase units is continuously increased. Ultimately, in the third stage, the erase count of physical erase unit B1 will be much lower than that of other physical erase units, thus adversely affecting the lifespan of the memory storage device 10.

[0072] This invention provides a wear leveling method that can perform wear leveling operations on both closed and open physical erase units to adapt to user habits, thereby effectively extending the lifespan of the memory storage device and improving data stability.

[0073] Figure 8 is a flowchart illustrating a wear leveling method according to an exemplary embodiment of the present invention. Please refer to Figure 8. In one exemplary embodiment, the memory management circuit 51 can determine whether each physical erase unit meets the preset conditions for triggering the wear leveling operation based on the number of erases and the write time of the multiple physical erase units of the rewritable non-volatile memory module 43.

[0074] In step S801, the memory management circuit 51 may obtain multiple erase counts for multiple physical erase units and calculate an average erase count based on the multiple erase counts. In an exemplary embodiment, the memory management circuit 51 may periodically obtain multiple erase counts for multiple physical erase units of the rewritable non-volatile memory module 43 and calculate an average erase count based on the multiple erase counts. In an exemplary embodiment, the memory management circuit 51 may, for example, obtain multiple erase counts for multiple physical erase units of the rewritable non-volatile memory module 43 according to an instruction from the host system 11 and calculate an average erase count based on the multiple erase counts.

[0075] In step S802, the memory management circuit 51 determines whether the difference between the number of erases and the average number of erases for each physical erase unit in the rewritable non-volatile memory module 43 is greater than a preset threshold. Specifically, if the difference between the number of erases and the average number of erases for a physical erase unit is larger, it indicates that the number of erases for this physical erase unit is much higher (or much lower) than other physical erase units. This physical erase unit needs to be put into wear leveling operation to avoid affecting the service life of the memory storage device 10. The value of the preset threshold can be designed according to actual needs, and the present invention does not impose any limitations. If there is at least one physical erase unit whose difference between the number of erases and the average number of erases is greater than the preset threshold, then proceed to step S803; otherwise, the wear leveling method of FIG8 ends.

[0076] In step S803, the memory management circuit 51 can further determine whether the write time of at least one physical erase unit is greater than a preset time threshold. Specifically, when data is written to a physical erase unit, the memory management circuit 51 can record a timestamp in the physical erase unit, wherein the timestamp is used to characterize the time point when the physical erase unit is written to. The memory management circuit 51 can, for example, calculate the write time of the physical erase unit using this timestamp. For example, the memory management circuit 51 can calculate the time length (i.e., the write time) between the time point when the physical erase unit is written to and the current time point using this timestamp. Accordingly, the memory management circuit 51 can determine whether the physical erase unit meets the preset condition by determining whether the write time of a physical erase unit is greater than the preset time threshold. The value of the preset time threshold can be designed according to actual needs, and the present invention does not impose any limitations.

[0077] In one exemplary embodiment, the memory management circuit 51 may, for example, randomly determine whether the write time of the at least one physical erase unit is greater than a preset time threshold. In another exemplary embodiment, the memory management circuit 51 may, for example, determine whether the write time of the at least one physical erase unit is greater than the preset time threshold based on the difference between the number of erases of the at least one physical erase unit and the average number of erases, in descending order.

[0078] In one exemplary embodiment, the memory management circuit 51 may determine whether the write time of at least one physical erase unit (e.g., five physical erase units) is greater than a preset time threshold by ranking the number of erases from highest to lowest. Specifically, the memory management circuit 51 may obtain the timestamps of the five physical erase units in descending order of the number of erases and determine whether the write time represented by these timestamps is greater than the preset time threshold. More specifically, firstly, the memory management circuit 51 may obtain the timestamp of the physical erase unit with the highest number of erases among the five physical erase units, calculate the write time of the physical erase unit with the highest number of erases, and determine whether this write time is greater than the preset time threshold. If the write time of the physical erase unit with the highest number of erases is not greater than the preset time threshold, then the physical erase unit with the highest number of erases does not meet the preset condition and does not need to be put into the wear leveling operation, proceeding to step S804.

[0079] In step S804, the memory management circuit 51 determines whether the physical erase unit with the highest number of erases is the last of the five physical erase units. Since the physical erase unit with the highest number of erases is not the last of the five physical erase units (meaning that four of the five physical erase units have not yet been executed in step S803), the circuit returns to step S803. The memory management circuit 51 then determines whether the write time of the physical erase unit with the highest number of erases among the four physical erase units is greater than a preset time threshold. If the write time of the physical erase unit with the highest number of erases among the four physical erase units is not greater than the preset time threshold, the circuit proceeds to step S804 and repeats the above implementation details until all four physical erase units have completed step S803, or the write time of one of the four physical erase units is greater than the preset time threshold, and then proceeds to step S805.

[0080] On the other hand, if the write time of the physical erase unit with the highest number of erases among the four physical erase units is greater than a preset time threshold, then the physical erase unit with the highest number of erases among the four physical erase units meets the preset condition, and the process proceeds to step S805. In step S805, the memory management circuit 51 can determine whether the physical erase unit with the highest number of erases among the four physical erase units (i.e., the current physical erase unit that meets the preset condition) is full. In other words, the memory management circuit 51 can determine whether the current physical erase unit is an open physical erase unit or a closed physical erase unit.

[0081] If the current physical erase unit is not full (i.e., the current physical erase unit is an open physical erase unit), proceed to step S806. In step S806, the memory management circuit 51 determines whether the current physical erase unit stores valid data. If the current physical erase unit does not store valid data, proceed to step S807. In step S807, the memory management circuit 51 can associate the current physical erase unit with the idle pool 72, so that the current physical erase unit can be used in subsequent write operations to store user data written by the host system 11. Conversely, if the current physical erase unit stores valid data, proceed to step S808. In step S808, the memory management circuit 51 can perform a first wear leveling operation on the current physical erase unit.

[0082] In an exemplary embodiment, the implementation details of the memory management circuit 51 performing the first wear leveling operation can be shown, for example, in Figures 9 and 10. Figure 9 is a flowchart illustrating the execution of the first wear leveling operation according to an exemplary embodiment of the present invention; Figure 10 is a schematic diagram of the memory pool and the idle pool according to an exemplary embodiment of the present invention. Please refer to Figures 9 and 10. In step S901, the memory management circuit 51 can select the physical erase unit with the highest number of erases from the idle pool 72 as the first target physical erase unit. That is, the memory management circuit 51 can select the physical erase unit B3 with the highest number of erases (i.e., 515 times) from the idle pool 72 as the first target physical erase unit. Next, in step S902, the memory management circuit 51 can move all the data in the current physical erase unit (i.e., physical erase unit B1 in Figure 10) to the first target physical erase unit B3 to complete the first wear leveling operation.

[0083] To further explain, the current physical erase unit B1 meets preset conditions, meaning that the difference between the number of erases of the current physical erase unit B1 and the average number of erases is greater than a preset threshold, and its writing time is also greater than a preset time threshold. In other words, the number of erases of the current physical erase unit B1 differs significantly from the number of erases of other physical erase units in the rewritable non-volatile memory module 43. Therefore, the current physical erase unit B1 needs to be put into wear leveling operation to maintain the service life of the memory storage device 10. In addition, since the current physical erase unit B1 is an open physical erase unit that is not fully written, in order to address the poor data stability of open physical units, the first wear leveling operation provided by this invention involves moving all the data stored in the current physical erase unit B1 to the first target physical erase unit B3. In this way, the first wear leveling operation provided by this invention not only improves the service life of the memory storage device 10, but also further improves the data stability of the memory storage device 10.

[0084] In one exemplary embodiment, the implementation details of the memory management circuit 51 performing the first wear leveling operation may be as shown in Figures 10 to 12, for example. Figure 11 is a flowchart of performing the first wear leveling operation according to an exemplary embodiment of the present invention; Figure 12 is a schematic diagram of the storage pool and idle pool according to an exemplary embodiment of the present invention. Please refer to Figures 10 to 12. In step S1101, the memory management circuit 51 may determine whether there is a first target entity erase unit that is not fully written. Specifically, the first target entity erase unit is the entity erase unit used to store all the data of the current entity erase unit in the first wear leveling operation. In one exemplary embodiment, the memory management circuit 51 may, for example, determine whether the first target entity erase unit in the previous first wear leveling operation is fully written, in order to decide whether to continue using the first target entity erase unit in the previous first wear leveling operation.

[0085] If no unwritten first target entity erase unit exists, proceed to step S1102. Refer to Figure 10 for details. In step S1102, the memory management circuit 51 selects the entity erase unit B3 with the highest number of erase cycles from the idle pool 72 as the first target entity erase unit. Next, in step S1103, the memory management circuit 51 moves all data from the current entity erase unit B1 to the first target entity erase unit B3 to complete the first wear leveling operation.

[0086] It is worth mentioning that, since the current physical erase unit B1 is an open physical erase unit that is not fully written, in order to address the poor data stability of the open physical unit, the first wear leveling operation moves all the data stored in the current physical erase unit B1 to the first target physical erase unit B3. This can improve the lifespan of the memory storage device 10 while also improving the data stability of the memory storage device 10.

[0087] Conversely, if there is a first target entity erasure unit that is not fully written, then proceed to step S1104. Please refer to Figure 12 here. In step S1104, the memory management circuit 51 can determine whether the remaining capacity of the first target entity erasure unit that is not fully written (for example, entity erasure unit B6) is sufficient to store all the data in the current entity erasure unit B1.

[0088] If the remaining capacity of the first target entity erasure unit B6, which is not yet fully written, is insufficient to store all the data in the current entity erasure unit B1, then return to step S1102, and execute steps S1102 and S1103 in sequence to complete the first wear leveling operation.

[0089] Conversely, if the remaining capacity of the first target entity erasure unit B6, which is not yet fully written, is sufficient to store all the data in the current entity erasure unit B1, then proceed to step S1105. In step S1105, the memory management circuit 51 can move all the data in the current entity erasure unit B1 to the first target entity erasure unit B6, which is not yet fully written, to complete the first wear leveling operation.

[0090] It is worth mentioning that the first wear leveling operation, which moves all the data stored in the current physical erase unit B1 to the first target physical erase unit B6, can improve the lifespan of the memory storage device 10 while also enhancing its data stability. Furthermore, using the first target physical erase unit B6 to perform the first wear leveling operation effectively avoids wasting the storage space of the memory storage device 10.

[0091] On the other hand, if the current physical erase unit is full (meaning the current physical erase unit is a closed physical erase unit), then proceed to step S809. In step S809, the memory management circuit 51 may perform a second wear leveling operation for the current physical erase unit.

[0092] In one exemplary embodiment, the implementation details of the memory management circuit 51 performing the second wear leveling operation may be as shown in Figures 13 to 16, where Figure 13 is a flowchart illustrating the execution of the second wear leveling operation according to an exemplary embodiment of the present invention; Figures 14 to 16 are schematic diagrams of the storage pool and idle pool according to an exemplary embodiment of the present invention. Please refer to Figures 13 to 16. In step S1301, the memory management circuit 51 may determine whether there is a second target entity erase unit that is not fully written. Specifically, the second target entity erase unit is the entity erase unit used to store the valid data of the current entity erase unit in the second wear leveling operation. In one exemplary embodiment, the memory management circuit 51 may determine whether the second target entity erase unit in the previous second wear leveling operation is fully written, in order to decide whether to continue using the second target entity erase unit in the previous second wear leveling operation.

[0093] If no second target entity erase unit is found to be unfilled, proceed to step S1302. Refer to Figure 14 for details. In step S1302, the memory management circuit 51 selects the entity erase unit B3 with the highest number of erases (i.e., 515 times) from the idle pool 72 as the second target entity erase unit. Next, in step S1303, the memory management circuit 51 moves valid data from the current entity erase unit (i.e., entity erase unit B2 in Figure 14) to the second target entity erase unit B3 to complete the second wear leveling operation.

[0094] Conversely, if there is a second target entity erasure unit that is not fully written, then proceed to step S1304. In step S1304, the memory management circuit 51 can further determine whether the remaining capacity of the second target entity erasure unit that is not fully written is sufficient to store the valid data in the current entity erasure unit.

[0095] If the remaining capacity of the second target physical erase unit is sufficient to store the valid data in the current physical erase unit, then proceed to step S1305. Please refer to Figure 15 here. In step S1305, the memory management circuit 51 can move the valid data from the current physical erase unit (i.e., physical erase unit B2 in Figure 15) to the second target physical erase unit (e.g., physical erase unit B1 in Figure 15) that is not yet full, to complete the second wear leveling operation. In this exemplary embodiment, as shown in Figure 15, after completing the second wear leveling operation, physical erase unit B1 is still not full; therefore, physical erase unit B1 remains associated with the open pool 711. In another exemplary embodiment, after completing the second wear leveling operation, physical erase unit B1 may, for example, be full, thus being associated with the closed pool 712.

[0096] Conversely, if the remaining capacity of the second target entity erase unit is insufficient to store the valid data in the current entity erase unit, then proceed to step S1306. Please refer to Figure 16 here. In step S1306, the memory management circuit 51 selects the entity erase unit B3 with the highest number of erases (i.e., 515 times) from the idle pool 72 as the second target entity erase unit. Next, in step S1307, the memory management circuit 51 sequentially moves the valid data in the current entity erase unit (i.e., entity erase unit B2 in Figure 16) to the unfilled second target entity erase unit (e.g., entity erase unit B1 in Figure 16) and the second target entity erase unit B3 to complete the second wear leveling operation. After completing the second wear leveling operation, as shown in Figure 16, entity erase unit B1 can be filled and thus associated with the closed pool 712, and entity erase unit B3 is not filled and thus associated with the open pool 711.

[0097] Based on the above, the second wear leveling operation of the present invention can effectively avoid wasting the storage space of the memory storage device 10 by using the second target entity erasure unit that is not fully written.

[0098] Figure 17 is a flowchart of a wear leveling method according to an exemplary embodiment of the present invention. Please refer to Figure 17. In step S1701, based on the number of erases and the write time of each physical erase unit, it is determined whether each physical erase unit meets a preset condition. In step S1702, if there is a current physical erase unit that meets the preset condition, it is determined whether the current physical erase unit is full. In step S1703, if the current physical erase unit is not full, it is determined whether the current physical erase unit stores valid data. In step S1704, if the current physical erase unit stores valid data, a first wear leveling operation is performed on the current physical erase unit.

[0099] However, since the steps in Figure 17 have been described in detail above, they will not be repeated here. It is worth noting that each step in Figure 17 can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Furthermore, the method in Figure 17 can be used in conjunction with the above embodiments, or it can be used alone, and the present invention is not limited thereto.

[0100] In summary, the wear leveling method and memory storage device proposed in the exemplary embodiments of the present invention can further perform wear leveling operations on open physical erase units, based on conventional wear leveling methods for closed physical erase units, to cater to user habits. Furthermore, in the wear leveling operation for open physical erase units, by moving all data from the open physical erase units to the target physical erase unit, the lifespan of the memory storage device can be extended while simultaneously improving data stability. Moreover, by reusing unfilled target physical erase units, storage space waste can be effectively avoided.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wear leveling method, characterized in that, For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical erase units, the wear leveling method includes: Based on whether the number of erasures and the writing time of each of the plurality of entity erasure units reach a preset threshold, it is determined whether each of the plurality of entity erasure units meets the preset conditions. If there is a current entity erasure unit among the plurality of entity erasure units that meets the preset conditions, determine whether the current entity erasure unit is filled. If the current entity erase unit is not full, perform a first wear leveling operation on the current entity erase unit; If the current entity erase unit is full, a second wear leveling operation is performed on the current entity erase unit.

2. The wear leveling method according to claim 1, further comprising: if the current entity erase unit is not filled, the method includes: Determine whether the current entity erasure unit stores valid data; If the current entity erasure unit has stored valid data, perform a first wear leveling operation on the current entity erasure unit; If the current entity erasure unit does not store valid data, then the current entity erasure unit is associated with the idle pool.

3. The wear leveling method according to claim 1, wherein the step of determining whether each of the plurality of physical erase units meets the preset condition based on the number of erases and the writing time of each of the plurality of physical erase units includes: Determine whether the difference between the number of erasures of each of the plurality of entity erasure units and the average number of erasures is greater than a preset threshold. If there is at least one entity eraser among the plurality of entity eraser units whose difference is greater than the preset threshold, determine whether the writing time of each of the at least one entity eraser unit is greater than the preset time threshold. as well as If there is a current entity erasure unit among the at least one entity erasure unit whose writing time is greater than the preset time threshold, it is determined that the current entity erasure unit satisfies the preset condition.

4. The wear leveling method according to claim 1, wherein the step of performing the first wear leveling operation includes: Select the entity eraser with the highest number of erases from the idle pool as the first target entity eraser; as well as All data from the current entity erasure unit is moved to the first target entity erasure unit.

5. The wear leveling method according to claim 1, wherein the step of performing the first wear leveling operation includes: Determine if there is a first target entity erasure unit that is not fully written; as well as If there is no unwritten first target entity erasure unit, select the entity erasure unit with the highest number of erasures from the idle pool as the first target entity erasure unit, and move all data in the current entity erasure unit to the first target entity erasure unit.

6. The wear leveling method according to claim 5, wherein the step of performing the first wear leveling operation includes: If there is a first target entity erasure unit that is not fully written, determine whether the remaining capacity of the first target entity erasure unit that is not fully written is sufficient to store all the data in the current entity erasure unit; If so, all the data in the current entity erasure unit will be moved to the first target entity erasure unit that is not yet fully written. as well as If not, the entity erasure unit with the highest number of erasures is selected from the idle pool as the first target entity erasure unit, and all data in the current entity erasure unit is moved to the first target entity erasure unit.

7. The wear leveling method according to claim 1, wherein the step of performing the second wear leveling operation includes: Determine if there is a second target entity erasure unit that is not fully written; as well as If there is no unwritten second target entity erasure unit, select the entity erasure unit with the highest number of erasures from the idle pool as the second target entity erasure unit, and move the valid data in the current entity erasure unit to the second target entity erasure unit.

8. The wear leveling method according to claim 7, wherein the step of performing the second wear leveling operation includes: If there is a second target entity erasure unit that is not fully written, determine whether the remaining capacity of the second target entity erasure unit that is not fully written is sufficient to store the valid data in the current entity erasure unit; If so, the valid data in the current entity erasure unit is moved to the second target entity erasure unit that is not yet fully written. as well as If not, the entity erasure unit with the highest number of erasures is selected from the idle pool as the second target entity erasure unit, and the valid data in the current entity erasure unit is sequentially moved to the second target entity erasure unit that is not full and the second target entity erasure unit.

9. The wear equalization method according to claim 1, further comprising: Obtain multiple erasure counts for the multiple entity erasure units; as well as The average number of erasures is calculated based on the multiple erasure counts.

10. A memory storage device, characterized in that, include: A connection interface unit for coupling to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical erasure units; as well as The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Based on the number of erasures and the writing time of each of the plurality of entity erasure units, it is determined whether each of the plurality of entity erasure units meets the preset conditions. If there is a current entity erasure unit among the plurality of entity erasure units that meets the preset conditions, determine whether the current entity erasure unit is filled. If the current entity erase unit is not full, perform a first wear leveling operation on the current entity erase unit; If the current entity erase unit is full, a second wear leveling operation is performed on the current entity erase unit.

11. The memory storage device of claim 10, wherein if the current entity erase unit is not full, the memory control circuit unit is further configured to... Determine whether the current entity erasure unit stores valid data; If the current entity erasure unit has stored valid data, perform a first wear leveling operation on the current entity erasure unit; If the current entity erasure unit does not store valid data, then the current entity erasure unit is associated with the idle pool.

12. The memory storage device according to claim 10, wherein the memory control circuit unit is further configured to determine whether the difference between the number of erasures of each of the plurality of physical erasure units and the average number of erasures is greater than a preset threshold. If at least one of the plurality of physical erase units has a difference greater than the preset threshold, the memory control circuit unit is further configured to determine whether the write time of each of the at least one physical erase unit is greater than the preset time threshold, and If there is a current entity erase unit among the at least one entity erase unit whose write time is greater than the preset time threshold, the memory control circuit unit is further used to determine that the current entity erase unit meets the preset condition.

13. The memory storage device of claim 10, wherein the memory control circuit unit is further configured to select from the idle pool the physical erase unit with the highest number of erases as the first target physical erase unit, and The memory control circuit unit is also used to move all the data of the current entity erasure unit to the first target entity erasure unit.

14. The memory storage device according to claim 10, wherein the memory control circuit unit is further configured to determine whether there is a first target entity erasure unit that is not fully written, and If there is no unwritten first target entity erasure unit, the memory control circuit unit is further configured to select the entity erasure unit with the highest number of erasures from the idle pool as the first target entity erasure unit, and move all data in the current entity erasure unit to the first target entity erasure unit.

15. The memory storage device according to claim 14, wherein if there is a first target entity erasure unit that is not fully written, the memory control circuit unit is further configured to determine whether the remaining capacity of the first target entity erasure unit that is not fully written is sufficient to store all the data in the current entity erasure unit. If so, the memory control circuit unit is further configured to move all the data in the current entity erasure unit to the first target entity erasure unit that is not yet fully written, and If not, the memory control circuit unit is further configured to select the entity erase unit with the highest number of erases from the idle pool as the first target entity erase unit, and move all the data in the current entity erase unit to the first target entity erase unit.

16. The memory storage device of claim 10, wherein the memory control circuit unit is further configured to determine whether there is a second target entity erasure unit that is not fully written to, and If there is no unwritten second target entity erasure unit, the memory control circuit unit is further configured to select the entity erasure unit with the highest number of erasures from the idle pool as the second target entity erasure unit, and move the valid data in the current entity erasure unit to the second target entity erasure unit.

17. The memory storage device according to claim 16, wherein if there is a second target entity erasure unit that is not fully written, the memory control circuit unit is further configured to determine whether the remaining capacity of the second target entity erasure unit that is not fully written is sufficient to store the valid data in the current entity erasure unit. If so, the memory control circuit unit is further configured to move the valid data in the current entity erasure unit to the second target entity erasure unit that is not yet fully written, and If not, the memory control circuit unit is further configured to select the entity erase unit with the highest number of erases from the idle pool as the second target entity erase unit, and sequentially move the valid data in the current entity erase unit to the second target entity erase unit that is not full and the second target entity erase unit.

18. The memory storage device of claim 10, wherein the memory control circuit unit is further configured to obtain a plurality of erase counts of the plurality of physical erase units, and calculate an average erase count based on the plurality of erase counts.

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