Buck-boost chip, control method, screen module, and electronic device

Abstract

The present application relates to the technical field of chips, and relates to a buck-boost chip, a control method, a screen module, and an electronic device. The chip comprises a first voltage port, a second voltage port, a first transistor, a second transistor, and a control circuit. A first terminal of the first transistor and a first terminal of the second transistor are both coupled to the first voltage port, a second terminal of the first transistor is coupled to the second voltage port, and a second terminal of the second transistor is grounded. A control terminal of the first transistor is coupled to a first output terminal of the control circuit, and a control terminal of the second transistor is coupled to a second output terminal of the control circuit. When the chip is in a boost mode, the first voltage port is configured to couple to a power supply via an inductor, and the second voltage port is configured to couple to a load. When the chip is in a buck mode, the first voltage port is configured to couple to the load via the inductor, and the second voltage port is configured to couple to the power supply. In this way, the issue in the industry of lacking a standardized solution for power supply chips can be addressed.

Description

A buck-boost chip, a control method, a screen module, and an electronic device.

[0001] This application claims priority to Chinese Patent Application No. 202411189849.8, filed on August 27, 2024, entitled "A buck-boost chip, control method, screen module and electronic device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and in particular to a buck-boost chip, a control method, a screen module, and an electronic device. Background Technology

[0003] Organic light-emitting diode (OLED) displays in terminal devices typically require power chips to provide power. In large-size, high-brightness displays, the power consumption of the power chip is very high, and its efficiency affects the overall power efficiency of the display device. Many current terminal devices (such as mobile phones, tablets, laptops, and desktops) require high-brightness, large-size displays, making high-power, high-efficiency power chips crucial. Because different terminal devices (such as mobile phones, tablets, laptops, and desktops) have different battery architectures, the form and architecture of power chips vary. There is no standardized solution for power chips in the industry. Summary of the Invention

[0004] This application provides a buck-boost chip, a control method, a screen module, and an electronic device, which solves the problem that there is no standardized solution for power chips in the industry.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, a buck-boost chip is provided, comprising a first voltage port, a second voltage port, a first transistor, a second transistor, and a control circuit. A first terminal of the first transistor and a first terminal of the second transistor are both coupled to the first voltage port, and a second terminal of the first transistor is coupled to the second voltage port; a second terminal of the second transistor is grounded; a control terminal of the first transistor is coupled to a first output terminal of the control circuit, and a control terminal of the second transistor is coupled to a second output terminal of the control circuit. Wherein, when the chip is in boost mode, the first voltage port is used to couple to a power supply via an inductor, and the second voltage port is used to couple to a load; and, when the chip is in buck mode, the first voltage port is used to couple to a load via an inductor, and the second voltage port is used to couple to a power supply.

[0007] In the above technical solution, the buck-boost chip uses two transistors, and by changing the connection method of the external circuit of the buck-boost chip, the same chip can support both boost and buck modes. Therefore, the buck-boost chip is suitable for electronic devices supporting both single-cell and multi-cell batteries, and its application scenarios are relatively wide. In both boost and buck modes, the first and second transistors can be reused, resulting in a simpler chip circuit, smaller wafer area and cost, avoiding conduction losses caused by additional switching transistors, and improving power efficiency.

[0008] In one possible implementation of the first aspect, the chip further includes a mode port, which has a first state and a second state; the first state and the second state are different. If the mode port is in the first state, the chip is used to switch to buck mode; if the mode port is in the second state, the chip is also used to switch to boost mode. In the above possible implementations, the boost mode and buck mode of the chip are switched by fixing the mode port in hardware. For scenarios where the load can act as both a power source and a load, this fixed hardware method of switching the boost mode and buck mode of the chip cannot be used; only automatic switching or software switching methods can be employed. These scenarios require higher digital computing power, resulting in more complex, larger-scale, and more expensive digital control circuits for the chip. Compared to software switching and automatic switching methods, this implementation method offers a simpler and more reliable control method.

[0009] In one possible implementation of the first aspect, the control circuit includes a common control circuit, a buck control circuit, a boost control circuit, and a selection switch. The first output terminal of the common control circuit is coupled to the first output terminal of the control circuit, the second output terminal of the common control circuit is coupled to the second output terminal of the control circuit, the switching terminal of the common control circuit is coupled to the first terminal of the selection switch, the second terminal of the selection switch is coupled to the buck control circuit, and the third terminal of the selection switch is coupled to the boost control circuit. In the above possible implementation, since two transistors are used, both boost and buck modes of the chip can be supported. Therefore, there are two driving circuits in the control circuit for driving the transistors, and some circuits in the control circuit can be reused. The control circuits for the first and second transistors are divided into two parts: one part is a common control circuit that can be reused in both boost and buck modes of the chip, and the other part is a boost control circuit and a buck control circuit that cannot be reused in both boost and buck modes of the chip. By switching the common control circuit with the boost control circuit or the buck control circuit to form a loop in different modes using the selection switch, the control of the chip's boost or buck modes can be supported. Because the shared control circuit is reused, there is no need to set up two separate controllers for the boost and buck modes of the chip, resulting in a simpler chip circuit and smaller wafer area and cost.

[0010] In one possible implementation of the first aspect, when the first and second terminals of the selector switch are connected, a shared control circuit and a buck control circuit are used to control the first transistor to turn on and the second transistor to turn off during a first time period of a preset buck cycle, and to control the first transistor to turn off and the second transistor to turn on during a second time period of the preset buck cycle; and the control chip inputs voltage through the second voltage port and outputs voltage through the first voltage port. When the first and third terminals of the selector switch are connected, a shared control circuit and a boost control circuit are used to control the first transistor to turn off and the second transistor to turn on during a first time period of a preset boost cycle, and to control the first transistor to turn on and the second transistor to turn off during a second time period of the preset boost cycle; and the control chip inputs voltage through the first voltage port and outputs voltage through the second voltage port. In the above possible implementations, the shared control circuit and the boost control circuit or the buck control circuit are switched to form a loop in different modes, thereby supporting the control of the chip's boost mode or buck mode. This allows for the reuse of the shared control circuit, saving circuit area and cost.

[0011] In one possible implementation of the first aspect, the control circuit further includes a mode selection circuit, and the chip also includes a mode port; the selection terminal of the selection switch is coupled to the first terminal of the mode selection circuit, and the second terminal of the mode selection circuit is coupled to the mode port. The mode port includes a first state and a second state. The first state and the second state are different. If the mode port is in the first state, the mode selection circuit controls the first terminal of the selection switch to be connected to the second terminal of the selection switch; or, if the mode port is in the second state, the mode selection circuit also controls the first terminal of the selection switch to be connected to the third terminal of the selection switch. In the above possible implementations, the different states of the mode port indicate that the mode selection circuit controls the selection switch to switch to the corresponding state. This can support the switching between the chip's boost mode and buck mode, is compatible with single-cell and multi-cell battery scenarios, and has strong adaptability.

[0012] In one possible implementation of the first aspect, the chip further includes a feedback port; the common control circuit includes an output voltage sampling circuit, an error amplifier, a pulse width modulation (PWM) comparator, a flip-flop, a frequency controller, a dead-time control circuit, a first drive circuit, and a second drive circuit. The input of the common control circuit is coupled to the feedback port, which is used to couple the load. The first terminal of the output voltage sampling circuit is coupled to the input of the common control circuit, the second terminal of the output voltage sampling circuit is grounded, and the third terminal of the output voltage sampling circuit is coupled to the first input of the error amplifier; the second input of the error amplifier is used to input a reference voltage; the output of the error amplifier is coupled to the first input of the PWM comparator; the output of the PWM comparator is coupled to the first input of the flip-flop; the second input of the flip-flop is coupled to the frequency controller; the output of the flip-flop is coupled to the first input of the dead-time control circuit; the second input of the dead-time control circuit is used to input the dead time; the output of the dead-time control circuit is coupled to the inputs of the first drive circuit and the second drive circuit; the output of the first drive circuit is coupled to the first output of the common control circuit, and the output of the second drive circuit is coupled to the second output of the common control circuit. Among the above possible implementations, circuits such as the output voltage sampling circuit, error amplifier, PWM comparator, trigger, frequency controller, dead-time control circuit, first drive circuit and second drive circuit can be reused, thereby reusing most of the control loop of the control circuit, which can save a lot of chip area and optimize chip cost to a great extent.

[0013] In one possible implementation of the first aspect, the chip further includes a negative voltage circuit and a third voltage port; the shared control circuit also includes an input voltage feedforward amplifier. The third voltage port is used for power supply coupling. The input terminals of both the negative voltage circuit and the input terminal of the input voltage feedforward amplifier are coupled to the third voltage port, and the output terminal of the input voltage feedforward amplifier is coupled to the second input terminal of the PWM comparator. In the above possible implementations, adding an input voltage feedforward amplifier to the shared control circuit can improve the dynamic performance of the buck-boost chip. Furthermore, since the input terminal of the input voltage feedforward amplifier reuses the input terminal of the third negative voltage circuit, sharing the input voltage, no additional port is required, saving chip cost.

[0014] In one possible implementation of the first aspect, the control circuit further includes a current sampling circuit. The first terminal of the current sampling circuit is coupled to the first terminal of the second transistor, the second terminal of the current sampling circuit is coupled to the second terminal of the second transistor, and the third terminal of the current sampling circuit is coupled to the third input terminal of the PWM comparator. When the chip is in buck mode, the frequency controller is used to control the first transistor to turn off during a constant off-time, or to control the second transistor to turn on during a constant on-time. When the chip is in boost mode, the frequency controller is also used to control the second transistor to turn off during a constant off-time, or to control the first transistor to turn on during a constant on-time. In the above possible implementations, when the chip is in a constant on-time peak current control mode or a constant off-time valley current control mode, a boost current sampling circuit is used, further multiplexing the boost current sampling circuit, and multiple control modes can be supported.

[0015] In one possible implementation of the first aspect, the buck control circuit includes a buck loop compensation circuit, and the boost control circuit includes a boost loop compensation circuit. In the above possible implementations, the boost loop compensation circuit and the buck loop compensation circuit cannot be reused; therefore, they are connected to the control loop via a selector switch. This supports switching between the chip's boost and buck modes, is compatible with both single-cell and multi-cell battery scenarios, and has strong adaptability.

[0016] In one possible implementation of the first aspect, when the chip is in boost mode, the first voltage port is specifically used to couple the higher voltage end of the first and second terminals of the inductor, where the load voltage is higher than the power supply voltage; and when the chip is in buck mode, the first voltage port is specifically used to couple the higher voltage end of the first and second terminals of the inductor, where the power supply voltage is higher than the load voltage. In the above possible implementations, by fixing the first and second voltage ports to the higher voltage position, the switching between boost and buck modes of the chip is achieved. This ensures compatibility with both boost and buck modes of the chip, compatibility with single-cell and multi-cell battery scenarios, strong adaptability, and a relatively simple circuit connection method.

[0017] In one possible implementation of the first aspect, the first transistor is an N-type transistor, the third transistor is a P-type transistor, the second voltage port is specifically used to couple to the load through the third transistor, and the third output terminal of the control circuit is used to couple to the control terminal of the third transistor. In the above possible implementation, by placing a P-type transistor outside the buck-boost chip to prevent current leakage, both the first and second transistors inside the buck-boost chip can be implemented using N-type transistors. Since N-type transistors of similar specifications have smaller area and cost and higher efficiency, the buck-boost chip has a smaller area and cost and higher efficiency. Furthermore, this implementation can prevent current leakage and achieve short-circuit protection.

[0018] In one possible implementation of the first aspect, when the chip is in boost mode, the control circuit controls the first transistor to turn off and the second transistor to turn on during a first time period of a preset boost cycle, and controls the first transistor to turn on and the second transistor to turn off during a second time period of the preset boost cycle. The control circuit is also used to increase the preset boost cycle when the ratio of the voltage at the feedback port to the voltage at the first voltage port is less than or equal to a first preset value, or when the ratio of the voltage at the feedback port to the voltage supplied by the power supply is less than or equal to a second preset value, while the chip is in boost mode. In the above possible implementations, in application scenarios where the input and output have very small duty cycles, the on-time of the second transistor is very small, possibly lower than the minimum on-time of the second transistor, which may cause unstable output voltage. By increasing the preset boost cycle, the switching frequency of the chip in boost mode is reduced, increasing the actual on-time of the second transistor in this application scenario, and preventing the actual on-time of the second transistor from being less than the minimum on-time. This ensures that when the input voltage of the first voltage port pin1 is close to the output voltage of the second voltage port pin2, a stable output voltage can be achieved.

[0019] In one possible implementation of the first aspect, the chip further includes a chip power supply circuit, a power selection circuit, a voltage regulator, and a fourth voltage port. The fourth voltage port is used for coupling power. A first terminal of the voltage regulator is coupled to the fourth voltage port; a second terminal of the voltage regulator is coupled to a first terminal of the power selection circuit. A second terminal of the power selection circuit is coupled to the chip power supply circuit; a third terminal of the power selection circuit is coupled to a second voltage port. In the above possible implementation, the chip power supply circuit can be coupled to either the voltage regulator or the second voltage port through the power selection circuit, and the voltage regulator is coupled to the power supply through the fourth voltage port. The chip power supply circuit can select one of the voltage of the power supply and the voltage at the second voltage port as its power source. In this way, the chip power supply circuit can obtain sufficient voltage to drive the power transistor device. This implementation can support high-power buck-boost chips.

[0020] In one possible implementation of the first aspect, a power supply selection circuit is used to control the first and second terminals of the power supply selection circuit to conduct when the voltage at the fourth voltage port is higher than a specified voltage, while the chip is in boost mode. Alternatively, it controls the third and second terminals of the power supply selection circuit to conduct when the voltage at the fourth voltage port is lower than a specified voltage. In the above possible implementations, when the voltage at the fourth voltage port is higher, it can be used as the power supply voltage for the chip's power circuit; when the voltage at the fourth voltage port is lower, it can be used as the power supply voltage for the chip's power circuit. This allows for a higher voltage to be provided to the chip's power circuit, making it sufficient to drive the power transistors. Furthermore, it improves the power output capability without increasing the chip area.

[0021] In one possible implementation of the first aspect, the specified voltage is the voltage of the second voltage port. In the above possible implementations, without increasing the internal power supply area of ​​the chip, the existing output voltage is used to automatically switch the chip's power supply circuit to a high-voltage source, thereby improving the chip's power output performance.

[0022] Secondly, a control method for a buck-boost chip is provided. The chip includes a first voltage port, a second voltage port, a first transistor, a second transistor, and a control circuit. The first terminal of the first transistor and the first terminal of the second transistor are both coupled to the first voltage port. The second terminal of the first transistor is coupled to the second voltage port. The second terminal of the second transistor is grounded. The control terminal of the first transistor is coupled to the first output terminal of the control circuit. The control terminal of the second transistor is coupled to the second output terminal of the control circuit. The method includes: if it is determined that the chip is in buck mode, the control circuit controls the first transistor to turn on and the second transistor to turn off during a first time period of a preset buck cycle, and controls the first transistor to turn off and the second transistor to turn on during a second time period of the preset buck cycle; and the control chip inputs voltage through a second voltage port and outputs voltage through a first voltage port; wherein the first voltage port is coupled to a power supply through an inductor, and the second voltage port is used to couple to a load; or, if it is determined that the chip is in boost mode, the control circuit controls the first transistor to turn off and the second transistor to turn on during a first time period of a preset boost cycle, and controls the first transistor to turn on and the second transistor to turn off during a second time period of the preset boost cycle; and the control chip inputs voltage through a first voltage port and outputs voltage through a second voltage port; wherein the first voltage port is coupled to a load through an inductor, and the second voltage port is used to couple to a power supply.

[0023] In one possible implementation of the second aspect, the chip further includes a mode port. The mode port includes a first state and a second state; the first state and the second state are different. The method further includes: detecting the state of the mode port; if the mode port is in the first state, determining that the chip is in buck mode; if the mode port is in the second state, determining that the chip is in boost mode.

[0024] In one possible implementation of the second aspect, the method further includes: when the chip is in buck mode, the control circuit controls the first transistor to turn off during a constant off-time, or controls the second transistor to turn on during a constant on-time. When the chip is in boost mode, the control circuit controls the second transistor to turn off during a constant off-time, or controls the first transistor to turn on during a constant on-time.

[0025] In one possible implementation of the second aspect, the method further includes: when the chip is in boost mode, the control circuit increases the preset boost cycle when the ratio of the voltage at the feedback port to the voltage at the first voltage port is less than or equal to a first preset value, or when the ratio of the voltage at the feedback port to the voltage provided by the power supply is less than or equal to a second preset value.

[0026] In one possible implementation of the second aspect, the chip further includes a chip power supply circuit, a power supply selection circuit, and a fourth voltage port. The fourth voltage port is used for coupling power. The method further includes: when the chip is in boost mode, the power supply selection circuit controls the chip power supply circuit to receive the voltage at the fourth voltage port when the voltage at the fourth voltage port is higher than a specified voltage; or, when the voltage at the fourth voltage port is lower than a specified voltage, controlling the chip power supply circuit to receive the voltage at the second voltage port.

[0027] In one possible implementation of the second aspect, the specified voltage is the voltage of the second voltage port.

[0028] Thirdly, a screen module is provided, the screen module including a screen and a buck-boost chip provided in the first aspect or any possible implementation of the first aspect, the load being the screen.

[0029] Fourthly, an electronic device is provided, comprising a power supply and a buck-boost chip provided in the first aspect or any possible implementation thereof.

[0030] Understandably, the control method, screen module and electronic device of any of the buck-boost chips provided above are all applied to the corresponding buck-boost chips provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects of the corresponding chips provided above, and will not be repeated here. Attached Figure Description

[0031] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0032] Figure 2 is a schematic diagram of the structure of a power chip provided in an embodiment of this application;

[0033] Figure 3 is a schematic diagram of the structure of a first power chip provided in an embodiment of this application;

[0034] Figure 4 is a schematic diagram of the structure of a second power chip provided in an embodiment of this application;

[0035] Figure 5 is a schematic diagram of a step-up / step-down circuit provided in an embodiment of this application;

[0036] Figure 6 is a schematic diagram of a buck-boost chip provided in an embodiment of this application;

[0037] Figure 7 is a schematic diagram of a buck-boost chip provided in an embodiment of this application;

[0038] Figure 8 is a schematic diagram of a buck-boost chip provided in an embodiment of this application.

[0039] Figure 9 is a schematic diagram of a buck-boost chip provided in an embodiment of this application;

[0040] Figure 10 is a schematic diagram of a partial structure of a control circuit provided in an embodiment of this application;

[0041] Figure 11 is a schematic diagram of a buck-boost chip provided in an embodiment of this application;

[0042] Figure 12 is a schematic diagram of a buck-boost chip provided in an embodiment of this application;

[0043] Figure 13 is a schematic diagram of a buck-boost chip provided in an embodiment of this application;

[0044] Figure 14 is a schematic diagram of a buck-boost chip provided in an embodiment of this application.

[0045] Figure 15 is a schematic diagram of a coupling method for a chip power supply circuit provided in an embodiment of this application;

[0046] Figure 16 is a schematic diagram of a coupling method for a chip power supply circuit according to an embodiment of this application;

[0047] Figure 17 is a schematic flowchart of a control method for a buck-boost chip provided in an embodiment of this application;

[0048] Figure 18 is a schematic flowchart of a control method for a buck-boost chip provided in an embodiment of this application;

[0049] Figure 19 is a schematic flowchart of a control method for a buck-boost chip provided in an embodiment of this application. Detailed Implementation

[0050] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0051] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0052] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0053] First, let me explain some of the basic concepts involved in this application:

[0054] A display device is a device used to present information or images. Display devices are widely used in various applications, such as tablets, computers, televisions, mobile phones, projectors, and other electronic devices. With the evolution of materials and technology, various display devices with small weight and size have been gradually developed. Types of display devices include at least liquid crystal displays (LCDs), field emission displays, plasma display panels (PDPs), and organic light-emitting diode (OLED) displays. Compared to traditional liquid crystal displays, organic light-emitting diode (OLED) displays have advantages such as faster response time, superior color purity and brightness, higher contrast, and wider viewing angles. Generally, OLED display devices can be divided into passive matrix OLEDs (PMOLEDs) and active matrix OLEDs (AMOLEDs) based on their driving method. AMOLEDs are driven by thin-film transistors (TFTs), which include storage capacitors, thus enabling large-size and high-resolution display devices. AMOLED displays can be manufactured much larger than PMOLED displays and are not limited by size and resolution. Therefore, AMOLED displays are considered the future direction of display technology. AMOLED displays have pixels arranged in a matrix, each pixel including an organic light-emitting (EL) element. AMOLED displays also have corresponding driving thin-film transistors for controlling light emission.

[0055] An EL power supply refers to the power supply used to provide a positive voltage ELVDD and a negative voltage ELVSS to each EL element. The power supply providing ELVDD can be called a positive voltage power supply circuit, and the power supply providing ELVSS can be called a negative voltage power supply circuit. The higher the brightness and the larger the size of an AMOLED display, the higher the power and the greater the number of organic light-emitting EL elements, thus increasing the power demand on the EL power supply. The power system of an AMOLED display device consists of multiple types of power supplies, such as power supplies for EL elements, power supplies for computing, and power supplies for logic and the system. Among these, the power supply for EL elements has the highest power, requiring even higher-power EL power chips for devices such as tablets and laptops with large AMOLED screens. Since the EL power supply accounts for the largest proportion of power in large-size, high-brightness AMOLED display devices, the efficiency of the EL power chip almost determines the overall power efficiency of the AMOLED display device. Currently, electronic devices such as mobile phones, tablets, laptops, and desktop computers have a large demand for high-brightness, large-size AMOLED displays, thus creating a strong demand for high-power, high-efficiency EL power chips. Meanwhile, due to the different battery architectures of various electronic devices such as mobile phones, tablets, and laptops, EL power chip solutions vary in form and architecture, and there is no standardized high-efficiency solution in the industry.

[0056] This application provides an electronic device, which can be a mobile phone, tablet computer, laptop computer, desktop monitor, car display, etc. As shown in FIG1, the electronic device 1000 includes a processor 100, a power supply device 200, and a display module 300. The display module 300 includes a power chip 310 and a display device 320. The power chip 310 can be disposed on a printed circuit board (PCB). For example, the display module 300 can be a screen module, and the display device 320 can be a screen. Optionally, the power chip 310 may not be disposed in the display module 300. The processor 100 is coupled to the display device 320, and both the power supply device 200 and the display device 320 are coupled to the power chip 310. The processor 100 is used to transmit data with the display device 320 and instruct the display device 320 to display information or images. The power chip 310 can be a chip that provides ELVDD and ELVSS to the display device 320. Power supply device 200 supplies power to power chip 310, which converts the voltage provided by power supply device 200 and sends the converted voltage to display device 320. Figure 2 shows a possible example of the display module 300 in Figure 1. Power chip 310 may include a positive voltage power supply circuit 311 and a negative voltage power supply circuit 312. The positive voltage power supply circuit 311 and the negative voltage power supply circuit 312 are coupled to external transistors and inductors of power chip 310. Display device 320 includes pixels arranged in a matrix, each pixel coupled with ELVDD (shaded area) and ELVSS (unshaded area). Positive voltage power supply circuit 311 provides ELVDD to display device 320, and negative voltage power supply circuit 312 provides ELVSS to display device 320. Each pixel may include two transistors, one capacitor, and one EL element. The specific coupling method of the electronic components of the screen module can be referred to Figure 2.

[0057] In some possible implementations, the positive voltage power supply circuit 311 in the power chip 310 of FIG2 can be a boost circuit. The positive voltage power supply circuit 311 is used to boost the power supplied by the power supply device 200 and then send it to the display device 320.

[0058] In some examples, as shown in Figure 3, the display module 300 may also include an inductor, and the first power supply chip 310A may include a first positive voltage circuit 311A ​​and a first negative voltage circuit 312A. The power supply device 200 may be a single-cell battery power supply 200A, which can be a power supply composed of a single battery or multiple batteries connected in parallel. The display device 320 is not shown in Figure 3; however, the display device 320 and its coupling method can be referred to in Figure 2. The first positive voltage circuit 311A ​​includes two transistors and a boost controller 400A. The specific coupling method of these electronic devices is shown in Figure 3. The boost controller 400A is used to control the two transistors to turn on or off. For example, the boost controller 400A controls the upper transistor to turn off and the lower transistor to turn on, so that the single-cell battery power supply 200A can charge the inductor. Alternatively, the boost controller 400A controls the upper transistor to turn on and the lower transistor to turn off, so that the single-cell battery power supply 200A and the inductor can discharge together, thereby sending the boosted ELVDD voltage.

[0059] In this embodiment, the first power chip 310A is typically used in small-sized electronic devices with small display devices (such as screens), such as tablets and mobile phones. The voltage provided by the single-cell battery power supply 200A is typically less than 4.6V. The first power chip 310A boosts this lower voltage to power the small-sized electronic device. However, the first power chip 310A has the following problems: First, since the first positive voltage circuit 311A ​​is a boost circuit, its input voltage needs to be lower than its output voltage. The first power chip 310A needs to couple the lower voltage of the single-cell battery power supply 200A, meaning the electronic device is only compatible with the single-cell battery power supply 200A, limiting its application scenarios. This embodiment cannot accommodate both the input voltage of the single-cell battery power supply 200A and the multi-cell battery power supply (which can be a power supply consisting of two or more batteries connected in series). Second, the voltage provided by the single-cell battery power supply 200A to the first power chip 310A is too low to drive the power transistor devices of the first negative voltage circuit 312A. Therefore, this embodiment cannot support power chips with higher power. Third, the two transistors inside the first positive voltage circuit 311A ​​cannot both be N-type metal-oxide-semiconductor (NMOS). For example, the upper transistor is a P-type metal-oxide-semiconductor (PMOS). If both the upper and lower transistors are NMOS, short-circuit protection cannot be achieved. However, PMOS has a larger area and lower efficiency. Therefore, the first power chip 310A has a large wafer area and low power efficiency. Fourth, when the input voltage and output voltage of the first positive voltage circuit 311A ​​are close, it cannot output stably, posing a risk of water ripple.

[0060] In some other possible implementations, the positive voltage power supply circuit 311 in the power chip 310 of FIG2 can be a buck circuit. The positive voltage power supply circuit 311 is used to step down the power supplied by the power supply device 200 and then send it to the display device 320.

[0061] In some examples, as shown in Figure 4, the display module 300 may also include an inductor, and the second power supply chip 310B may include a second positive voltage circuit 311B and a second negative voltage circuit 312B. The power supply device 200 may be a multi-cell battery power supply 200B, which may be a power supply consisting of two or more cells connected in series. The display device 320 is not shown in Figure 3; however, the display device 320 and its coupling method can be referred to in Figure 2. The second positive voltage circuit 311B includes two transistors and a buck controller 400B. The specific coupling method of these electronic devices is shown in Figure 3. The buck controller 400B is used to control the two transistors to turn on or off. For example, the buck controller 400B controls the upper transistor to turn on and the lower transistor to turn off, so that the multi-cell battery power supply 200B can charge the inductor and provide the bucked ELVDD voltage to the display device 320. Alternatively, the buck controller 400B controls the upper transistor to turn off and the lower transistor to turn on, so that the inductor discharges.

[0062] In this embodiment, the second power chip 310B is typically used in large-sized electronic devices with large display devices (such as screens), such as laptops. The voltage provided by the multi-cell battery power supply 200B is typically greater than 5V. The second power chip 310B steps down the lower voltage to power smaller electronic devices. However, the second power chip 310B has the following problems: because the second positive voltage circuit 311B is a step-down circuit, its input voltage needs to be higher than its output voltage. The second power chip 310B needs to couple with the higher-voltage multi-cell battery power supply 200B, thus limiting the application scenarios of the electronic device to one that is compatible with the multi-cell battery power supply 200B.

[0063] In some other possible implementations, the positive voltage power supply circuit 311 in the power chip 310 of FIG2 can be a buck-boost circuit. The buck-boost circuit can be a circuit that can both boost and buck voltage. The positive voltage power supply circuit 311 is used to boost or buck the power supplied by the power supply device 200 and send it to the display device 320 according to the needs of the display device 320.

[0064] In some examples, Figure 5 illustrates a possible example of a buck-boost circuit. This circuit includes four transistors (transistor Q1, transistor Q2, transistor Q3, and transistor Q4), an inductor L1, and an input power supply that provides the input voltage Vin. The specific coupling of the individual components can be seen in Figure 5. This buck-boost circuit requires two controllers, such as a boost controller and a buck controller. The controllers control the four transistors to turn on or off, thus switching the circuit to boost or buck mode. For example, in buck mode, transistor Q4 remains on, and transistor Q3 remains off. During the first period of buck mode, transistor Q1 is on, transistor Q2 is off, the input power supply charges inductor L1, and the output voltage Vout is reduced. During the second period of buck mode, transistor Q2 is on, transistor Q1 is off, and inductor L1 discharges. Alternatively, in boost mode, transistor Q1 remains on, and transistor Q2 remains off. During the first period when the circuit is in boost mode, control transistor Q3 is turned on and control transistor Q4 is turned off, and the input power supply charges inductor L1. During the second period when the circuit is in boost mode, control transistor Q3 is turned off and control transistor Q4 is turned on, and the input power supply and inductor L1 together output the boosted output voltage Vout.

[0065] In this embodiment, the buck-boost circuit requires four transistors, each with high current-carrying capacity and voltage withstand capability, resulting in a larger wafer area and higher cost. Furthermore, while the buck-boost circuit only requires two switching transistors for both boost and buck operations, current flows through an additional switching transistor, generating additional conduction losses and lower power efficiency. Moreover, because four transistors are required, the chip needs two separate controllers to manage the circuit in different modes, leading to complex circuitry and a larger overall area.

[0066] In some other possible implementations, the positive voltage power supply circuit 311 in the power chip 310 of FIG2 can be a circuit that supports boost or buck voltage. By changing the coupling method between the power chip 310 port and the power supply device 200 and the display device 320, the power chip 310 can achieve either boost or buck voltage functionality.

[0067] In some examples, as shown in Figures 6(a) and 6(b), the buck-boost chip 310C can be applied to an electronic device 1000 including a display device 320. For example, the buck-boost chip 310C can be the power chip 310 in Figure 2. The buck-boost chip 310C can also be applied to chargers, double data rate synchronous dynamic random access memory (DDR), central processing units (CPUs), and related power supply fields. The following description uses the power chip 310 in Figure 2 as an example. This chip includes a first voltage port pin1, a second voltage port pin2, a first transistor T1, a second transistor T2, and a control circuit 400C. Exemplarily, the first voltage port pin1, the second voltage port pin2, the first transistor T1, the second transistor T2, and the control circuit 400C are located in a third positive voltage circuit 311C. The chip also includes a third negative voltage circuit 312C and a third voltage port pin3, which is used to couple the power supply 200C. Control circuit 400C is used to control the on / off state of the first transistor T1 and the second transistor T2. Control circuit 400C includes a boost control loop, thereby supporting the buck-boost chip 310C in boost mode; control circuit 400C also includes a buck control loop, thereby supporting the buck-boost chip 310C in buck mode. The chip is externally coupled with inductor L2. In this embodiment, "port" can refer to a pin of the chip. The transistors in this embodiment are used as switching transistors, which are power devices in a direct current-to-direct current (DC-DC) converter circuit used to control the switching of current paths, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). The first transistor T1 and the second transistor T2 can form a switching half-bridge (or power half-bridge), which is a power circuit unit in a DC-DC circuit composed of two switching transistors, controlled to periodically switch to support the buck-boost chip 310C in both boost and buck modes. The first transistor T1 can be called the high-side (HS) half-bridge transistor, and the second transistor T2 can be called the low-side (LS) half-bridge transistor. The first transistor T1, the second transistor T2, and the inductor L2 constitute the power phase (the circuit they form can be called a power circuit). The power phase is the power section of a DC-DC converter circuit, typically composed of an inductor and two or more switching transistors, used to convert and transmit electrical energy under the control of the control circuit 400C.The first terminal of the first transistor T1 and the first terminal of the second transistor T2 are coupled to the switching pin (SW PIN) of the switching half-bridge. The SW PIN is the node between the upper and lower switching transistors of the switching half-bridge in the DC-DC circuit, and is usually connected to the external inductor L2 through a chip pin. The SW PIN is coupled to the first voltage port pin1. The second terminal of the first transistor T1 is coupled to the second voltage port pin2. The second terminal of the second transistor T2 is grounded. The control terminal of the first transistor T1 is coupled to the first output terminal of the control circuit 400C, and the control terminal of the second transistor T2 is coupled to the second output terminal of the control circuit 400C. The third negative voltage circuit 312C is coupled to the third voltage port pin3.

[0068] For example, as shown in Figure 6(a), when the buck-boost chip 310C is in boost mode, the first voltage port pin1 is used to couple to the power supply 200C (which may be the aforementioned power supply device 200) through the inductor L2, and the second voltage port pin2 is used to couple to the load 320C (which may be the aforementioned display device 320 or other devices requiring power). When the buck-boost chip 310C is in boost mode, the power supply 200C may be a single-cell battery. For example, during the first period when the buck-boost chip 310C is in boost mode, the control circuit 400C controls the first transistor T1 to turn off and the second transistor T2 to turn on, and the power supply 200C charges the inductor L2. During the second period when the buck-boost chip 310C is in boost mode, the control circuit 400C controls the first transistor T1 to turn on and the second transistor T2 to turn off, the inductor L2 discharges, and the power supply 200C and the inductor L2 together supply power to the load 320C, thereby sending the boosted voltage through the second voltage port pin2. As shown in Figure 6(b), when the buck-boost chip 310C is in buck mode, the first voltage port pin1 is used to couple to the load 320C through inductor L2, and the second voltage port pin2 is used to couple to the power supply 200C. When the buck-boost chip 310C is in buck mode, the power supply 200C can be a series of batteries. For example, during the first period when the buck-boost chip 310C is in buck mode, the control circuit 400C controls the first transistor T1 to turn on and the second transistor T2 to turn off, the power supply 200C charges the inductor L2 and supplies power to the load 320C, thereby sending the stepped-down voltage to the load 320C through the inductor L2. During the second period when the buck-boost chip 310C is in buck mode, the control circuit 400C controls the first transistor T1 to turn off and the second transistor T2 to turn on, and the inductor L2 discharges.

[0069] In this embodiment, the buck-boost chip 310C uses two transistors, and by changing the connection method of the external circuit of the buck-boost chip 310C, it can support either boost mode or buck mode. Therefore, the buck-boost chip 310C is suitable for both electronic devices supporting single-cell batteries and electronic devices supporting multiple-cell batteries, making its application scenarios quite wide. In both boost and buck modes, the buck-boost chip 310C can reuse the first transistor T1 and the second transistor T2, eliminating the need for four transistors. This simplifies the chip circuit, reduces wafer area and cost, avoids conduction losses caused by additional switching transistors, and improves power supply efficiency.

[0070] In some possible implementations, the first voltage port pin1 couples the higher voltage end of the first and second terminals of the inductor L2, and the second voltage port pin2 couples the higher voltage end of the load 320C and the power supply 200C.

[0071] In some examples, when the buck-boost chip 310C is in boost mode, the first voltage port pin1 is specifically used to couple the higher voltage of the first and second terminals of inductor L2. For the second voltage port pin2, the voltage of load 320C is higher than the voltage of power supply 200C. And, when the buck-boost chip 310C is in buck mode, the first voltage port pin1 is specifically used to couple the higher voltage of the first and second terminals of inductor L2. For the second voltage port pin2, the voltage of power supply 200C is higher than the voltage of load 320C.

[0072] For example, as shown in Figure 6(a), when the buck-boost chip 310C is in boost mode, in the loop from power supply 200C to power circuit and then to load 320C, the voltage on the right side of inductor L2 is greater than the voltage on the left side of inductor L2, and the voltage received by load 320C is greater than the voltage provided by power supply 200C. As shown in Figure 6(b), when the buck-boost chip 310C is in buck mode, in the loop from power supply 200C to power circuit and then to load 320C, the voltage on the right side of inductor L2 is greater than the voltage on the left side of inductor L2, and the voltage provided by power supply 200C is greater than the voltage received by load 320C.

[0073] In this embodiment, by fixing the first voltage port pin1 and the second voltage port pin2 to a higher voltage position, the buck-boost chip 310C can switch between boost and buck modes. Therefore, the buck-boost chip 310C is compatible with both boost and buck modes. This embodiment is compatible with both single-cell and multi-cell battery scenarios, exhibiting strong adaptability and a relatively simple circuit connection method.

[0074] In some possible implementations, as shown in Figures 7(a) and 7(b), the buck-boost chip 310C further includes a mode pin. The mode pin has a first state and a second state. The first state and the second state are different. If the mode pin is in the first state, the buck-boost chip 310C is used to switch to buck mode; if the mode pin is in the second state, the buck-boost chip 310C is also used to switch to boost mode.

[0075] For example, the first state indicates that the buck-boost chip 310C switches to buck mode, and the second state indicates that the buck-boost chip 310C switches to boost mode. For instance, the first state could be a floating mode pin, and the second state could be a grounded mode pin. In some scenarios, such as when a computer is charging a phone simultaneously with a charger, the buck-boost circuit in the computer can be as shown in Figure 5. The computer's battery serves as both the power source for the phone and the load for charging the computer. In this scenario, switching between boost and buck modes requires software switching or automatic switching within the buck-boost circuit. Switching via a fixed mode pin is not possible in this scenario.

[0076] In this embodiment, during the computer charging scenario, the computer battery serves as both a power source and a load. Therefore, a hardware-fixed method using a mode pin cannot be employed to switch between the computer's boost and buck modes. This scenario demands high digital computing power, resulting in more complex, larger-scale, and more expensive digital control circuitry for the chip. In contrast, this embodiment uses a hardware-fixed mode pin to switch between the boost and buck modes of the 310C buck-boost chip. Compared to software switching and automatic switching, this embodiment offers a simpler and more reliable control method.

[0077] In some possible implementations, some circuits in the control circuit 400C can be reused in both the boost and buck modes of the buck-boost chip 310C. This implementation does not require a separate boost controller for the boost mode and a separate buck controller for the buck mode, as shown in Figure 5.

[0078] In some examples, as shown in Figures 7(a) and 7(b), the control circuit 400C includes a common control circuit 410C, a boost control circuit 420C, a buck control circuit 430C, and a selector switch 440C. The first output terminal of the common control circuit 410C is coupled to the first output terminal of the control circuit 400C; the second output terminal of the common control circuit 410C is coupled to the second output terminal of the control circuit 400C; the switching terminal of the common control circuit 410C is coupled to the first terminal of the selector switch 440C; the second terminal of the selector switch 440C is coupled to the buck control circuit 430C; and the third terminal of the selector switch 440C is coupled to the boost control circuit 420C.

[0079] For example, the shared control circuit 410C and the boost control circuit 420C are used to jointly perform the function of controlling the buck-boost chip 310C to be in boost mode, and the shared control circuit 410C and the buck control circuit 430C are used to jointly perform the function of controlling the buck-boost chip 310C to be in buck mode. The selector switch 440C is used to connect the loop between the shared control circuit 410C and the boost control circuit 420C, or the selector switch 440C is used to connect the loop between the shared control circuit 410C and the buck control circuit 430C.

[0080] In this embodiment, since only two transistors are needed to support the buck-boost chip 310C in both boost and buck modes, two drive circuits for driving the transistors are used in the control circuit 400C, and some circuits in the control circuit 400C can be reused. The control circuit 400C for the first transistor T1 and the second transistor T2 is divided into two parts: one part is a shared control circuit 410C that can be reused in both boost and buck modes of the buck-boost chip 310C; the other part is a boost control circuit 420C and a buck control circuit 430C that cannot be reused in both boost and buck modes of the buck-boost chip 310C. By switching the shared control circuit 410C with the boost control circuit 420C or the buck control circuit 430C in different modes using a selection switch 440C, the buck-boost chip 310C can be controlled to be in either boost or buck mode. Because the shared control circuit 410C is reused, there is no need to set up two separate controllers for the boost and buck modes of the buck-boost chip 310C, resulting in a simpler chip circuit and smaller wafer area and cost.

[0081] In some examples, as shown in Figure 7(a), when the first terminal of the selector switch 440C is connected to the third terminal of the selector switch 440C, the control circuit 410C and the boost control circuit 420C are used to control the first transistor T1 to turn off and the second transistor T2 to turn on during the first time period of the preset boost cycle, and to control the first transistor T1 to turn on and the second transistor T2 to turn off during the second time period of the preset boost cycle; and to control the buck-boost chip 310C to input voltage through the first voltage port pin1 and output voltage through the second voltage port pin2. As shown in Figure 7(b), when the first terminal of the selector switch 440C is connected to the second terminal of the selector switch 440C, the shared control circuit 410C and the buck control circuit 430C are used to control the first transistor T1 to be turned on and the second transistor T2 to be turned off during the first time period of the preset buck cycle, and to control the first transistor T1 to be turned off and the second transistor T2 to be turned on during the second time period of the preset buck cycle; and to control the buck-boost chip 310C to input voltage through the second voltage port pin2 and output voltage through the first voltage port pin1.

[0082] In this embodiment, the shared control circuit 410C is switched to form a loop with either the boost control circuit 420C or the buck control circuit 430C in different modes, thereby supporting the control of the buck-boost chip 310C to be in either boost or buck mode. This allows for the reuse of the shared control circuit 410C, saving circuit area and cost.

[0083] In some examples, as shown in Figures 7(a) and 7(b), the control circuit 400C also includes a mode selection circuit 450C. The selection terminal of the selection switch 440C is coupled to the first terminal of the mode selection circuit 450C, and the second terminal of the mode selection circuit 450C is coupled to the mode port (mode pin). If the mode selection circuit 450C is in the first state, it controls the first terminal of the selection switch 440C to be connected to the second terminal; or, if the mode selection circuit 450C is in the second state, it controls the first terminal of the selection switch 440C to be connected to the third terminal.

[0084] For example, the mode selection circuit 450C may include a level detection circuit 451C, which generates a corresponding level based on the state of the mode port mode pin (e.g., floating, grounded, connected to a high level, or connected to a low level). For instance, the level detection circuit 451C outputs a high level when the mode port mode pin is in a first state, which controls the first terminal of the selection switch 440C to conduct with its second terminal. The level detection circuit 451C also outputs a low level when the mode port mode pin is in a second state, which controls the first terminal of the selection switch 440C to conduct with its third terminal.

[0085] In this embodiment, the mode port mode pin being in either the first or second state can instruct the mode selection circuit 450C to control the selection switch 440C to switch to the corresponding state. This supports switching between boost and buck modes for the buck-boost chip 310C, making it compatible with both single-cell and multi-cell battery scenarios, and offering strong adaptability.

[0086] In some examples, as shown in Figures 8 and 9, the chip also includes a feedback port fb pin (also referred to as the output feedback pin, FB pin). The common control circuit 410C includes an output voltage sampling circuit 411C, an error amplifier 412C, a pulse width modulation (PWM) comparator 413C, a flip-flop 414C, a frequency controller 415C, a dead-time control circuit 416C, a first drive circuit 417C, and a second drive circuit 418C. The input of the common control circuit 410C is coupled to the feedback port fb pin, which is used to couple the load 320C. The first terminal of the output voltage sampling circuit 411C is coupled to the input terminal of the common control circuit 410C, the second terminal of the output voltage sampling circuit 411C is grounded, and the third terminal of the output voltage sampling circuit 411C is coupled to the first input terminal of the error amplifier 412C. The second input terminal of the error amplifier 412C is used to input the reference voltage Vref. The output terminal of the error amplifier 412C is coupled to the first input terminal of the PWM comparator 413C. The output terminal of the PWM comparator 413C is coupled to the first input terminal of the trigger 414C. The second input terminal of the trigger 414C is coupled to the frequency controller 415C. The output terminal of the trigger 414C is coupled to the first input terminal of the dead-time control circuit 416C. The second input terminal of the dead-time control circuit 416C is used to input the dead time. The output terminal of the dead-time control circuit 416C is coupled to the input terminal of the first drive circuit 417C and the input terminal of the second drive circuit 418C. The output terminal of the first drive circuit 417C is coupled to the first output terminal of the common control circuit 410C, and the output terminal of the second drive circuit 418C is coupled to the second output terminal of the common control circuit 410C.

[0087] For example, when the second voltage port pin2 or the first voltage port pin1 is used as a voltage output terminal coupled to the load 320C, it is used to output voltage feedback information. The feedback port fb pin is used to couple the output voltage signal and transmit the output voltage feedback information to the output voltage sampling circuit 411C. Referring to Figure 10(a), the output voltage sampling circuit 411C may include resistors Rfb1 and Rfb2. The first end of resistor Rfb1 is coupled to the feedback port fb pin, and the second end of resistor Rfb1 and the first end of resistor Rfb2 are both coupled to the error amplifier 412C. The second end of resistor Rfb2 is grounded. The error amplifier 412C can be used for DC-DC circuit voltage control, where the sampled output voltage of the controlled circuit is fed back and compared with a stable reference voltage Vref. The PWM comparator 413C can be used for DC-DC circuit loop control. The main principle of the duty cycle adjustable PWM wave is that the DC wave and the triangular wave are compared by the comparator, so that the comparator output terminal outputs a PWM wave to drive the switching transistor. The flip-flop 414C can be an RS flip-flop 414C, or a reset / set flip-flop 414C, used for DC-DC circuit loop control to toggle the drive signal for the switching transistor. The frequency controller 415C can be used to generate a fixed / variable frequency based on the chip's internal clock signal and other timing information. The dead-time control circuit 416C can be used for DC-DC circuit loop control to control the time interval between the switching transistor's on and off. The drive circuit can be the driving section of the switching transistor in the DC-DC circuit, used to generate control signals for turning the power phase switching transistor on or off.

[0088] In this embodiment, the output voltage sampling circuit 411C, error amplifier 412C, PWM comparator 413C, trigger 414C, frequency controller 415C, dead-time control circuit 416C, first drive circuit 417C and second drive circuit 418C can be reused, thereby reusing most of the control loop of the control circuit 400C, which can save a lot of chip area and optimize chip cost to a great extent.

[0089] In some examples, as shown in Figures 8 and 9, the common control circuit 410C also includes an input voltage feedforward amplifier 419C. A third voltage port pin 3 is used to couple the power supply 200C. The input of the third negative voltage circuit 312C and the input of the input voltage feedforward amplifier 419C are both coupled to the third voltage port pin 3, and the output of the input voltage feedforward amplifier 419C is coupled to the second input of the PWM comparator 413C.

[0090] For example, due to the isolation provided by inductor L2, sampling the input voltage information requires an additional port. Using the input voltage information of the third negative voltage circuit 312C as a feedforward voltage in the loop can enhance the dynamic performance of the third positive voltage circuit 311C. For instance, when the buck-boost chip 310C is in boost mode, the input voltage information of the third voltage port pin3 can be used to control the third positive voltage circuit 311C; when the buck-boost chip 310C is in buck mode, the input voltage information of the second voltage port pin2 or the third voltage port pin3 can be used to control the third positive voltage circuit 311C.

[0091] In this embodiment, adding an input voltage feedforward amplifier 419C to the common control circuit 410C can improve the dynamic performance of the buck-boost chip 310C. Furthermore, the input terminal of the input voltage feedforward amplifier 419C reuses the input terminal of the third negative voltage circuit 312C, sharing the same input voltage, thus avoiding the need for additional ports and saving chip costs.

[0092] In some examples, as shown in Figures 8 and 9, the selector switch 440C may include a first switch 441C, the boost control circuit 420C may include a boost loop compensation circuit 421C, and the buck control circuit 430C may include a buck loop compensation circuit 431C. A first switching terminal of the common control circuit 410C (e.g., the output of the error amplifier 412C) is coupled to a first terminal of the first switch 441C, a second terminal of the first switch 441C is coupled to the buck loop compensation circuit 431C, and a third terminal of the first switch 441C is coupled to the boost loop compensation circuit 421C. The selection terminal of the first switch 441C is coupled to a first terminal of the mode selection circuit 450C.

[0093] In some examples, as shown in Figures 8 and 9, the buck-boost chip 310C may further include an adder 460C in the current-mode control loop. The selector switch 440C may further include a second switch 442C and a third switch 443C. The boost control circuit 420C may further include a boost current sampling circuit 422C and a boost slope compensation circuit 423C, and the buck control circuit 430C may further include a buck current sampling circuit 432C and a buck slope compensation circuit 433C. The first terminal of the adder 460C is coupled to the third input terminal of the PWM comparator 413C, the second terminal of the adder 460C is coupled to the second switching terminal of the common control circuit 410C, and the third terminal of the adder 460C is coupled to the third switching terminal of the common control circuit 410C. The second switching terminal of the common control circuit 410C is coupled to the first terminal of the second switch 442C, and the third switching terminal of the common control circuit 410C is coupled to the first terminal of the third switch 443C. The second terminal of the second switch 442C is coupled to the buck current sampling circuit 432C, and the third terminal of the second switch 442C is coupled to the boost current sampling circuit 422C. The selection terminal of the second switch 442C is coupled to the first terminal of the mode selection circuit 450C. The second terminal of the third switch 443C is coupled to the buck slope compensation circuit 433C, and the third terminal of the third switch 443C is coupled to the boost slope compensation circuit 423C. The selection terminal of the third switch 443C is coupled to the first terminal of the mode selection circuit 450C.

[0094] For example, different compensation parameters are set for different modes (such as boost mode and buck mode) to achieve the corresponding functions. The loop compensation circuit can be the control part in a DC-DC circuit, usually composed of a sampling circuit, an error amplifier, a comparator, resistors and capacitors, used to generate control signals to determine the on and off of the switching transistors in the power phase. The loop compensation circuit can be a type II compensator, which can be used for loop control of DC-DC circuits, consisting of a loop compensation network composed of two capacitors and one resistor. Please refer to Figure 10(b), the buck loop compensation circuit 431C includes a resistor Rcomp1, a capacitor Ccomp1 and a capacitor connected in parallel with the resistor Rcomp1. The first end of the resistor Rcomp1 is coupled to the first switch 441C, the second end of the resistor Rcomp1 is coupled to the capacitor Ccomp1, and the capacitor Ccomp1 is grounded. Referring to Figure 10(c), the boost loop compensation circuit 421C includes a resistor Rcomp2, a capacitor Ccomp2, and a capacitor connected in parallel with the resistor Rcomp2. The first terminal of the resistor Rcomp2 is coupled to the first switch 441C, and the second terminal of the resistor Rcomp2 is coupled to the capacitor Ccomp2, which is grounded. The mode selection circuit 450C can select different compensation parameters for the loop compensation circuit by switching the conducting ends of the first switch 441C, corresponding to the resistance and capacitance values ​​of the compensation circuit required for the buck and boost transfer functions, respectively. The mode selection circuit 450C can select the peak current information of the input loop by switching the conducting ends of the second switch 442C, converting the voltage drop of the second transistor T2 in buck mode and the voltage drop of the first transistor T1 in boost mode into the peak current information required by the loop, respectively. The mode selection circuit 450C can select the slope compensation information of the input loop by switching the conducting ends of the third switch 443C, corresponding to different slope compensation values ​​required for buck and boost modes, respectively.

[0095] For example, the calculation method for the loop compensation resistor Rcomp (e.g., resistors Rcomp1 and Rcomp2) can be found in:

[0096] Where fcomp_p is the pole frequency of the compensation circuit, fcomp_z is the zero frequency of the compensation circuit, gm1 is the gain of the error amplifier 412C, and fBW is the bandwidth of the compensation circuit.

[0097] The calculation method for loop compensation capacitor Ccomp (e.g., capacitors Ccomp1 and Ccomp2) can be found here:

[0098] When the 310C buck converter is in buck mode, the slope compensation (amperes per second) range is:

[0099] Where D is the duty cycle of the transistor, and L is the inductance value (in microhenries).

[0100] When the 310C buck-boost chip is in boost mode, the slope compensation (amperes per second) ranges as follows:

[0101] Where V is the voltage output to load 320C.

[0102] In this embodiment, the boost loop compensation circuit 421C and buck loop compensation circuit 431C, the boost current sampling circuit 422C and buck current sampling circuit 432C, and the boost ramp compensation circuit 423C and buck ramp compensation circuit 433C cannot be reused. Therefore, they are connected to the control loop via a selector switch 440C. This allows for switching between boost and buck modes of the buck-boost chip 310C, making it compatible with both single-cell and multi-cell battery scenarios, and providing strong adaptability.

[0103] In some examples and scenarios, as shown in Figure 11, when the buck-boost chip 310C operates in boost mode, a constant on-time peak current control mode can be used; as shown in Figure 12, when the buck-boost chip 310C operates in buck mode, a constant off-time valley current control mode can be used. Since the peak and valley currents can be obtained by acquiring the voltage information of the second transistor T2, the buck-boost chip 310C does not need to set the second switch 442C, or the second switch 442C can keep the first and third terminals on. Thus, the first terminal of the boost current sampling circuit 422C is coupled to the first terminal of the second transistor T2, the second terminal of the current sampling circuit is coupled to the second terminal of the second transistor T2, and the third terminal of the current sampling circuit is coupled to the third input terminal of the PWM comparator 413C through the adder 460C. The selection switch 440C also includes a fourth switch 444C. The frequency controller 415C is coupled to the first terminal of the fourth switch 444C, the second terminal of the fourth switch 444C is used to input the constant off-time Toff, and the third terminal of the fourth switch 444C is used to output the constant on-time Ton. The fourth switch 444C is used to select the turn-off and turn-on times of the access loop. When the buck-boost chip 310C is in buck mode, the frequency controller 415C is used to control the first transistor T1 to turn off during the constant turn-off time Toff, or to control the second transistor T2 to turn on during the constant turn-on time Ton. When the buck-boost chip 310C is in boost mode, the frequency controller 415C is also used to control the second transistor T2 to turn off during the constant turn-off time Toff, or to control the first transistor T1 to turn on during the constant turn-on time Ton.

[0104] In this embodiment, when the chip is in constant on-time peak current control mode or constant off-time valley current control mode, the boost current sampling circuit 422C is used, and the boost current sampling circuit 422C is further reused, and multiple control modes can be supported.

[0105] In some possible implementations, when the buck-boost chip 310C is in boost mode, to avoid current leakage, the first transistor T1 and the second transistor T2 can typically be an NMOS and a PMOS, respectively. Alternatively, the second transistor T2 can use an NMOS with a body diode direction controllability. However, both of these methods result in a larger wafer area and a more complex control circuit 400C. Therefore, a PMOS can be externally coupled to the buck-boost chip 310C to avoid current leakage, allowing both transistors inside the buck-boost chip 310C to be NMOS transistors without the need for a body diode direction controllability.

[0106] In some examples, as shown in Figure 13, the first transistor T1 is an N-type transistor, the second voltage port pin2 is specifically used to couple to the load 320C through the third transistor T3, and the third output terminal of the control circuit 400C is used to couple to the control terminal of the third transistor T3, which is a P-type transistor.

[0107] For example, the control circuit 400C also includes a shutdown drive circuit 470C, which is used to couple the control terminal of the third transistor T3. The shutdown drive circuit 470C can be used to receive the boost control loop command from the buck-boost chip 310C, and control the third transistor T3 to turn on when the gate voltage of the third transistor T3 is low, and control the third transistor T3 to turn off when the gate voltage of the third transistor T3 is high.

[0108] For example, when the buck-boost chip 310C is adapted to a single-cell battery and operates in boost mode, the internal switching half-bridge of the buck-boost chip 310C consists of two NMOS transistors, the first transistor T1 and the second transistor T2. Due to the presence of the body diode of the first transistor T1, even if the channel of the first transistor T1 is turned off, a path may still be formed between the power supply 200C and the load 320C, causing leakage or short circuit. Therefore, connecting a PMOS transistor in series on the external output path of the buck-boost chip 310C can isolate the path between the power supply 200C and the load 320C. The gate of the third transistor T3 is connected to the turn-off drive circuit 470C inside the chip. The turn-off drive circuit 470C can control the conduction and turn-off states of the third transistor T3, thereby providing short-circuit protection.

[0109] In this embodiment, by placing a PMOS transistor outside the buck-boost chip 310C to prevent current leakage, both the first transistor T1 and the second transistor T2 inside the buck-boost chip 310C can be implemented using NMOS transistors. Since NMOS transistors of similar specifications have smaller area and cost, and higher efficiency, the buck-boost chip 310C has a smaller area and cost, and higher efficiency. Furthermore, this embodiment can prevent current leakage and achieve short-circuit protection.

[0110] In some examples, when the buck-boost chip 310C is in boost mode, the input voltage at the first voltage port pin1 and the output voltage at the second voltage port pin2 typically have a large difference, for example, a voltage difference of 100–300 mV, to achieve stable operation. Alternatively, a down-mode control method can be implemented to ensure stable operation when the input voltage at the first voltage port pin1 is close to the output voltage at the second voltage port pin2. However, this method requires both the first transistor T1 and the second transistor T2 to be low-voltage devices, and the first transistor T1 must be a PMOS; it is not suitable for schemes where both the first transistor T1 and the second transistor T2 are NMOS. Therefore, the problem of unstable circuit operation when the input voltage is close to the output voltage can be avoided by reducing the boost mode frequency of the buck-boost chip 310C.

[0111] For example, the control circuit 400C is configured to control the first transistor T1 to turn off and the second transistor T2 to turn on during a first time period of the preset boost cycle, and to control the first transistor T1 to turn on and the second transistor T2 to turn off during a second time period of the preset boost cycle. The control circuit 400C is also configured to increase the preset boost cycle when the ratio of the voltage at the feedback port fb pin to the voltage at the first voltage port pin1 is less than or equal to a first preset value, or when the ratio of the voltage at the feedback port fb pin to the voltage supplied by the power supply is less than or equal to a second preset value.

[0112] Exemplarily, the control circuit 400C also includes a frequency reduction control circuit and a minimum on-time circuit 480C. Optionally, the frequency reduction control circuit and the frequency controller 415C can be the same entity. The minimum on-time circuit 480C can be used to preset the minimum on-time of the first transistor T1 and the second transistor T2 according to the dynamic parameters of the internal switching half-bridge. This information is retained and provided to the frequency reduction control circuit. The frequency reduction control circuit can be used to automatically calculate and control the reduction of the switching frequency of the switching half-bridge based on the output voltage and the minimum on-time of the second transistor T2. When the buck-boost chip 310C is in boost mode, when the input voltage and output voltage are close, the on-time of the second transistor T2 accounts for a small proportion of the preset boost cycle. If the preset boost cycle is short, the on-time of the second transistor T2 is very short. If the on-time of the second transistor T2 is lower than the minimum on-time of the second transistor T2, this may cause the output voltage to be unstable. To address this issue, when the output voltage is close to the input voltage, the frequency reduction control circuit controls the reduction of the switching frequency based on the input voltage, output voltage, and the minimum on-time of the second transistor T2. This increases the preset boost cycle, ensuring that the on-time of the second transistor T2 is greater than or equal to the minimum on-time, thereby guaranteeing stable output.

[0113] In this embodiment, in applications where the input and output have near-minimum duty cycles, the on-time of the second transistor T2 is very short, potentially lower than its minimum on-time, which could lead to unstable output voltage. By increasing the preset boost cycle and reducing the switching frequency of the boost mode of the buck-boost chip 310C, the actual on-time of the second transistor T2 in this application scenario is increased, preventing it from being less than its minimum on-time. This ensures a stable output voltage when the input voltage at the first voltage port pin1 is close to the output voltage at the second voltage port pin2.

[0114] In some possible implementations, when the buck-boost chip 310C is in boost mode, the chip power supply circuit 510C can select one of the power supply voltage and the output voltage of the second voltage port pin 2 as the power source.

[0115] In some examples, as shown in Figure 14, the buck-boost chip 310C also includes a chip power supply circuit 510C, a power selection circuit 520C, and a voltage regulator 530C (low dropout regulator, LDO). The first terminal of the voltage regulator 530C is coupled to a fourth voltage port; the second terminal of the voltage regulator 530C is coupled to the first terminal of the power selection circuit 520C; the second terminal of the power selection circuit 520C is coupled to the chip power supply circuit 510C; and the third terminal of the power selection circuit 520C is coupled to the second voltage port pin2. The voltage regulator 530C can be a linear regulator. The fourth voltage port can be the same port as the third voltage port pin3, or it can be a different port.

[0116] For example, the chip power supply circuit 510C can be a power supply for the chip's internal drive circuit. The voltage regulator 530C is used to maintain the stability of the voltage provided by the power supply 200C. Figure 15 shows some components in the third negative voltage circuit 312C, which may include a level shifter 500C, three transistors, and a capacitor Cbst. The coupling method of each component is shown in Figure 15, where the fourth transistor T4 and the fifth transistor T5 can be power transistors of the third negative voltage circuit 312C. The level shifter 500C can be used to convert a voltage signal into an input power signal. The chip power supply circuit 510C is used to power the level shifter 500C. When the voltage of the level shifter 500C is too low, the switching speed of the fourth transistor T4 and the fifth transistor T5 slows down, and the on-resistance increases, which affects the power supply efficiency of the buck-boost chip 310C. In this embodiment, a higher voltage chip power supply circuit 510C is required to drive the power transistors. The power selection circuit 520C allows the chip power supply circuit 510C to select one of the voltages from the power supply 200C and the output voltage of the second voltage port pin2 as a power source. For example, as shown in Figure 16, the power selection circuit 520C may include two diodes, which can form a diode pair. The diode pair is used to select the higher voltage between the power supply voltage and the output voltage of the second voltage port pin2, thereby supplying power to the chip power supply circuit 510C with that higher voltage.

[0117] In this embodiment, the chip power supply circuit 510C can be coupled to either the voltage regulator 530C or the second voltage port pin2 via the power supply selection circuit 520C. The voltage regulator 530C is coupled to the power supply 200C. The chip power supply circuit 510C can select either the voltage of the power supply 200C or the voltage at the second voltage port pin2 as its power source. Thus, the chip power supply circuit 510C can obtain sufficient voltage to drive the power transistor device. This embodiment can support higher power buck-boost chips 310C.

[0118] In some examples, when the buck-boost chip 310C is in boost mode, the power selection circuit 520C controls the first and second terminals of the power selection circuit 520C to conduct when the voltage at the fourth voltage port is higher than a specified voltage. Alternatively, it controls the third and second terminals of the power selection circuit 520C to conduct when the voltage at the fourth voltage port is lower than a specified voltage.

[0119] For example, when the buck-boost chip 310C is in boost mode, the first and second terminals of the power selection circuit 520C can be turned on first, allowing the power supply 200C to supply power to the chip power circuit 510C through the regulator 530C. As the battery power of the power supply 200C may decrease (e.g., below 3V), the voltage at the fourth voltage port gradually decreases. Because the buck-boost chip 310C is in boost mode, the voltage at the second voltage port pin2 (e.g., above 4.6V) is higher than the voltage at the fourth voltage port. When the voltage supplied by the power supply 200C falls below a specified voltage, the system switches to supply power to the chip power circuit 510C using the output voltage of the second voltage port pin2.

[0120] In this embodiment, when the voltage at the fourth voltage port is high, it can be used as the supply voltage for the chip power supply circuit 510C; when the voltage at the fourth voltage port is low, the voltage at the second voltage port pin 2 can be used. This provides a higher voltage to the chip power supply circuit 510C, making it sufficient to drive the power transistors. Furthermore, it improves the power output capability without increasing the chip area.

[0121] In some examples, the specified voltage is the voltage of the second voltage port pin2. For example, when the voltage at the fourth voltage port is lower than the voltage at the second voltage port pin2, the output voltage of the second voltage port pin2 is switched to power the chip power supply circuit 510C.

[0122] In this embodiment, without increasing the internal power supply area of ​​the chip, the existing output voltage is used to enable the chip power supply circuit 510C to automatically switch to a high voltage source, thereby improving the chip power output performance.

[0123] The following examples, in conjunction with Figures 6 to 16, illustrate the possible operating modes of the buck-boost chip 310C.

[0124] In some examples, the buck-boost chip 310C needs to implement a boost function. The first voltage port pin1 of the buck-boost chip 310C is coupled to the power supply 200C via inductor L2. The second voltage port pin2 of the buck-boost chip 310C is coupled to the load 320C. The third voltage port pin3 of the buck-boost chip 310C is coupled to the power supply 200C. The mode port mode pin is in the second state. The mode selection circuit 450C controls each switch to connect the boost control circuit 420C to the loop of the common control circuit 410C according to the state of the mode port mode pin. In the initial state, the first transistor T1 is off, the second transistor T2 is off, and the voltage at the feedback port fb pin is 0. The output voltage sampling circuit 411C outputs the corresponding voltage signal to the error amplifier 412C. The error amplifier 412C compares this voltage signal with the reference voltage Vref and outputs the comparison result. This comparison result, together with the signal from the boost loop compensation circuit 421C, serves as the input signal to the first input terminal of the PWM comparator 413C. The input voltage feedforward amplifier 419C receives a voltage signal from the third voltage port pin3. The output signal of the input voltage feedforward amplifier 419C serves as the input signal to the second input terminal of the PWM comparator 413C. The output signal of the PWM comparator 413C and the signal of the frequency controller 415C pass through the trigger 414C, dead-time control circuit 416C, and other circuits. The output signal of the dead-time control circuit 416C instructs the first drive circuit 417C to control the first transistor T1 to turn on. At this time, the power supply 200C charges the inductor L2 and supplies power to the load 320C through the first transistor T1. The boost current sampling circuit 422C samples the current across the second transistor T2. When the current difference between the two ends reaches a threshold, the output signal of the boost current sampling circuit 422C and the signal of the boost ramp compensation circuit 423C pass through the adder 460C, PWM comparator 413C, trigger 414C, and dead-time control circuit 416C. The signal output by the dead-time control circuit 416C instructs the first drive circuit 417C to turn off the first transistor T1 and instructs the second drive circuit 418C to turn on the second transistor T2. At this time, inductor L2 charges. Then, the signal at the feedback port fb pin instructs the first transistor T1 to turn on again, and power supply 200C and inductor L2 discharge together, providing the boosted voltage to load 320C. Thus, the buck-boost chip 310C achieves boost mode under a preset boost cycle.

[0125] For example, in this process, when the first transistor T1 is turned off, the third transistor T3 is turned off under the control of the turn-off drive circuit 470C; when the first transistor T1 is turned on, the third transistor T3 is turned on under the control of the turn-off drive circuit 470C. The minimum on-time circuit 480C determines the minimum on-time of the first transistor T1 and the second transistor T2, and outputs the minimum on-time to the frequency controller 415C. The frequency controller 415C increases the preset boost cycle when the ratio of the voltage at the feedback port fb pin to the voltage at the first voltage port pin1 is less than or equal to a first preset value, or when the ratio of the voltage at the feedback port fb pin to the voltage provided by the power supply 200C is less than or equal to a second preset value (that is, when the input voltage and output voltage are close).

[0126] For example, in this process, when the voltage at the fourth voltage port is higher than a specified voltage, the power supply selection circuit 520C controls its first and second terminals to conduct. This couples the voltage regulator 530C with the chip power supply circuit 510C, and the power supply 200C supplies power to the chip power supply circuit 510C. As the power supply 200C gradually depletes, the voltage at the fourth voltage port falls below the specified voltage. At this point, the power supply selection circuit 520C controls its third and second terminals to conduct. This couples the second voltage port pin2 with the chip power supply circuit 510C, and the output voltage at pin2 supplies power to the chip power supply circuit 510C.

[0127] In other examples, the buck-boost chip 310C needs to implement a buck function. The first voltage port pin1 of the buck-boost chip 310C is coupled to the load 320C through inductor L2. The second voltage port pin2 of the buck-boost chip 310C is coupled to the power supply 200C. The third voltage port pin3 of the buck-boost chip 310C is coupled to the power supply 200C. The mode port mode pin is in the first state. The mode selection circuit 450C controls each switch to connect the buck control circuit 430C to the loop of the common control circuit 410C according to the state of the mode port mode pin. In the initial state, the first transistor T1 is off, the second transistor T2 is off, and the voltage at the feedback port fb pin is 0. The output voltage sampling circuit 411C outputs the corresponding voltage signal to the error amplifier 412C. The error amplifier 412C compares this voltage signal with the reference voltage Vref and outputs the comparison result. This comparison result, together with the signal from the buck loop compensation circuit 431C, serves as the input signal to the first input terminal of the PWM comparator 413C. The input voltage feedforward amplifier 419C receives a voltage signal from the third voltage port pin3. The signal output by the input voltage feedforward amplifier 419C serves as the input signal to the second input terminal of the PWM comparator 413C. The signal output by the PWM comparator 413C and the signal from the frequency controller 415C pass through circuits such as the trigger 414C and the dead-time control circuit 416C. The signal output by the dead-time control circuit 416C instructs the first drive circuit 417C to control the first transistor T1 to turn on. At this time, the power supply 200C charges the inductor L2 and provides a stepped-down voltage to the load 320C through the first transistor T1. The step-down current sampling circuit 432C samples the current across the first transistor T1. When the current difference across the two ends reaches a threshold, the signal output by the step-down current sampling circuit 432C and the signal from the step-down slope compensation circuit 433C pass through the adder 460C, the PWM comparator 413C, the trigger 414C, and the dead-time control circuit 416C. The signal output by the dead-time control circuit 416C instructs the first drive circuit 417C to turn off the first transistor T1 and instructs the second drive circuit 418C to turn on the second transistor T2. At this time, inductor L2 discharges. Then, the signal at the feedback port fb pin instructs the first transistor T1 to turn on again, and the power supply 200C and the voltage that charges inductor L2, which is then supplied to the load 320C via the first transistor after being stepped down, discharge together, providing the load 320C with a stepped-up voltage. In this way, the buck-boost chip 310C achieves buck mode under a preset buck cycle.

[0128] Based on the buck-boost chip 310C provided in Figures 6 to 16, this application embodiment also proposes a control method for the buck-boost chip 310C. The structure of the buck-boost chip 310C can refer to the chip structure in the above chip embodiments, and will not be repeated here. As shown in Figure 17, the method includes at least the following steps:

[0129] S100: If it is determined that the buck-boost chip 310C is in buck mode, the control circuit 400C controls the first transistor T1 to turn on and the second transistor T2 to turn off during the first time period of the preset buck cycle, and controls the first transistor T1 to turn off and the second transistor T2 to turn on during the second time period of the preset buck cycle; and controls the buck-boost chip 310C to input voltage through the second voltage port pin2 and output voltage through the first voltage port pin1; wherein, the first voltage port pin1 is coupled to the power supply 200C through an inductor, and the second voltage port pin2 is used to couple to the load 320C; or...

[0130] S200: If it is determined that the buck-boost chip 310C is in boost mode, the control circuit 400C controls the first transistor T1 to turn off and the second transistor T2 to turn on during the first time period of the preset boost cycle, and controls the first transistor T1 to turn on and the second transistor T2 to turn off during the second time period of the preset boost cycle; and controls the buck-boost chip 310C to input voltage through the first voltage port pin1 and output voltage through the second voltage port pin2; wherein, the first voltage port pin1 is coupled to the load 320C through an inductor, and the second voltage port pin2 is used to couple to the power supply 200C.

[0131] In one possible implementation, the buck-boost chip 310C can switch between boost and buck modes by different states of the mode port mode pin. In some examples, the method may further include: detecting the state of the mode port mode pin. If the mode port mode pin is in a first state, the control circuit 400C determines that the buck-boost chip 310C is in buck mode. If the mode port mode pin is in a second state, the control circuit 400C determines that the buck-boost chip 310C is in boost mode.

[0132] In one possible implementation, the mode port (mode pin) is coupled to the selection circuit via a mode selection circuit 450C. The mode selection circuit 450C controls the connection between the two ends of the selection switch 440C according to different states of the mode port (mode pin), thereby controlling the buck control circuit 430C or the boost control circuit 420C to enter the loop of the control circuit 400C, thus allowing the buck-boost chip 310C to switch to buck mode or boost mode. In some examples, the method may further include: if the mode port (mode pin) is in a first state, the mode selection circuit 450C controls the first end of the selection switch 440C to be connected to the second end of the selection switch 440C; if the mode port (mode pin) is in a second state, the mode selection circuit 450C controls the first end of the selection switch 440C to be connected to the third end of the selection switch 440C. S200 may include: when the first terminal of the selector switch 440C is connected to the third terminal of the selector switch 440C, the common control circuit 410C and the boost control circuit 420C control the buck-boost chip 310C to be in boost mode, controlling the buck-boost chip 310C to input voltage through the first voltage port pin1 and output voltage through the second voltage port pin2. S100 may include: when the first terminal of the selector switch 440C is connected to the second terminal of the selector switch 440C, the common control circuit 410C and the buck control circuit 430C control the buck-boost chip 310C to be in buck mode, controlling the buck-boost chip 310C to input voltage through the second voltage port pin2 and output voltage through the first voltage port pin1. In one possible implementation, the buck-boost chip 310C may employ a constant on-time peak current control mode or a constant off-time valley current control mode. In some examples, when the buck-boost chip 310C is in buck mode, the frequency controller 415C controls the first transistor T1 to turn off during a constant off-time, or controls the second transistor T2 to turn on during a constant on-time. When the buck-boost chip 310C is in boost mode, the frequency controller 415C controls the second transistor T2 to turn off during a constant off-time, or controls the first transistor T1 to turn on during a constant on-time.

[0133] In one possible implementation, when the buck-boost chip 310C is in boost mode, and the input voltage at the first voltage port pin1 is close to the output voltage at the second voltage port pin2, the conduction time of the second transistor T2 is short within a preset boost cycle. If the actual conduction time of the second transistor T2 is less than the minimum conduction time, it may cause output voltage instability. Therefore, the conduction time of the second transistor T2 within each preset boost cycle can be increased by reducing the frequency. In some examples, when the buck-boost chip 310C is in boost mode, the method may further include: the control circuit 400C increasing the preset boost cycle when the ratio of the voltage at the feedback port fb pin to the voltage at the first voltage port pin1 is less than or equal to a first preset value, or when the ratio of the voltage at the feedback port fb pin to the voltage supplied by the power supply is less than or equal to a second preset value.

[0134] For example, Figure 18 illustrates one possible flow for reducing the frequency. Control circuit 400C determines whether buck-boost chip 310C is in boost mode. If not in boost mode, control circuit 400C controls buck-boost chip 310C to operate normally at the original frequency. If in boost mode, control circuit 400C determines whether the output voltage drops as the input voltage gradually approaches the output voltage. For example, an output voltage drop means that the required on-time of the second transistor T2 corresponding to the output voltage is less than the minimum on-time of the second transistor T2. If the output voltage does not drop, control circuit 400C controls buck-boost chip 310C to operate normally at the original frequency. If the output voltage drops, control circuit 400C increases the preset boost cycle.

[0135] In one possible implementation, when the buck-boost chip 310C is in boost mode, its chip power supply circuit 510C requires a higher voltage to drive the power transistor device of the third negative voltage circuit 312C. Typically, the chip power supply circuit 510C is powered by the voltage at a fourth voltage port. As the power supply 200C consumes power, the voltage at the fourth voltage port may become insufficient. Therefore, a power supply selection circuit 520C can provide a path between the chip power supply circuit 510C and the second voltage port pin2, supplying power to the chip power supply circuit 510C through the output voltage of the second voltage port pin2. In some examples, the method further includes: when the buck-boost chip 310C is in boost mode, if the voltage at the fourth voltage port is higher than a specified voltage, the power supply selection circuit 520C controls the chip power supply circuit 510C to receive the voltage at the fourth voltage port; or, if the voltage at the fourth voltage port is lower than a specified voltage, the power supply circuit 510C controls the chip power supply circuit 510C to receive the voltage at the second voltage port. Exemplarily, the specified voltage is the voltage at the second voltage port pin2.

[0136] For example, Figure 19 illustrates one possible power supply flow for the chip power supply circuit 510C. The first and second terminals of the power selection circuit 520C are connected, and the buck-boost chip 310C supplies power to the chip power supply circuit 510C through the voltage received from the fourth voltage port by the voltage regulator 530C. The buck-boost chip 310C determines whether it is in boost mode. If it is not in boost mode, the power selection circuit 520C keeps its first and second terminals connected. If it is in boost mode, it determines whether the voltage at the second voltage port pin2 is greater than the voltage sent by the voltage regulator 530C. If the voltage at the second voltage port pin2 is not greater than the voltage sent by the voltage regulator 530C, the power selection circuit 520C keeps its first and second terminals connected. If the voltage at the second voltage port pin2 is greater than the voltage sent by the voltage regulator 530C, the power supply selection circuit 520C controls the third terminal and the second terminal of the power supply selection circuit 520C to be turned on.

[0137] It is understood that the control method of the buck-boost chip 310C described above can be applied to the aforementioned chip embodiments. Since the effects of each structure and function have been described in detail in the aforementioned chip embodiments, they will not be repeated here.

[0138] It is understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0139] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0140] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0141] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.

[0142] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0143] In addition, the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.

[0144] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A buck-boost chip, characterized in that, The chip includes a first voltage port, a second voltage port, a first transistor, a second transistor, and a control circuit. The first terminal of the first transistor and the first terminal of the second transistor are both coupled to the first voltage port, and the second terminal of the first transistor is coupled to the second voltage port; the second terminal of the second transistor is grounded; the control terminal of the first transistor is coupled to the first output terminal of the control circuit, and the control terminal of the second transistor is coupled to the second output terminal of the control circuit. Wherein, when the chip is in boost mode, the first voltage port is used for inductor coupling to the power supply, and the second voltage port is used for coupling to the load; and When the chip is in buck mode, the first voltage port is used to couple to the load through the inductor, and the second voltage port is used to couple to the power supply.

2. The chip according to claim 1, characterized in that, The chip also includes a mode port, which includes a first state and a second state; the first state and the second state are different. If the mode port is in the first state, the chip is used to switch to the buck mode; If the mode port is in the second state, the chip is also used to switch to the boost mode.

3. The chip according to claim 1 or 2, characterized in that, The control circuit includes a common control circuit, a buck control circuit, a boost control circuit, and a selection switch; The first output terminal of the common control circuit is coupled to the first output terminal of the control circuit, the second output terminal of the common control circuit is coupled to the second output terminal of the control circuit, the switching terminal of the common control circuit is coupled to the first terminal of the selection switch, the second terminal of the selection switch is coupled to the buck control circuit, and the third terminal of the selection switch is coupled to the boost control circuit.

4. The chip according to claim 3, characterized in that, When the first terminal of the selection switch is connected to the second terminal of the selection switch, the common control circuit and the buck control circuit are used to control the first transistor to be turned on and the second transistor to be turned off during a first time period of the preset buck cycle, and to control the first transistor to be turned off and the second transistor to be turned on during a second time period of the preset buck cycle; and to control the chip to input voltage through the second voltage port and output voltage through the first voltage port. When the first terminal of the selection switch is connected to the third terminal of the selection switch, the common control circuit and the boost control circuit are used to control the first transistor to turn off and the second transistor to turn on during a first time period of the preset boost cycle, and to control the first transistor to turn on and the second transistor to turn off during a second time period of the preset boost cycle. And control the chip to input voltage through the first voltage port and output voltage through the second voltage port.

5. The chip according to claim 4, characterized in that, The control circuit further includes a mode selection circuit, and the chip further includes a mode port; the selection terminal of the selection switch is coupled to a first terminal of the mode selection circuit, and the second terminal of the mode selection circuit is coupled to the mode port; the mode port includes a first state and a second state; the first state and the second state are different; If the mode port is in the first state, the mode selection circuit is used to control the first terminal of the selection switch to be connected to the second terminal of the selection switch; Alternatively, if the mode port is in the second state, the mode selection circuit is also used to control the first terminal of the selection switch to be connected to the third terminal of the selection switch.

6. The chip according to any one of claims 3-5, characterized in that, The chip also includes a feedback port; the common control circuit includes an output voltage sampling circuit, an error amplifier, a pulse width modulation (PWM) comparator, a trigger, a frequency controller, a dead-time control circuit, a first drive circuit, and a second drive circuit. The input terminal of the shared control circuit is coupled to the feedback port, and the feedback port is used to couple the load. The first terminal of the output voltage sampling circuit is coupled to the input terminal of the common control circuit; the second terminal of the output voltage sampling circuit is grounded; and the third terminal of the output voltage sampling circuit is coupled to the first input terminal of the error amplifier. The second input terminal of the error amplifier is used to input a reference voltage. The output terminal of the error amplifier is coupled to the first input terminal of the PWM comparator. The output terminal of the PWM comparator is coupled to the first input terminal of the flip-flop. The second input terminal of the flip-flop is coupled to the frequency controller. The output terminal of the flip-flop is coupled to the first input terminal of the dead-time control circuit. The second input terminal of the dead-time control circuit is used to input the dead-time. The output terminal of the dead-time control circuit is coupled to the input terminal of the first driving circuit and the input terminal of the second driving circuit. The output terminal of the first driving circuit is coupled to the first output terminal of the common control circuit, and the output terminal of the second driving circuit is coupled to the second output terminal of the common control circuit.

7. The chip according to claim 6, characterized in that, The chip also includes a negative voltage circuit and a third voltage port; the common control circuit also includes an input voltage feedforward amplifier. The third voltage port is used to couple the power supply; The input terminal of the negative voltage circuit and the input terminal of the input voltage feedforward amplifier are both coupled to the third voltage port, and the output terminal of the input voltage feedforward amplifier is coupled to the second input terminal of the PWM comparator.

8. The chip according to claim 6 or 7, characterized in that, The control circuit also includes a current sampling circuit; The first terminal of the current sampling circuit is coupled to the first terminal of the second transistor, the second terminal of the current sampling circuit is coupled to the second terminal of the second transistor, and the third terminal of the current sampling circuit is coupled to the third input terminal of the PWM comparator. When the chip is in the buck mode, the frequency controller is used to control the first transistor to turn off during a constant off time, or to control the second transistor to turn on during a constant on time. When the chip is in the boost mode, the frequency controller is also used to control the second transistor to turn off during a constant off time, or to control the first transistor to turn on during a constant on time.

9. The chip according to any one of claims 1-8, characterized in that, When the chip is in the boost mode, the first voltage port is specifically used to couple the higher voltage end of the first and second terminals of the inductor, where the load voltage is higher than the power supply voltage; and, When the chip is in the buck mode, the first voltage port is specifically used to couple the higher voltage end of the first and second terminals of the inductor, and the voltage of the power supply is higher than the voltage of the load.

10. The chip according to any one of claims 6-9, characterized in that, The first transistor is an N-type transistor, the third transistor is a P-type transistor, the second voltage port is specifically used to couple to the load through the third transistor, and the third output terminal of the control circuit is used to couple to the control terminal of the third transistor.

11. The chip according to claim 10, characterized in that, When the chip is in the boost mode, The control circuit is used to control the first transistor to turn off and the second transistor to turn on during a first time period of a preset boost cycle, and to control the first transistor to turn on and the second transistor to turn off during a second time period of the preset boost cycle. The control circuit is further configured to increase the preset boost cycle when the ratio of the voltage at the feedback port to the voltage at the first voltage port is less than or equal to a first preset value, or when the ratio of the voltage at the feedback port to the voltage provided by the power supply is less than or equal to a second preset value.

12. The chip according to any one of claims 1-11, characterized in that, The chip also includes a chip power supply circuit, a power supply selection circuit, a voltage regulator, and a fourth voltage port; The fourth voltage port is used to couple the power supply; The first terminal of the voltage regulator is coupled to the fourth voltage port; the second terminal of the voltage regulator is coupled to the first terminal of the power supply selection circuit. The second terminal of the power supply selection circuit is coupled to the chip power supply circuit; the third terminal of the power supply selection circuit is coupled to the second voltage port.

13. The chip according to claim 12, characterized in that, When the chip is in the boost mode, the power supply selection circuit is used to control the first terminal and the second terminal of the power supply selection circuit to be turned on when the voltage of the fourth voltage port is higher than a specified voltage; or, when the voltage of the fourth voltage port is lower than a specified voltage, control the third terminal and the second terminal of the power supply selection circuit to be turned on.

14. The chip according to claim 13, characterized in that, The specified voltage is the voltage of the second voltage port.

15. A control method for a buck-boost chip, characterized in that, The chip includes a first voltage port, a second voltage port, a first transistor, a second transistor, and a control circuit; the first terminal of the first transistor and the first terminal of the second transistor are both coupled to the first voltage port; the second terminal of the first transistor is coupled to the second voltage port; the second terminal of the second transistor is grounded. The control terminal of the first transistor is coupled to the first output terminal of the control circuit; the control terminal of the second transistor is coupled to the second output terminal of the control circuit; the method further includes: If the chip is determined to be in buck mode, the control circuit controls the first transistor to turn on and the second transistor to turn off during a first time period of a preset buck cycle, and controls the first transistor to turn off and the second transistor to turn on during a second time period of the preset buck cycle; and controls the chip to input voltage through the second voltage port and output voltage through the first voltage port; wherein the first voltage port is inductibly coupled to the power supply, and the second voltage port is used to couple to the load; or... If the chip is determined to be in boost mode, the control circuit controls the first transistor to turn off and the second transistor to turn on during a first time period of the preset boost cycle, and controls the first transistor to turn on and the second transistor to turn off during a second time period of the preset boost cycle; and controls the chip to input voltage through the first voltage port and output voltage through the second voltage port; wherein the first voltage port is coupled to the load through the inductor, and the second voltage port is used to couple to the power supply.

16. The method according to claim 15, characterized in that, The chip further includes a mode port, which includes a first state and a second state; the first state and the second state are different; the method further includes: Detect the status of the mode port; If the mode port is in the first state, it is determined that the chip is in the buck mode; If the mode port is in the second state, it is determined that the chip is in the boost mode.

17. The method according to claim 15 or 16, characterized in that, The method further includes: When the chip is in the buck mode, the control circuit controls the first transistor to turn off during a constant off time, or controls the second transistor to turn on during a constant on time. When the chip is in the boost mode, the control circuit controls the second transistor to turn off during a constant off time, or controls the first transistor to turn on during a constant on time.

18. The method according to any one of claims 15-17, characterized in that, The chip also includes a feedback port; The feedback port is used to couple the load; the method further includes: When the chip is in the boost mode, the control circuit increases the preset boost cycle when the ratio of the voltage at the feedback port to the voltage at the first voltage port is less than or equal to a first preset value, or when the ratio of the voltage at the feedback port to the voltage provided by the power supply is less than or equal to a second preset value.

19. The method according to any one of claims 15-18, characterized in that, The chip further includes a chip power supply circuit, a power supply selection circuit, and a fourth voltage port; the fourth voltage port is used to couple the power supply; the method further includes: When the chip is in the boost mode, the power supply selection circuit controls the chip power supply circuit to receive the voltage at the fourth voltage port when the voltage at the fourth voltage port is higher than a specified voltage; or, when the voltage at the fourth voltage port is lower than the specified voltage, controls the chip power supply circuit to receive the voltage at the second voltage port.

20. The method according to claim 19, characterized in that, The specified voltage is the voltage of the second voltage port.

21. A screen module, characterized in that, The screen module includes a screen and a buck-boost chip as described in any one of claims 1-14, wherein the load is the screen.

22. An electronic device, characterized in that, The electronic device includes a power supply and a buck-boost chip as described in any one of claims 1-14.

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