Half-bridge power module and manufacturing method therefor, and full-bridge power module and electric device

Abstract

Provided in the present application are a half-bridge power module (100) and a manufacturing method therefor, and a full-bridge power module (200) and an electric device (300). The half-bridge power module (100) comprises: a bottom plate (1); and a first substrate (2) and a second substrate (3), wherein the first substrate (2) and the second substrate (3) are arranged on the bottom plate (1) side by side in a second direction and are spaced apart from each other, the first substrate (2) is provided with a first half-bridge unit (4), which comprises a plurality of wide-bandgap power chips (43), and the second substrate (3) is provided with a second half-bridge unit (5), which comprises a plurality of silicon-based power chips (53), the first substrate (2) being electrically connected to the second substrate (3).

Description

Half-bridge power modules and their manufacturing methods, full-bridge power modules and electrical equipment

[0001] This application claims priority to Chinese Patent Application No. 202411204999.1, filed on August 29, 2024, entitled "Half-bridge power module and manufacturing method thereof, full-bridge power module and electrical equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a half-bridge power module and its manufacturing method, a full-bridge power module, and electrical equipment. Background Technology

[0003] With the development of new energy vehicle technology, more and more new energy vehicle main drive inverters are adopting power semiconductor modules.

[0004] Currently, the power semiconductor modules on the market are mainly Si IGBT modules and SiC MOSFET modules. The main drawback of Si IGBT modules is their high switching losses, while the main drawback of SiC MOSFET modules is their high cost due to limitations in the silicon carbide substrate manufacturing process, making it difficult to meet the explosive growth in demand from the new energy vehicle market. The technology of hybrid parallel connection of Si IGBT and SiC MOSFET devices is still in its early stages, and there is room for improvement in the packaging technology of existing hybrid Si IGBT and SiC MOSFET power modules. Summary of the Invention

[0005] In view of the above problems, this application provides a half-bridge power module and its manufacturing method, a full-bridge power module and electrical equipment, which integrates a wide bandgap power chip and a silicon-based power chip, and can balance switching losses and product costs, optimize manufacturing process and improve production efficiency.

[0006] This application provides a half-bridge power module, including: a base plate; a first substrate and a second substrate, wherein the first substrate and the second substrate are arranged side by side and spaced apart along a first direction on the base plate, the first substrate is provided with a first half-bridge unit, the first half-bridge unit including a plurality of wide bandgap power chips, the second substrate is provided with a second half-bridge unit, the second half-bridge unit including a plurality of silicon-based power chips, and the substrate and the second substrate are electrically connected.

[0007] The half-bridge power module of this application integrates a wide-bandgap power chip and a silicon-based power chip, forming a hybrid single-phase half-bridge power module. This allows for better expansion of current specifications and power levels while addressing switching losses and product cost. Furthermore, by placing the wide-bandgap power chip (a type of wide-bandgap semiconductor device) on a first substrate and the silicon-based power chip (a type of silicon-based semiconductor device) on a second substrate, compared to related technologies that place different types of power components on the same substrate, this approach allows for the use of appropriate connection processes between different types of power components and their corresponding substrates, based on the material type of the power components. This optimizes the manufacturing process of the half-bridge power module, improves production efficiency and product yield, and reduces costs.

[0008] In some embodiments, the half-bridge power module further includes a DC positive terminal, a DC negative terminal, and an AC terminal, wherein the DC positive terminal and the DC negative terminal are located on the same substrate.

[0009] In some embodiments, the DC positive terminal and the DC negative terminal are disposed on the first substrate.

[0010] In some embodiments, either the DC positive terminal or the DC negative terminal is located on a different substrate from the AC terminal.

[0011] In some embodiments, a first conductive metal layer is provided on the first substrate, the first conductive metal layer includes a first DC positive electrode region, and the DC positive terminal is disposed in the first DC positive electrode region.

[0012] In some embodiments, the first conductive metal layer further includes a first DC negative electrode region, wherein the DC negative terminal is disposed in the first DC negative electrode region.

[0013] In some embodiments, the first conductive metal layer further includes a first AC region, the first half-bridge unit includes a first upper bridge chip group and a first lower bridge chip group, the first upper bridge chip group is disposed in the first DC positive region, the first lower bridge chip group is disposed in the first AC region, and both the first upper bridge chip group and the first lower bridge chip group include a plurality of the wide bandgap power chips.

[0014] In some embodiments, the first upper bridge chipset and the first lower bridge chipset are arranged along a second direction.

[0015] In some embodiments, the wide bandgap power chips in the first upper bridge chipset and the first lower bridge chipset are arranged along a first direction.

[0016] In some embodiments, a plurality of wide-bandgap power chips in the first upper bridge chipset are connected to the first AC region via a first connection line, and a plurality of wide-bandgap power chips in the first lower bridge chipset are connected to the first DC negative region via a second connection line.

[0017] In some embodiments, at least a portion of the first DC positive region, the first AC region, and the first DC negative region extend along the first direction and are arranged along the second direction.

[0018] In some embodiments, the first upper bridge chipset and the first lower bridge chipset further include a first type of diode, which is arranged along a first direction with the wide bandgap power chip.

[0019] In some embodiments, the first type of diode of the first upper bridge chipset is connected in series with the first type of diode of the first lower bridge chipset, and the first type of diode is connected in parallel with the wide bandgap power chip in the same chipset.

[0020] In some embodiments, the first type of diode uses the same substrate material as the wide bandgap power chip.

[0021] In some embodiments, the first type of diode is a wide-bandgap Schottky diode.

[0022] In some embodiments, the diodes and the wide-bandgap power chip are arranged alternately along the first direction.

[0023] In some embodiments, a second conductive metal layer is provided on the second substrate, the second conductive metal layer includes a second DC positive electrode region, and the first DC positive electrode region is electrically connected to the second DC positive electrode region.

[0024] In some embodiments, the second conductive metal layer further includes a second DC negative electrode region, wherein the first DC negative electrode region is electrically connected to the second DC negative electrode region.

[0025] In some embodiments, the second conductive metal layer further includes a second AC region, wherein the first AC region is electrically connected to the second AC region.

[0026] In some embodiments, the AC terminal is located in the second AC area.

[0027] In some embodiments, the second half-bridge unit includes a second upper-bridge chip group and a second lower-bridge chip group. The second upper-bridge chip group is located in the second DC positive region, and the second lower-bridge chip group is located in the second AC region. Both the second upper-bridge chip group and the second lower-bridge chip group include a plurality of the silicon-based power chips.

[0028] In some embodiments, the second upper bridge chip group and the second lower bridge chip group are arranged along a second direction.

[0029] In some embodiments, each of the second upper bridge chip group and the second lower bridge chip group includes a plurality of the silicon-based power chips arranged along the first direction.

[0030] In some embodiments, a plurality of silicon-based power chips in the second upper bridge chipset are connected to the second AC region via a third connection line, and a plurality of silicon-based power chips in the second lower bridge chipset are connected to the second DC negative region via a fourth connection line.

[0031] In some embodiments, at least a portion of the second DC positive region, the second AC region, and the second DC negative region extend along the first direction and are arranged along the second direction.

[0032] In some embodiments, the first DC positive region and the second DC positive region are arranged opposite to each other along the first direction.

[0033] In some embodiments, the first DC negative region and the second DC negative region are arranged opposite to each other along the first direction.

[0034] In some embodiments, the first communication area and the second communication area are arranged opposite to each other along the first direction.

[0035] In some embodiments, the second upper bridge chipset and the second lower bridge chipset further include a second type of diode, which is arranged along a first direction with the silicon-based power chip.

[0036] In some embodiments, the second type of diode of the second upper bridge chip group is connected in series with the second type of diode of the second lower bridge chip group, and the second type of diode is connected in parallel with the silicon-based power chip in the same chip group.

[0037] In some embodiments, the second type of diode is made of the same substrate material as the silicon-based power chip.

[0038] In some embodiments, the second type of diode is a silicon substrate fast recovery diode.

[0039] In some embodiments, the second type of diode and the silicon-based power chip are arranged alternately along the first direction.

[0040] In some embodiments, the wide bandgap power chip includes a SiC MOSFET, and the silicon-based power chip includes a Si IGBT.

[0041] In some embodiments, the first conductive metal layer further includes a first SiC driving layer group, comprising a first SiC gate driving layer and a first SiC source driving layer, wherein the gate of the SiC MOSFET of the first upper bridge chip group is electrically connected to the first SiC gate driving layer, and the source of the SiC MOSFET of the first upper bridge chip group is electrically connected to the first SiC source driving layer.

[0042] In some embodiments, the first conductive metal layer further includes a second SiC driving layer group, including a second SiC gate driving layer and a second SiC source driving layer, wherein the gate of the SiC MOSFET of the first lower bridge chip group is electrically connected to the second SiC gate driving layer, and the source of the SiC MOSFET of the first lower bridge chip group is electrically connected to the second SiC source driving layer.

[0043] In some embodiments, the second conductive metal layer further includes: a first IGBT driving layer group, including: a first IGBT gate driving layer and a first IGBT emitter driving layer, wherein the gate of the Si IGBT in the second upper bridge chip group is electrically connected to the first IGBT gate driving layer, and the emitter of the Si IGBT in the second upper bridge chip group is electrically connected to the first IGBT emitter driving layer.

[0044] In some embodiments, the second conductive metal layer further includes a second IGBT driving layer group, comprising a second IGBT gate driving layer and a second IGBT emitter driving layer, wherein the gate of the Si IGBT in the second lower bridge chip group is electrically connected to the second IGBT gate driving layer, and the emitter of the Si IGBT in the second lower bridge chip group is electrically connected to the second IGBT emitter driving layer.

[0045] In some embodiments, the base plate includes a first side and a second side opposite to each other along a second direction, and a third side and a fourth side opposite to each other along the first direction; the first SiC driving layer group is located on the side of the first DC positive electrode region facing the first side.

[0046] In some embodiments, the second SiC driving layer group is located on the side of the first DC negative electrode region facing the second side.

[0047] In some embodiments, the first IGBT drive layer group is located on the side of the second DC positive region facing the first side.

[0048] In some embodiments, the second IGBT drive layer group is located on the side of the second DC negative electrode region facing the second side.

[0049] In some embodiments, the wide bandgap power chip is connected to the first substrate using a first connection process, which is one of a sintering process and a welding process.

[0050] In some embodiments, the silicon-based power chip is connected to the second substrate using a second connection process, which is one of a sintering process and a welding process.

[0051] In some embodiments, one of the first connection process and the second connection process is a sintering process, and the other is a welding process.

[0052] In some embodiments, both the first connection process and the second connection process are sintering processes, or both the first connection process and the second connection process are welding processes, and the process parameters of the first connection process and the second connection process are different, including process temperature and process duration.

[0053] Secondly, this application provides a full-bridge power module, including: the above-mentioned half-bridge power module, wherein there are multiple half-bridge power modules, and the multiple half-bridge power modules are connected to form a full-bridge power module.

[0054] Thirdly, this application provides an electrical device, which includes a power module, the power module including the half-bridge power module described in the first aspect above, and / or the full-bridge power module described in the second aspect above.

[0055] Thirdly, this application provides a method for manufacturing a half-bridge power module, used to manufacture the half-bridge power module described in the first aspect above, comprising the following steps:

[0056] The wide-bandgap power chip is fixed to the first substrate, and the silicon-based power chip is fixed to the second substrate;

[0057] The wide-bandgap power chip is bonded to the first substrate via interconnecting wires, and the silicon-based power chip is bonded to the second substrate via interconnecting wires.

[0058] Electrical tests were performed on the first half-bridge unit formed by the wide bandgap power chip and the second half-bridge unit formed by the silicon-based power chip, respectively.

[0059] The first substrate and the second substrate, which have passed the electrical test, are respectively fixed to the base plate;

[0060] The first substrate and the second substrate are connected by a connecting line;

[0061] Install housing and connection terminals.

[0062] In some embodiments, fixing the wide bandgap power chip to the first substrate and fixing the silicon-based power chip to the second substrate respectively includes: fixing the wide bandgap power chip to the first substrate through a first connection process, and fixing the silicon-based power chip to the second substrate through a second connection process; the first connection process is one of a sintering process and a welding process; the second connection process is one of a sintering process and a welding process.

[0063] In some embodiments, one of the first connection process and the second connection process is a sintering process, and the other is a welding process.

[0064] In some embodiments, both the first connection process and the second connection process are sintering processes, or both the first connection process and the second connection process are welding processes, and the process parameters of the first connection process and the second connection process are different, including process temperature and process duration.

[0065] In some embodiments, fixing the first substrate and the second substrate, which have passed the electrical test, to the base plate includes: soldering both the first substrate and the second substrate to the base plate. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0067] Figure 1 is a schematic diagram of the internal layout of an embodiment of the half-bridge power module of this application;

[0068] Figure 2 is a schematic diagram of the internal bonding of the half-bridge power module shown in Figure 1;

[0069] Figure 3 is a schematic diagram of the internal bonding of another embodiment of the half-bridge power module of this application;

[0070] Figure 4 is a schematic diagram of the structure of a wide bandgap power chip according to some embodiments of this application;

[0071] Figure 5 is a schematic diagram of the structure of a silicon-based power chip according to some embodiments of this application;

[0072] Figure 6 is a schematic diagram of the structure of a diode according to some embodiments of this application;

[0073] Figure 7 is a schematic diagram of the structure of a full-bridge power module according to some embodiments of this application;

[0074] Figure 8 is a schematic diagram of the manufacturing method of the half-bridge power module according to an embodiment of this application;

[0075] Figure 9 is a detailed manufacturing process diagram of the half-bridge power module according to an embodiment of this application;

[0076] Figure 10 is a manufacturing process diagram of the hybrid module in the related technology;

[0077] Figure 11 is a schematic diagram of the full-bridge power module according to an embodiment of this application;

[0078] Figure 12 is a schematic diagram of electrical equipment according to some embodiments of this application;

[0079] Figure 13 is a schematic diagram of an electrical device according to some other embodiments of this application.

[0080] Explanation of reference numerals in the attached drawings: 100 - Half-bridge power module; 1 - Base plate; 1a - First side; 1b - Second side; 1c - Third side; 1d - Fourth side; 2 - First substrate; 21 - First conductive metal layer; 211 - First DC positive region; 212 - First AC region; 213 - First DC negative region; 214 - First SiC driving layer group; 2141 - First SiC gate driving layer; 2142 - First SiC source driving layer; 215 - Second SiC driving layer group; 2151 - Second SiC gate driving layer; 2152 - Second SiC source driving layer; 3 - Second substrate; 31 - Second conductive metal layer; 311 - Second DC positive region; 312 - Second AC region; 313 - Second DC negative region; 314-First IGBT driving layer group; 3141-First IGBT gate driving layer; 3142-First IGBT emitter driving layer; 315-Second IGBT driving layer group; 3151-Second IGBT gate driving layer; 3152-Second IGBT emitter driving layer; 4-First half-bridge unit; 41-First upper bridge chipset; 42-First lower bridge chipset; 43-Wide bandgap power chip; 431-Source; 432-Gate; 433-Drain; 5-Second half-bridge unit; 51-Second upper bridge chipset; 52-Second lower bridge chipset; 53-Silicon-based power chip; 531-Emitter; 532-Gate; 533-Collector; 6-Diode; 6a-Type I diode; 6b-Type II diode; 61-Anode; 62-Cathode; 7-Connecting wire; 71-First connecting wire; 72-Second connecting wire; 73-Third connecting wire; 74-Fourth connecting wire; 8-Drive terminal; 9-DC positive terminal; 10-DC negative terminal; 11-AC terminal; 200-Full bridge power module; 300-Electrical equipment. Detailed Implementation

[0081] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0082] With the development of new energy vehicle technology, more and more new energy vehicle main drive inverters are adopting power semiconductor modules. Currently, the power semiconductor modules on the market are mainly Si IGBT modules and SiC MOSFET modules. The main disadvantage of Si IGBT modules is their high switching losses, while the main disadvantage of SiC MOSFET modules is their high cost due to limitations in the manufacturing process of silicon carbide substrates, making it difficult to meet the explosive growth in demand from the new energy vehicle market. The technology of hybrid parallel connection of Si IGBTs and SiC MOSFETs is still in its early stages, and there is room for improvement in the packaging technology of existing hybrid Si IGBT and SiC MOSFET power modules.

[0083] In view of this, this application provides a half-bridge power module and its manufacturing method, a full-bridge power module, and an electrical device. The half-bridge power module integrates a wide-bandgap power chip and a silicon-based power chip, forming a single-phase half-bridge power module that combines wide-bandgap power chips and silicon-based power chips. This allows for better expansion of current specifications and power levels while addressing switching losses and product cost issues. Furthermore, by arranging the wide-bandgap power chip, which belongs to wide-bandgap semiconductor devices, on a first substrate, and the silicon-based power chip, which belongs to silicon-based semiconductor devices, on a second substrate, compared to related technologies that place different types of power components on the same substrate, this approach allows different types of power components and their corresponding substrates to adopt appropriate connection processes based on the material type of the power components. This optimizes the manufacturing process of the half-bridge power module, improves production efficiency and product yield, and reduces costs.

[0084] The half-bridge power module 100 of the first aspect embodiment of this application is described below with reference to Figures 1-7.

[0085] Referring to Figures 1-3, the half-bridge power module 100 of this embodiment may include: a base plate 1, a first substrate 2, and a second substrate 3.

[0086] The base plate 1 can be a thermally conductive metal component with good thermal conductivity. The base plate 1 can provide mounting support and heat dissipation for the first substrate 2 and the second substrate 3. The first substrate 2 and the second substrate 3 are both disposed on the same base plate 1, and the first substrate 2 and the second substrate 3 are arranged side by side and spaced apart along a first direction (the X direction shown in Figure 1).

[0087] The first substrate 2 and the second substrate 3 can both be one of the following: thick film printed ceramic substrate (TPC), direct bonded copper ceramic substrate (DBC), active metal bonded ceramic substrate (AMB), direct electroplated copper ceramic substrate (DPC), or other types of substrates. The first substrate 2 and the second substrate 3 can be the same type of substrate or different types of substrates.

[0088] Both the first substrate 2 and the second substrate 3 include a ceramic layer and metal layers located on both sides of the ceramic layer. The ceramic layer can be at least one of alumina, silicon nitride, and aluminum nitride, and the metal layer can be a copper layer or a metal layer made of other conductive metal materials. One of the metal layers can serve as a conductive metal layer, which can be divided into multiple conductive areas according to the circuit layout requirements. Each conductive area can be used to set up power components (including the wide bandgap power chip 43, silicon-based power chip 53, diode 6, and other types of components mentioned below) and connection circuits connecting different power components (the connection circuits are not shown in the figure and can be reasonably set according to the arrangement of each power chip, and will not be described in detail below). The other metal layer can serve as a heat dissipation surface for connecting with the base plate 1 for heat dissipation.

[0089] The first substrate 2 is provided with a first half-bridge unit 4, which includes multiple wide-bandgap power chips 43. In other words, the multiple wide-bandgap power chips 43 form the first half-bridge unit 4. Optionally, the first half-bridge unit 4 includes at least one half-bridge circuit, and each half-bridge circuit is composed of two wide-bandgap power chips 43. The second substrate 3 is provided with a second half-bridge unit 5, which includes multiple silicon-based power chips 53. In other words, the multiple silicon-based power chips 53 form the second half-bridge unit 5. Optionally, the second half-bridge unit 5 includes at least one half-bridge circuit, and each half-bridge circuit is composed of two silicon-based power chips 53. The first substrate 2 and the second substrate 3 are electrically connected. For example, the first half-bridge unit 4 is connected to the second half-bridge unit 5, and together they form the circuit portion of the half-bridge power module 100.

[0090] The wide bandgap semiconductor material can include SiC, GaN, etc., meaning the wide bandgap power chip 43 is a SiC device or a GaN device. The SiC device can be a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The silicon-based power chip 53 can be a Si-based fully controllable power chip, such as a Si IGBT (Insulated Gate Bipolar Transistor) or a Si MOSFET.

[0091] In other words, the half-bridge power module 100 of this embodiment is a hybrid module that integrates wide bandgap semiconductor devices and silicon semiconductor devices. Furthermore, since this application places power components of the same type on the same substrate (including the first substrate 2 and the second substrate 3 mentioned above), different types of power components and corresponding substrates can adopt corresponding connection processes according to the material type of the power components, thereby optimizing the manufacturing process of the half-bridge power module 100 and improving the performance of the half-bridge power module 100.

[0092] The half-bridge power module 100 of this application embodiment integrates a wide-bandgap power chip 43 and a silicon-based power chip 53, forming a single-phase half-bridge power module 100 that combines the wide-bandgap power chip 43 and the silicon-based power chip 53. This allows for better expansion of current specifications and power levels while addressing switching losses and product cost issues. Furthermore, by placing the wide-bandgap power chip 43, which is also a wide-bandgap semiconductor device, on the first substrate 2, and the silicon-based power chip 53, which is also a silicon-based semiconductor device, on the second substrate 3, compared to related technologies that place different types of power components on the same substrate, different types of power components and their corresponding substrates can be connected using appropriate processes based on the material type of the power components. This optimizes the manufacturing process of the half-bridge power module 100, improves production efficiency and product yield, and reduces costs.

[0093] Furthermore, by setting up two substrates, the first substrate 2 and the second substrate 3, compared to the related technology which sets up multiple substrates in the same power module, the number of connecting lines 7 can be significantly reduced, the circuit layout can be simplified, the space utilization can be improved, and the inductance can be reduced.

[0094] For ease of description, the following explanation will use the wide bandgap power chip 43 as a SiC MOSFET and the silicon-based power chip 53 as a Si IGBT as examples.

[0095] In some embodiments, referring to Figures 1-3, the half-bridge power module 100 further includes multiple power terminals, which may include a DC positive terminal 9, a DC negative terminal 10, and an AC terminal 11. The DC positive terminal 9 and the DC negative terminal 10 are located on the same substrate. For example, the DC positive terminal 9 and the DC negative terminal 10 are simultaneously located on the first substrate 2 or on the second substrate 3, to ensure that at least one of the wide-bandgap power chip 43 and the silicon-based power chip 53 has the shortest commutation circuit.

[0096] Furthermore, the DC positive terminal 9 and the DC negative terminal 10 can be simultaneously located on the first substrate 2. This minimizes the length of the commutation circuit where the wide bandgap power chip 43 is located, which is beneficial for improving its operating efficiency.

[0097] Optionally, either the DC positive terminal 9 or the DC negative terminal 10 is located on a different substrate from the AC terminal 11. For example, the DC positive terminal 9 and the DC negative terminal 10 are located on the first substrate 2, and the AC terminal 11 is located on the second substrate 3; or, the DC positive terminal 9 and the DC negative terminal 10 are located on the second substrate 3, and the AC terminal 11 is located on the first substrate 2. In this way, on the one hand, it is beneficial to simplify the internal structure of the half-bridge power module 100 and facilitate circuit layout; on the other hand, it can at least shorten the commutation circuit of one of the power elements, the wide-bandgap power chip 43 and the silicon-based power chip 53, and reduce the inductance of that part.

[0098] In some embodiments, the first substrate 2 includes a first surface located on one side in the thickness direction, and the second substrate 3 may include a second surface along one side in the thickness direction. For example, taking a horizontally placed substrate as an example, the first surface may be the upper surface of the first substrate 2, and the second surface may be the upper surface of the second substrate 3. Of course, a first thermally conductive metal layer may also be provided on the surface of the first substrate 2 opposite to the first surface, and the first thermally conductive metal layer may be connected to the base plate, for example, by welding. Similarly, a second thermally conductive metal layer may be provided on the surface of the second substrate 3 opposite to the second surface, and the second thermally conductive metal layer may be connected to the base plate, for example, by welding.

[0099] The first substrate 2 has a first conductive metal layer 21 on its first surface. The first conductive metal layer 21 has a plurality of first conductive regions. The plurality of first conductive regions may include a first DC positive electrode region 211, a first AC electrode region 212 and a first DC negative electrode region 213. The DC positive terminal 9 is disposed in the first DC positive electrode region 211 and the DC negative terminal 10 is disposed in the first DC negative electrode region 213.

[0100] The second surface of the second substrate 3 is provided with a second conductive metal layer 31. The second conductive metal layer 31 is provided with a plurality of second conductive regions, including a second DC positive electrode region 311, a second AC region 312, and a second DC negative electrode region 313. The AC terminal 11 is provided in the second AC region 312.

[0101] The first DC positive region 211 and the second DC positive region 311 are electrically connected, for example, through a connecting wire 7, to jointly form the DC positive region of the half-bridge power module 100. The first DC negative region 213 and the second DC negative region 313 are electrically connected, for example, through a connecting wire 7, to jointly form the DC negative region of the half-bridge power module 100. The first AC region 212 and the second AC region 312 are electrically connected, for example, through a connecting wire 7, to jointly form the AC region of the half-bridge power module 100.

[0102] In other words, in this embodiment, the DC positive terminal 9 and the DC negative terminal 10 are disposed on the first substrate 2, and the AC terminal 11 is disposed on the second substrate 3. Since the wide bandgap power chip 43 is disposed on the first substrate 2, the commutation circuit of the wide bandgap power chip 43 can be shortened, and the parasitic inductance of the first half-bridge unit 4 can be reduced.

[0103] The connecting wire 7 in this application can be a conductive metal wire made of gold, silver, copper, aluminum, copper strip, filter bag, metal connecting piece, or other materials. The DC positive region can be used for DC input, the DC negative region can be used for DC output, and the AC region can output AC. The connection method between the connecting wire 7 and the power element and the conductive region is bonding, that is, the connecting wire 7 is a bonding wire.

[0104] Optionally, the connection line 7 used to connect the wide-bandgap power chip 43 and the first substrate 2 may be different from the connection line 7 used to connect the silicon-based power chip 53 and the second substrate 3. For example, copper wires may be used to connect the wide-bandgap power chip 43 and the first substrate 2, while aluminum wires may be used to connect the silicon-based power chip 53 and the second substrate 3. Of course, this application does not limit this; the connection lines 7 of the wide-bandgap power chip 43 and the silicon-based power chip 53 can be reasonably selected according to actual needs to maximize the reliability of the circuit connection and minimize line resistance.

[0105] In this embodiment, the corresponding conductive areas on the first substrate 2 and the second substrate 3 are connected by a connecting line 7. The connecting line 7 is located inside the half-bridge power module 100. In particular, the first AC region 212 and the second AC region 312 are connected inside the half-bridge power module 100, which can effectively reduce the commutation inductance between the wide bandgap power chip 43 and the silicon-based power chip 53, and is beneficial to improving the electrical performance of the half-bridge power module 100.

[0106] In some embodiments, referring to Figures 1-3, the first half-bridge unit 4 includes a first upper-bridge chip group 41 and a first lower-bridge chip group 42. The first upper-bridge chip group 41 is disposed in the first DC positive region 211, and the first lower-bridge chip group 42 is disposed in the first AC region 212. Depending on the different shapes of the first DC positive region 211 and the first AC region 212, the first upper-bridge chip group 41 and the first lower-bridge chip group 42 can be arranged along a second direction (the Y direction shown in Figure 1) or along a first direction (the X direction shown in Figure 1). This embodiment does not limit this arrangement.

[0107] Both the first upper bridge chipset 41 and the first lower bridge chipset 42 include a number of wide bandgap power chips 43. The number of wide bandgap power chips 43 in the first upper bridge chipset 41 are connected in parallel with each other. The wide bandgap power chips 43 in the first upper bridge chipset 41 and the wide bandgap power chips 43 in the first lower bridge chipset 42 correspond one-to-one, and the two corresponding wide bandgap power chips 43 are connected to form a half-bridge circuit.

[0108] The second half-bridge unit 5 includes a second upper bridge chip group 51 and a second lower bridge chip group 52. The second upper bridge chip group 51 is located in the second DC positive region 311, and the second lower bridge chip group 52 is located in the second AC region 312. Depending on the different shapes of the second DC positive region 311 and the second AC region 312, the second upper bridge chip group 51 and the second lower bridge chip group 52 can be arranged along a second direction or along a first direction. Both the second upper bridge chip group 51 and the second lower bridge chip group 52 include a plurality of silicon-based power chips 53. The plurality of silicon-based power chips 53 in the second upper bridge chip group 51 are connected in parallel with each other. The silicon-based power chips 53 in the second upper bridge chip group 51 and the silicon-based power chips 53 in the second lower bridge chip group 52 correspond one-to-one, and the two corresponding silicon-based power chips 53 are connected to form a half-bridge circuit.

[0109] Thus, the hybrid module integrating the wide bandgap power chip 43 and the silicon-based power chip 53 in this embodiment has amplified its current specifications and power levels, improved its electrical performance, and can better meet the usage requirements in high-voltage and high-current operating scenarios, such as as an automotive-grade power module.

[0110] In some embodiments, referring to Figures 1-3, the first upper bridge chip group 41 and the first lower bridge chip group 42 are arranged along a second direction, and the wide bandgap power chips 43 in the first upper bridge chip group 41 and the first lower bridge chip group 42 are arranged along a first direction.

[0111] During the operation of the half-bridge power module 100, the direction of DC current flow is from the DC positive terminal region to the DC negative terminal region. The multiple wide-bandgap power chips 43 in the first upper-bridge chipset 41 are arranged along the first direction, and each wide-bandgap power chip 43 is connected to the first AC region 212 along the connecting line 7 (i.e. the first connecting line 71) along the second direction. This makes the arrangement direction of the multiple wide-bandgap power chips 43 perpendicular to the current flow direction between the first upper-bridge chipset 41 and the first AC region 212. In addition, each wide-bandgap power chip 43 in the first upper-bridge chipset 41 has a relatively close or even the same current path, which improves the current distribution. This makes each wide-bandgap power chip 43 in the first upper-bridge chipset 41 have good dynamic current sharing performance, which is conducive to ensuring the uniform distribution of current stress and thermal stress among each wide-bandgap power chip 43.

[0112] In other words, by setting it up as described above, it is possible to ensure that each wide bandgap power chip 43 in the first wide bandgap chipset has good dynamic current sharing performance, which is beneficial to ensuring the uniform distribution of current stress and thermal stress among each wide bandgap power chip 43.

[0113] The second upper bridge chip group 51 and the second lower bridge chip group 52 are arranged along the second direction. Each of the two upper bridge chip groups 51 and the second lower bridge chip group 52 includes a number of silicon-based power chips 53 arranged in parallel along the first direction.

[0114] Understandably, the multiple silicon-based power chips 53 in the second upper bridge chipset 51 are arranged along the first direction, and each silicon-based power chip 53 is connected to the second AC region 312 by the connecting line 7 (i.e. the third connecting line 73) along the second direction. This makes the arrangement direction of the multiple silicon-based power chips 53 perpendicular to the current flow direction between the second upper bridge chipset 51 and the second AC region 312. The silicon-based power chips 53 in the second upper bridge chipset 51 have relatively close or even the same current path, which improves the current distribution. This makes the silicon-based power chips 53 in the second upper bridge chipset 51 have good dynamic current sharing performance, which is conducive to ensuring the uniform distribution of current stress and thermal stress among the silicon-based power chips 53.

[0115] Similarly, when multiple silicon-based power chips 53 in the second lower-bridge chipset 52 are arranged along the first direction, and each silicon-based power chip 53 is connected to the second DC negative terminal region 313 via a connecting line 7 (i.e., the fourth connecting line 74) along the second direction, the current output direction within the second DC negative terminal region 313 is the same as the current direction between each silicon-based power chip 53 and the second DC negative terminal region 313. This allows each silicon-based power chip 53 in the second lower-bridge chipset 52 to have good dynamic current sharing performance, which is beneficial for ensuring a uniform distribution of current stress and thermal stress among the silicon-based power chips 53. Of course, the current output direction within the DC negative terminal region is related to the location of the DC negative terminal 10, and this embodiment does not impose any restrictions on this.

[0116] In other words, by setting it up as described above, it is possible to ensure that each silicon-based power chip 53 of the first silicon-based chipset has good dynamic current sharing performance, which is beneficial to ensuring the uniform distribution of current stress and thermal stress among each silicon-based power chip 53.

[0117] In some embodiments, referring to Figures 1-3, a plurality of wide-bandgap power chips 43 in the first upper-bridge chipset 41 are connected to the first AC region 212 via a connection line 7 (i.e., the first connection line 71) along the second direction, and a plurality of wide-bandgap power chips 43 in the first lower-bridge chipset 42 are connected to the first DC negative region 213 via a connection line 7 (i.e., the second connection line 72) along the second direction. This facilitates dynamic current sharing among the wide-bandgap power chips 43 in the first upper-bridge chipset 41.

[0118] Several silicon-based power chips 53 in the second upper-bridge chipset 51 are connected to the second AC region 312 via connecting lines 7 along the second direction, and several silicon-based power chips 53 in the second lower-bridge chipset 52 are connected to the second DC negative region 313 via connecting lines 7 along the second direction. This facilitates dynamic current sharing among the silicon-based power chips 53 in the second upper-bridge chipset 51.

[0119] In some embodiments, at least a portion of the first DC positive region 211, the first AC region 212, and the first DC negative region 213 extend along a first direction and are arranged along a second direction.

[0120] For example, the first DC positive region 211 can be formed as a whole into a square extending along the first direction, or a part of the first DC positive region 211 can extend along the first direction and the other part can extend along the second direction; the first DC negative region 213 can be formed as a whole into a square extending along the first direction, or a part of the first DC negative region 213 can extend along the first direction and the other part can extend along the second direction; the first AC region 212 can be formed as a whole into a square extending along the first direction, or a part of the first AC region 212 can extend along the first direction and the other part can extend along the second direction; the shape and size of any two of the first DC positive region 211, the first AC region 212 and the first DC negative region 213 can be the same or different, and can be reasonably set according to actual needs. The portions of the first DC positive region 211, the first AC region 212, and the first DC negative region 213 extending along the first direction can be arranged along the second direction. The first upper bridge chip group 41 is located in the portion of the first DC positive region 211 extending along the first direction, and the first lower bridge chip group 42 is located in the portion of the first AC region 212 extending along the first direction.

[0121] In this way, it is possible for multiple wide bandgap power chips 43 arranged along the first direction on the first DC positive region 211 to be connected to the first AC region 212 through the connecting line 7 along the second direction, and for multiple wide bandgap power chips 43 arranged along the first direction on the first AC region 212 to be connected to the first DC negative region 213 through the connecting line 7 along the second direction, so as to improve the current sharing among the wide bandgap power chips 43.

[0122] Referring to Figures 1-3, at least a portion of the second DC positive region 311, the second AC region 312, and the second DC negative region 313 extend along the first direction and are arranged along the second direction.

[0123] For example, the second DC positive region 311 can be formed as a whole into a square extending along the first direction, or a portion of the second DC positive region 311 can extend along the first direction while the other portion can extend along the second direction; the second DC negative region 313 can be formed as a whole into a square extending along the first direction, or a portion of the second DC negative region 313 can extend along the first direction while the other portion can extend along the second direction; the second AC region 312 can be formed as a whole into a square extending along the first direction, or a portion of the second AC region 312 can extend along the first direction while the other portion can extend along the second direction; the shape and size of any two of the second DC positive region 311, the second AC region 312, and the second DC negative region 313 can be the same or different, and can be reasonably set according to actual needs. The portions of the second DC positive region 311, the second AC region 312, and the second DC negative region 313 extending along the first direction can be arranged along the second direction, the second upper bridge chip group 51 is disposed in the portion of the second DC positive region 311 extending along the first direction, and the second lower bridge chip group 52 is disposed in the portion of the second AC region 312 extending along the first direction.

[0124] In this way, it is possible for multiple silicon-based power chips 53 arranged along the first direction on the second DC positive region 311 to be connected to the second AC region 312 through the connecting line 7 along the second direction, and for multiple silicon-based power chips 53 arranged along the first direction on the second AC region 312 to be connected to the second DC negative region 313 through the connecting line 7 along the second direction, so as to improve the current sharing among the silicon-based chips.

[0125] In some embodiments, the first DC positive region 211 and the second DC positive region 311 are arranged opposite to each other along a first direction, the first DC negative region 213 and the second DC negative region 313 are arranged opposite to each other along a first direction, and the first AC region 212 and the second AC region 312 are arranged opposite to each other along a first direction. That is, any two corresponding conductive regions on the first substrate 2 and the second substrate 3 are arranged opposite to each other along the first direction. The arrangement along the first direction, as shown in the figure, can be two regions arranged in the first direction. In this way, on the one hand, the internal layout of the half-bridge power module 100 can be more regular and simple, and the space utilization rate can be higher. On the other hand, the connection line 7 between two corresponding conductive regions can be shortened, thereby reducing the inductance of the half-bridge power module 100.

[0126] Referring to Figure 3, in some embodiments, the first upper-bridge chip group 41 and the first lower-bridge chip group 42 are also provided with diodes 6 (i.e., first-type diodes 6a). The first-type diodes 6a have the same substrate material type as the wide-bandgap power chip 43, and the first-type diodes 6a and wide-bandgap power chips 43 are connected in parallel in a one-to-one correspondence. For example, the first-type diodes 6a in the first upper-bridge chip group 41 and the first lower-bridge chip group 42 can be wide-bandgap substrate Schottky diodes, such as SiC SBDs (Schottky first-type diodes 6a). The first-type diodes 6a are connected in parallel with the wide-bandgap power chip 43, which can help to bear the reverse current and prevent the SiC MOSFE from being damaged by excessive reverse current. In addition, by connecting the SiC SBDs in parallel, when the SiC MOSFE is turned off, the reverse recovery loss of the SiC SBDs is lower, which can greatly reduce power loss and improve conversion efficiency, thereby improving the performance of the half-bridge power module 100. In this process, the first type of diode 6a in the first upper bridge chip group 41 can be connected to the first AC region 212 via the connecting line 7, and the first type of diode 6a in the first lower bridge chip group 42 can be connected to the first DC negative region 213 via the connecting line 7.

[0127] Optionally, the first type of diode 6a and the wide bandgap power chip 43 can be arranged alternately along the first direction to prevent severe thermal coupling when two wide bandgap power chips 43 are arranged adjacent to each other or two first type of diodes 6a are arranged adjacent to each other, thereby reducing the heat dissipation pressure of the module.

[0128] Referring to Figures 1 and 2, in some embodiments, the second upper bridge chip group 51 and the second lower bridge chip group 52 are further provided with diodes 6 (i.e., second type diodes 6b), and the second type diodes 6b have the same substrate material type as the silicon-based power chip 53. Optionally, the second type diodes 6b correspond one-to-one with the silicon-based power chips 53, and the corresponding silicon-based power chips 53 and second type diodes 6b are connected in parallel to form a chip pair. For example, the second type diodes 6b can be silicon substrate fast recovery second type diodes 6b, and the second type diodes 6b can be connected in reverse parallel with the silicon-based power chips 53.

[0129] In this embodiment, by connecting the second type of diode 6b in reverse parallel to the silicon-based power chip 53, the overall reverse current carrying capacity of the module can be enhanced, which is beneficial to improving the overall efficiency and reliability of the half-bridge power module 100. Specifically, the second type of diode 6b in the second upper bridge chip group 51 can be connected to the second AC region 312 via the connecting line 7, and the second type of diode 6b in the second lower bridge chip group 52 can be connected to the second DC negative region 313 via the connecting line 7.

[0130] Optionally, the second type diode 6b and the silicon-based power chip 53 can be arranged alternately along the first direction to prevent severe thermal coupling when the two silicon-based power chips 53 are arranged adjacent to each other or the two second type diodes 6b are arranged adjacent to each other, thereby reducing the heat dissipation pressure of the module.

[0131] Optionally, only the first upper-bridge chip group 41 and the first lower-bridge chip group 42 may have diodes 6 made of the same material as the wide-bandgap power chip 43; or, only the second upper-bridge chip group 51 and the second lower-bridge chip group 52 may have diodes 6 made of the same material as the silicon-based power chip 53; or, the first upper-bridge chip group 41 and the first lower-bridge chip group 42 may have diodes 6 made of the same material as the wide-bandgap power chip 43, while the second upper-bridge chip group 51 and the second lower-bridge chip group 52 may have diodes 6 made of the same material as the silicon-based power chip 53.

[0132] Referring to Figure 6, the diode 6 includes a cathode 62 and an anode 61. The anode 61 is located at the top of the diode 6 (i.e., the side of the diode 6 facing away from the substrate) and is used for electrical connection with other conductive areas (including the first conductive area and the second conductive area). The cathode 62 is located at the bottom of the diode 6 (i.e., the side of the diode 6 facing the substrate) and is connected to the conductive area thereon by sintering or welding.

[0133] In some embodiments, the wide-bandgap power chip 43 includes a SiC MOSFET, and the silicon-based power chip 53 includes a Si IGBT. That is, the half-bridge power module 100 of this embodiment packages the SiC MOSFET and the Si IGBT in parallel, facilitating the switching action of the SiC MOSFET using drive signals with different timings, while the Si IGBT bears most of the conduction current. This solves the problems of high switching losses and low switching frequency of IGBTs, and allows a larger current to be controlled by a SiC MOSFET with a smaller current carrying capacity, thus addressing the high cost of SiC. In this way, both the performance and cost of the half-bridge power module 100 can be balanced.

[0134] Referring to Figure 4, the SiC MOSFET includes a source 431, a gate 432, and a drain 433. The drain 433 is located on the side of the SiC MOSFET facing the conductive metal layer and is connected to the conductive region thereon through a welding or sintering process. The source 431 and the gate 432 are located on the side of the SiC MOSFET away from the conductive metal layer and are used to connect to other conductive regions.

[0135] Referring to Figure 5, the Si IGBT includes an emitter 531, a gate 532, and a collector 533. The collector 533 is located at the bottom of the Si IGBT (the side of the Si IGBT facing the conductive metal layer) and is used to connect with the conductive region thereon by means of sintering, welding, etc. The emitter 531 and the gate 532 are located on the side of the Si IGBT away from the conductive metal layer and are used to connect with other conductive regions.

[0136] In some embodiments, referring to Figures 1-3, the first conductive metal layer 21 may further include two SiC driving layer groups, which correspond to the first upper bridge chip group 41 and the first lower bridge chip group 42, respectively. The two SiC driving layer groups are: a first SiC driving layer group 214 and a second SiC driving layer group 215.

[0137] The first SiC driving layer group 214 may include a first SiC gate driving layer 2141 and a first SiC source driving layer 2142. The gate 432 of the SiC MOSFET of the first upper bridge chip group 41 is connected to the first SiC gate driving layer 2141 through the connection line 7, and the source 431 of the SiC MOSFET of the first upper bridge chip group 41 is connected to the first SiC source driving layer 2142 through the connection line 7.

[0138] The second SiC driving layer group 215 may include a second SiC gate driving layer 2151 and a second SiC source driving layer 2152. The gate 432 of the SiC MOSFET of the first lower bridge chip group 42 is connected to the second SiC gate driving layer 2151 through the connection line 7, and the source 431 of the SiC MOSFET of the first lower bridge chip group 42 is connected to the second SiC source driving layer 2152 through the connection line 7.

[0139] Optionally, the second conductive metal layer 31 may further include two IGBT driving layer groups, which correspond to the second upper bridge chip group 51 and the second lower bridge chip group 52, respectively. The two IGBT driving layer groups are: a first IGBT driving layer group 314 and a second IGBT driving layer group 315.

[0140] The first IGBT driving layer group 314 may include a first IGBT gate driving layer 3141 and a first IGBT emitter driving layer 3142. The gate 532 of the Si IGBT of the second upper bridge chip group 51 is connected to the first IGBT gate driving layer 3141 through the connection line 7, and the emitter 531 of the Si IGBT of the second upper bridge chip group is connected to the first IGBT emitter driving layer 3142 through the connection line 7.

[0141] The second IGBT driving layer group 315 may include a second IGBT gate driving layer 3151 and a second IGBT emitter driving layer 3152. The gate 532 of the Si IGBT of the second lower bridge chip group 52 is connected to the second IGBT gate driving layer 3151 through the connection line 7, and the emitter 531 of the Si IGBT of the second lower bridge chip group 52 is connected to the second IGBT emitter driving layer 3152 through the connection line 7.

[0142] Thus, by setting up the first SiC driving layer group 214 and the second SiC driving layer group 215, the first IGBT driving layer group 314 and the second IGBT driving layer group 315, the connection between each wide bandgap power chip 43, silicon-based power chip 53 and external circuits can be facilitated.

[0143] Optionally, driving terminals 8 are provided on the first SiC gate driving layer 2141, the first IGBT gate driving layer 3141, the first SiC source driving layer 2142, the first IGBT emitter driving layer 3142, the second SiC gate driving layer 2151, the second IGBT gate driving layer 3151, the second SiC source driving layer 2152, and the second IGBT emitter driving layer 3152. Each driving terminal 8 can be led out perpendicularly to the substrate to simplify the internal circuit structure of the half-bridge power module 100, reduce space occupation, and facilitate the connection of the half-bridge power module 100 with external circuits.

[0144] In some embodiments, the base plate 1 includes a first side 1a and a second side 1b opposite to each other along a second direction, and a third side 1c and a fourth side 1d opposite to each other along a first direction. The first SiC driving layer group 214 is located on the side of the first DC positive region 211 facing the first side 1a, and the second SiC driving layer group 215 is located on the side of the first DC negative region 213 facing the second side 1b. This makes the distance between the first SiC driving layer and the first upper bridge chip group 41 closer, and the distance between the second SiC driving layer and the first lower bridge chip group 42 closer, which can shorten the length of the connection line 7 of each wide bandgap power chip 43 in the first half-bridge unit 4, thereby shortening the commutation circuit of the wide bandgap power chip 43 and helping to reduce the circuit inductance.

[0145] The first IGBT driving layer group 314 is located on the side of the second DC positive region 311 facing the first side 1a, and the second IGBT driving layer group 315 is located on the side of the second DC negative region 313 facing the second side 1b. This brings the first IGBT driving layer group 314 closer to the second upper bridge chip group 51, and the second IGBT driving layer group 315 closer to the second lower bridge chip group 52. This shortens the length of the connection lines 7 of the various silicon-based power chips 53 within the second half-bridge unit 5, thereby shortening the commutation circuit of the silicon-based power chips 53 and reducing the circuit inductance.

[0146] Among them, one end of the DC positive terminal 9 is connected to the first DC positive region 211, and the other end is led out from the third side 1c along the first direction. One end of the DC negative terminal 10 is connected to the first DC negative region 213, and the other end is led out from the third side 1c along the first direction. One end of the AC terminal 11 is connected to the second AC region 312, and the other end is led out from the fourth side 1d along the first direction.

[0147] In some embodiments, the wide bandgap power chip 43 and the first substrate 2 are connected by a first connection process, which can be a sintering process or a welding process. This can better meet the conductivity and heat dissipation requirements between the wide bandgap power chip 43 and the first substrate 2, making it more suitable for high-power applications and resulting in a more reliable structure.

[0148] The silicon-based power chip 53 and the second substrate 3 are connected by a second connection process. The first connection process can be a sintering process or a welding process. In this way, the connection process between the silicon-based power chip 53 and the second substrate 3 is simpler and the cost is lower.

[0149] Optionally, one of the first connection process and the second connection process is a sintering process, and the other is a welding process. That is to say, the connection process used between the wide bandgap power chip 43 and the first substrate 2 is different from the connection process used between the silicon-based power chip 53 and the second substrate 3.

[0150] Optionally, both the first and second connection processes can be sintering processes, or both can be welding processes. Furthermore, the process parameters for the first and second connection processes can differ, and these parameters may include process temperature, process duration, and other parameters affecting the connection effect. In other words, the connection process used between the wide-bandgap power chip 43 and the first substrate 2, and the connection process used between the silicon-based power chip 53 and the second substrate 3, can be the same type, differing only in their process parameters.

[0151] In this embodiment, the wide-bandgap power chip 43 and the silicon-based power chip 53 are disposed on two different substrates, and the connection method between the wide-bandgap power chip 43 and the first substrate 2 is different from the connection method between the silicon-based power chip 53 and the second substrate 3. This allows the connection processes of the wide-bandgap power chip 43 and the first substrate 2 and the silicon-based power chip 53 and the second substrate 3 to be carried out simultaneously, which helps to shorten the manufacturing process of the half-bridge power module 100 and improve production efficiency. In addition, this embodiment matches the connection methods of the wide-bandgap power chip 43 and the silicon-based power chip 53 with their respective materials and operating conditions (including heat generation and current handling) when the half-bridge power module 100 is working, which helps to improve the overall performance of the half-bridge power module 100 while taking into account manufacturing cost and efficiency.

[0152] The full-bridge power module 200 of the second aspect of this application is described below with reference to FIG7.

[0153] Referring to Figure 7, the full-bridge power module 200 of this embodiment includes the half-bridge power module 100 described in the above embodiment. Specifically, there can be multiple half-bridge power modules 100, where multiple means two or more. The multiple half-bridge power modules 100 are connected to form the full-bridge power module 200.

[0154] For example, as shown in Figure 7, there are three half-bridge power modules 100, including a first half-bridge power module 100, a second half-bridge power module 100, and a third half-bridge power module 100. These three half-bridge power modules 100 can constitute a three-phase full-bridge power module 200, and each half-bridge power module 100 corresponds to one single phase. Specifically, the first half-bridge power module 100 can correspond to phase U, the second half-bridge power module 100 can correspond to phase V, and the third half-bridge power module 100 can correspond to phase W. The first, second, and third half-bridge power modules 100 can be arranged sequentially, or their order can be adjusted as needed. Optionally, the three half-bridge power modules 100 can share a common base plate 1 to further simplify the structure of the full-bridge power module 200.

[0155] The full-bridge power module 200 according to the embodiments of this application is composed of multiple half-bridge power modules 100 as described in the above embodiments. Since each half-bridge power module 100 is a number of parallel half-bridge circuits formed by wide-bandgap power chips 43 and silicon-based power chips 53, the current specification of the full-bridge power module 200 is greatly amplified, which can better convert DC power into AC power for use by electrical devices. It has stronger electrical performance and is more suitable for use as an automotive-grade power module.

[0156] The following describes an electrical appliance 300 according to a third aspect embodiment of this application.

[0157] The electrical device 300 in this embodiment can be a new energy vehicle or other types of electrical device 300. The electrical device 300 may include a power module, which may include the half-bridge power module 100 in the first aspect embodiment above, and / or the full-bridge power module 200 in the second aspect embodiment above.

[0158] Specifically, the electrical equipment 300 also includes an energy storage device and an electrical device. The energy storage device can be a battery pack, and the electrical device can be a motor, such as a three-phase AC motor. A power module is located between the energy storage device and the electrical device, and the power module can convert the DC power generated by the energy storage device into AC power for the use of the electrical device.

[0159] The electrical equipment 300 may be equipped with only a half-bridge power module 100, or only a full-bridge power module 200, or the half-bridge power module 100 and the full-bridge power module 200 may be combined as needed.

[0160] The electrical device 300 in this embodiment of the application can convert the direct current generated by the energy storage device into alternating current to power the electrical device, such as the electric motor, by setting a power module, thereby providing power for the vehicle's movement. Furthermore, since the power module adopts the half-bridge power module 100 and / or the full-bridge power module 200 in the above embodiment, the power level is higher, and it can better perform AC-DC conversion, resulting in more reliable performance.

[0161] The manufacturing method of a half-bridge power module 100 according to a fourth aspect embodiment of this application is described below with reference to Figures 8-10.

[0162] Referring to Figure 8, the manufacturing method of the half-bridge power module 100 in this embodiment can be used to manufacture the half-bridge power module 100 in the above embodiments. The manufacturing method of this embodiment will be described below using the wide-bandgap power chip 43 as a SiC MOSFET, the silicon-based power chip 53 as a Si IGBT, and the diode 6 (silicon-based) as examples. The manufacturing method of this embodiment may include the following steps:

[0163] S101, the wide bandgap power chip 43 is fixed to the first substrate 2, and the silicon-based power chip 53 is fixed to the second substrate 3;

[0164] The SiC MOSFET can be fixed to the first substrate 2 by sintering. Specifically, the SiC MOSFET of the first upper bridge chip group 41 is sintered to the first DC positive region 211 on the first substrate 2, and the SiC MOSFET of the first lower bridge chip group 42 is sintered to the first AC region 212 on the first substrate 2. Simultaneously, the Si IGBT and diode 6 can be fixed to the second substrate 3 by welding. Specifically, the Si IGBT and diode 6 of the second upper bridge chip group 51 are welded to the second DC positive region 311 on the second substrate 3, and the Si IGBT and diode 6 of the second lower bridge chip group 52 are welded to the second AC region 312 on the second substrate 3. It can be understood that the sintering process of the SiC MOSFET to the first substrate 2 and the welding process of the Si IGBT and diode 6 to the second substrate 3 are independent of each other and can be performed simultaneously.

[0165] S102, the wide bandgap power chip 43 is bonded to the first substrate 2 via the connection line 7, and the silicon-based power chip 53 is bonded to the second substrate 3 via the connection line 7;

[0166] For example, the SiC MOSFET can be bonded to the first substrate 2 with copper wires, and the Si IGBT and diode 6 can be bonded to the second substrate 3 with aluminum wires. It can be understood that the bonding process between the wide bandgap power chip 43 and the first substrate 2, as well as the bonding process between the Si IGBT, diode 6 and the second substrate 3, are independent of each other and can be carried out simultaneously.

[0167] S103, electrical tests are performed on the first half-bridge unit 4 formed by the wide bandgap power chip 43 and the second half-bridge unit 5 formed by the silicon-based power chip 53 respectively;

[0168] Specifically, electrical testing is performed on the first circuit unit formed on the first substrate 2 to eliminate unqualified first substrate 2; electrical testing is performed on the second circuit unit formed on the second substrate 3 to eliminate unqualified second substrate 3. It is understood that the electrical testing of the first circuit unit and the electrical testing of the second circuit unit are independent of each other and can be performed simultaneously.

[0169] S104, fix the first substrate 2 and the second substrate 3, which have passed the electrical test, to the base plate 1 respectively;

[0170] For example, the first substrate 2 and the second substrate 3 are both welded to the base plate 1, so that the first substrate 2, the second substrate 3 and the base plate 1 are formed into an integral structure.

[0171] S105, the first substrate 2 and the second substrate 3 are connected by the connecting line 7;

[0172] Specifically, each first conductive region on the first conductive metal layer 21 and the corresponding second conductive region on the second conductive metal layer 31 can be connected by connecting lines 7. For example, the first DC positive region 211 and the second DC positive region 311 can be connected by connecting lines 7 to jointly form the DC positive region of the half-bridge power module 100; the first DC negative region 213 and the second DC negative region 313 can be connected by connecting lines 7 to jointly form the DC negative region of the half-bridge power module 100; and the first AC region 212 and the second AC region 312 can be connected by connecting lines 7 to jointly form the AC region of the half-bridge power module 100.

[0173] S106, mounting housing and connection terminals.

[0174] The connection terminals may also include a drive terminal 8 and a power terminal. The power terminal may include the aforementioned DC positive terminal 9, DC negative terminal 10, and AC terminal 11. The drive terminal 8 is a terminal connected to each of the drive layers, such as the first SiC gate drive layer 2141, the first IGBT gate drive layer 3141, the first SiC source drive layer 2142, the first IGBT emitter drive layer 3142, the second SiC gate drive layer 2151, the second IGBT gate drive layer 3151, the second SiC source drive layer 2152, and the second IGBT emitter drive layer 3152.

[0175] After the first substrate 2 and the second substrate 3 are both mounted to the base plate 1 and the first substrate 2 and the second substrate 3 form a complete circuit, the various drive terminals 8 and power terminals are installed. Then, the overall structure composed of the first substrate 2, the second substrate 3 and the base plate 1 is assembled with the housing to form a complete half-bridge power module 100.

[0176] Referring to Figures 9 and 10, the manufacturing method of the half-bridge power module 100 in this embodiment and the manufacturing method of the hybrid module in related technologies will be analyzed below. In order to meet the packaging requirements of different chips and to comprehensively consider manufacturing costs, the following description will use SiC MOSFET chips with sintering process and copper wire bonding, and Si IGBT chips with welding process and aluminum wire bonding as examples:

[0177] Please refer to Figure 10, which illustrates the manufacturing process of a hybrid module in the related technology. In a module structure where the substrate is not separated (i.e., SiC MOSFETs and Si IGBTs are located on the same substrate), the key processes and sequence are as follows: First, a sintering process is performed to sinter the SiC MOSFETs onto the ceramic substrate; then, a wire bonding process is performed to bond the SiC MOSFETs to the ceramic substrate using copper wires; electrical testing is performed on the half-bridge unit where the SiC MOSFETs are located, rejecting defective products and allowing qualified products to proceed to the next process; a soldering process is performed to solder the Si IGBTs onto the same ceramic substrate; a second wire bonding process is performed, connecting the Si IGBTs to the ceramic substrate using aluminum wires; electrical testing is performed on the hybrid module half-bridge unit, rejecting defective products and allowing qualified products to proceed to the next process; a second soldering process is performed to solder the ceramic substrate to base plate 1; finally, the housing is installed and terminals are connected. In this scheme, the processes for SiC MOSFETs and Si IGBTs can only be performed sequentially, resulting in a longer manufacturing process. This not only reduces production efficiency but also lowers the overall production yield and increases costs. Assuming the cost of SiC MOSFET packaging is A and the defect rate is a; and the cost of Si IGBT packaging is B and the defect rate is b, then the expected value of the loss caused by the defect rate in the entire production process is: A×a+A×(1-a)×b+B×b. That is, the defects generated in the Si IGBT packaging stage will cause the qualified products generated in the SiC MOSFET packaging stage to be scrapped.

[0178] Figure 9 shows the manufacturing process of the half-bridge power module 100 of this application as a hybrid module. It also takes the SiC MOSFET as an example, which is bonded to the first substrate 2 by copper wire through a sintering process, and the Si IGBT as an example, which is bonded to the second substrate 3 by aluminum wire through a welding process.

[0179] Because this application adopts a hybrid module design with separate substrates (SiC MOSFETs and Si IGBTs are on different substrates), the packaging and testing processes of the half-bridge unit where the SiC MOSFET is located (i.e., the first half-bridge unit 4 mentioned above) and the half-bridge unit where the Si IGBT is located (i.e., the second half-bridge unit 5 mentioned above) can be carried out in parallel, thereby improving production efficiency.

[0180] Furthermore, the half-bridge unit containing the SiC MOSFET and the half-bridge unit containing the Si IGBT can be separately tested and screened for electrical defects. After rejecting defective products, they proceed to secondary soldering, where the first substrate 2 containing the SiC MOSFET and the second substrate 3 containing the Si IGBT are soldered to the same base plate 1. Then, the connection between the first substrate 2 and the second substrate 3 is made, that is, the copper layers of the corresponding conductive areas of the first substrate 2 and the second substrate 3 are connected by bonding wires. Finally, the housing is installed and the terminals are connected.

[0181] In this application, since the packaging and testing of SiC MOSFETs and Si IGBTs can be carried out in parallel, in addition to improving production efficiency, production yield can also be improved and costs reduced. Similarly, assuming the cost of the SiC MOSFET packaging stage is A and the defect rate is a; and the cost of the Si IGBT packaging stage is B and the defect rate is b, then the expected value of the loss caused by the defect rate in the entire production process is: A×a+B×b. Compared with the manufacturing methods in related technologies, the manufacturing method of this application embodiment can reduce the loss by A×(1-a)×b, thereby greatly reducing production costs and improving efficiency.

[0182] In summary, the manufacturing method of the half-bridge power module 100 in this application adopts a hybrid module design that places SiC MOSFETs and Si IGBTs on different substrates. This allows the packaging and testing processes of the half-bridge unit containing SiC MOSFETs and the half-bridge unit containing Si IGBTs to proceed in parallel, thereby improving production efficiency, increasing production yield, reducing costs, and making it suitable for mass production.

[0183] In some embodiments, fixing the wide-bandgap power chip 43 to the first substrate 2 and the silicon-based power chip 53 to the second substrate 3 may include the following steps:

[0184] The wide-bandgap power chip 43 is fixed to the first substrate 2 by a first connection process, and the silicon-based power chip 53 is fixed to the second substrate 3 by a second connection process. The first connection process is one of sintering and welding processes; the second connection process is one of sintering and welding processes.

[0185] For example, the wide bandgap power chip 43 can be fixed to the first substrate 2 by sintering, which can better meet the conductivity and heat dissipation requirements between the wide bandgap power chip 43 and the first substrate 2, making it more suitable for high-power applications and more reliable in structure; the wide bandgap power chip 43 can also be fixed to the first substrate 2 by welding, which is a simpler connection method and has a lower cost.

[0186] The silicon-based power chip 53 is fixed to the second substrate 3 by a sintering process, which can better meet the conductivity and heat dissipation requirements between the silicon-based power chip 53 and the second substrate 3, making it more suitable for high-power applications and more reliable in structure. The silicon-based power chip 53 is fixed to the second substrate 3 by a welding process, which makes the connection process between the silicon-based power chip 53 and the second substrate 3 simpler and lower in cost.

[0187] It should also be noted that the wide-bandgap power chip 43 and the silicon-based power chip 53 are disposed on two different substrates, and the connection method between the wide-bandgap power chip 43 and the first substrate 2 is different from the connection method between the silicon-based power chip 53 and the second substrate 3. This allows the connection process between the wide-bandgap power chip 43 and the first substrate 2 and the silicon-based power chip 53 and the second substrate 3 to be carried out simultaneously, which helps to shorten the manufacturing process of the half-bridge power module 100 and improve production efficiency. In addition, this embodiment matches the connection methods of the wide-bandgap power chip 43 and the silicon-based power chip 53 with their respective materials and operating conditions (including heat generation and current handling) when the half-bridge power module 100 is working, which helps to improve the overall performance of the half-bridge power module 100 while taking into account manufacturing cost and efficiency.

[0188] Optionally, one of the first connection process and the second connection process is a sintering process, and the other is a welding process. That is, the connection process used between the wide-bandgap power chip 43 and the first substrate 2 is different from the connection process used between the silicon-based power chip 53 and the second substrate 3. In this way, it is convenient to select an appropriate process based on the materials and functions of the power components (including the aforementioned wide-bandgap power chip 43 and silicon-based power chip 53) and the substrates (including the aforementioned first substrate 2 and second substrate 3), thereby achieving higher connection performance and product quality.

[0189] Optionally, both the first and second connection processes can be sintering processes, or both can be welding processes. Furthermore, the process parameters for the first and second connection processes can differ, including process temperature, process duration, and other parameters affecting the connection effect. In other words, the connection process used between the wide-bandgap power chip 43 and the first substrate 2 can be the same as the connection process used between the silicon-based power chip 53 and the second substrate 3, differing only in the process parameters. This allows for convenient selection of appropriate process parameters based on the materials and functions of the power components (including the aforementioned wide-bandgap power chip 43 and silicon-based power chip 53) and the substrates (including the aforementioned first substrate 2 and second substrate 3), achieving higher connection performance and product quality.

[0190] In some embodiments, fixing the first substrate 2 and the second substrate 3, which have passed the electrical test, to the base plate 1 includes: welding both the first substrate 2 and the second substrate 3 to the base plate 1.

[0191] In other words, in this embodiment, the connection process between the first substrate 2 and the base plate 1 is the same as the connection process between the second substrate 3 and the base plate 1, and both are welding. This simplifies the process complexity of this step, improves production efficiency, and makes it easier to implement.

[0192] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0193] It should be noted that the embodiments referred to in the specification, such as "one embodiment," "embodiment," "exemplary embodiment," and "some embodiments," may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0194] Generally speaking, terms should be understood at least in part by their use in context. For example, at least in part by context, the term "one or more" as used in the text can be used to describe any feature, structure, or characteristic of the singular meaning, or a combination of features, structures, or characteristics of the plural meaning. Similarly, at least in part by context, terms such as "a" or "the" can also be understood to convey either singular or plural usage.

[0195] It should be readily understood that the terms “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “on top of something” but also “on top of something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0196] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A half-bridge power module (100), wherein, include: Base plate (1); A first substrate (2) and a second substrate (3) are arranged side by side and spaced apart on the base plate (1) along a first direction. The first substrate (2) is provided with a first half-bridge unit (4), which includes a plurality of wide bandgap power chips (43). The second substrate (3) is provided with a second half-bridge unit (5), which includes a plurality of silicon-based power chips (53). The first substrate (2) and the second substrate (3) are electrically connected.

2. The half-bridge power module (100) according to claim 1, wherein, The half-bridge power module (100) also includes a DC positive terminal (9), a DC negative terminal (10), and an AC terminal (11), wherein the DC positive terminal (9) and the DC negative terminal (10) are on the same substrate.

3. The half-bridge power module (100) according to claim 2, wherein, The DC positive terminal (9) and the DC negative terminal (10) are disposed on the first substrate (2).

4. The half-bridge power module (100) according to claim 2, wherein, Either the DC positive terminal (9) or the DC negative terminal (10) is located on a different substrate from the AC terminal (11).

5. The half-bridge power module (100) according to claim 2, wherein, The first substrate (2) has a first conductive metal layer (21). The first conductive metal layer (21) includes a first DC positive electrode region (211), and the DC positive terminal (9) is disposed in the first DC positive electrode region (211).

6. The half-bridge power module (100) according to claim 5, wherein, The first conductive metal layer (21) further includes a first DC negative electrode region (213), and the DC negative terminal (10) is disposed in the first DC negative electrode region (213).

7. The half-bridge power module (100) according to claim 6, wherein, The first conductive metal layer (21) further includes a first AC region (212), and the first half-bridge unit (4) includes a first upper bridge chip group (41) and a first lower bridge chip group (42). The first upper bridge chip group (41) is located in the first DC positive region (211), and the first lower bridge chip group (42) is located in the first AC region (212). Both the first upper bridge chip group (41) and the first lower bridge chip group (42) include a plurality of wide bandgap power chips (43).

8. The half-bridge power module (100) according to claim 7, wherein, The first upper bridge chip group (41) and the first lower bridge chip group (42) are arranged along the second direction.

9. The half-bridge power module (100) according to claim 8, wherein, The wide bandgap power chips (43) in the first upper bridge chip group (41) and the first lower bridge chip group (42) are arranged along the first direction.

10. The half-bridge power module (100) according to claim 7, wherein, A plurality of the wide-bandgap power chips (43) in the first upper bridge chipset (41) are connected to the first AC area (212) via a first connection line (71). A plurality of the wide bandgap power chips (43) in the first lower bridge chipset (42) are connected to the first DC negative region (213) via a second connection line (72).

11. The half-bridge power module (100) according to claim 7, wherein, At least a portion of each of the first DC positive region (211), the first AC region (212), and the first DC negative region (213) extends along the first direction and is arranged along the second direction.

12. The half-bridge power module (100) according to claim 7, wherein, The first upper bridge chip group (41) and the first lower bridge chip group (42) further include a first type of diode (6a), which is arranged along a first direction with the wide bandgap power chip (43).

13. The half-bridge power module (100) according to claim 12, wherein, The first type of diode (6a) of the first upper bridge chip group (41) is connected in series with the first type of diode (6a) of the first lower bridge chip group (42), and the first type of diode (6a) is connected in parallel with the wide bandgap power chip (43) in the same chip group.

14. The half-bridge power module (100) according to claim 12, wherein, The first type of diode (6a) has the same substrate material as the wide bandgap power chip (43).

15. The half-bridge power module (100) according to claim 12, wherein, The first type of diode (6a) is a wide bandgap substrate Schottky diode (6).

16. The half-bridge power module (100) according to claim 12, wherein, The diode (6) and the wide bandgap power chip (43) are arranged alternately along the first direction.

17. The half-bridge power module (100) according to claim 7, wherein, The second substrate (3) has a second conductive metal layer (31). The second conductive metal layer (31) includes a second DC positive electrode region (311), and the first DC positive electrode region (211) is electrically connected to the second DC positive electrode region (311).

18. The half-bridge power module (100) according to claim 17, wherein, The second conductive metal layer (31) further includes a second DC negative electrode region (313), and the first DC negative electrode region (213) is electrically connected to the second DC negative electrode region (313).

19. The half-bridge power module (100) according to claim 18, wherein, The second conductive metal layer (31) further includes a second AC region (312), and the first AC region (212) is electrically connected to the second AC region (312).

20. The half-bridge power module (100) according to claim 19, wherein, The AC terminal (11) is located in the second AC area (312).

21. The half-bridge power module (100) according to claim 20, wherein, The second half-bridge unit (5) includes a second upper bridge chip group (51) and a second lower bridge chip group (52). The second upper bridge chip group (51) is located in the second DC positive region (311), and the second lower bridge chip group (52) is located in the second AC region (312). Both the second upper bridge chip group (51) and the second lower bridge chip group (52) include a plurality of silicon-based power chips (53).

22. The half-bridge power module (100) according to claim 21, wherein, The second upper bridge chip group (51) and the second lower bridge chip group (52) are arranged along the second direction.

23. The half-bridge power module (100) according to claim 22, wherein, Both the second upper bridge chip group (51) and the second lower bridge chip group (52) include a plurality of silicon-based power chips (53) arranged along the first direction.

24. The half-bridge power module (100) according to claim 21, wherein, A plurality of silicon-based power chips (53) in the second upper bridge chip group (51) are connected to the second AC region (312) via a third connection line (73), and a plurality of silicon-based power chips (53) in the second lower bridge chip group (52) are connected to the second DC negative region (313) via a fourth connection line (74).

25. The half-bridge power module (100) according to claim 19, wherein, At least a portion of each of the second DC positive region (311), the second AC region (312), and the second DC negative region (313) extends along the first direction and is arranged along the second direction.

26. The half-bridge power module (100) according to claim 19, wherein, The first DC positive region (211) and the second DC positive region (311) are arranged opposite to each other along the first direction.

27. The half-bridge power module (100) according to claim 19, wherein, The first DC negative pole region (213) and the second DC negative pole region (313) are arranged opposite to each other along the first direction.

28. The half-bridge power module (100) according to claim 19, wherein, The first communication area (212) and the second communication area (312) are arranged opposite to each other along the first direction.

29. The half-bridge power module (100) according to claim 21, wherein, The second upper bridge chip group (51) and the second lower bridge chip group (52) also include a second type of diode (6b), which is arranged along the first direction with the silicon-based power chip (53).

30. The half-bridge power module (100) according to claim 29, wherein, The second type diode (6b) of the second upper bridge chip group (51) is connected in series with the second type diode (6b) of the second lower bridge chip group (52), and the second type diode (6b) is connected in parallel with the silicon-based power chip (53) in the same chip group.

31. The half-bridge power module (100) according to claim 29, wherein, The second type of diode (6b) has the same substrate material as the silicon-based power chip (53).

32. The half-bridge power module (100) according to claim 29, wherein, The second type of diode (6b) is a silicon substrate fast recovery diode (6).

33. The half-bridge power module (100) according to claim 29, wherein, The second type of diode (6b) and the silicon-based power chip (53) are arranged alternately along the first direction.

34. The half-bridge power module (100) according to any one of claims 5-33, wherein, The wide bandgap power chip (43) includes a SiC MOSFET, and the silicon-based power chip (53) includes a Si IGBT.

35. The half-bridge power module (100) according to claim 34, wherein, The first conductive metal layer (21) further includes: The first SiC driving layer group (214) includes: a first SiC gate driving layer (2141) and a first SiC source driving layer (2142), wherein the gate (432) of the SiC MOSFET of the first upper bridge chip group (41) is electrically connected to the first SiC gate driving layer (2141), and the source (431) of the SiC MOSFET of the first upper bridge chip group (41) is electrically connected to the first SiC source driving layer (2142).

36. The half-bridge power module (100) according to claim 35, wherein, The first conductive metal layer (21) further includes: The second SiC driving layer group (215) includes: a second SiC gate driving layer (2151) and a second SiC source driving layer (2152). The gate (432) of the SiC MOSFET of the first lower bridge chip group (42) is electrically connected to the second SiC gate driving layer (2151), and the source (431) of the SiC MOSFET of the first lower bridge chip group (42) is electrically connected to the second SiC source driving layer (2152).

37. The half-bridge power module (100) according to claim 34, wherein, The second conductive metal layer (31) also includes: The first IGBT driving layer group (314) includes: a first IGBT gate driving layer (3141) and a first IGBT emitter driving layer (3142), the gate (532) of the Si IGBT of the second upper bridge chip group (51) is electrically connected to the first IGBT gate driving layer (3141), and the emitter (531) of the Si IGBT of the second upper bridge chip group is electrically connected to the first IGBT emitter driving layer (3142).

38. The half-bridge power module (100) according to claim 37, wherein, The second conductive metal layer (31) further includes: The second IGBT driving layer group (315) includes: a second IGBT gate driving layer (3151) and a second IGBT emitter driving layer (3152), wherein the gate (532) of the Si IGBT in the second lower bridge chip group (52) is electrically connected to the second IGBT gate driving layer (3151), and the emitter (531) of the Si IGBT in the second lower bridge chip group (52) is electrically connected to the second IGBT emitter driving layer (3152).

39. The half-bridge power module (100) according to claim 36, wherein, The base plate (1) includes a first side (110a) and a second side (110b) opposite each other along the second direction, and a third side (110c) and a fourth side (110d) opposite each other along the first direction; The first SiC driving layer group (214) is located on the side of the first DC positive region (211) facing the first side (110a).

40. The half-bridge power module (100) according to claim 39, wherein, The second SiC driving layer group (215) is located on the side of the first DC negative electrode region (213) facing the second side (110b).

41. The half-bridge power module (100) according to claim 38, wherein, The first IGBT drive layer group (314) is located on the side of the second DC positive region (311) facing the first side (110a).

42. The half-bridge power module (100) according to claim 41, wherein, The second IGBT drive layer group (315) is located on the side of the second DC negative electrode region (313) facing the second side (110b).

43. The half-bridge power module (100) according to claim 1, wherein, The wide bandgap power chip (43) is connected to the first substrate (2) using a first connection process, which is either a sintering process or a welding process.

44. The half-bridge power module (100) according to claim 43, wherein, The silicon-based power chip (53) is connected to the second substrate (3) using a second connection process, which is either a sintering process or a welding process.

45. The half-bridge power module (100) according to claim 44, wherein, One of the first connection process and the second connection process is a sintering process, and the other is a welding process.

46. ​​The half-bridge power module (100) according to claim 44, wherein, Both the first and second joining processes are sintering processes, or both the first and second joining processes are welding processes. Furthermore, the process parameters of the first connection process are different from those of the second connection process, and the process parameters include: process temperature and process duration.

47. A full-bridge power module (200), wherein, include: The half-bridge power module (100) according to any one of claims 1-46, wherein there are multiple half-bridge power modules (100), and the multiple half-bridge power modules (100) are connected to form a full-bridge power module (200).

48. An electrical appliance (300), wherein, Includes a power module, said power module comprising the half-bridge power module (100) according to any one of claims 1-46.

49. An electrical appliance (300), wherein, Includes a power module, the power module including the full-bridge power module (200) of claim 47.

50. A method for manufacturing a half-bridge power module (100), used to manufacture the half-bridge power module (100) according to any one of claims 1-46, wherein, Includes the following steps: The wide bandgap power chip (43) is fixed to the first substrate (2), and the silicon-based power chip (53) is fixed to the second substrate (3); The wide bandgap power chip (43) is bonded to the first substrate (2) via a connecting line (7), and the silicon-based power chip (53) is bonded to the second substrate (3) via a connecting line (7); Electrical tests were performed on the first half-bridge unit (4) formed by the wide bandgap power chip (43) and on the second half-bridge unit (5) formed by the silicon-based power chip (53); The first substrate (2) and the second substrate (3), which have passed the electrical test, are respectively fixed to the base plate (1); The first substrate (2) and the second substrate (3) are connected by a connecting line (7); Install housing and connection terminals.

51. The method for manufacturing a half-bridge power module (100) according to claim 50, wherein, The steps of fixing the wide-bandgap power chip (43) to the first substrate (2) and fixing the silicon-based power chip (53) to the second substrate (3) include: The wide bandgap power chip (43) is fixed to the first substrate (2) by a first connection process, and the silicon-based power chip (53) is fixed to the second substrate (3) by a second connection process; The first connection process is one of sintering and welding. The second joining process is either sintering or welding.

52. The method for manufacturing the half-bridge power module (100) according to claim 51, wherein, One of the first connection process and the second connection process is a sintering process, and the other is a welding process.

53. The method for manufacturing the half-bridge power module (100) according to claim 51, wherein, Both the first and second joining processes are sintering processes, or both the first and second joining processes are welding processes. Furthermore, the process parameters of the first connection process are different from those of the second connection process, and the process parameters include: process temperature and process duration.

54. The method for manufacturing a half-bridge power module (100) according to claim 50, wherein, The step of fixing the first substrate (2) and the second substrate (3) that have passed the electrical test to the base plate (1) includes: Both the first substrate (2) and the second substrate (3) are soldered to the base plate (1).

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