Chip packaging structure and manufacturing method therefor
By using deformable connection layers and a pressing structure in the chip packaging structure, high-precision alignment of optical waveguides was achieved, solving the problem of unfriendly flip-chip structure design and reducing chip design requirements and costs.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-08-22
- Publication Date
- 2026-03-05
AI Technical Summary
Existing flip-chip packaging structures impose significant limitations on chip design, making it difficult to achieve high-precision alignment of optical waveguides, resulting in unfriendly designs and high costs.
By employing a deformable connecting layer and a pressing structure, the first and second optical waveguides are located on the same horizontal plane, and docking coupling is achieved through positive mounting, reducing design requirements and costs.
This achieves high-precision alignment of optical waveguides, reduces chip design requirements and costs, and improves the flexibility and efficiency of chip packaging.
Smart Images
Figure CN2025116422_05032026_PF_FP_ABST
Abstract
Description
Chip Packaging Structure and Fabrication Method
[0001] This application claims priority to Chinese Patent Application No. 202411228097.1, filed on September 2, 2024, entitled “Chip Packaging Structure and Manufacturing Method Thereof”, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, specifically to a chip packaging structure and its fabrication method. Background Technology
[0003] Butt coupling, also known as face-to-face coupling, involves directly aligning and coupling one end of an optical element with the other, requiring minimal power loss in transmitted radiation. Butt coupling is a common passive coupling method for optical devices. The mounting accuracy has a significant impact on coupling insertion loss; therefore, butt coupling places high demands on mounting precision.
[0004] Because the processing precision of the optical waveguide of the chip to the front side of the chip is high, and the substrate and carrier may have material tolerances, the existing technology usually adopts the flip-chip method. First, a limiting structure is formed on the substrate, and the front sides of the two chips are attached to the substrate. The limiting structure aligns the optical waveguides of the two chips, and then subsequent steps such as heat dissipation substrate and carrier mounting are performed.
[0005] Existing flip-chip packaging structures impose significant limitations on chip structural design and are not design-friendly. Therefore, there is an urgent need to develop a chip docking and coupling packaging structure with low design requirements. Summary of the Invention
[0006] This application provides a chip packaging structure and its fabrication method, which can reduce design requirements and design costs.
[0007] In a first aspect, a chip packaging structure is provided, comprising: a chip carrier; a first substrate mounted on the chip carrier; a first chip mounted on the first substrate via a first interconnect layer, the back side of the first chip being connected to the first substrate via the first interconnect layer, the first chip including a first optical waveguide; and a second chip mounted on the first substrate via a second interconnect layer, the back side of the second chip being connected to the first substrate via the second interconnect layer, the second chip including a second optical waveguide; wherein the first interconnect layer and the second interconnect layer are configured to deform so that the first optical waveguide and the second optical waveguide are located on the same horizontal plane.
[0008] This application provides a chip packaging structure in which the back of the chip is connected to the substrate through a deformable connection layer. The deformable connection layer can deform under force to align the optical waveguides of the two chips, realizing docking coupling based on positive mounting, which reduces chip design requirements and costs.
[0009] A chip carrier is a base or pedestal used to mount integrated circuit chips, typically used to connect chips, circuit boards, or other electronic devices.
[0010] For example, the first substrate can be mounted on the chip carrier by means of welding, adhesive bonding, magnetic bonding, or press bonding.
[0011] A chip consists of a front and a back side, which can be identified by markings, pin layout, optical features, design structure, or manufacturing documentation. The front side of a chip generally refers to the functional layer fabricated using processes such as epitaxy and deposition.
[0012] The first chip can be an active chip or a passive chip, and the second chip can be an active chip or a passive chip. The first and second chips can be semiconductor optical amplifiers (SOAs), laser diodes (LDs), silicon photonics (SiPh) chips, tunable laser Mach Zehnder (TLMZ) chips, etc. This application does not limit the number of chips disposed on the first substrate; in addition to the first and second chips, other chips may be present.
[0013] This application does not limit the number of first substrates. The first chip and the second chip can be mounted on the same substrate or on different substrates.
[0014] It should be understood that when the first optical waveguide and the second optical waveguide are aligned in three dimensions, the first chip and the second chip can complete optical communication.
[0015] In conjunction with the first aspect, in some implementations of the first aspect, the first connecting layer and the second connecting layer are adhesive layers or nanoporous gold (NPG) layers.
[0016] This application provides a chip packaging structure in which the connection layer uses deformable materials such as adhesive or NPG, which can deform under force, so that the first optical waveguide and the second optical waveguide are located on the same horizontal plane, realizing docking coupling based on positive mounting, reducing chip design requirements and costs.
[0017] In conjunction with the first aspect, in some implementations of the first aspect, the chip packaging structure further includes a pressure plate disposed on the first chip and the second chip, for deforming the first connection layer and the second connection layer so that the first optical waveguide and the second optical waveguide are located on the same horizontal plane.
[0018] This application does not limit the size and shape of the tablet. For example, the tablet can be a plate with protrusions on its surface, or simply a plate with two parallel sides, or a plate with grooves on its surface, or a suction nozzle with protrusions or grooves on its surface.
[0019] It should be understood that the press can be removed after it causes the deformable connecting layer to deform, so that the first optical waveguide and the second optical waveguide are on the same horizontal plane.
[0020] This application provides a chip packaging structure in which a pressure plate is disposed on the chip. The pressure plate can be subjected to force to cause the deformable connection layer to deform, so that the first optical waveguide and the second optical waveguide are located on the same horizontal plane, realizing docking coupling based on positive mounting, reducing chip design requirements and costs.
[0021] In conjunction with the first aspect, in some implementations of the first aspect, the pressing sheet is provided with a first protrusion and a second protrusion on the surfaces facing the first chip and the second chip, the first protrusion being located on the front side of the first chip and the second protrusion being located on the front side of the second chip.
[0022] In one possible implementation, the first and second protrusions can be formed by an etching process. Since the chip fabrication also uses an etching process, the mounting accuracy can be increased.
[0023] Optionally, the first protrusion can make hard contact with the front of the first chip, or it can be connected by means of glue or other methods.
[0024] This application provides a chip packaging structure in which a first protrusion and a second protrusion of a specific height are provided on the surface of the pressing sheet facing the first chip and the second chip, respectively, to apply pressure to the first chip and the second chip, so that the first optical waveguide and the second optical waveguide are located on the same horizontal plane, thereby realizing docking coupling based on positive mounting, reducing chip design requirements and costs.
[0025] In conjunction with the first aspect, in some implementations of the first aspect, the parallelism between the surfaces of the first chip and the second chip and the surface of the pressing sheet is less than 0.5 μm.
[0026] This application provides a chip packaging structure in which the parallelism between the surfaces of the first chip and the second chip and the surface of the pressing sheet is less than 0.5 μm, which is more conducive to the docking and coupling of the first chip and the second chip.
[0027] In conjunction with the first aspect, some implementations of the first aspect further include a spacer disposed on the first substrate and / or on the third chip, the spacer being used to even out the force on the third chip, the third chip including the first chip and / or the second chip.
[0028] The gaskets can be made of materials such as glue or rubber. For example, gasket 1 is located between the first substrate and the pressure plate, and gasket 2 is located between the third chip and the pressure plate. When the pressure plate is subjected to a downward force to squeeze the third chip, gaskets 1 and 2 can make the pressure on the third chip more uniform and gentle.
[0029] This application provides a chip packaging structure in which a spacer can be placed on a first substrate and a chip to buffer and protect the surface of the chip and prevent damage to the surface of the chip when subjected to force.
[0030] In conjunction with the first aspect, some implementations of the first aspect further include a third connection layer disposed on the first substrate and / or on a third chip, the third connection layer being used to uniformly distribute the force on the third chip, the third chip including the first chip and / or the second chip.
[0031] The third connecting layer can be a deformable structure such as adhesive or NPG. For example, the third connecting layer 1 is located between the first substrate and the pressure plate, and the third connecting layer 2 is located between the third chip and the pressure plate. When the pressure plate is subjected to a downward force to squeeze the third chip, the third connecting layer 1 and the third connecting layer 2 can make the pressure on the third chip more uniform and gentle.
[0032] This application provides a chip packaging structure in which a third connection layer can be disposed on a first substrate and a chip to buffer and protect the surface of the chip and prevent damage to the surface of the chip when subjected to force.
[0033] In conjunction with the first aspect, in some implementations of the first aspect, the first substrate includes a second substrate and a third substrate, the first chip is mounted on the second substrate through the first interconnect layer, and the second chip is mounted on the third substrate through the second interconnect layer.
[0034] The second substrate can be any one of a thermo electric cooler (TEC), a transition substrate, or an aluminum nitride substrate, and the third substrate can be any one of a TEC, a transition substrate, or an aluminum nitride substrate.
[0035] As the demand for integrated optical devices gradually increases, the requirements for substrates for different optical chips also show significant differences. Sharing the same substrate cannot meet the chip performance requirements. In order to meet the docking and coupling requirements based on special substrates such as TEC or optoelectronic hybrid substrates such as glass, this application provides a chip packaging structure in which the first chip and the second chip can be located on different substrates, which facilitates temperature control and wiring.
[0036] In conjunction with the first aspect, in some implementations of the first aspect, the chip carrier, the first substrate, the first chip, or the second chip are provided with marking points, which are used for mounting and positioning.
[0037] This application provides a chip packaging structure in which marking points can be set on the chip carrier, the first substrate, the first chip or the second chip to increase the mounting accuracy in the horizontal two-dimensional direction.
[0038] In conjunction with the first aspect, in some implementations of the first aspect, the substrate includes a thermo electric cooler (TEC), a transition substrate, or an aluminum nitride substrate.
[0039] Existing chip packaging structures typically employ flip-chip bonding, requiring the substrate to be an etchable substrate such as silicon, which limits the packaging design. The chip packaging structure provided in this application allows for a high degree of substrate flexibility, using TEC, transition substrates, or aluminum nitride substrates to meet the needs of various application scenarios.
[0040] In conjunction with the first aspect, in some implementations of the first aspect, the first chip and the second chip are docked and coupled.
[0041] In a second aspect, an electronic device is provided, which is provided with the chip packaging structure described in the first aspect and any possible implementation thereof.
[0042] Thirdly, a method for fabricating a chip packaging structure is provided. The method includes: mounting a first substrate onto a chip carrier; mounting a first chip onto the first substrate via a first interconnect layer, wherein the back side of the first chip is connected to the first substrate via the first interconnect layer, and the first chip includes a first optical waveguide; mounting a second chip onto the first substrate via a second interconnect layer, wherein the back side of the second chip is connected to the first substrate via the second interconnect layer, and the second chip includes a second optical waveguide; applying pressure to the first chip and the second chip to deform the first interconnect layer and the second interconnect layer, wherein the first optical waveguide and the second optical waveguide are located on the same horizontal plane.
[0043] In conjunction with the third aspect, in some implementations of the third aspect, the first connecting layer and the second connecting layer are adhesive layers or nanoporous gold layers.
[0044] In conjunction with the third aspect, in some implementations of the third aspect, applying pressure to the first chip and the second chip to deform the first interconnect layer and the second interconnect layer includes: placing a pressure plate on the first chip and the second chip; and applying pressure to the first chip and the second chip through the pressure plate to deform the first interconnect layer and the second interconnect layer.
[0045] In conjunction with the third aspect, in some implementations of the third aspect, the surface of the pressing sheet facing the first chip and the second chip is provided with a first protrusion and a second protrusion, and the step of placing the pressing sheet on the first chip and the second chip includes: placing the first protrusion on the front side of the first chip and placing the second protrusion on the front side of the second chip.
[0046] In conjunction with the third aspect, in some implementations of the third aspect, the parallelism between the surfaces of the first chip and the second chip and the surface of the pressing sheet is less than 0.5 μm.
[0047] In conjunction with the third aspect, in some implementations of the third aspect, the method further includes: removing the tablet.
[0048] In conjunction with the third aspect, in some implementations of the third aspect, the first substrate includes a second substrate and a third substrate, and the step of mounting the first chip on the first substrate through the first interconnect layer includes: mounting the first chip on the second substrate through the first interconnect layer; the step of mounting the second chip on the first substrate through the second interconnect layer includes: mounting the second chip on the third substrate through the second interconnect layer.
[0049] In conjunction with the third aspect, in some implementations of the third aspect, before applying pressure to the first chip and the second chip, the method further includes: providing a pad on the third chip and / or the first substrate, the pad being used to even out the force on the third chip, the third chip comprising the first chip and / or the second chip.
[0050] In conjunction with the third aspect, in some implementations of the third aspect, before applying pressure to the first chip and the second chip, the method further includes: providing a third connection layer on the third chip and / or the first substrate, the third connection layer being used to uniformly distribute the force on the third chip, the third chip comprising the first chip and / or the second chip.
[0051] In conjunction with the third aspect, in some implementations of the third aspect, the method further includes: setting marking points on the chip carrier, the first substrate, the first chip, or the second chip, the marking points being used for mounting and positioning.
[0052] In conjunction with the third aspect, in some implementations of the third aspect, the substrate includes a TEC, a transition substrate, or an aluminum nitride substrate.
[0053] In conjunction with the third aspect, in some implementations of the third aspect, the first chip and the second chip are docked and coupled.
[0054] The beneficial effects of the third aspect and any possible implementation of the third aspect correspond to the beneficial effects of the first aspect and any possible implementation of the first aspect, which will not be elaborated further. Attached Figure Description
[0055] Figure 1 is a side view of a chip packaging structure 100 provided in an embodiment of this application.
[0056] Figure 2 is a side view of a chip packaging structure 200 provided in an embodiment of this application.
[0057] Figure 3 is an example diagram of the fabrication process of a chip packaging structure provided in an embodiment of this application.
[0058] Figure 4 is a side view of another chip packaging structure 400 provided in an embodiment of this application.
[0059] Figure 5 is a side view of another chip packaging structure 500 provided in an embodiment of this application.
[0060] Figure 6 is an exemplary flowchart of a method for fabricating another chip packaging structure provided in an embodiment of this application.
[0061] Figure 7 is a side view of a chip packaging structure 700 provided in an embodiment of this application.
[0062] Figure 8 is a side view of a chip packaging structure 800 provided in an embodiment of this application.
[0063] Figure 9 is a top view of a chip packaging structure provided in an embodiment of this application.
[0064] Figure 10 is a side view of another chip packaging structure 1000 provided in an embodiment of this application.
[0065] Figure 11 is an exemplary flowchart of a method for fabricating another chip packaging structure provided in an embodiment of this application. Detailed Implementation
[0066] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort should fall within the scope of protection of this application.
[0067] In the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design that is described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.
[0068] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.
[0069] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0070] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.
[0071] To facilitate understanding of the embodiments of this application, some definitions involved in this application will be briefly explained first.
[0072] 1. Passive Chip: A type of chip widely used in integrated photonics for photonic integrated circuits. These chips mainly consist of optical waveguides, coupling devices, and other optical functional devices, but do not contain active optical devices (such as lasers or photodetectors).
[0073] 2. Active Optoelectronic Chips: Optoelectronic devices that integrate active optical components within a single chip. These devices can generate, amplify, modulate, or detect optical signals, and perform energy conversion and signal processing between the optical and electronic domains. Active optoelectronic chips typically include light sources (such as lasers), photodetectors (such as photodetectors), and possibly optical modulators.
[0074] 3. Insertion loss (IL): The reduction in signal power from input to output, that is, the loss introduced by components such as connectors, transmission lines, and couplers during signal transmission.
[0075] Hybrid integration packaging technology combines passive and active chips using bonding, coupling alignment, and other packaging techniques to achieve high-efficiency photoelectric conversion. Hybrid integrated optoelectronic circuits offer advantages such as high optimizability of individual devices, high product yield, full utilization of the performance of both passive photonic and active electronic devices, and greater flexibility in selecting functional components. Therefore, hybrid integration technology is widely used in optical communication and optical sensing fields.
[0076] In hybrid optoelectronic integrated circuits, photonic and electronic devices are fabricated on different substrates based on their chosen materials, structures, and fabrication processes. A coupling scheme is needed to couple passive and active chips together. Butt coupling, also known as face-to-face coupling, involves directly aligning one end of an optical element with the end of another, requiring minimal power loss in transmitted radiation. Butt coupling is a common passive coupling method for optical devices. The mounting accuracy significantly affects insertion loss; therefore, butt coupling places high demands on mounting precision.
[0077] Docking coupling refers to aligning the optical waveguides of two chips, enabling optical communication between them. During chip packaging, the chip is mounted and assembled with the substrate and carrier. Due to significant errors that can occur during the manufacturing process of the substrate and carrier, misalignment of the optical waveguides may exist after the two chips are packaged according to the preset steps.
[0078] Because the processing precision of the optical waveguides on the front side of the chip is high, and material tolerances may exist in the substrate and carrier, existing technologies typically employ flip-chip mounting. This involves first forming a limiting structure on the substrate, then mounting the front sides of two chips onto the substrate. The limiting structure aligns the optical waveguides of the two chips before subsequent steps such as mounting the heat dissipation substrate and carrier are performed. Existing flip-chip packaging structures impose significant limitations on chip structural design, making chip design less user-friendly. While front-mount docking structures require less modification to the chip and are more user-friendly, the design challenge lies in the inability to guarantee Z-axis (chip package height direction) mounting accuracy due to material tolerances. This application designs a chip packaging structure based on front-mount mounting, where the chips are front-mounted and a deformable connection layer is used to align the optical waveguides of the two chips.
[0079] Figure 1 is a side view of a chip packaging structure 100 provided in an embodiment of this application.
[0080] The chip packaging structure 100 includes a chip carrier 110, a first substrate 120, a first connection layer 130, a second connection layer 140, a first chip 150, and a second chip 160.
[0081] The first substrate 120 is mounted on the chip carrier 110. The chip carrier 110 is a base or pedestal for mounting integrated circuit chips, typically used to connect chips, circuit boards, or other electronic devices. Exemplarily, the first substrate 120 can be mounted on the chip carrier 110 by means of soldering, adhesive bonding, magnetic bonding, press bonding, etc.
[0082] A first chip 150 is mounted on a first substrate 120 via a first connection layer 130, and the back side of the first chip 150 is connected to the first substrate 120 via the first connection layer 130. A second chip 160 is mounted on the first substrate 120 via a second connection layer 140, and the back side of the second chip 160 is connected to the first substrate 120 via the second connection layer 140.
[0083] The first connecting layer 130 and the second connecting layer 140, as deformable connecting layers, can compensate for the tolerance of the substrate. The tolerance of the substrate refers to the dimensional fluctuation between the actual thickness of the substrate and the design specifications during the manufacturing process.
[0084] The first chip 150 includes a first optical waveguide 151, and the second chip 160 includes a second optical waveguide 161.
[0085] The chip includes a front and a back side. The front and back sides of the first chip 150 and the second chip 160 can be determined by markings, pin layout, optical features, design structure or production documentation.
[0086] The first chip 150 can be an active chip or a passive chip, and the second chip 160 can also be an active chip or a passive chip. The first chip 150 and the second chip 160 can be semiconductor optical amplifiers (SOAs), laser diodes (LDs), silicon photonics (SiPh) chips, tunable laser Mach Zehnder (TLMZ) chips, etc. This application does not limit the number of chips disposed on the first substrate 120; other chips besides the first chip 150 and the second chip 160 may also be present.
[0087] The first connecting layer 130 and the second connecting layer 140 are used to deform, so that the first optical waveguide 151 and the second optical waveguide 161 are located on the same horizontal plane. It should be understood that when the first optical waveguide 151 and the second optical waveguide 161 are aligned in three dimensions, the first chip 150 and the second chip 160 can complete optical communication. Existing technologies make it difficult to achieve the first optical waveguide 151 and the second optical waveguide 161 being on the same horizontal plane; the embodiments of this application can solve this problem.
[0088] In some possible implementations, the first connecting layer 130 and the second connecting layer 140 are adhesive layers or NPG layers.
[0089] In some possible implementations, the first substrate 120 can be any one of a TEC, a transition substrate, or an aluminum nitride substrate.
[0090] Figure 2 is a side view of a chip packaging structure 200 provided in an embodiment of this application.
[0091] The chip package structure 200, relative to the chip package structure 100, has a pressure plate 170 on the first chip 150 and the second chip 160. The pressure plate 170 is used to deform the first connection layer 130 and the second connection layer 140 so that the first optical waveguide 151 and the second optical waveguide 161 are located on the same horizontal plane.
[0092] This application does not limit the size and shape of the tablet 170. For example, the tablet 170 may be a plate with protrusions on its surface, or simply a plate with two parallel sides, or a plate with grooves on its surface, or a suction nozzle with protrusions on its surface.
[0093] Figure 3 is an example of the fabrication process of a chip packaging structure provided in an embodiment of this application. The chip packaging structure shown in Figure 1 or Figure 2 can be obtained according to this process.
[0094] 310. Mount the first substrate onto the chip carrier.
[0095] The first substrate 120 is mounted on the chip carrier 110. The chip carrier 110 is a base or pedestal for mounting integrated circuit chips, typically used to connect chips, circuit boards, or other electronic devices. Exemplarily, the first substrate 120 can be mounted on the chip carrier 110 by means of soldering, adhesive bonding, magnetic bonding, press bonding, etc.
[0096] 320. The chip is mounted on the first substrate.
[0097] The first chip 150 is mounted on the first substrate 120 through the first connection layer 130, and the back side of the first chip 150 is connected to the first substrate 120 through the first connection layer 130.
[0098] The second chip 160 is mounted on the first substrate 120 through the second connection layer 140, and the back side of the second chip 160 is connected to the first substrate 120 through the second connection layer 140.
[0099] The first chip 150 includes a first optical waveguide 151, and the second chip 160 includes a second optical waveguide 161.
[0100] In some possible implementations, the first connecting layer 130 and the second connecting layer 140 are adhesive layers or NPG layers.
[0101] 330, the first and second connecting layers deform.
[0102] For example, a machine can be used to apply pressure to the first chip 150 and the second chip 160, causing the first connection layer 130 and the second connection layer 140 to deform, with the first optical waveguide 151 and the second optical waveguide 161 located on the same horizontal plane.
[0103] For example, the pressure plate 170 can be placed on the first chip 150 and the second chip 160, so that the first connection layer 130 and the second connection layer 140 are deformed, and the first optical waveguide 151 and the second optical waveguide 161 are located on the same horizontal plane, resulting in the chip packaging structure shown in FIG2.
[0104] 340, Remove the tablet.
[0105] When the clamping sheet 170 is placed on the first chip 150 and the second chip 160, after the first connection layer 130 and the second connection layer 140 are deformed and the first optical waveguide 151 and the second optical waveguide 161 are on the same horizontal plane, the clamping sheet 170 can be removed to obtain the chip packaging structure shown in Figure 1.
[0106] It should be understood that the wafer 170 may also remain as part of the chip packaging structure, and this application does not impose any restrictions on this.
[0107] Figure 4 is a side view of another chip packaging structure 400 provided in an embodiment of this application.
[0108] The chip packaging structure 400 includes a chip carrier 410, a second substrate 420, a third substrate 430, a first interconnect layer 440, a second interconnect layer 450, a third interconnect layer 460, a first chip 470, a second chip 480, a pressing sheet 490, a pad 41, and a pad 42.
[0109] The second substrate 420 and the third substrate 430 are mounted on the chip carrier 410. The chip carrier 410 is a base or pedestal for mounting integrated circuit chips, typically used to connect chips, circuit boards, or other electronic devices. Exemplarily, the second substrate 420 and the third substrate 430 can be mounted on the chip carrier 410 by means of soldering, adhesive bonding, magnetic bonding, press bonding, etc.
[0110] A first chip 470 is mounted on a second substrate 420 via a first connecting layer 440, and the back side of the first chip 470 is connected to the second substrate 420 via the first connecting layer 440. A second chip 480 is mounted on a third substrate 430 via a second connecting layer 450, and the back side of the second chip 480 is connected to the third substrate 430 via the second connecting layer 450. The first connecting layer 440 and the second connecting layer 450 are made of deformable materials such as adhesive or NPG.
[0111] The first chip 470 includes a first optical waveguide 471, and the second chip 480 includes a second optical waveguide 481.
[0112] The pressing sheet 490 is disposed on the first chip 470 and the second chip 480 to deform the first connecting layer 440 and the second connecting layer 450 so that the first optical waveguide 471 and the second optical waveguide 481 are located on the same horizontal plane.
[0113] The surface of the pressing plate 490 facing the first chip 470 and the second chip 480 is provided with a first protrusion 491 and a second protrusion 492. The first protrusion 491 is located on the front side of the first chip 470, and the second protrusion 492 is located on the front side of the second chip 480.
[0114] A third connecting layer 460 is provided between the pressing sheet 490 and the second substrate 420. The third connecting layer 460 can be a deformable structure such as adhesive or NPG. When the pressing sheet 490 is subjected to a downward force to compress the first chip 470, the third connecting layer 460 can make the pressure on the first chip 470 more uniform and gentle.
[0115] A spacer 41 and a spacer 42 are provided between the pressing sheet 490 and the second chip 480. The spacer 41 and the spacer 42 can be made of materials such as glue or rubber. When the pressing sheet 490 is subjected to a downward force to compress the second chip 480, the third connecting layer 460 can make the pressure on the second chip 480 more uniform and gentle.
[0116] In one possible implementation, the parallelism between the surfaces of the first chip 470 and the second chip 480 and the surface of the pressing sheet 490 is less than 0.5 μm.
[0117] Figure 5 is a side view of a chip packaging structure 500 provided in an embodiment of this application.
[0118] Compared to chip package structure 400, chip package structure 500 removes the pressure plate 490. Other structural details can be found in Figure 4 and will not be repeated here. Optionally, one or more of the spacers 41, 42, and third interconnect layer 460 may be removed; this example should not be construed as a limitation of this application.
[0119] Figure 6 is an exemplary flowchart of another method for fabricating a chip packaging structure provided in an embodiment of this application. The chip packaging structure shown in Figure 4 or Figure 5 can be obtained according to this flowchart.
[0120] 610. Mount the substrate onto the chip carrier.
[0121] The second substrate 420 and the third substrate 430 are mounted onto the chip carrier 410. This mounting method includes, but is not limited to, soldering, adhesive bonding, magnetic bonding, and press bonding.
[0122] The second substrate 420 and the third substrate 430 can be a thermoelectric cooler (TEC), a transition substrate, or an aluminum nitride (AlN) substrate, etc. This application embodiment does not limit the number of substrates mounted on the chip carrier 410. The second substrate 420 and the third substrate 430 in the figure are merely examples; the second substrate 420 and the third substrate 430 can also be a single substrate, and the chip carrier 410 can also have other substrates.
[0123] 620, mount the chip onto the substrate.
[0124] The first chip 470 is mounted on the second substrate 420 via the first interconnect layer 440, and the second chip 480 is mounted on the third substrate 430 via the second interconnect layer 450. It should be understood that mounting the first chip 470 and the second chip 480 on different substrates facilitates temperature control and wiring.
[0125] The first chip 470 and the second chip 480 can be semiconductor optical amplifiers (SOA), laser diodes (LD), silicon photonics (SiPh) chips, tunable laser Mach Zehnder (TLMZ) chips, etc.
[0126] The first connecting layer 440 and the second connecting layer 450 can be deformable structures such as adhesive or NPG.
[0127] 630 utilizes the optical waveguide docking coupling between the control chips via the pressing mechanism.
[0128] For example, the nozzle 408 can be connected to the pressure plate 490. The pressure plate 490 has a first protrusion 491 and a second protrusion 492 on the surface facing the first chip 470 and the second chip 480. The first protrusion 491 is located on the front side of the first chip 470, and the second protrusion 492 is located on the front side of the second chip 480.
[0129] The third connection layer 460 is located between the second substrate 420 and the pressing sheet 490. It should be understood that the third connection layer 460 in the embodiments of this application is only illustrative. If the area of the first chip 470 is large enough to cover most of the area of the second substrate 420, the third connection layer 460 may not be provided. This example should not be construed as a limitation of this application.
[0130] In this embodiment, the height of the chip packaging structure can be controlled through the first connection layer 440, the second connection layer 450, and the third connection layer 460. The first connection layer 440, the second connection layer 450, and the third connection layer 460 can be deformable structures such as adhesive or NPG.
[0131] The suction nozzle 408 applies a downward force to the pressure plate 490, which in turn presses the first chip 470 and the second chip 480 downwards. At the same time, it causes the first connecting layer 440, the second connecting layer 450 and the third connecting layer 460 to deform until the first optical waveguide 471 and the second optical waveguide 481 are on the same horizontal plane.
[0132] The optical waveguides between the first chip 470 and the second chip 480 are coupled by a butt coupling method. The parallelism between the surfaces of the first chip 470 and the second chip 480 and the surface of the pressing sheet 490 is less than 0.5 μm.
[0133] Optionally, spacers can be used to cushion and protect the chip surface. These spacers can be made of materials such as adhesive or rubber. For example, spacers 41 and 42 are located between the pressure plate 49 and the second chip 480. When the pressure plate 490 is subjected to a downward force pressing the second chip 480, spacers 41 and 42 can make the pressure on the second chip 480 more even and gentle. It should be understood that spacers 41 and 42 are merely examples; if the area of the second protrusion 492 in contact with the second chip 480 is large, spacers 41 and 42 may not be used.
[0134] 640, Remove nozzle 408.
[0135] Removing nozzle 408 yields the chip package structure shown in Figure 4.
[0136] In one possible implementation, the tablet 490 can also be part of the nozzle 408. In this case, removing the nozzle 408 will simultaneously remove the tablet 490, resulting in the chip package structure shown in Figure 5.
[0137] The shape of the suction nozzle in this embodiment is only for illustration. It is sufficient to provide downward force to the pressing tablet 490. This example should not be construed as a limitation of this application.
[0138] Figure 7 is a side view of a chip packaging structure 700 provided in an embodiment of this application.
[0139] The chip packaging structure 700 includes a chip carrier 710, a second substrate 720, a third substrate 730, a first interconnect layer 740, a second interconnect layer 750, a third interconnect layer 760, a first chip 770, a second chip 780, and a pressing sheet 790.
[0140] The second substrate 720 and the third substrate 730 are mounted on the chip carrier 710.
[0141] A first chip 770 is mounted on a second substrate 720 via a first interconnect layer 740, and the back side of the first chip 770 is connected to the second substrate 720 via the first interconnect layer 740. A second chip 780 is mounted on a third substrate 730 via a second interconnect layer 750, and the back side of the second chip 780 is connected to the third substrate 730 via the second interconnect layer 750.
[0142] The first chip 770 includes a first optical waveguide 771, and the second chip 780 includes a second optical waveguide 781.
[0143] The pressing sheet 790 is disposed on the first chip 770 and the second chip 780 to deform the first connecting layer 740 and the second connecting layer 750 so that the first optical waveguide 771 and the second optical waveguide 781 are located on the same horizontal plane.
[0144] A first protrusion 791 is provided on the surface of the pressing plate 790 facing the first chip 770, and the first protrusion 791 is located on the front side of the first chip 770.
[0145] A third connecting layer 760 is provided between the pressing sheet 790 and the second substrate 720. The third connecting layer 760 can be a deformable structure such as adhesive or NPG. When the pressing sheet 790 is subjected to a downward force to compress the first chip 770, the third connecting layer 760 can make the pressure on the first chip 770 more uniform and gentle.
[0146] Figure 8 is a side view of a chip packaging structure 800 provided in an embodiment of this application.
[0147] The chip packaging structure 800 includes a chip carrier 810, a second substrate 820, a third substrate 830, a first interconnect layer 840, a second interconnect layer 850, a third interconnect layer 860, a first chip 870, a second chip 880, and a pressing sheet 890.
[0148] The second substrate 820 and the third substrate 830 are mounted on the chip carrier 810.
[0149] The first chip 870 is mounted on the second substrate 820 via the first interconnect layer 840, and the back side of the first chip 870 is connected to the second substrate 820 via the first interconnect layer 840. The second chip 880 is mounted on the third substrate 830 via the second interconnect layer 850, and the back side of the second chip 880 is connected to the third substrate 830 via the second interconnect layer 850.
[0150] The first chip 870 includes a first optical waveguide 871, and the second chip 880 includes a second optical waveguide 881.
[0151] The surface of the pressing plate 890 facing the first chip 870 is provided with a groove 891, which fits into the front side of the first chip 870.
[0152] The pressing plate 890 is disposed on the first chip 870 and the second chip 880 to deform the first connecting layer 840 and the second connecting layer 850 so that the first optical waveguide 871 and the second optical waveguide 881 are located on the same horizontal plane.
[0153] The fabrication process of the chip packaging structure shown in Figures 7 and 8 can be found in the descriptions of Figures 3 and 6, and will not be repeated here.
[0154] Figure 9 is a top view of a chip packaging structure provided in an embodiment of this application. The die-casting layer, bonding layer, and spacer are omitted in Figure 9. During the fabrication of the chip packaging structure, marking points can be designed on the first chip, second chip, second substrate, third substrate, or chip carrier. These marking points are used for mounting and positioning, increasing the alignment accuracy of the chip in the X-direction (horizontal direction) and Y-direction (vertical direction).
[0155] In the chip packaging structures shown in Figures 1, 2, 4, 5, 7, and 8, the deformable interconnect layer is located between the chip and the substrate. The first, second, and third interconnect layers are all deformable interconnect layers. It should be understood that this deformable interconnect layer can also be located between the substrate and the chip carrier. Figures 10 and 11 are used as examples to describe a chip packaging structure where the deformable interconnect layer is located between the substrate and the chip carrier. Other chip packaging structures can be referenced in Figures 1, 2, 4, 5, 7, and 8, with the position of the deformable interconnect layer adjusted accordingly. This application will not repeat the details.
[0156] Figure 10 is a side view of another chip packaging structure 1000 provided in an embodiment of this application.
[0157] The chip packaging structure 1000 includes a chip carrier 1010, a first interconnect layer 1020, a second interconnect layer 1030, a second substrate 1040, a third substrate 1050, a first chip 1060, a second chip 1070, a pressing sheet 1090, a spacer 101, a spacer 102, and a spacer 103.
[0158] The second substrate 1040 is mounted on the chip carrier 1010 via the first interconnect layer 1020, and the third substrate 1050 is mounted on the chip carrier 1010 via the second interconnect layer 1030. The chip carrier 1010 is a base or socket for mounting integrated circuit chips, typically used to connect chips, circuit boards, or other electronic devices. The first interconnect layer 1020 and the second interconnect layer 1030 are made of deformable materials such as adhesive or NPG.
[0159] A first chip 1060 is mounted on a second substrate 1040, with the back side of the first chip 1060 connected to the second substrate 1040. A second chip 1070 is mounted on a third substrate 1050, with the back side of the second chip 1070 connected to the third substrate 1050. Exemplarily, the first chip 1060 and the second chip 1070 can be mounted on the second substrate 1040 and the third substrate 1050 by means of soldering, adhesive bonding, magnetic bonding, or press bonding.
[0160] The first chip 1060 includes a first optical waveguide 1061, and the second chip 1070 includes a second optical waveguide 1071.
[0161] The pressing sheet 1090 is disposed on the first chip 1060 and the second chip 1070 to deform the first connecting layer 1020 and the second connecting layer 1030 so that the first optical waveguide 1061 and the second optical waveguide 1071 are located on the same horizontal plane.
[0162] The pressing plate 1090 has a first protrusion 1091 and a second protrusion 1092 on the surface facing the first chip 1060 and the second chip 1070. The first protrusion 1091 is located on the front side of the first chip 1060, and the second protrusion 1092 is located on the front side of the second chip 1070.
[0163] A spacer 101 is provided between the pressing sheet 1090 and the second substrate 1040, a spacer 102 is provided between the pressing sheet 1090 and the second chip 1070, and a spacer 103 is provided between the pressing sheet 1090 and the third substrate 1050. Spacers 101, 102, and 103 can be made of materials such as adhesive or rubber. When the pressing sheet 1090 is subjected to a downward force pressing the first chip 1060 and the second chip 1070, the spacers 101, 102, and 103 can make the pressure on the first chip 1060 and the second chip 1070 more uniform and gentle.
[0164] In some possible implementations, the second substrate 1040 and the third substrate 1050 can be any one of a TEC, a transition substrate, or an aluminum nitride substrate.
[0165] The optical waveguides between the first chip 1060 and the second chip 1070 are coupled by a docking coupling method. In some possible implementations, the parallelism between the surfaces of the first chip 1060 and the second chip 1070 and the surface of the pressure plate 1090 is less than 0.5 μm.
[0166] Figure 11 is an exemplary flowchart of another method for fabricating a chip packaging structure provided in an embodiment of this application. The chip packaging structure shown in Figure 10 can be obtained according to this flowchart.
[0167] 1110, mount the chip onto the substrate.
[0168] The first chip 1060 is mounted on the second substrate 1040, and the second chip 1070 is mounted on the third substrate 1050. This mounting method includes, but is not limited to, soldering, adhesive bonding, magnetic bonding, and press bonding. It should be understood that mounting the first chip 1060 and the second chip 1070 on different substrates facilitates temperature control and wiring; however, the first chip 1060 and the second chip 1070 can also be mounted on the same substrate. This example should not be construed as limiting the scope of this application.
[0169] The second substrate 1040 and the third substrate 1050 can be TEC, interposer, or aluminum nitride (AlN) substrate, etc. The first chip 1060 and the second chip 1070 can be SOA, LD, SiPh chip, TLMZ chip, etc.
[0170] Optionally, marking points can also be designed on the first chip 1060, the second chip 1070, the second substrate 1040 and the third substrate 1050. These marking points are used for mounting and positioning to increase the alignment accuracy of the chip mounting in the X direction (horizontal direction) and Y direction (vertical direction).
[0171] 1120, mount the chip and substrate onto the die-casting plate.
[0172] The semiconductor structure obtained in step 1010, including a first chip 1060, a second chip 1070, a second substrate 1040, and a third substrate 1050, is mounted onto a pressing sheet 1090. A first protrusion 1091 and a second protrusion 1092 are provided on the surfaces of the pressing sheet 1090 facing the first chip 1060 and the second chip 1070, respectively. The first protrusion 1091 is located on the front side of the first chip 1060, and the second protrusion 1092 is located on the front side of the second chip 1070.
[0173] It should be understood that the flipping of the pressing sheet 1090 before mounting the first chip 1060 and the second chip 1070 in this embodiment is merely an example. The reason is that the area of the pressing sheet 1090 is larger than that of the first chip 1060 and the second chip 1070. The chip packaging structure obtained by flipping the pressing sheet 1090 before mounting the first chip 1060 and the second chip 1070 is more robust. This example should not be construed as a limitation of this application.
[0174] Optionally, a gasket can be used to buffer and protect the surface of the chip. The gasket can be made of materials such as adhesive or rubber. For example, a gasket 101 is provided between the pressing sheet 1090 and the second substrate 1040, a gasket 102 is provided between the pressing sheet 1090 and the second chip 1070, and a gasket 103 is provided between the pressing sheet 1090 and the third substrate 1050.
[0175] The spacer 101 is located between the second substrate 1040 and the pressing sheet 1090. It should be understood that the spacer 101 in the embodiments of this application is only illustrative. If the area of the first chip 1060 is large enough to cover most of the area of the second substrate 1040, the spacer 101 may not be provided. The same applies to the spacer 103. This example should not be construed as a limitation of this application.
[0176] Optionally, gaskets 101, 102 and 103 can also be replaced with deformable connecting layers, which can be deformable structures such as adhesive or NPG.
[0177] 1130, using a deformable connection layer to connect the chip carrier.
[0178] The second substrate 1040 is mounted on the chip carrier 1010 via the first connecting layer 1020, and the third substrate 1050 is mounted on the chip carrier 1010 via the second connecting layer 1030. The first connecting layer 1020 and the second connecting layer 1030 can be deformable structures such as adhesive or NPG. This application embodiment does not limit the number of substrates mounted on the chip carrier 1010. The second substrate 1040 and the third substrate 1050 in the figure are merely examples; the second substrate 1040 and the third substrate 1050 can also be a single substrate, and the chip carrier 1010 can also have other substrates.
[0179] The nozzle 1008 can be connected to the tablet 1090, and the tablet 1090 can also be part of the nozzle 1008.
[0180] In this embodiment, the height control of the chip packaging structure is achieved through the first connection layer 1020 and the second connection layer 1030.
[0181] The suction nozzle 1008 applies a downward force to the pressure plate 1090, and at the same time uses the upper surface of the pressure plate 1090 as a leveling reference surface. The pressure plate 1090 is pressed downward by the force to squeeze the first chip 1060 and the second chip 1070, causing the first connecting layer 1020 and the second connecting layer 1030 to deform. The first optical waveguide 1061 and the second optical waveguide 1071 are located on the same horizontal plane.
[0182] When the pressure plate 1090 is subjected to a downward force to compress the first chip 1060 and the second chip 1070, the gaskets 101, 102 and 103 can make the pressure on the first chip 1060 and the second chip 1070 more uniform and gentle.
[0183] The optical waveguides between the first chip 1060 and the second chip 1070 are coupled by a docking coupling method. In some possible implementations, the parallelism between the first chip 1060, the second chip 1070, and the pressing sheet 1090 is less than 0.5 μm.
[0184] 1140, Remove nozzle 1008.
[0185] Removing nozzle 1008 yields the chip packaging structure shown in Figure 10.
[0186] It should be understood that the tablet press 1090 can also be part of the suction nozzle 1008, in which case the tablet press 1090 is removed simultaneously. The shape of the suction nozzle in this embodiment is only illustrative and is sufficient to provide downward force to the tablet press 1090. This example should not be construed as a limitation of this application.
[0187] This application also provides an electronic device having a chip packaging structure as shown in Figures 1, 2, 4, 5, 7, and 10.
[0188] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A chip packaging structure, characterized in that, include: Chip carrier; The first substrate is mounted on the chip carrier; A first chip is mounted on a first substrate via a first connection layer, and the back side of the first chip is connected to the first substrate via the first connection layer. The first chip includes a first optical waveguide. The second chip is mounted on the first substrate through a second connection layer, and the back side of the second chip is connected to the first substrate through the second connection layer. The second chip includes a second optical waveguide. The first connecting layer and the second connecting layer are used to deform so that the first optical waveguide and the second optical waveguide are located on the same horizontal plane.
2. The chip packaging structure according to claim 1, characterized in that, The first connecting layer and the second connecting layer are adhesive layers or nanoporous gold layers.
3. The chip packaging structure according to claim 1 or 2, characterized in that, Also includes: A pressing device is placed on top of the first chip and the second chip to deform the first connection layer and the second connection layer so that the first optical waveguide and the second optical waveguide are located on the same horizontal plane.
4. The chip packaging structure according to claim 3, characterized in that, The pressing sheet has a first protrusion and a second protrusion on its surface facing the first chip and the second chip, respectively. The first protrusion is located on the front side of the first chip, and the second protrusion is located on the front side of the second chip.
5. The chip packaging structure according to claim 3 or 4, characterized in that, The parallelism between the surfaces of the first chip and the second chip and the surface of the pressed sheet is less than 0.5 μm.
6. The chip packaging structure according to any one of claims 1 to 5, characterized in that, It also includes a spacer disposed on the first substrate and / or on the third chip, the spacer being used to even out the force on the third chip, the third chip including the first chip and / or the second chip.
7. The chip packaging structure according to any one of claims 1 to 6, characterized in that, It also includes a third connection layer disposed on the first substrate and / or on the third chip, the third connection layer being used to uniformly distribute the force on the third chip, the third chip including the first chip and / or the second chip.
8. The chip packaging structure according to any one of claims 1 to 7, characterized in that, The first substrate includes a second substrate and a third substrate. The first chip is mounted on the second substrate through the first interconnect layer, and the second chip is mounted on the third substrate through the second interconnect layer.
9. The chip packaging structure according to any one of claims 1 to 8, characterized in that, The chip carrier, the first substrate, the first chip, or the second chip are provided with marking points, which are used for mounting and positioning.
10. The chip packaging structure according to any one of claims 1 to 9, characterized in that, The first substrate includes a semiconductor cooler (TEC), a transition substrate, or an aluminum nitride substrate.
11. The chip packaging structure according to any one of claims 1 to 10, characterized in that, The first chip and the second chip are docked and coupled.
12. An electronic device, characterized in that, It is provided with a chip packaging structure as described in any one of claims 1 to 11.
13. A method for fabricating a chip packaging structure, characterized in that, include: The first substrate is mounted on the chip carrier; The first chip is mounted on the first substrate through the first connection layer, and the back side of the first chip is connected to the first substrate through the first connection layer. The first chip includes a first optical waveguide. The second chip is mounted on the first substrate through the second connection layer, and the back side of the second chip is connected to the first substrate through the second connection layer. The second chip includes a second optical waveguide. Pressure is applied to the first chip and the second chip, causing the first connection layer and the second connection layer to deform, and the first optical waveguide and the second optical waveguide are located on the same horizontal plane.
14. The method according to claim 13, characterized in that, The first connecting layer and the second connecting layer are adhesive layers or nanoporous gold layers.
15. The method according to claim 13 or 14, characterized in that, Applying pressure to the first chip and the second chip to deform the first interconnect layer and the second interconnect layer includes: The tablet is placed on top of the first chip and the second chip; Pressure is applied to the first chip and the second chip by the pressing plate, causing the first connection layer and the second connection layer to deform.
16. The method according to claim 15, characterized in that, The surface of the pressing sheet facing the first chip and the second chip is provided with a first boss and a second boss. The step of placing the tablet on the first chip and the second chip includes: The first protrusion is disposed on the front side of the first chip, and the second protrusion is disposed on the front side of the second chip.
17. The method according to claim 15 or 16, characterized in that, The parallelism between the surfaces of the first chip and the second chip and the surface of the pressed sheet is less than 0.5 μm.
18. The method according to any one of claims 15 to 17, characterized in that, The method further includes: Remove the tablet.
19. The method according to any one of claims 13 to 18, characterized in that, The first substrate includes a second substrate and a third substrate. The step of mounting the first chip onto the first substrate via the first interconnect layer includes: The first chip is mounted on the second substrate via the first interconnect layer; The step of mounting the second chip onto the first substrate via the second interconnect layer includes: The second chip is mounted on the third substrate via the second interconnect layer.
20. The method according to any one of claims 13 to 19, characterized in that, Before applying pressure to the first chip and the second chip, the method further includes: A pad is disposed on the third chip and / or the first substrate, the pad being used to even out the force on the third chip, the third chip comprising the first chip and / or the second chip.
21. The method according to any one of claims 13 to 20, characterized in that, Before applying pressure to the first chip and the second chip, the method further includes: A third connection layer is disposed on the third chip and / or the first substrate, the third connection layer being used to uniformly distribute the force on the third chip, the third chip including the first chip and / or the second chip.
22. The method according to any one of claims 13 to 21, characterized in that, The method further includes: Marking points are provided on the chip carrier, the first substrate, the first chip, or the second chip, and the marking points are used for mounting and positioning.
23. The method according to any one of claims 13 to 22, characterized in that, The first substrate includes a semiconductor cooler (TEC), a transition substrate, or an aluminum nitride substrate.
24. The method according to any one of claims 13 to 23, characterized in that, The first chip and the second chip are docked and coupled.
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