Semiconductor device fabrication method and semiconductor device fabrication system

Abstract

Provided is a semiconductor device fabrication method comprising: performing bevel filling on an unbonded region of a polymerized substrate in which a first substrate having a laser absorption layer and a second substrate are bonded to each other; irradiating the laser absorption layer with a laser; and separating the first substrate from the second substrate in the polymerized substrate.

Description

Semiconductor device manufacturing method and semiconductor device manufacturing system

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a system for manufacturing a semiconductor device.

[0002] Patent Document 1 discloses a method for manufacturing a NAND flash memory including a three-dimensional memory cell array in which a plurality of memory cells are arranged three-dimensionally and a CMOS circuit that controls the memory cell array. The manufacturing method includes bonding a first substrate and a second substrate, each substrate having a semiconductor element including a CMOS and a memory cell array, via a separable layer, and separating the first substrate at the separable layer.

[0003] Patent Document 2 discloses a manufacturing method for forming a semiconductor device by bonding a semiconductor substrate having memory cells to a semiconductor substrate having a CMOS, in which an insulating film is filled in an unbonded area on the periphery of the bonded substrates, and then back-grinding is performed.

[0004] Japanese Patent Publication No. 2021-44408 Japanese Patent Publication No. 2021-48303

[0005] The technology according to the present disclosure appropriately separates the first substrate and the second substrate in a laminated substrate in which the first substrate and the second substrate are bonded together.

[0006] One aspect of the present disclosure is a method for manufacturing a semiconductor device, comprising: performing bevel filling on an unbonded region of a laminated substrate in which a first substrate having a laser absorption layer and a second substrate are bonded together; irradiating the laser absorption layer with a laser; and separating the first substrate from the second substrate in the laminated substrate.

[0007] According to the present disclosure, in a laminated substrate in which a first substrate and a second substrate are bonded together, the first substrate and the second substrate can be appropriately separated.

[0008] 1 is a flow diagram showing main steps of wafer processing; FIG. 2 is an explanatory diagram showing main steps of wafer processing; FIG. 3 is an explanatory diagram showing bonding of a first wafer and a second wafer; FIG. 4 is an explanatory diagram showing an example of bevel filling of an unbonded region; FIG. 5 is an explanatory diagram showing another example of bevel filling of an unbonded region; FIG. 6 is an explanatory diagram showing irradiating a laser absorption layer with laser light; FIG. 7 is an explanatory diagram showing separating the first wafer and the second wafer; FIG. 8 is an explanatory diagram showing main steps of preparing a first wafer according to an embodiment; FIG. 9 is a flow diagram showing main steps of preparing a first wafer according to an embodiment; FIG. 10 is an explanatory diagram showing some steps of preparing a first wafer according to an embodiment; FIG. 11 is an explanatory diagram showing some steps of preparing a first wafer according to an embodiment; FIG. 12 is a plan view showing an outline of the configuration of a wafer processing apparatus according to an embodiment; FIG. 13 is a plan view showing an outline of the configuration of an interface modification apparatus according to an embodiment; FIG. 14 is a side view showing an outline of the configuration of an interface modification apparatus according to an embodiment; FIG. 15 is an explanatory diagram showing wafer processing according to a comparative example.

[0009] In the manufacturing process of semiconductor devices, a device layer formed on the surface of a first semiconductor substrate (hereinafter referred to as "wafer") is transferred to a second wafer in a bonded wafer. This transfer of the device layer from the first wafer to the second wafer is performed, for example, by irradiating a separation layer inside the first wafer with laser light to reduce the bonding strength between the first and second wafers, and then separating the first wafer from the second wafer. Furthermore, after separation, the first wafer is reused and bonded to the next second wafer.

[0010] An unbonded region B may occur at the peripheral edge of the overlapped wafer T, where the beveled portions of the first wafer W and the second wafer S are not bonded to each other (see FIG. 2 ). The inventors have conducted extensive research and found that, even if the bonding strength of the separation layer of the first wafer W is reduced during separation of the first wafer W, separation in the unbonded region B may be prioritized over separation in the separation layer because there is no bonding strength in the unbonded region B. In this case, as shown in the comparative example of FIG. 16 , a portion of the bevel of the first wafer W corresponding to the unbonded region B may be separated from the overlapped wafer T while remaining bonded to the first wafer W. If a portion of the bevel is lost in this way, the area in which devices can be formed on the first wafer W separated from the overlapped wafer T may be limited, resulting in reduced productivity. Furthermore, in a process in which bonding and separation are repeated two or more times, this type of bevel loss may occur repeatedly, resulting in significant consumption of the area in which devices can be formed.

[0011] The technology disclosed herein appropriately separates a first substrate and a second substrate in a laminated substrate in which the first substrate and the second substrate are bonded. Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to the drawings. Note that in this specification and the drawings, elements having substantially the same functional configuration are designated by the same reference numerals, and redundant description will be omitted.

[0012] In the method for manufacturing a semiconductor device according to this embodiment, first, a first wafer W is prepared as a first substrate (St1 in FIG. 1 ), and a second wafer S is prepared as a second substrate (St2 in FIG. 1 ). The preparation of the first wafer W and the preparation of the second wafer S may be performed in parallel. Hereinafter, as shown in FIGS. 2 and 3 , the surface of the first wafer W that is to be bonded to the second wafer S is referred to as the front surface Wa, and the surface opposite the front surface Wa is referred to as the back surface Wb. Similarly, the surface of the second wafer S that is to be bonded to the first wafer W is referred to as the front surface Sa, and the surface opposite the front surface Sa is referred to as the back surface Sb.

[0013] The first wafer W prepared in St1 is a semiconductor wafer such as a silicon substrate. In one embodiment, the first wafer W has a substantially circular disk shape. As shown in FIG. 3A , a laminated film is formed on the front surface Wa of the first wafer W. The laminated film includes, in order from the front surface Wa, a laser absorption layer P, an etching stop layer Q, a device layer Dw, and a surface film Fw. The laser absorption layer P, the etching stop layer Q, the device layer Dw, and the surface film Fw are each formed on the first wafer W by a process including, for example, chemical vapor deposition (CVD) in a film formation apparatus (not shown) or reactive ion etching (RIE) in an etching apparatus (not shown). Other desired films may be formed between the laser absorption layer P, the etching stop layer Q, the device layer Dw, and the surface film Fw as components of the laminated film. Details of the formation of the laminated film will be described later.

[0014] The device layer Dw according to this embodiment includes at least a portion of a memory cell array of a NAND flash memory. However, the technology according to the present disclosure is not limited thereto and can also be applied to the manufacture of other semiconductor devices by bonding substrates having other desired devices. In one embodiment, the device layer Dw includes at least a portion of a memory cell array of a DRAM. In another embodiment, the device layer Dw includes at least a portion of a peripheral circuit for controlling the memory cell array of a NAND flash memory or the memory cell array of a DRAM. Note that, in some cases, devices are not formed in the device layer Dw when it is prepared in St1, and devices are formed in a subsequent process. In other words, the device layer Dw may be a region where devices are to be formed, such as a region where devices are to be formed in a process after St1.

[0015] The surface film Fw may be, for example, an oxide film (THOX film, SiO ２ film, TEOS film), SiC film, SiCN film, adhesive, etc.

[0016] As will be described later, the laser absorption layer P absorbs laser light (e.g., CO ２The laser absorption layer P is made of, for example, an oxide film (SiO ２ However, there is no particular limitation as long as it absorbs laser light.

[0017] The etching stop layer Q is configured to enable selective wet etching on the separation surface of the overlapped wafer T after separation of the first wafer W, which will be described later. Specifically, since the laser absorption layer P is the main separation surface during separation of the first wafer W, a portion of the laser absorption layer P and the etching stop layer Q remain on the side of the first device layer Dw after separation. In this state, selective etching of the laser absorption layer P and the etching stop layer Q first removes only the laser absorption layer P. Subsequently, selective etching of the etching stop layer Q and the first device layer Dw removes only the etching stop layer Q. This improves the total thickness variation (TTV) of the first device layer Dw after wet etching. The material of the etching stop layer Q is, for example, polycrystalline silicon (Poly-Si), but is not particularly limited as long as it ensures an etching selectivity between the etching stop layer Q and the first device layer Dw. Details of the method for forming the etching stop layer Q will be described later.

[0018] The second wafer S prepared in St2 is a semiconductor wafer such as a silicon substrate. In one embodiment, the second wafer S has a substantially circular disk shape. As shown in FIG. 3B, a laminated film Ms is formed on the surface Sa of the second wafer S. The laminated film Ms includes a device layer Ds and a surface film Fs, in this order from the surface Sa side. The device layer Ds and the surface film Fs are each formed on the second wafer S by a process including CVD in a film formation apparatus (not shown), for example.

[0019] The device layer Ds and the surface film Fs are the same as the device layer Dw and the surface film Fw of the first wafer W, respectively. The device layer Ds according to this embodiment includes at least a portion of a peripheral circuit for controlling a memory cell array of a NAND flash memory. In one embodiment, when the device layer Dw of the first wafer W includes at least a portion of a memory cell array of a DRAM, the device layer Ds includes at least a portion of a peripheral circuit for controlling the memory cell array. In another embodiment, when the device layer Dw of the first wafer W includes at least a portion of a peripheral circuit for controlling the memory cell array, the device layer Ds includes at least a portion of the memory cell array of a NAND flash memory. In yet another embodiment, when the device layer Dw of the first wafer W includes at least a portion of a peripheral circuit for controlling the memory cell array, the device layer Ds includes at least a portion of the memory cell array of a DRAM.

[0020] After preparing the first wafer W and the second wafer S as described above, the first wafer W and the second wafer S are bonded together as shown in FIG. 3( c) to form a first overlapping wafer T1 as an overlapping substrate (St3 in FIGS. 1 and 2). In St3, the surface film Fw of the first wafer W and the surface film Fs of the second wafer S are bonded together. Any method for bonding the first wafer W and the second wafer S may be used. For example, the surface films Fw and Fs may be modified by plasma treatment in a surface modification device (not shown), and then the surface films Fw and Fs may be hydrophilized by supplying pure water to them in a surface hydrophilization device (not shown). After that, the surface films Fw and Fs may be bonded together in a bonding device (not shown) by van der Waals forces and hydrogen bonds (intermolecular forces).

[0021] Next, as shown in FIG. 4 or FIG. 5 , bevel filling is performed on the unbonded region B1 of the periphery of the first overlapped wafer T1 (Step 4 in FIGS. 1 and 2 ). The bevel filling includes injecting a liquid filler G into the bevel portion of the first overlapped wafer T1, including the unbonded region B1. In one embodiment, the process includes injecting the liquid filler G into the unbonded region B and then baking (firing) the filler G to solidify it. As an example, in a bevel filling device 70 (described later), the first overlapped wafer T1 is rotated while injecting the liquid filler G from an injector 9. This causes the filler G to be filled in the unbonded region B1 around the entire periphery of the first overlapped wafer T1. The filler G may be filled only in the unbonded region B1, as shown in FIG. 4 . Alternatively, the filler G may be filled in the entire bevel portion, including the unbonded region B1, as shown in FIG. 5 . The first overlapped wafer T1 filled with the filler material G is sent to, for example, a baking apparatus 80 (described later) to bake the filler material G. In one embodiment, the first overlapped wafer T1 is then sent to a cleaning apparatus 90 (described later) to clean and remove excess filler material G adhering to unnecessary locations.

[0022] Next, as shown in Fig. 6, the laser absorbing layer P is irradiated with laser light L (St5 in Figs. 1 and 2). In St5, for example, in a laser processing device 50 described later, pulsed laser light is irradiated onto the laser absorbing layer P or the interface between the laser absorbing layer P and the etching stop layer Q. The type of laser light can be determined depending on the material of the laser absorbing layer P or other target material for laser irradiation. In one embodiment, the laser light is CO ２ Laser light, CO ２The wavelength of the laser light is, for example, 8.9 μm to 11 μm. In one embodiment, the laser light is IR laser light, and the wavelength of the IR laser light is, for example, 1.5 μm to 2.5 μm. The laser light L may be irradiated spirally over the entire surface of the laser absorbing layer P in a planar view, or may be irradiated concentrically over the entire surface of the laser absorbing layer P in an annular pattern. The laser light L may also be irradiated in pulses onto the laser absorbing layer P while a lens (not shown) included in the laser irradiation device is moved linearly. In this case, for example, a linear movement mechanism (transporter) may be provided for the lens to move the lens horizontally, or the laser light from the lens may be scanned by, for example, a galvanometer scanner (not shown). The laser light L passes through the first wafer W from the back surface Wb side of the first wafer W and is absorbed in the laser absorbing layer P. This laser light L reduces the bonding strength at the laser absorbing layer P, the interface between the laser absorbing layer P and the wafer W, or the interface between the laser absorbing layer P and the etching stop layer Q.

[0023] In the following description, the interface inside the first overlapping wafer T1 where the bonding strength has decreased (in this embodiment, the inner surface of the laser absorbing layer P) may be referred to as the "separation surface" in the technology of the present disclosure. Furthermore, in this embodiment, "decreased bonding strength" refers to a state where the bonding strength has decreased at least compared to before the irradiation of the laser light L, and includes separation between the laser absorbing layer P and the etching stop layer Q.

[0024] Next, as shown in FIG. 7 , the first wafer W is separated from the second wafer S in the first overlapping wafer T1 (St6 in FIGS. 1 and 2 ). In St6, for example, in a separation device 60 described later, the first wafer W is separated using the laser absorption layer P, the bonding strength of which has been reduced in St5, as a base point. Note that in this specification, the second wafer S after at least some of the layers formed on the first wafer W have been transferred and the first wafer W has been separated is referred to as the "second wafer S to which the layers have been transferred" or simply as the "second wafer S." In the example of FIG. 7 , the first device layer Dw, the surface films Fw and Fs, the second device layer Ds, and the second wafer S are referred to as the "second wafer S to which the first device layer Dw has been transferred" or simply as the "second wafer S." The same applies to the second overlapping wafer T2 described later.

[0025] The first wafer W can be separated by any method. For example, as shown in FIG. 7( a), a suction chuck 210 suction-holds the back surface Sb of the second wafer S, and a suction pad 211 suction-holds the front surface Wa of the first wafer W. Then, as shown in FIG. 7( b), while the suction pad 211 suction-holds the first wafer W, the suction pad 211 is raised to separate the first wafer W. At this time, as described above, the bonding strength is reduced inside the laser absorption layer P or at the interface between the laser absorption layer P and the etching stop layer Q due to the irradiation of the laser light L. Therefore, the first wafer W can be separated without applying a large load. Furthermore, since the unbonded region B1 is bevel-filled, a bonding force is generated in the unbonded region B1, ensuring separation at the interface. This prevents partial bevel damage, as shown in the comparative example of FIG. 16. As a result, the first device layer Dw transferred to the second wafer S can be widened, improving productivity.

[0026] Next, the separated surface of the first overlapping wafer T1 obtained by separating the first wafer W is subjected to surface treatment (St7 in FIGS. 1 and 2). In St7, the separated surface may be cleaned in, for example, a cleaning apparatus 90. Alternatively, the separated surface may be polished and planarized or removed in, for example, a polishing apparatus (not shown) or an etching apparatus (not shown). Details of the surface treatment according to this embodiment will be described later.

[0027] In one embodiment, the surface treatment includes a chemical mechanical polishing (CMP) process. In the CMP process, a polishing pad is brought into contact with the separated surface of the first overlapped wafer T1, and the surface is polished while applying pressure. In this process, the filler G according to this embodiment serves to prevent damage to the unbonded region of the bevel portion of the first overlapped wafer T1 due to the pressure.

[0028] In one embodiment, the material of the filler G is selected from the viewpoint of resistance to the laser light irradiation in St5. In this case, if the surface treatment in St7 includes CMP, it is preferable that the filler G also be resistant to each process step included in CMP. In one embodiment, if the filler G filled in St4 does not have resistance to one of the CMP processes, the filler G is removed after the separation of the first wafer W (St6) and before the CMP is performed in the surface treatment (St7). In this case, when the CMP is performed in the surface treatment (St7), another filler G that is resistant to each process step included in CMP is again filled in the unbonded region B1 of the first overlapped wafer T1. This prevents the unbonded region B1 from being damaged during the subsequent CMP. The refilling of the other filler G can be performed in the same manner as in St4 described above.

[0029] Next, a wiring layer Wr is formed on the surface-treated first overlapping wafer T1 (St8 in FIGS. 1 and 2 ). The wiring layer Wr can be formed by a known wiring process (BEOL: Back End of Line). Since a third wafer U (described later) is further bonded to the wiring layer Wr of the first overlapping wafer T1 according to this embodiment, a bonding surface film Ft is provided on the wiring layer Wr in St8. In one embodiment, the manufacturing method ends without bonding another wafer to the wiring layer Wr of the first overlapping wafer T1. In this case, the wiring layer Wr does not necessarily have to have a bonding surface film Ft.

[0030] Next, a third wafer U is prepared (St9 in FIGS. 1 and 2 ). The preparation of the third wafer U in St9 is similar to the preparation of the first wafer W in St1. That is, a stacked film including a laser absorption layer P, an etching stop layer Q, a third device layer Du, and a surface film Fu is formed on the surface of the third wafer U. The absorption layer P, the etching stop layer Q, the third device layer Du, and the surface film Fu of the third wafer U according to this embodiment are similar to the absorption layer P, the etching stop layer Q, the first device layer Dw, and the surface film Fw of the first wafer W, respectively. In one embodiment, the third device layer Du of the third wafer U includes devices different from the first device layer Dw of the first wafer W.

[0031] 1 and 2 , the second wafer S onto which the first device layer Dw has been transferred is bonded to a third wafer U to obtain a second overlapping wafer T2 as an overlapping substrate (St10). The bonding between the third wafer U and the second wafer S in St10 is similar to the bonding between the first wafer W and the second wafer S in St3. Thereafter, the filler G is filled in the unbonded region B2 of the second overlapping wafer T2 by bevel filling (St11) of the second overlapping wafer T2. In one embodiment, if the filler G filled in the unbonded region B1 of the first overlapping wafer T1 has been removed in a process prior to St11, the filler G is filled in both the unbonded regions B1 and B2 in St11. Thereafter, irradiation with laser light L (St12), separation of the third wafer U (St13), surface treatment of the second wafer S onto which the third device layer Du has been transferred (St14), and formation of a wiring layer Wr (St15) are sequentially performed. St11 to St15 are the same as St4 to St8. In this embodiment, the manufacturing method ends after the wiring layer Wr is formed in St15. In one embodiment, after the wiring layer Wr is formed in St15, another wafer (not shown) may be further bonded onto the wiring layer Wr of the second overlapping wafer T2, and steps similar to St3 to St8 may be performed. Note that in this specification, the first overlapping wafer T1 and the second overlapping wafer T2 may be collectively referred to simply as "overlapping wafers T1 and T2."

[0032] In the separation of St13, since the unbonded regions B1 and B2 are bevel filled, a bonding force is generated in the unbonded regions B1 and B2, and therefore it is possible to ensure separation at the bonding interface between the second wafer S and the third wafer U. This makes it possible to prevent repeated damage to the bevel and to prevent consumption of the region where a device can be formed, even in a process in which bonding and separation are repeated two or more times.

[0033] The first wafer W separated in St7 is reused (St20 in FIG. 1 ). As an example of the recycling process for the first wafer W, the laser absorbing layer P remaining on the first wafer W is etched and removed in an etching apparatus (not shown). The etching of the laser absorbing layer P may be dry etching or wet etching. From this perspective, the laser absorbing layer P is configured to be selectively etched with respect to the front surface Wa of the first wafer W. In one embodiment, when a sacrificial layer is present between the laser absorbing layer P and the first wafer W, selective etching is first performed between the laser absorbing layer P and the sacrificial layer, and then selective etching is performed between the sacrificial layer and the front surface Wa of the first wafer W.

[0034] The first wafer W from which the laser absorbing layer P has been removed is then subjected to the same process as in St1, and a separation layer Mw, a first device layer Dw, and a surface film Fw are formed on the front surface Wa. In this way, the first wafer W is reused for the next second wafer S. Note that the first wafer W from which the laser absorbing layer P has been removed is a bare wafer with no film formed on the front surface Wa, and therefore may be reused as the next second wafer S.

[0035] The third wafer U separated in St13 is reused (St21 in FIG. 1) in the same manner as the first wafer W in St20.

[0036] 8, a manufacturing method according to one embodiment will be described below in which, in preparation of a first wafer W (St1 in FIG. 1), at least a part of a 3D NAND memory cell array is formed in a device layer Dw of the first wafer W. The device layer Dw includes memory holes H formed by the following method, for example.

[0037] Specifically, the preparation of the first wafer W (St1 in FIG. 1) according to this embodiment includes the steps shown in FIGS. 9 and 10. FIGS. 10A to 10C are diagrams showing an example of the state of the device layer Dw in major steps among the steps. The same applies to the preparation of the third wafer U in St9 in FIG. 1.

[0038] First, a laser absorbing layer P is formed above the surface Wa of the first wafer W (Step 101 in FIGS. 9 and 10). The laser absorbing layer P is a desired oxide film (SiO ２ film, TEOS film).

[0039] Next, an etching stop layer Q is formed above the laser absorption layer P (Step 102 in FIGS. 9 and 10). The etching stop layer Q is made of polycrystalline silicon.

[0040] Next, an etching stop structure ES is formed in a part of the etching stop layer Q corresponding to a position where a memory hole H, which will be described later, is to be formed (St103 in FIG. 9).

[0041] In St103, first, a recess ES' is formed in the part of the etching stop layer Q (St103a in FIG. 10). Then, a pad Pd and an oxide film Ox are formed in the recess ES' (St103b in FIG. 10). The pad Pd has the function of stopping etching so that the laser absorption layer P, the first wafer W, and the like below the pad Pd are not etched in a high aspect ratio (HAR) etching process when forming the memory hole H, which will be described later. Examples of materials for the pad Pd include titanium nitride (TiN), tungsten (W), and tungsten silicide (WSi ２ However, the present invention is not limited to these, and other known materials that have the above-mentioned effects may be used.

[0042] In one embodiment, the etching stop structure ES is configured not to have a pad Pd. In this case, the etching stop layer Q may be configured not to have an etching stop structure ES. Furthermore, in this case, the etching stop layer Q may be formed to have a thickness sufficient to prevent etching below the pad Pd in ​​the etching step for forming the memory hole H, which will be described later.

[0043] Next, an alternating layer AL in which a plurality of oxide films and nitride films are alternately stacked as a laminated film is formed above the etching stop layer Q (Step 104 in FIGS. 9 and 10).

[0044] Next, deep holes DH are formed by HAR etching so as to penetrate the alternating layers AL at positions where memory holes H are to be formed (Step 105 in FIGS. 9 and 10 ). Step 105 can be performed using a known patterning device and etching device. The deep holes DH formed by etching stop at the etching stop structures ES and do not reach the laser absorption layer P or the first wafer W. This allows for subsequent separation of the laser absorption layer P to be performed favorably. Furthermore, the possibility of reusing the separated first wafer W is improved.

[0045] Next, the etching stop structure ES is removed (Step 106 in FIGS. 9 and 10). The etching stop structure ES is removed by, for example, dry etching.

[0046] Next, a memory hole H is formed in the deep hole DH from which the etching stop structure ES has been removed (Step 107 in FIGS. 9 and 10). The memory hole H can be formed by, for example, forming various films on the sidewall of the deep hole DH.

[0047] After the memory holes H are formed, a wiring layer Wr and a surface film Fw are formed as shown in FIG. 10C (Step 108 in FIG. 9). The wiring layer Wr according to this embodiment includes a conductive material that forms a signal network or a power supply network. The surface film Fw includes a copper pad Cu that is electrically connected to the wiring layer Wr.

[0048] In one embodiment, a memory hole H with an even higher aspect ratio is obtained by further forming another deep hole DH above the deep hole DH formed in St105 and St106. Specifically, as shown in FIGS. 11 and 12, after the execution of St101 to St106, St110 to St113 are further executed, and then St107 and St108 are executed.

[0049] After St106 is performed, first, a sacrificial layer SL is formed in the deep hole DH (St110 in FIGS. 11 and 12).

[0050] Next, above the deep hole DH filled with the sacrificial layer SL, another alternating layer AL of multiple oxide and nitride films is formed (St111 in FIGS. 11 and 12 ). The other alternating layer AL is configured to include an etching stop portion EP. The etching stop portion EP has the function of stopping etching so that the area below the etching stop portion EP is not etched during HAR etching of the other alternating layer AL. The material of the etching stop portion EP is not particularly limited as long as it can ensure an etching selectivity relative to the oxide or nitride film that constitutes the other alternating layer AL.

[0051] Next, at the position where the memory hole H is to be formed, another deep hole DH is formed by performing HAR etching so as to penetrate the other alternating layers AL (Step 112 in FIGS. 11 and 12 ). Step 112 is the same as Step 105 described above. The etching of the other deep hole DH formed by the etching stops at the etching stop portion EP.

[0052] Next, the etching stopper EP is removed, and then the sacrificial layer SL is removed (Step 113 in FIGS. 11 and 12). The etching stopper EP and the sacrificial layer SL are removed by, for example, dry etching. By Step 113, the lower deep hole DH formed by Steps 105 and 106 is connected to another upper deep hole DH, forming a single deep hole.

[0053] Thereafter, various films are formed on the sidewalls of the communicating deep holes DH in Step St107 to form memory holes H. In addition, a wiring layer Wr and a surface film Fw are formed in Step St108.

[0054] Referring again to FIG. 8 , in preparation of the second wafer S (St2 in FIG. 1 ), a second wafer S is prepared on which a peripheral circuit for controlling a memory cell array is formed in the device layer Ds. The peripheral circuit according to this embodiment includes a CMOS (Complementary Metal-Oxide-Semiconductor) and a wiring layer Wr electrically connected to the CMOS. The surface film Fs of the second wafer S also includes a copper pad Cu electrically connected to the wiring layer Wr. Note that in St2, the second wafer S may be prepared on which a peripheral circuit has already been formed, or the second wafer S may be prepared by forming the peripheral circuit in St2.

[0055] After the first wafer W and the second wafer S are prepared as described above, the first wafer W and the second wafer S are bonded together to obtain a first overlapping wafer T1 (St3 in FIGS. 1 and 8).

[0056] Next, bevel filling of the unbonded region B of the first overlapping wafer T1 (St4 in FIGS. 1 and 8), irradiation of the laser light L onto the laser absorption layer P (St5 in FIGS. 1 and 8), and separation of the first wafer W (St6 in FIGS. 1 and 8) are sequentially performed.

[0057] Next, a surface treatment is performed on the separated surface of the first overlapping wafer T1 from which the first wafer W has been separated (St7 in FIGS. 1 and 8 ). In the surface treatment according to this embodiment, the laser absorbing layer P remaining on the separated surface of the first overlapping wafer T1 after separation of the first wafer W is removed. Subsequently, the etching stop layer Q is removed. Removal of the laser absorbing layer P may include, for example, selective etching of the laser absorbing layer P relative to the etching stop layer Q. Removal of the etching stop layer Q may also include selective etching of the etching stop layer Q relative to the device layer Dw of the first wafer W. Surface treatment including selective etching of the etching stop layer Q can improve the total thickness variation (TTV) of the first overlapping wafer T1 after the surface treatment.

[0058] In this embodiment, at least a portion of the memory hole H included in the device layer Dw is exposed on the separation surface of the first overlapping wafer T1 after the surface treatment. Then, a wiring layer Wr is formed to be electrically connected to the exposed memory hole H (St8 in FIGS. 1 and 8 ). In one embodiment, after the surface treatment, a portion of the memory hole H including a polycrystalline silicon film doped with impurities and rendered conductive is exposed. In this case, the wiring layer Wr can be formed in St8 so as to be electrically connected to the polycrystalline silicon film.

[0059] Thereafter, a surface film Ft for bonding may be formed when bonding the first overlapped wafer T1 and the third wafer U. Thereafter, the second overlapped wafer T2 may be formed by further performing bonding with the third wafer U (St9 to St15). In this case, the third wafer U may be configured to include at least a part of the memory cell array of the 3D NAND, similar to the first wafer W.

[0060] A wafer processing system 1 will be described below as an example of a substrate processing system capable of performing the bonding and separation of the first substrate and the second substrate in the wafer processing method described above.

[0061] 13 , wafer processing system 1 has a configuration in which a load / unload station 2 and a processing station 3 are integrally connected. In load / unload station 2, for example, a cassette C capable of accommodating a plurality of overlapping wafers T1, T2 is loaded and unloaded between the load / unload station 2 and the outside. Processing station 3 is equipped with various processing devices that perform desired processing on overlapping wafers T1, T2.

[0062] The carry-in / out station 2 is provided with a cassette mounting table 10 on which a cassette C capable of accommodating a plurality of overlapping wafers T1, T2 is mounted. A wafer transfer device 20 is provided adjacent to the cassette mounting table 10 on the positive side of the X-axis of the cassette mounting table 10. The wafer transfer device 20 moves on a transfer path 21 extending in the Y-axis direction, and is configured to be able to transfer the overlapping wafers T1, T2 between the cassette C on the cassette mounting table 10 and a transition stage 30, which will be described later.

[0063] In the loading / unloading station 2, a transition stage 30 is provided adjacent to the wafer transport device 20 on the positive X-axis side of the wafer transport device 20 for transferring the overlapping wafers T1 and T2 between the processing station 3.

[0064] In the processing station 3, a wafer transfer device 40, a laser processing device 50, a separation device 60, a bevel filling device 70, a baking device 80, and a cleaning device 90 are arranged.

[0065] The wafer transfer device 40 is provided on the positive X-axis side of the transition stage 30. The wafer transfer device 40 is configured to be movable on a transfer path 41 extending in the X-axis direction, and is configured to be able to transfer the overlapped wafers T1 and T2 to the transition stage 30 of the carry-in / out station 2, the laser processing device 50, the separation device 60, the bevel fill device 70, the bake device 80, and the cleaning device 90.

[0066] The laser processing device 50 irradiates the laser absorption layer P at the interface between the first wafer W and the second wafer S with laser light L1, thereby forming a region of reduced bonding strength where the first wafer W and the second wafer S are separated. The laser processing device 50 has a control device 51, which will be described later.

[0067] As shown in FIGS. 14 and 15 , the laser processing apparatus 50 includes a chuck 100 that holds the overlapping wafers T1 and T2 on their upper surfaces. The chuck 100 suction-holds the back surface Sb of the second wafer S, with the first wafer W positioned on top and the second wafer S positioned on the bottom. The chuck 100 is supported by a slider table 102 via an air bearing 101. A rotation mechanism 103 is provided on the underside of the slider table 102. The rotation mechanism 103 incorporates, for example, a motor as a drive source. The chuck 100 is configured to be rotatable about a vertical axis by the rotation mechanism 103 via the air bearing 101. The slider table 102 is configured to be movable on rails 106 extending in the Y-axis direction on a base 105 via a movement mechanism 104 provided on the underside of the slider table 102. The drive source of the movement mechanism 104 is not particularly limited, but may be, for example, a linear motor.

[0068] A laser head 110 is provided above the chuck 100. The laser head 110 has a lens 111. The lens 111 irradiates the laser absorption layer P of the overlapping wafers T1 and T2 held by the chuck 100 with laser light L1. This causes the first wafer W and the laminated film to separate at the portion irradiated with the laser light L1, forming a reduced bonding strength region where the first wafer W and the second wafer S are separated. The location of the reduced bonding strength region is not particularly limited as long as separation occurs at the interface between the first wafer W and the second wafer S and the bonding strength can be reduced. That is, separation between the first wafer W and the second wafer S may occur at the interface between the first wafer W and the laminated film as shown in the figure, or may occur at the interface between the laminated films or the interface between the second wafer S and the laminated film.

[0069] The laser head 110 is supported by a support member 112. The laser head 110 is configured to be able to move up and down by an elevating mechanism 114 along rails 113 extending in the vertical direction. The laser head 110 is also configured to be able to move in the Y-axis direction by a moving mechanism 115. The elevating mechanism 114 and the moving mechanism 115 are each supported by a support column 116.

[0070] In the illustrated example, the chuck 100 is configured to be rotatable relative to the laser head 110 and movable horizontally by the rotation mechanism 103 and the movement mechanism 104, but the laser head 110 may be configured to be rotatable relative to the chuck 100 and movable horizontally. Alternatively, both the chuck 100 and the laser head 110 may be configured to be rotatable relative to each other and movable horizontally.

[0071] 7A, the separation device 60 includes a suction chuck 210 and a suction pad 211. Then, by the method described above, the first wafer W is separated from the second wafer S, starting from the bonding strength reduced region.

[0072] The bevel fill device 70 includes an injector 9 as shown in FIG. 4 or 5 and is configured to be able to inject filler G into the bevel portions of the overlapping wafers T1, T2. As an example, the bevel fill device 70 includes a chuck (not shown) similar to the chuck 100. The overlapping wafers T1, T2 are held on the chuck, and filler G is injected from the injector 9 into the bevel portions while the overlapping wafers T1, T2 are rotated. This makes it possible to inject filler G into the bevel portions around the entire periphery of the overlapping wafers T1, T2. In one embodiment, the bevel fill device 70 is controlled to inject filler G only into the unbonded regions of the bevel portions of the overlapping wafers T1, T2.

[0073] The baking device 80 is configured to bake (fire) the filler G in the overlapping wafers T1 and T2 in which the filler G has been injected into the bevel portion.

[0074] The cleaning device 90 performs a cleaning process on the first wafer W and the second wafer S after the filler G has been injected by the bevel fill device 70 or after the filler G has been baked by the bake device 80, thereby removing particles on these wafers and the filler G adhering to unnecessary locations. The cleaning method can be selected arbitrarily.

[0075] In one embodiment, the wafer processing system 1 is divided into a plurality of systems, including one wafer processing system including a laser processing device 50 and a separation device 60, and another wafer processing system including a bevel fill device 70 and a bake device 80. Wafers W, S, U, overlapping wafers T1, T2, etc. are transported between these multiple systems, and desired processing is performed on each wafer.

[0076] The wafer processing system 1 described above is provided with a control device 51 and at least one control device 95. The control device 51 individually controls the operations of the laser processing devices 50. The control device 95 controls the entire series of wafer processing operations in the wafer processing system 1.

[0077] Controller 51 and controller 95 each process computer-executable instructions that cause laser processing device 50 and wafer processing system 1 to perform the various steps described in this disclosure. Controller 51 and controller 95 can each be configured to control elements of laser processing device 50 and wafer processing system 1 to perform the various steps described herein. In one embodiment, some or all of controller 51 can be included in laser processing device 50, and some or all of controller 95 can be included in wafer processing system 1.

[0078] The control device 51 and the control device 95 may each include a processing unit, a storage unit, and a communication interface. The control device 51 and the control device 95 may each be realized by, for example, a computer. The processing unit may be configured to read a program providing logic or routines that enable various control operations from the storage unit and execute the read program to perform various control operations. This program may be stored in the storage unit in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit and read from the storage unit and executed by the processing unit. The medium may be various computer-readable storage media or a communication line connected to the communication interface. The storage medium may be temporary or non-temporary. The processing unit may be a CPU (Central Processing Unit) or one or more circuits. The storage unit may include a RAM (Random Access Memory), a ROM (Read Only Memory), a HDD (Hard Disk Drive), a SSD (Solid State Drive), or a combination thereof. The communication interface may communicate between the laser processing device 50 and the wafer processing system 1 via a communication line such as a LAN (Local Area Network).

[0079] In this embodiment, the control device 51 is installed separately from the laser processing device 50, but the control device 51 may be configured integrally with the control device 95. In other words, the operation of the laser processing device 50 may be controlled by the control device 95.

[0080] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims. For example, the components of the above-described embodiments may be arbitrarily combined. Such an arbitrary combination naturally provides the functions and effects of each of the components involved in the combination, and also provides other functions and effects that are apparent to those skilled in the art from the description of this specification.

[0081] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that would be apparent to a person skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0082] B: Unbonded region P: Laser absorbing layer S: Second wafer T: Overlapped wafer W: First wafer

Claims

1. A method for manufacturing a semiconductor device, comprising: performing bevel filling on an unbonded region of a laminated substrate in which a first substrate having a laser absorption layer and a second substrate are bonded; irradiating the laser absorption layer with a laser; and separating the first substrate from the second substrate in the laminated substrate.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising: forming an etching stop layer on said laser absorption layer; and forming a device layer on said etching stop layer.

3. The method for manufacturing a semiconductor device according to claim 2, further comprising: forming a wiring layer on the first substrate; and forming a surface film for bonding.

4. The method for manufacturing a semiconductor device according to claim 2, further comprising, after separating the first substrate from the second substrate, surface treating the separation surface of the second substrate onto which the device layer has been transferred, wherein the etching stop layer is made of a material capable of being selectively etched relative to the separation surface, and the surface treating comprises removing the etching stop layer by selectively etching the etching stop layer relative to the separation surface.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the surface treatment includes exposing at least a portion of the device layer from the separation surface.

6. The method for manufacturing a semiconductor device according to claim 2, wherein forming the device layer includes forming a stacked film on the etching stop layer and etching the stacked film to form a deep hole, and forming the etching stop layer includes forming an etching stop structure in a part of the etching stop layer corresponding to a position in the device layer where the deep hole is to be formed, and the etching stop structure is configured to stop the etching that forms the deep hole at the etching stop structure.

7. The method of claim 6, wherein the etch stop structure includes a pad made of a material selected from one or more of titanium nitride, tungsten, and tungsten silicide.

8. The method for manufacturing a semiconductor device according to claim 1, further comprising, after separating the first substrate from the laminated substrate, removing the filler material filled in the unbonded region by the bevel fill.

9. The method for manufacturing a semiconductor device according to claim 8, further comprising, after separating the first substrate from the laminated substrate, surface-treating the separation surface of the laminated substrate from which the first substrate has been separated, and further comprising, after removing the filler and before surface-treating the separation surface, again performing the bevel fill on the unbonded region of the laminated substrate.

10. The method for manufacturing a semiconductor device according to claim 2, wherein the device layer includes at least a portion of a memory cell array.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the second substrate includes another device layer, and the other device layer includes at least a part of a peripheral circuit for controlling the memory cell array.

12. The method for manufacturing a semiconductor device according to claim 1, further comprising: forming a second laminated substrate by bonding a third substrate having a laser absorption layer to the laminated substrate; performing bevel filling on an unbonded region of the second laminated substrate; irradiating the laser absorption layer of the third substrate with a laser; and separating the third substrate from the second substrate in the second laminated substrate.

13. A semiconductor device manufacturing system comprising: a laser irradiation device that irradiates a laser onto a laser absorption layer of an overlapped substrate formed by bonding a first substrate having a laser absorption layer to a second substrate, the overlapped substrate having a bevel filled unbonded region; and a separation device that separates the first substrate from the second substrate in the overlapped substrate.

14. The semiconductor device manufacturing system according to claim 13, further comprising a bevel fill device that performs bevel fill on the unbonded region of the laminated substrate.

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