Optical connection structure

Abstract

In the present invention, a first surface (100a) of a first chip (100) and a second surface (120a) of a second chip (120) are joined so as to face each other, and a first core (101) exposed at the first surface (100a) of the first chip (100) and a second core (121) exposed at the second surface (120a) of the second chip (120) are disposed so as to overlap in a waveguide direction. The first surface (100a) and the second surface (120a) are joined by solder (111) in a joining region other than an optical connection region.

Description

Optical connection structure

[0001] The present invention relates to an optical connection structure.

[0002] Fiber arrays (FAs) are used to input optical output from photonic integrated circuits (PICs) with multiple channels, such as planar lightwave circuits (PLCs) and silicon photonics (SiPh), into a transmission line (Non-Patent Document 1).

[0003] T. Barwicz et al., "Compliant Polymer Interface Demonstration with Standard Plug-In Connection to Fiber Cables", IEEE Photonics Conference , DOI: 10.1109 / IPCon.2018.8527162, 2018.

[0004] However, the above-mentioned technology has the problem of increasing the cost of optical devices. For example, the time-consuming alignment process specific to optical fibers during assembly increases costs. Furthermore, the end face of the fiber array is connected to the end face of the PIC, but the bonding area is small when bonding these end faces, so additional structures are required to ensure sufficient strength (reliability). These additional structures increase the cost of optical devices.

[0005] The present invention has been made to solve the above problems, and has as its object to reduce the cost of optical devices without reducing reliability.

[0006] The optical connection structure according to the present invention comprises a first chip on which a planar lightwave circuit is formed, and a second chip on which silicon photonics is formed, wherein one first surface of the first chip and one second surface of the second chip are joined together with a first region formed on the first surface and a second region formed on the second surface facing each other, and a first core of the first optical waveguide constituting the planar lightwave circuit, which is exposed on the first surface in the first region, and a second core made of Si of the second optical waveguide constituting the silicon photonics, which is exposed on the second surface in the second region, are arranged to overlap in the waveguiding direction, and the second core of the second optical waveguide is made thinner than in other regions, thereby reducing optical confinement.

[0007] As described above, according to the present invention, the first surface of the first chip and the second surface of the second chip are joined facing each other, and the first core exposed on the first surface of the first chip and the second core exposed on the second surface of the second chip are arranged to overlap in the waveguide direction, thereby reducing the cost of the optical device without reducing reliability.

[0008] Fig. 1 is a cross-sectional view showing a partial configuration of an optical connection structure according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing a partial configuration of an optical connection structure according to a second embodiment of the present invention. Fig. 3 is a cross-sectional view showing a partial configuration of an optical connection structure according to a third embodiment of the present invention. Fig. 4 is a cross-sectional view showing a partial configuration of an optical connection structure according to a fourth embodiment of the present invention. Fig. 5 is a cross-sectional view showing a partial configuration of an optical connection structure according to a fifth embodiment of the present invention. Fig. 6 is a cross-sectional view showing a partial configuration of an optical connection structure according to a sixth embodiment of the present invention.

[0009] Hereinafter, an optical connection structure according to an embodiment of the present invention will be described.

[0010] First Embodiment First, an optical connection structure according to a first embodiment of the present invention will be described with reference to Fig. 1. Fig. 1 shows a cross section of a plane perpendicular to the waveguide direction, illustrating a part of the optical connection structure.

[0011] This optical connection structure includes a first chip 100 having a planar lightwave circuit formed thereon and a second chip 120 having silicon photonics formed thereon. The first chip 100 and the second chip 120 are arranged such that a first surface 100a of the first chip 100 faces a second surface 120a of the second chip 120. The first surface 100a and the second surface 120a are bonded together such that a first region 104 formed on the first surface 100a faces a second region 124 formed on the second surface 120a. The first surface 100a can be the top or bottom surface of the first chip 100. The second surface 120a can be the top or bottom surface of the second chip 120.

[0012] In the first region 104 of the first chip 100, the top surface of the first core 101 of the first optical waveguide that constitutes the planar lightwave circuit is exposed on the first surface 100a. A first cladding layer 102 and a second cladding layer 103 are formed around the first core 101 to constitute the first optical waveguide. The first optical waveguide that constitutes the planar lightwave circuit of the first chip 100 is made of, for example, silica-based glass. Although not shown, a very thin cladding layer can be formed on the first surface 100a of the first chip 100.

[0013] In the second region 124 of the second chip 120, the upper surface of a second core 121 made of Si of a second optical waveguide constituting silicon photonics is exposed on the second surface 120a. A third cladding layer 122 and a fourth cladding layer 123 are formed around the second core 121 to form the second optical waveguide. The third cladding layer 122 and the fourth cladding layer 123 are made of, for example, silicon oxide.

[0014] The first core 101 exposed at the first surface 100a in the first region 104 and the second core 121 exposed at the second surface 120a in the second region 124 are overlapped in the waveguiding direction and arranged parallel to each other. The second core 121 of the second optical waveguide is made thinner (having a smaller cross-sectional size) than the other regions, thereby reducing the optical confinement.

[0015] Furthermore, the first surface 100a and the second surface 120a are joined (solder-joined) with solder 111 in a joining region other than the optical connection region where the first region 104 and the second region 124 face each other. The optical connection device also includes a refractive index matching layer 112 for matching the refractive index between the first region 104 and the second region 124. The refractive index matching layer 112 is provided so as to fill the space between the first region 104 and the second region 124 in the optical connection region. In the first embodiment, a gap is created between the first chip 100 and the second chip 120 by the thickness of the solder 111, but the provision of the refractive index matching layer 112 makes it possible to fill the gap.

[0016] As described above, by arranging the first core 101 of the first optical waveguide and the second core 121 of the second optical waveguide close to each other and parallel to each other, light can be adiabatically coupled between the two optical waveguides, and light can be input and output even between optical waveguides made of different materials. By bonding on the top or bottom surface of the chip rather than on the end surface of the chip, the mounting speed can be improved, and the bonding area (adhesion area) can be increased, thereby improving reliability. Thus, according to the first embodiment, it is possible to reduce the cost of optical devices, such as chips on which planar lightwave circuits are formed and chips on which silicon photonics are formed, without reducing reliability.

[0017] Second Embodiment Next, an optical connection structure according to a second embodiment will be described with reference to Fig. 2. Fig. 2 shows a cross section of a plane perpendicular to the waveguide direction, illustrating a part of the optical connection structure.

[0018] This optical connection structure includes a first chip 100 having a planar lightwave circuit formed thereon and a second chip 120 having silicon photonics formed thereon. The first chip 100 and the second chip 120 are arranged such that a first surface 100a of the first chip 100 faces a second surface 120a of the second chip 120. The first surface 100a and the second surface 120a are bonded together such that a first region 104 formed on the first surface 100a faces a second region 124 formed on the second surface 120a. The first surface 100a can be the top or bottom surface of the first chip 100. The second surface 120a can be the top or bottom surface of the second chip 120.

[0019] In the first region 104 of the first chip 100, the top surface of a first core 101 of a first optical waveguide that constitutes the planar lightwave circuit is exposed on the first surface 100a. A first cladding layer 102a and a second cladding layer 103 are formed around the first core 101 to constitute the first optical waveguide. The first optical waveguide that constitutes the planar lightwave circuit of the first chip 100 is made of, for example, silica-based glass. Furthermore, the first cladding layer 102a is made of silica-based glass doped with B (boron) or P (phosphorus).

[0020] In the second region 124 of the second chip 120, the upper surface of a second core 121 made of Si of a second optical waveguide constituting silicon photonics is exposed on the second surface 120a. A third cladding layer 122 and a fourth cladding layer 123 are formed around the second core 121 to form the second optical waveguide. The third cladding layer 122 and the fourth cladding layer 123 are made of, for example, silicon oxide.

[0021] The first core 101 exposed at the first surface 100a in the first region 104 and the second core 121 exposed at the second surface 120a in the second region 124 are overlapped in the waveguiding direction and arranged parallel to each other. The second core 121 of the second optical waveguide is made thinner than the other regions, thereby reducing optical confinement.

[0022] Furthermore, the first surface 100a and the second surface 120a are anodically bonded by metal foil 113 in a bonding region other than the optical connection region where the first region 104 and the second region 124 face each other. The metal foil 113 is formed in the bonding region of the second surface 120a (third cladding layer 122) of the second chip 120. For example, the metal foil 113 can be formed by depositing metal in predetermined locations on the third cladding layer 122 using a sputtering method or the like. The metal foil 113 can be made of a material that can be used for anodic bonding, such as Fe, Ni, Co, Ti, or an alloy thereof.

[0023] As is well known, anodic bonding can be performed by bringing the first cladding layer 102a and the metal foil 113 into contact with each other and applying a DC voltage of several hundred volts between them, with the metal foil 113 acting as the anode. Anodic bonding allows the first cladding layer 102a, which is made of a glass-based material, and the metal foil 113 to be bonded together without using any intermediate material such as solder or adhesive.

[0024] Also, a refractive index matching layer 112 is provided to match the refractive index between the first region 104 and the second region 124. The refractive index matching layer 112 is provided so as to fill the space between the first region 104 and the second region 124 in the optical connection region. In the second embodiment, a gap is created between the first chip 100 and the second chip 120 by the thickness of the metal foil 113, but by providing the refractive index matching layer 112, the gap can be filled.

[0025] As described above, by arranging the first core 101 of the first optical waveguide and the second core 121 of the second optical waveguide close to each other and parallel to each other, light can be adiabatically coupled between the two optical waveguides, and light can be input and output even between optical waveguides made of different materials. By bonding the top or bottom surface of the chip rather than the end surface of the chip, the mounting speed can be improved, and the increased bonding area can improve reliability. Thus, in the second embodiment, too, the cost of an optical device formed by a chip on which a planar lightwave circuit is formed and a chip on which silicon photonics is formed can be reduced without reducing reliability.

[0026] Third Embodiment Next, an optical connection structure according to a third embodiment will be described with reference to Fig. 3. Fig. 3 shows a cross section of a plane perpendicular to the waveguide direction, illustrating a part of the optical connection structure.

[0027] This optical connection structure includes a first chip 100 having a planar lightwave circuit formed thereon and a second chip 120 having silicon photonics formed thereon. The first chip 100 and the second chip 120 are arranged such that a first surface 100a of the first chip 100 faces a second surface 120a of the second chip 120. The first surface 100a and the second surface 120a are bonded together such that a first region 104 formed on the first surface 100a faces a second region 124 formed on the second surface 120a. The first surface 100a can be the top or bottom surface of the first chip 100. The second surface 120a can be the top or bottom surface of the second chip 120.

[0028] In the first region 104 of the first chip 100, the top surface of the first core 101 of the first optical waveguide constituting the planar lightwave circuit is exposed on the first surface 100a. The top surface of the first core 101 is exposed on the first surface 100a without the fifth cladding layer 105 (described later) being formed. A first cladding layer 102 and a second cladding layer 103 are formed around the first core 101 to form the first optical waveguide. The first optical waveguide constituting the planar lightwave circuit of the first chip 100 is made of, for example, silica-based glass. In the third embodiment, the first surface 100a of the first chip 100 includes a very thin fifth cladding layer 105. The fifth cladding layer 105 is made of silica-based glass doped with B (boron) or P (phosphorus).

[0029] In the second region 124 of the second chip 120, the upper surface of a second core 121 made of Si of a second optical waveguide constituting silicon photonics is exposed on the second surface 120a. A third cladding layer 122 and a fourth cladding layer 123 are formed around the second core 121 to form the second optical waveguide. The third cladding layer 122 and the fourth cladding layer 123 are made of, for example, silicon oxide.

[0030] The first core 101 exposed at the first surface 100a in the first region 104 and the second core 121 exposed at the second surface 120a in the second region 124 are overlapped in the waveguiding direction and arranged parallel to each other. The second core 121 of the second optical waveguide is made thinner than the other regions, thereby reducing optical confinement.

[0031] Furthermore, the first surface 100a and the second surface 120a are anodically bonded via the fifth cladding layer 105 by the metal foil 113 in a bonding region other than the optical connection region where the first region 104 and the second region 124 face each other. The metal foil 113 is formed in the bonding region of the second surface 120a (third cladding layer 122) of the second chip 120. For example, the metal foil 113 can be formed by depositing metal at predetermined locations on the third cladding layer 122 by a sputtering method or the like. The metal foil 113 can be made of a material that can be used for anodic bonding, such as Fe, Ni, Co, Ti, or an alloy thereof.

[0032] As is well known, anodic bonding can be performed by bringing the fifth cladding layer 105 and the metal foil 113 into contact with each other and applying a DC voltage of about several hundred volts between them, with the metal foil 113 acting as the anode. Anodic bonding allows the fifth cladding layer 105, made of a glass-based material, and the metal foil 113 to be bonded together without using an intervening material such as solder or adhesive.

[0033] Also, a refractive index matching layer 112 may be provided to match the refractive index between the fifth cladding layer 105 formed in the first region 104 and the second region 124. The refractive index matching layer 112 is provided so as to fill the space between the first region 104 and the second region 124 in the optical connection region. In the third embodiment, a gap is created between the fifth cladding layer 105 of the first chip 100 and the second chip 120 by the thickness of the metal foil 113, but the provision of the refractive index matching layer 112 makes it possible to fill the gap.

[0034] As described above, by arranging the first core 101 of the first optical waveguide and the second core 121 of the second optical waveguide close to each other and parallel to each other, light can be adiabatically coupled between the two optical waveguides, and light can be input and output even between optical waveguides made of different materials. By bonding on the top or bottom surface of the chip rather than on the end surface of the chip, the mounting speed can be improved, and the increased bonding area can improve reliability. Thus, in the third embodiment, too, the cost of an optical device formed by a chip on which a planar lightwave circuit is formed and a chip on which silicon photonics is formed can be reduced without reducing reliability.

[0035] [Fourth Embodiment] Next, an optical connection structure according to a fourth embodiment will be described with reference to Fig. 4. Fig. 4 shows a cross section of a plane perpendicular to the waveguide direction, illustrating a part of the optical connection structure.

[0036] This optical connection structure includes a first chip 100 having a planar lightwave circuit formed thereon and a second chip 120 having silicon photonics formed thereon. The first chip 100 and the second chip 120 are arranged such that a first surface 100a of the first chip 100 faces a second surface 120a of the second chip 120. The first surface 100a and the second surface 120a are bonded together such that a first region 104 formed on the first surface 100a faces a second region 124 formed on the second surface 120a. The first surface 100a can be the top or bottom surface of the first chip 100. The second surface 120a can be the top or bottom surface of the second chip 120.

[0037] In the first region 104 of the first chip 100, the top surface of the first core 101 of the first optical waveguide constituting the planar lightwave circuit is exposed on the first surface 100a. The top surface of the first core 101 is exposed on the first surface 100a without the glass layer 106 (described later) being formed. A first cladding layer 102 and a second cladding layer 103 are formed around the first core 101 to form the first optical waveguide. The first optical waveguide constituting the planar lightwave circuit of the first chip 100 is made of, for example, silica-based glass. In the fourth embodiment, the first surface 100a of the first chip 100 includes a very thin glass layer 106. The glass layer 106 is formed using the well-known SOG (spin-on-glass) process. The glass layer 106 can be formed to a thickness of, for example, 0.1 μm.

[0038] In the second region 124 of the second chip 120, the upper surface of a second core 121 made of Si of a second optical waveguide constituting silicon photonics is exposed on the second surface 120a. A third cladding layer 122 and a fourth cladding layer 123 are formed around the second core 121 to form the second optical waveguide. The third cladding layer 122 and the fourth cladding layer 123 are made of, for example, silicon oxide.

[0039] The first core 101 exposed at the first surface 100a in the first region 104 and the second core 121 exposed at the second surface 120a in the second region 124 are overlapped in the waveguiding direction and arranged parallel to each other. The second core 121 of the second optical waveguide is made thinner than the other regions, thereby reducing optical confinement.

[0040] Furthermore, the first surface 100a and the second surface 120a are anodically bonded via the glass layer 106 by metal foil 113 in a bonding region other than the optical connection region where the first region 104 and the second region 124 face each other. The metal foil 113 is formed in the bonding region of the second surface 120a (third cladding layer 122) of the second chip 120. For example, the metal foil 113 can be formed by depositing metal in predetermined locations on the third cladding layer 122 using a sputtering method or the like. The metal foil 113 can be made of a material that can be used for anodic bonding, such as Fe, Ni, Co, Ti, or an alloy thereof.

[0041] As is well known, anodic bonding can be performed by bringing the glass layer 106 and the metal foil 113 into contact with each other and applying a DC voltage of several hundred volts between them, with the metal foil 113 acting as the anode. Anodic bonding allows the glass layer 106, made of a glass-based material, and the metal foil 113 to be bonded together without using an intervening material such as solder or adhesive.

[0042] Furthermore, a refractive index matching layer 112 may be provided to match the refractive index between the glass layer 106 formed in the first region 104 and the second region 124. The refractive index matching layer 112 is provided to fill the space between the first region 104 and the second region 124 in the optical connection region. In the fourth embodiment, a gap is created between the glass layer 106 of the first chip 100 and the second chip 120 by the thickness of the metal foil 113, but the provision of the refractive index matching layer 112 makes it possible to fill the gap.

[0043] Furthermore, by forming a recess in the third cladding layer 122 where the metal foil 113 is to be formed and then forming the metal foil 113, the surface of the third cladding layer 122 on which the metal foil 113 is formed can be made flat and step-free. By forming the metal foil 113 in a flat state on the surface of the third cladding layer 122 in this way, a structure can be achieved in which the glass layer 106 of the first chip 100 and the second chip 120 are in direct contact with each other without any gaps. With this configuration, there is no need to provide a refractive index matching layer or the like.

[0044] As described above, by arranging the first core 101 of the first optical waveguide and the second core 121 of the second optical waveguide close to each other and parallel to each other, light can be adiabatically coupled between the two optical waveguides, and light can be input and output even between optical waveguides made of different materials. By bonding the top or bottom surface of the chip rather than the end surface of the chip, the mounting speed can be improved, and the bonding area can be increased, thereby improving reliability. Thus, in the fourth embodiment, too, it is possible to reduce the cost of optical devices, such as those formed with a chip on which a planar lightwave circuit is formed and a chip on which silicon photonics is formed, without reducing reliability.

[0045] Fifth Embodiment Next, an optical connection structure according to a fifth embodiment will be described with reference to Fig. 5. Fig. 5 shows a cross section of a plane perpendicular to the waveguide direction, illustrating a part of the optical connection structure.

[0046] This optical connection structure includes a first chip 100 having a planar lightwave circuit formed thereon and a second chip 120 having silicon photonics formed thereon. The first chip 100 and the second chip 120 are arranged such that a first surface 100a of the first chip 100 faces a second surface 120a of the second chip 120. The first surface 100a and the second surface 120a are bonded together such that a first region 104 formed on the first surface 100a faces a second region 124 formed on the second surface 120a. The first surface 100a can be the top or bottom surface of the first chip 100. The second surface 120a can be the top or bottom surface of the second chip 120.

[0047] In the first region 104 of the first chip 100, the top surface of the first core 101 of the first optical waveguide constituting the planar lightwave circuit is exposed on the first surface 100a. The top surface of the first core 101 is exposed on the first surface 100a without the glass layer 106 (described later) being formed. A first cladding layer 102 and a second cladding layer 103 are formed around the first core 101 to form the first optical waveguide. The first optical waveguide constituting the planar lightwave circuit of the first chip 100 is made of, for example, silica-based glass. In the fifth embodiment, the first surface 100a of the first chip 100 is provided with a very thin glass layer 106. The glass layer 106 is formed using the well-known SOG process. The glass layer 106 can be formed to a thickness of, for example, 0.1 μm.

[0048] In the second region 124 of the second chip 120, the upper surface of a second core 121 made of Si of a second optical waveguide constituting silicon photonics is exposed on the second surface 120a. A third cladding layer 122 and a fourth cladding layer 123 are formed around the second core 121 to form the second optical waveguide. The third cladding layer 122 and the fourth cladding layer 123 are made of, for example, silicon oxide.

[0049] The first core 101 exposed at the first surface 100a in the first region 104 and the second core 121 exposed at the second surface 120a in the second region 124 are overlapped in the waveguiding direction and arranged parallel to each other. The second core 121 of the second optical waveguide is made thinner than the other regions, thereby reducing optical confinement.

[0050] Furthermore, in the fifth embodiment, a core-shaped Si layer 121a is provided in the second chip 120 in a bonding region other than the optical connection region where the first region 104 and the second region 124 face each other. The upper surface of the Si layer 121a is exposed on the second surface 120a. The Si layer 121a extends, for example, in the same direction as the second core 121 and is arranged parallel to the second core 121. In this example, two Si layers 121a are provided, one on each side of the second core 121. The Si layer 121a can be fabricated in the same process as the second core 121 during the process of fabricating silicon photonics for the second chip 120.

[0051] In the fifth embodiment, the first surface 100a and the second surface 120a are anodically bonded to the glass layer 106 and the Si layer 121a in a bonding region other than the optical connection region where the first region 104 and the second region 124 face each other.

[0052] Anodic bonding can be performed by bringing the glass layer 106 and the Si layer 121a into contact with each other and applying a DC voltage of several hundred volts between them, with the Si layer 121a acting as the anode. Anodic bonding allows the glass layer 106, made of a glass-based material, and the Si layer 121a to be bonded together without using an intervening material such as solder or adhesive.

[0053] According to the fifth embodiment, the surface of the third cladding layer 122 on which the Si layer 121a is formed is flat and has no steps, and a structure can be achieved in which the glass layer 106 of the first chip 100 and the second chip 120 are in direct contact with each other without any gaps. With this configuration, there is no need to provide a refractive index matching layer or the like.

[0054] As described above, by arranging the first core 101 of the first optical waveguide and the second core 121 of the second optical waveguide close to each other and parallel to each other, light can be adiabatically coupled between the two optical waveguides, and light can be input and output even between optical waveguides made of different materials. By bonding the top or bottom surface of the chip rather than the end surface of the chip, the mounting speed can be improved, and the bonding area can be increased, thereby improving reliability. Thus, in the fifth embodiment, too, it is possible to reduce the cost of optical devices, such as those formed with a chip on which a planar lightwave circuit is formed and a chip on which silicon photonics is formed, without reducing reliability.

[0055] Sixth Embodiment Next, an optical connection structure according to a sixth embodiment will be described with reference to Fig. 6. Fig. 6 shows a cross section of a plane perpendicular to the waveguide direction, illustrating a part of the optical connection structure.

[0056] This optical connection structure includes a first chip 100 having a planar lightwave circuit formed thereon and a second chip 120 having silicon photonics formed thereon. The first chip 100 and the second chip 120 are arranged such that a first surface 100a of the first chip 100 faces a second surface 120a of the second chip 120. The first surface 100a and the second surface 120a are bonded together such that a first region 104 formed on the first surface 100a faces a second region 124 formed on the second surface 120a. The first surface 100a can be the top or bottom surface of the first chip 100. The second surface 120a can be the top or bottom surface of the second chip 120.

[0057] In the first region 104 of the first chip 100, the top surface of a first core 101 of a first optical waveguide that constitutes the planar lightwave circuit is exposed on the first surface 100a. A first cladding layer 102 and a second cladding layer 103 are formed around the first core 101 to constitute the first optical waveguide. The first optical waveguide that constitutes the planar lightwave circuit of the first chip 100 is made of, for example, silica-based glass. The first cladding layer 102a is made of silica-based glass doped with B (boron) or P (phosphorus).

[0058] In the second region 124 of the second chip 120, the upper surface of a second core 121 made of Si of a second optical waveguide constituting silicon photonics is exposed on the second surface 120a. A third cladding layer 122 and a fourth cladding layer 123 are formed around the second core 121 to form the second optical waveguide. The third cladding layer 122 and the fourth cladding layer 123 are made of, for example, silicon oxide.

[0059] The first core 101 exposed at the first surface 100a in the first region 104 and the second core 121 exposed at the second surface 120a in the second region 124 are overlapped in the waveguiding direction and arranged parallel to each other. The second core 121 of the second optical waveguide is made thinner than the other regions, thereby reducing optical confinement.

[0060] Furthermore, in the sixth embodiment, a core-shaped Si layer 121a is provided in the second chip 120 in a bonding region other than the optical connection region where the first region 104 and the second region 124 face each other. The upper surface of the Si layer 121a is exposed on the second surface 120a. The Si layer 121a extends, for example, in the same direction as the second core 121 and is arranged parallel to the second core 121. In this example, two Si layers 121a are provided, one on each side of the second core 121. The Si layer 121a can be fabricated in the same process as the second core 121 during the process of fabricating silicon photonics for the second chip 120.

[0061] In the sixth embodiment, the first cladding layer 102a and the Si layer 121a are anodically bonded to the first surface 100a and the second surface 120a in a bonding region other than the optical connection region where the first region 104 and the second region 124 face each other.

[0062] Anodic bonding can be performed by bringing the first cladding layer 102a and the Si layer 121a into contact with each other and applying a DC voltage of several hundred volts between them, with the Si layer 121a acting as the anode. Anodic bonding allows the first cladding layer 102a, made of a glass-based material, and the Si layer 121a to be bonded together without using any intermediate material such as solder or adhesive.

[0063] According to the sixth embodiment, the surface of the third cladding layer 122 on which the Si layer 121a is formed is flat and has no steps, and a structure can be achieved in which the first chip 100 and the second chip 120 are in direct contact with each other without any gaps. With this configuration, there is no need to provide a refractive index matching layer or the like.

[0064] As described above, by arranging the first core 101 of the first optical waveguide and the second core 121 of the second optical waveguide close to each other and parallel to each other, light can be adiabatically coupled between the two optical waveguides, and light can be input and output even between optical waveguides made of different materials. By bonding on the top or bottom surface of the chip rather than on the end surface of the chip, the speed of mounting can be improved, and the increased bonding area can improve reliability. Thus, even in the sixth embodiment, it is possible to reduce the cost of optical devices, such as those formed on a chip with a planar lightwave circuit and a chip with silicon photonics, without reducing reliability.

[0065] As described above, according to an embodiment of the present invention, the first surface of the first chip and the second surface of the second chip are joined facing each other, and the first core exposed on the first surface of the first chip and the second core exposed on the second surface of the second chip are arranged to overlap in the waveguide direction, thereby making it possible to reduce the cost of the optical device without reducing reliability.

[0066] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0067] 100...first chip, 100a...first surface, 101...first core, 102...first cladding layer, 103...second cladding layer, 104...first region, 111...solder, 112...refractive index matching layer, 120...second chip, 120a...second surface, 121...second core, 122...third cladding layer, 123...fourth cladding layer, 124...second region.

Claims

1. An optical connection structure comprising a first chip on which a planar lightwave circuit is formed, and a second chip on which silicon photonics is formed, wherein one first surface of the first chip and one second surface of the second chip are bonded together with a first region formed on the first surface and a second region formed on the second surface facing each other, wherein a first core of a first optical waveguide constituting the planar lightwave circuit and exposed on the first surface in the first region, and a second core made of Si of a second optical waveguide constituting the silicon photonics and exposed on the second surface in the second region, are arranged to overlap in the waveguiding direction, and wherein the second core of the second optical waveguide is made thinner than other regions, thereby reducing optical confinement.

2. An optical connection structure according to claim 1, wherein the first surface and the second surface are solder-joined in a joining area other than the optical connection area where the first area and the second area face each other.

3. An optical connection structure according to claim 1, wherein the first surface and the second surface are anodically bonded in a bonding area other than the optical connection area where the first area and the second area face each other.

4. An optical connection structure according to claim 2 or 3, comprising a refractive index matching layer provided to fill the space between the first region and the second region of the optical connection region, for matching the refractive index between the first region and the second region.

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