System and method for glitch power estimation

Abstract

A computing system for glitch power estimation receives a circuit design describing an electronic device and waveform data. One or more waveforms corresponding to one or more critical points in the circuit design are extracted from the waveform data. For each connected component, a zero-delay simulation is performed to generate a zero-delay output waveform associated with at least one internal node of the connected component, and a delay aware output waveform reconstruction to generate a delayed output waveform associated with at least one internal node of the connected component. One or more glitch toggles in the delayed output waveform are identified based on a comparison between the zero-delay output waveform and the delayed output waveform. A glitch power associated with the connected component based on toggles identified as glitch in the delayed output waveform is computed, and a glitch power report file is generated based on the glitch power.

Description

SYSTEM AND METHOD FOR GLITCH POWER ESTIMATIONTECHNICAL FIELD

[0001] This application is related to electronic design automation and, more specifically, to a computing system and method for glitch power estimation.BACKGROUND

[0002] Designing and fabricating electronic systems involves multiple steps, collectively referred to as a "design flow." The steps of a design flow depend upon the type of electronic system to be manufactured, its complexity, the design team, and the fabricator or foundry responsible for manufacturing the electronic system from a design. Initially, a specification for a new electronic system transforms into a logical design, often referred to as a register transfer level (RTL) description of the electronic system. This logical design describes the electronic system in terms of both the exchange of signals between hardware registers and the logical operations performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as System Verilog or Very High-speed Integrated Circuit Hardware Design Language (VHDL).

[0003] The logic of the electronic system undergoes analysis to confirm accurate performance of the desired functions, a process referred to as "functional verification." Design verification tools perform functional verification operations, including simulating, emulating, and / or formally verifying the logical design. For example, when a design verification tool emulates the logical design, the design verification tool provides transactions or sets of test vectors, generated by an emulated test bench, to the emulated logical design. The design verification tools determine the response of the emulated logical design to the transactions or test vectors and verify, from that response, that the logical design describes circuitry that accurately performs the intended functions.

[0004] The logical design of the electronic system undergoes additional forms of analysis, such as power estimation, which analyzes waveform data generated during simulation or emulation to estimate power consumption by the electronic system described by the logical design. One type of power estimation is gate-level power computation. Gate-level power computation, typically conducted post-placement and routing on a timing clean netlist, faces significant challenges due to the introduction of glitches when using delay annotations. These glitches increase power consumption and require accurate measurement to mitigate their impact. Timing clean netlist comes later in the design cycle when taking measures toreduce the glitch power becomes impossible. In existing art, glitch power is computed based on zero-delay / RTL vectors that are available early in the design cycle but rely on clock references to identify glitches by categorizing toggles based on their timing relative to clock edges. This approach encounters difficulties due to the complexity of identifying the launch clock for combinational cells, influenced by factors such as multiple clocks, differing frequencies, out-of-phase clocks, and clock domain crossings. Additional challenges include determining whether to consider the rising edge or falling edge of clock as reference as there can be two types of launch flops: one triggered by rise edge and the other by fall edge. Also, accounting for logic driven directly by primary inputs without any clock is difficult. Without a valid clock reference, glitch toggle identification becomes erroneous and time-consuming due to the high activity of the clock signal. Furthermore, determining the correct clock edge type (rise edge-triggered or fall edge-triggered) associated with launch flop is complicated, and logic driven by primary inputs without any clock exacerbates the problem. These challenges render the identification process time-consuming and prone to errors, hindering the precise measurement and reduction of glitch power.SUMMARY

[0005] This application discloses a computing system for implementing a method for glitch power estimation. The computing system receives as input, a circuit design describing an electronic device, and waveform data generated during a functional verification of at least one connected component in the circuit design. Further, the computing system extracts, from the waveform data, one or more waveforms corresponding to one or more critical points in the circuit design, wherein the one or more waveforms act as inputs to the at least one connected component. For each of the connected components, the computing system performs based on the one or more waveforms extracted, a zero-delay simulation to generate a zero-delay output waveform associated with at least one internal node of the connected component, and a delay aware output waveform reconstruction to generate a delayed output waveform associated with at least one internal node of the connected component. The computing system further identifies one or more glitch toggles in the delayed output waveform based on a comparison between the zero-delay output waveform and the delayed output waveform. Further, glitch power associated with the connected component based on toggles identified as glitch toggles in the delayed output waveform is computed, and a glitch power report file is generated based on the computed glitch power associated with the connected component. Embodiments are described below in greater detail.BRIEF DESCRIPTION OF FIGURES

[0006] Figures 1 and 2 illustrate an example of a computer system of the type that may be used to implement various embodiments.

[0007] Figure 3 illustrates an exemplary glitch power estimation system to perform glitch power estimation according to various embodiments.

[0008] Figure 4 illustrates a flowchart showing an example implementation of a method for glitch power estimation according to various embodiments.

[0009] Figure 5 shows an example of a connected component;

[0010] Figure 6 is a graphical user interface showing the delayed output waveforms and the zero-delay output waveforms for the connected component of Figure 5;

[0011] Figure 7 shows another example of a connected component; and

[0012] Figure 8 is a graphical user interface showing the delayed output waveforms and the zero-delay output waveforms for the circuit connected component of Figure 7.DETAILED DESCRIPTIONIllustrative Operating Environment

[0013] Various examples may be implemented through the execution of software instructions by a computing device 101, such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions but is conventionally a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random-access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random-access memory (RAM) 111 may store software instructions for execution by the processing unit 105.

[0014] The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 115-123. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117, which can be magnetic and / or removable, a removable optical disk drive 119, and / or a flash memory card. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, apointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer, and speakers. With various examples of the computing device 101, one or more of the peripheral devices 115-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-123 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0015] With some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 for communicating with other devices making up a network. The network interface 115 can translate data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus is not discussed here in more detail.

[0016] The computing device 101 is illustrated as an example only, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device 101 illustrated in Figure 1, which include only a subset of the components illustrated in Figure 1, or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0017] With some implementations, the processor unit 105 can have more than one processor core. Accordingly, Figure 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments. As seen in this figure, the processor unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 20 IB includes a computing engine 203 A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203 A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting,multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR, and XOR, and retrieving data. Each computing engine 203 A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and / or instructions for execution.

[0018] Each processor core 201 A and 201B is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 105. With some processor cores 201 A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201 A and 20 IB communicate through the interconnect 207 with an input / output interface 209 and a memory controller 210. The input / output interface 209 provides a communication interface to the bus 113. Similarly, the memory controller 210 controls the exchange of information to the system memory 107. With some implementations, the processor unit 105 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201 A and 201B. It also should be appreciated that the description of the computer network illustrated in Figure 1 and Figure 2 is provided as an example only and is not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments.Glitch power estimation

[0019] Figure 3 illustrates an example system including a design verification system 310 and a glitch power estimation system 320 that may be implemented according to various embodiments. Figure 4 illustrates a flowchart showing an example implementation of glitch power estimation for a circuit design 301, according to various embodiments. Referring to Figures 3 and 4, the design verification system 310, for example, implemented with a computer network 101 described above with reference to Figure 1, can receive the circuit design 301 describing an electronic device as input. In some embodiments, the circuit design 301 can describe the electronic device both in terms of an exchange of data signals between components in the electronic device, such as hardware registers, flip-flops, combinational logic, or the like, and in terms of logical operations that can be performed on the data signals in the electronic device. The circuit design 301 can model the electronic device at a registertransfer level (RTL), for example, with code in a hardware description language (HDL), such as System Verilog, Very high speed integrated circuit Hardware Design Language (VHDL), System C, or the like.

[0020] The design verification system 310, in a block 401 of Figure 4, can perform functional verification of the circuit design 301 describing the electronic device. The design verification system 310 can utilize a test bench 302 Ito generate test stimulus during functional verification operations, such as clock signals, activation signals, power signals, control signals, data signals or the like. The test stimulus, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 being functionally verified by the design verification system 310. In some embodiments, the test bench 302 can be written in an object-oriented programming language, for example, System Verilog or the like, which, when executed during elaboration, can dynamically generate test bench components for verification of the circuit design. A methodology library, for example, a Universal Verification Methodology (UVM) library, an Open Verification Methodology (OVM) library, an Advanced Verification Methodology (AVM) library, a Verification Methodology Manual (VMM) library, or the like, can be utilized as a base for creating the test bench 302. The design verification system 310 can record output created during functional verification of the circuit design 301 with stimulus from the test bench 302, called waveform data 305. In the present disclosure, the waveform data 305 is generated from functional verification of one or more logic gates in the circuit design 301.

[0021] The glitch power estimation system 320, for example, implemented with a computer network 101 described above with reference to Figure 1, can receive the circuit design 301 describing the electronic device, a parasitic file 303, a technology library 304, and the waveform data 305 generated during functional verification of logic gates in the circuit design 301 by the design verification system 310. In some embodiments, the circuit design 301 can be specified as a gate-level netlist, which can be a synthesized version of the circuit design 301 specified in the register transfer level (RTL) format. The gate-level netlist can describe logic gates and their interconnections or nets in the electronic device. In other embodiments, the design verification system 310 can include a synthesis engine, which can synthesize the RTL version of the circuit design 301 into the gate-level netlist.

[0022] The parasitic file 303 can describe or model the electronic device described in the circuit design 301 as a group of electrically independent parasitic models, for example, in a Standard Parasitic Exchange Format (SPEF), or the like, generated by a parasitic extractiontool. The technology library 304, for example, specified in a Liberty format, can describe standard cells in terms of timing information, internal energy, leakage power, pin capacitances, area, functionality, operating conditions, or the like.

[0023] The glitch power estimation system 320 includes an input processing system 322 that, in a block 402 of Figure 4, receives the circuit design 301 describing an electronic device and the waveform data 305 generated during the functional verification of at least one connected component in the circuit design, as input. In the present embodiment, the circuit design 301 is received in the form of Register-Transfer Level (RTL) design created using a Hardware Description Language (HDL) such as VHDL or Verilog.

[0024] The glitch power estimation system 320 further includes a waveform extraction system 324 that, in a block 404 of Figure 4, extracts from the waveform data, one or more waveforms corresponding to one or more critical points in the circuit design, wherein the one or more waveforms act as inputs to the at least one connected component in the circuit design 301. In some embodiments, the waveform extraction system 324, in a block 403 of Figure 4, can implement a time-based iterator to read the waveform data 305. The time-based iterator can read the waveform data 305 according to a chronological order as opposed to on a signal - by-signal basis, which allows the waveform extraction system 324 to read the waveform data 305 chronologically for all signals, instead of once for each signal in the waveform data 305. In some embodiments, the one or more critical points include one or more of a primary port, a register, a memory, and a hard macro.

[0025] The at least one connected component comprises one or more combinational logic gates between the critical points. In particular, the connected component takes inputs from the critical points. The inputs may correspond to primary inputs via a primary port or outputs from a registers, memories and / or hard-macros. Figure 5 shows an example of a connected component 500 comprising an XOR gate 505 connected to three input registers 510, 515, and 520, and one output register 525. Each of the input registers 510, 515, and 520 and the output register 525 are connected to a clock CLK.

[0026] Referring back to Figures 3 and 4, the glitch power estimation system 320 further includes a zero-delay output waveform reconstruction system 326 that, in a block 406 of Figure 4, performs zero-delay simulation and delay aware waveform reconstruction for each of the connected components, based on waveform data 305 corresponding to the inputs of the connected component. The zero-delay simulation is performed to generate a zero-delayoutput waveform associated with at least one internal node of the connected component, based on the waveforms extracted from the waveform data.

[0027] The glitch power estimation system 320 further includes a delay aware waveform reconstruction system 328 that in block 408 of Figure 4, generates a delayed output waveform associated with at least one internal node of the connected component, based on the one or more waveforms extracted from the waveform data.

[0028] Figure 6 is a graphical user interface 600 showing the delayed output waveforms and the zero-delay output waveforms for the connected component of Figure 5. Referring to Figures 5 and 6, the waveforms XOR IP1 Delayed, XOR IP2 Delayed, XOR IP3 Delayed and XOR OUT Delayed represent the delayed output waveforms at the outputs of the registers 510, 515, 520, and 525 respectively between timestamps TO and T3. The waveforms XOR IP1 Zero-delay, XOR IP2 Zero-delay, XOR IP3 Zero-delay and XOR OUT Zero-delay represent the zero-delay waveforms at the outputs of the registers 510, 515, 520, and 525 respectively between timestamps TO and T3.

[0029] Referring back to Figures 3 and 4, the glitch power estimation system 320 further includes a glitch identification system 330, that at decision block 410 of Figure 4, identifies one or more glitch toggles in the delayed output waveform based on a comparison between the zero-delay output waveform and the delayed output waveform. In the present example, the state transitions can be identified from the delayed output waveform XOR OUT Delayed. The state transition may be from LOW (or 0) to HIGH (or 1) or vice versa. The glitch identification system identifies the one or more glitch toggles in the delayed output waveform based on a comparison between the zero-delay output waveform and the delayed output waveform. The comparison can be performed by firstly, determining, from the zero-delay output waveform, at least two consecutive timestamps at which zero-delay transitions occur. The term ‘zero-delay transitions,’ as used herein, refers to state changes (or toggles) specifically in the zero-delay waveform. The term ‘state transitions,’ as used in the present disclosure, refer to state changes present in the delayed output waveform. Further, state transitions present in the delayed output waveform, between the consecutive timestamps determined from the zero-delay output waveform, can be detected. Furthermore, each of the one or more state transitions can be classified into one of a glitch toggle and a functional (or non-glitch) toggle based on zero-delay transitions in the zero-delay output waveform. In the present example, the state transitions between two consecutive state transitions in the zerodelay output waveform, at T1 and T2, can be considered.

[0030] Among the one or more state transitions detected, a state transition that occurs at an onset of a peak pulse duration in the delayed output waveform and that matches a previous zero-delay transition can be classified as a functional toggle, and the remaining state transitions can be glitch toggles. In other words, each of the zero-delay transitions in the zerodelay output waveform correspond to a functional toggle in the delayed output waveform with the remaining state transitions being glitch toggles. In some embodiment, the glitch identification system 330 further validates a count of functional toggles in the delayed output waveform based on the number of zero-delay transitions in the zero-delay output waveform. More specifically, the number of zero-delay transitions in the zero-delay output waveform equals the number of functional toggles in the delayed output waveform. In the absence of zero-delay transitions in the zero-delay output waveform, each state transition in the delayed output waveform forms a glitch toggle, as explained with reference to the example of Figure 7 below.

[0031] Figure 7 shows an example of a connected component 700 comprising an AND gate 705 that is connected to two input registers 710 and 715, and an output register 720. The input from the register 715 is negated using a NOT gate 725. Each of the input registers 710 and 715 and the output register 720 are connected to a clock CLK.

[0032] Figure 8 is a graphical user interface 800 showing the delayed output waveforms and the zero-delay output waveforms for the circuit connected component of Figure 7. The waveforms AND IP1 Delayed, AND IP2 Delayed, INV OUT Delayed and AND OUT Delayed represent the delayed output waveforms at the outputs of 710, 715, 725, and 705 respectively between timestamps TO and Tl. The waveforms AND IP1 Zero-delay, AND IP2 Zero-delay, INV OUT Zero-delay and AND OUT Zero-delay represent the zero-delay waveforms at the outputs of the registers 710, 715, 725, and 705 respectively between timestamps TO and Tl.

[0033] Similar to the previous example, state transitions in the delayed output waveform of the AND gate, i.e., AND OUT Delayed are identified based on a comparison between AND OUT Delayed and AND OUT Zero-delay. As there are no state transitions in AND OUT Zero-delay, every state transition in AND OUT Delayed is considered as a glitch toggle.

[0034] Referring back to Figures 3 and 4, the glitch power estimation system 320 further includes a glitch-aware power computation system 332 that, at decision block 412 of Figure 4, estimates glitch power associated with the connected component based on the glitchtoggles in the delayed output waveform. For example, a count or area of the glitch toggles may be used to compute the glitch power. In an embodiment, the glitch power is computed based on the glitch toggles, a predefined WHEN condition, attributes such as internal energy and / or pin capacitance obtained from the liberty file, wire capacitance obtained from the SPEF, and a derate factor calculated based on pulse width and port rise (or fall) transition time, using one or more predefined mathematical formulae. The glitch-aware power computation system 332, at decision block 414 of Figure 4, generates a glitch power report file 334 based on the computed glitch power associated with the connected component. In an implementation, the glitch power report file 334 provides the glitch power classified into inertial glitch power and transport glitch power. The transport glitch power can be further segregated into internal power and switching power. The computation of the above- mentioned categories of glitch power is known to a person skilled in the art, and hence no additional explanation is provided thereto.

[0035] Embodiments of the glitch power estimation described above can identify glitchy and non-glitchy toggles without a clock reference, which can be challenging and error-prone in scenarios involving multiple clocks, out-of-phase clocks, gated clocks, divided clocks, or the absence of a clock. For a given connected component, the zero-delay output waveform serves as a reference to distinguish between glitchy and non-glitchy toggles during delay- aware simulation. Since zero-delay simulation is faster compared to delay-aware simulation, this approach does not introduce any substantial run-time overhead.

[0036] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0037] The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager or may be provided as a portable electronicdevice configured to interface with a networked system either locally or remotely via wireless transmission.

[0038] The processor memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I / O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine-readable" and may be readable by a processing device.

[0039] Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, minicomputer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

[0040] A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams.However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program, or operation with unclear boundaries. Conclusion

[0041] While the application describes specific examples of carrying out embodiments of the disclosure, those skilled in the art will appreciate that there are numerous variations and permutations of the above-described systems and techniques that fall within the spirit and scope of the disclosure as set forth in the appended claims. For example, while specific terminology has been employed above to refer to electronic design automation processes, it should be appreciated that various examples of the disclosure may be implemented using any desired combination of electronic design automation processes.

[0042] One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0043] Although the specification may refer to “an,” “one,” “another,” or “some” example(s) in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.List of References101 computing device103 computing unit105 processing unit107 system memory109 read-only memory (ROM)111 random-access memory (RAM)113 bus115-123 peripheral devices115 network interface117 hard disk drive119 optical disk drive121 input devices 123 output devices 201A and 201B processor coresA and 203B computing engine A and 205B memory cache interconnect input / output interface memory controller design verification system circuit design test bench parasitic file technology library waveform data glitch power estimation system input processing system waveform extraction system zero-delay output waveform reconstruction system delay aware waveform reconstruction system glitch identification system glitch-aware power computation system glitch power report file

Claims

CLAIMS1. A method comprising: receiving as input, by a computing system, a circuit design describing an electronic device and waveform data generated during a functional verification of at least one connected component in the circuit design; extracting from the waveform data, by the computing system, one or more waveforms corresponding to one or more critical points in the circuit design, wherein the one or more waveforms act as inputs to the at least one connected component; performing, by the computing system, for each connected component of the at least one connected component, based on the one or more waveforms extracted from the waveform data: a zero-delay simulation to generate a zero-delay output waveform associated with at least one internal node of the connected component; and a delay aware output waveform reconstruction to generate a delayed output waveform associated with at least one internal node of the connected component; identifying, by the computing system, one or more glitch toggles in the delayed output waveform based on a comparison between the zero-delay output waveform and the delayed output waveform; computing, by the computing system, a glitch power associated with the at least one connected component based on the glitch toggles in the delayed output waveform; and generating, by the computing system, a glitch power report file based on the computed glitch power associated with the at least one connected component.

2. The method of claim 1, further comprising: reading, by the computing system, the waveform data using a time-based iterator.

3. The method of claim 1, wherein the one or more critical points comprise a primary port, a register, a memory, a hard macro, or a combination thereof.

4. The method of claim 3, wherein the at least one connected component comprises one or more combinational logic gates between the one or more critical points.

5. The method of claim 1, wherein the identifying, by the computing system, of the one or more glitch toggles comprises: determining, from the zero-delay output waveform, at least two consecutive timestamps at which zero-delay transitions occur; detecting, in the delayed output waveform, state transitions present between the consecutive timestamps determined from the zero-delay output waveform; and classifying each state transition of the one or more state transitions into one of a glitch toggle and a functional toggle based on zero-delay transitions in the zero-delay output waveform.

6. The method of claim 5, wherein, among the one or more state transitions detected, a state transition that occurs at an onset of a peak pulse duration in the delayed output waveform and that matches a previous zero-delay transition is classified as a functional toggle, and the remaining state transitions are glitch toggles.

7. The method of claim 5, further comprising: validating, by the computing system, a count of functional toggles in the delayed output waveform based on a number of zero-delay transitions in the zero-delay output waveform.

8. A system comprising: a memory system configured to store computer-executable instructions; and a computing system configured to, in response to execution of the computerexecutable instructions: receive, as input, a circuit design describing an electronic device and waveform data generated during a functional verification of at least one connected component in the circuit design; extract, from the waveform data, one or more waveforms corresponding to one or more critical points in the circuit design, wherein the one or more waveforms act as inputs to the at least one connected component; perform, for each connected component of the at least one connected component, based on the one or more waveforms extracted from the waveform data:a zero-delay simulation to generate a zero-delay output waveform associated with at least one internal node of the connected component; and a delay aware output waveform reconstruction to generate a delayed output waveform associated with at least one internal node of the connected component; identify one or more glitch toggles in the delayed output waveform based on a comparison between the zero-delay output waveform and the delayed output waveform; compute a glitch power associated with the at least one connected component based on the glitch toggles in the delayed output waveform; and generate a glitch power report file based on the computed glitch power associated with the at least one connected component.

9. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: read the waveform data using a time-based iterator.

10. The system of claim 8, wherein the one or more critical points comprise a primary port, a register, a memory, a hard macro, or a combination thereof.

11. The system of claim 10, wherein the at least one connected component comprises one or more combinational logic gates between the one or more critical points.

12. The system of claim 8, wherein the identification of the one or more glitch toggles comprises: determining, from the zero-delay output waveform, at least two consecutive timestamps at which zero-delay transitions occur; detecting, in the delayed output waveform, state transitions present between the consecutive timestamps determined from the zero-delay output waveform; and classifying each of the one or more state transitions into one of a glitch toggle and a functional toggle based on zero-delay transitions in the zero-delay output waveform.

13. The system of claim 12, wherein, among the one or more state transitions detected, a state transition that occurs at an onset of a peak pulse duration in the delayed output waveform and that matches a previous zero-delay transition is classified as a functional toggle, and the remaining state transitions are glitch toggles.

14. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: validate a count of functional toggles in the delayed output waveform based on a number of zero-delay transitions in the zero-delay output waveform.

15. An apparatus comprising: at least one computer-readable memory device storing instructions configured to cause one or more processing devices to: receive, as input, circuit design describing an electronic device and waveform data generated during a functional verification of at least one connected component in the circuit design; extract, from the waveform data, one or more waveforms corresponding to one or more critical points in the circuit design, wherein the one or more waveforms act as inputs to the at least one connected component; perform, for each connected component of the at least one connected component, based on the one or more waveforms extracted from the waveform data: a zero-delay simulation to generate a zero-delay output waveform associated with at least one internal node of the connected component; and a delay aware output waveform reconstruction to generate a delayed output waveform associated with at least one internal node of the connected component; identify one or more glitch toggles in the delayed output waveform based on a comparison between the zero-delay output waveform and the delayed output waveform; compute a glitch power associated with the at least one connected component based on the glitch toggles in the delayed output waveform; andgenerate a glitch power report file based on the computed glitch power associated with the at least one connected component.

16. The apparatus of claim 15, wherein the instructions are further configured to cause the one or more processing devices to: perform operations further comprising reading the waveform data using a time-based iterator.

17. The apparatus of claim 15, wherein the one or more critical points comprise a primary port, a register, a memory, a hard macro, or a combination thereof.

18. The apparatus of claim 17, wherein the at least one connected component comprises one or more combinational logic gates between the critical points.

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