Display panel and display apparatus

Abstract

The embodiments of the present invention relate to the technical field of display. Provided are a display panel and a display apparatus, which are used to improve the brightness uniformity of the display panel. The display panel comprises a substrate, a data line located on one side of the substrate, and a pixel driving circuit. The pixel driving circuit comprises a driving transistor, a bias adjustment transistor and a first connection component, wherein a gate electrode of the driving transistor is electrically connected to a first node, a first electrode of the driving transistor is electrically connected to a second node, and a second electrode of the driving transistor is electrically connected to a third node; and the first connection component is electrically connected to the bias adjustment transistor and the second node. The display panel further comprises a first semiconductor layer and a first metal layer, wherein the first semiconductor layer and the first metal layer are sequentially stacked in a direction away from the substrate; the first semiconductor layer comprises a channel of the driving transistor and a channel of the bias adjustment transistor, and the first metal layer comprises the gate electrode of the driving transistor and a gate electrode of the bias adjustment transistor; and the first connection component is located on the first semiconductor layer.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202411244774.9, filed on September 5, 2024, and entitled "Display panel and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) is one of the hotspots in the current flat panel display research field. Compared with liquid crystal display, OLED has the advantages of low energy consumption, low production cost, self-luminous, wide viewing angle and fast response speed, and has begun to replace traditional Liquid Crystal Display (LCD) in the flat panel display field such as mobile phones, PDAs and digital cameras.

[0004] The pixel driving circuit in the OLED display panel provides the driving current required for the light emitting element to emit light and display. However, the current display panel has a visual display uneven (Mura) phenomenon in the display state, which affects the display quality.

[0005] SUMMARY

[0006] Therefore, the present application provides a display panel and a display device to improve the display uniformity of the display panel.

[0007] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0008] a substrate;

[0009] a data line and a pixel driving circuit located on one side of the substrate;

[0010] The pixel driving circuit comprises a driving transistor, a bias adjustment transistor and a first connecting component, the gate of the driving transistor is electrically connected with a first node, the first pole of the driving transistor is electrically connected with a second node, and the second pole of the driving transistor is electrically connected with a third node; the first connecting component is electrically connected with the bias adjustment transistor and the second node;

[0011] The display panel further comprises a first semiconductor layer and a first metal layer, which are sequentially stacked in a direction away from the substrate; the first semiconductor layer comprises the channel of the driving transistor and the channel of the bias adjustment transistor, and the first metal layer comprises the gate of the driving transistor and the gate of the bias adjustment transistor;

[0012] The first connecting component is located in the first semiconductor layer

[0013] In a second aspect, an embodiment of the present application provides a display device, comprising the display panel.

[0014] The display panel and the display device provided by the embodiment of the present application can set the data line on the side of the second metal layer away from the substrate by locating the first connecting component in the first semiconductor layer, for example, set the data line on the second source-drain layer with a larger distance from the first semiconductor layer, increase the distance between the first connecting component and the data line in the direction perpendicular to the plane where the substrate is located, and thus reduce the coupling capacitance between the first connecting component and the data line, weaken the signal change amount of the second node when the data voltage changes, and thus avoid the influence of the potential change of the second node on the potential of the first node through the driving transistor and the threshold compensation transistor, further avoid the influence on the luminous brightness of the light emitting element, and improve the brightness uniformity of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor for those skilled in the art.

[0016] FIG. 1 is a simplified schematic diagram of a display panel provided by an embodiment of the present application;

[0017] FIG. 2 is a circuit schematic diagram of a sub-pixel in FIG. 1;

[0018] FIG. 3 is a working timing diagram of a pixel driving circuit provided by an embodiment of the present application;

[0019] FIG. 4 is a wiring schematic diagram of a pixel driving circuit provided by an embodiment of the present application;

[0020] FIG. 5 is a cross-sectional schematic diagram of a display panel provided by an embodiment of the present application;

[0021] FIG. 6 is a top view schematic diagram of a first semiconductor layer provided by an embodiment of the present application;

[0022] FIG. 7 is a top view schematic diagram of a first metal layer provided by an embodiment of the present application;

[0023] FIG. 8 is a top view schematic diagram of a second metal layer provided by an embodiment of the present application;

[0024] FIG. 9 is a top view schematic diagram of a second semiconductor layer provided by an embodiment of the present application;

[0025] FIG. 10 is a top view of a third metal layer according to an embodiment of the present application;

[0026] FIG. 11 is a top view of a first source-drain layer according to an embodiment of the present application;

[0027] FIG. 12 is a top view of a second source-drain layer according to an embodiment of the present application;

[0028] FIG. 13 is an enlarged view of a light-emitting control signal line according to an embodiment of the present application;

[0029] FIG. 14 is an enlarged view of another light-emitting control signal line according to an embodiment of the present application;

[0030] FIG. 15 is a top view of another first semiconductor layer according to an embodiment of the present application;

[0031] FIG. 16 is a simplified schematic view of another display panel according to an embodiment of the present application;

[0032] FIG. 17 is a wiring schematic view of another pixel driving circuit according to an embodiment of the present application;

[0033] FIG. 18 is a top view of another first source-drain layer according to an embodiment of the present application;

[0034] FIG. 19 is a top view of another second source-drain layer according to an embodiment of the present application;

[0035] FIG. 20 is a simplified schematic view of another display panel according to an embodiment of the present application;

[0036] FIG. 21 is a simplified schematic view of another display panel according to an embodiment of the present application;

[0037] FIG. 22 is a simplified schematic view of another display panel according to an embodiment of the present application;

[0038] FIG. 23 is a simplified schematic view of another display panel according to an embodiment of the present application;

[0039] FIG. 24 is a simplified schematic view of another display panel according to an embodiment of the present application;

[0040] FIG. 25 is a wiring schematic view of another pixel driving circuit according to an embodiment of the present application;

[0041] FIG. 26 is a schematic view of a second electrode plate and a shielding member according to an embodiment of the present application;

[0042] FIG. 27 is a wiring schematic view of another pixel driving circuit according to an embodiment of the present application;

[0043] Fig. 28 is a schematic view of the shielding component and the second sub bias adjustment signal line in Fig. 27;

[0044] Fig. 29 is a schematic wiring diagram of another pixel driving circuit provided by an embodiment of the present application,

[0045] Fig. 30 is a schematic view of the shielding component and the fourth sub reset signal line in Fig. 29;

[0046] Fig. 31 is a schematic view of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the drawings.

[0048] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0049] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0050] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0051] An embodiment of the present application provides a display panel, as shown in Fig. 1, which is a simplified schematic diagram of a display panel provided by an embodiment of the present application. The display panel 100 includes a substrate 1 and a plurality of sub-pixels 2 located on one side of the substrate 1. The display panel 100 includes a display area AA, and the sub-pixels 2 are located in the display area AA.

[0052] As shown in FIG. 2, the sub-pixel 2 includes a pixel driving circuit 21 and a light emitting element 22 electrically connected. The light emitting element 22 includes any one of an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), and a micro light emitting diode (Micro-LED), for example.

[0053] As shown in FIG. 2, the pixel driving circuit 21 includes a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, a first reset transistor T5, a second light emitting control transistor T6, a second reset transistor T7, and a bias adjustment transistor T8.

[0054] As shown in FIG. 2, the display panel 100 further includes a data line DATA, a first power voltage line PVDD, a bias adjustment signal line DVH, a first reset signal line REF1, a second reset signal line REF2, a first scan control signal line SP*, a second scan control signal line S1N, a third scan control signal line S2N, a light emitting control signal line EM, and a fourth scan control signal line SP.

[0055] The first power voltage line PVDD transmits a first power voltage Vpvdd, the data line DATA transmits a data voltage Vdata, the first reset signal line REF1 transmits a first reset voltage Vref1, the second reset signal line REF2 transmits a second reset voltage Vref2, and the bias adjustment signal line DVH transmits a bias adjustment voltage Vdvh.

[0056] The gate of the first light emitting control transistor T1 is electrically connected to the light emitting control signal line EM, the first electrode is electrically connected to the first power voltage line PVDD, and the second electrode is electrically connected to the second node N2.

[0057] The gate of the data writing transistor T2 is electrically connected to the fourth scan control signal line SP, the first electrode is electrically connected to the data line DATA, and the second electrode is electrically connected to the second node N2.

[0058] The gate of the driving transistor T3 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3.

[0059] The gate of the threshold compensation transistor T4 is electrically connected to the third scan control signal line S2N, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the first node N1.

[0060] The gate of the first reset transistor T5 is electrically connected with the second scan control signal line S1N, the first electrode is electrically connected with the first reset signal line REF1, and the second electrode is electrically connected with the first node N1.

[0061] The gate of the second light emitting control transistor T6 is electrically connected with the light emitting control signal line EM, the first electrode is electrically connected with the third node N3, and the second electrode is electrically connected with the light emitting element 22.

[0062] The gate of the second reset transistor T7 is electrically connected with the first scan control signal line SP*, the first electrode is electrically connected with the second reset signal line REF2, and the second electrode is electrically connected with the light emitting element 22.

[0063] The gate of the bias adjustment transistor T8 is electrically connected with the first scan control signal line SP*, the first electrode is electrically connected with the bias adjustment signal line DVH, and the second electrode is electrically connected with the second node N2.

[0064] As shown in FIG. 2, the pixel driving circuit 21 further comprises a storage capacitor Cst, the first plate of the storage capacitor Cst is electrically connected with the first node N1, and the second plate is electrically connected with the first power voltage line PVDD.

[0065] As shown in FIG. 3, which is a working timing diagram of a pixel driving circuit provided by the embodiment of the present application, the driving period of the pixel driving circuit 21 comprises a first bias adjustment stage t11, a reset stage t2, a data writing and threshold compensation stage t3, a second bias adjustment stage t12, and a light emitting stage t4. Among them,

[0066] In the first bias adjustment stage t11, the first scan control signal line SP* provides an enable level, the bias adjustment transistor T8 is turned on, and the bias adjustment voltage Vdvh provided by the bias adjustment signal line DVH is written to the second node N2, so as to refresh the potential of the first electrode of the driving transistor T3, and make the device characteristics of the driving transistor T3 be set to a determined initial state, thereby eliminating the influence of the data voltage written in the last frame on the device characteristics of the driving transistor T3.

[0067] In the reset stage t2, the second scan control signal line S1N provides an enable level, the first reset transistor T5 is turned on, and the first reset voltage Vref1 transmitted by the first reset signal line REF1 resets the potential of the first node N1 through the first reset transistor T5.

[0068] In the data writing and threshold compensation stage t3, the fourth scan control signal line SP provides an enable level, the data writing transistor T2 is turned on, the third scan control signal line S2N provides an enable level, the threshold compensation transistor T4 is turned on, and the data voltage Vdata transmitted by the data line DATA is written into the first node N1 through the data writing transistor T2, the driving transistor T3 and the threshold compensation transistor T4 until the driving transistor T3 is turned off, at which time the voltage difference between the gate and the source of the driving transistor T3 is its threshold voltage, so that the threshold voltage of the driving transistor T3 is compensated.

[0069] In the second bias adjustment stage t12, the first scan control signal line SP* provides an enable level, the bias adjustment transistor T8 is turned on, and the bias adjustment voltage Vdvh provided by the bias adjustment signal line DVH is written into the second node N2 to refresh the potential of the first electrode of the driving transistor T3. In the related art, after the data voltage is written into the gate of the driving transistor T3, i.e. the first node N1, the voltage of the first electrode of the driving transistor T3, i.e. the second node N2, will be discharged, which causes a large potential shift of the first electrode of the driving transistor T3. The embodiment of the present application sets the second bias adjustment stage t12, controls the bias adjustment transistor T8 to be turned on in the second bias adjustment stage t12, and writes the bias adjustment voltage Vdvh into the first electrode of the driving transistor T3 by using the bias adjustment transistor T8, wherein the bias adjustment voltage Vdvh is related to the data voltage Vdata, which can make the bias state of the driving transistor T3 consistent with the bias state when the data voltage is just written, can improve the stability of the working state of the driving transistor T3, improve the low-frequency flicker problem, and improve the display effect of the display panel 100.

[0070] In the second bias adjustment stage t12, the first scan control signal line SP* provides an enable level, the second reset transistor T7 is turned on, and the second reset voltage Vref2 provided by the second reset signal line REF2 is written into the anode of the light emitting element 22 to reset the potential of the anode of the light emitting element 22.

[0071] In the light emitting stage t3, the light emitting control signal line EM provides an enable level, the first light emitting control transistor T1 and the second light emitting control transistor T6 are turned on, and the light emitting element 22 emits light.

[0072] For example, the first light emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light emitting control transistor T6 and the second reset transistor T7 can be set as low temperature poly silicon (LTPS) transistors.

[0073] Optionally, at least one of the first reset transistor T5 and the threshold compensation transistor T4 can be configured as an oxide transistor in the embodiments of the present application. For example, the oxide transistor can include Indium Gallium Zinc Oxide (IGZO).

[0074] The oxide transistor has the advantages of small leakage current, and the low temperature polycrystalline silicon transistor has the advantages of high switching speed, high carrier mobility and small power. The display panel technology of LTPO (Low Temperature Polycrystalline Oxide) combining LTPO and IGZO can make the display panel not only have the advantages of high resolution, high response speed, high brightness and high aperture ratio of the LTPS display panel, but also have the advantage of small leakage current of IGZO, so as to improve the potential stability of the first node N1 and improve the display effect, which is beneficial to improve the display effect at low frequency. FIG. 2 shows that the first light-emitting control transistor T1, the data write transistor T2, the driving transistor T3, the second light-emitting control transistor T6 and the second reset transistor T7 are all configured as low temperature polycrystalline silicon transistors, and the first reset transistor T5 and the threshold compensation transistor T4 are both configured as oxide transistors.

[0075] For example, the first light-emitting control transistor T1, the data write transistor T2, the driving transistor T3, the second light-emitting control transistor T6 and the reset transistor T7 can be P-type transistors, and the first reset transistor T5 and the threshold compensation transistor T4 can be N-type transistors. The P-type transistor is turned on when the voltage difference between the gate and the source is less than the threshold voltage, which can also be understood as low-level conduction, i.e., the enable level is low. The N-type transistor is turned on when the voltage difference between the gate and the source is greater than the threshold voltage, which can also be understood as high-level conduction, i.e., the enable level is high.

[0076] In combination with FIG. 2 and FIG. 4, FIG. 4 is a wiring schematic diagram of a pixel driving circuit provided by the embodiments of the present application, in which two pixel driving circuits 21 arranged along a first direction h21 are taken as an example. The pixel driving circuit 21 further includes a first connecting component 30 electrically connected to the bias adjustment transistor T8 and the second node N2.

[0077] As shown in FIG. 4 and FIG. 5, FIG. 5 is a cross-sectional schematic diagram of a display panel provided by the embodiments of the present application. The display panel 100 further includes a plurality of conductive film layers including a first semiconductor layer SC1, a first metal layer M1 and a second metal layer MC. The first semiconductor layer SC1, the first metal layer M1 and the second metal layer MC are sequentially stacked in a direction away from the substrate 1, and adjacent two conductive film layers are separated by an insulating layer.

[0078] As shown in FIG. 4 and FIG. 6, FIG. 6 is a top view of a first semiconductor layer according to an embodiment of the present application, which shows the area where two pixel driving circuit rows and four pixel driving circuit columns are located, a pixel driving circuit row includes a plurality of pixel driving circuits 21 arranged along a first direction h21, and a pixel driving circuit column includes a plurality of pixel driving circuits 21 arranged along a second direction h22. The first semiconductor layer SC1 includes at least a channel T10 of a first light emitting control transistor T1, a channel T20 of a data writing transistor T2, a channel T30 of a driving transistor T3, a channel T60 of a second light emitting control transistor T6, a channel T70 of a second reset transistor T7, and a channel T80 of a bias adjusting transistor T8.

[0079] Optionally, the first semiconductor layer SC1 includes silicon material, and the silicon material includes amorphous silicon or polycrystalline silicon, and the polycrystalline silicon can include low-temperature polycrystalline silicon.

[0080] As shown in FIG. 4 and FIG. 7, FIG. 7 is a top view of a first metal layer according to an embodiment of the present application, which shows the area where two pixel driving circuit rows and four pixel driving circuit columns are located, a pixel driving circuit row includes a plurality of pixel driving circuits 21 arranged along a first direction h21, and a pixel driving circuit column includes a plurality of pixel driving circuits 21 arranged along a second direction h22. The first metal layer M1 includes a first plate C1 of a storage capacitor Cst, a gate G3 of the driving transistor T3, and a gate G8 of the bias adjusting transistor T8. In a direction h1 perpendicular to the plane where the substrate 1 is located, the first plate C1 of the storage capacitor Cst is located between the substrate 1 and a second plate C2, and the gate G3 of the driving transistor T3 overlaps with the channel of the driving transistor T3, and the gate G8 of the bias adjusting transistor T8 overlaps with the channel T80 of the bias adjusting transistor T8. Among them, the part of the first plate C1 of the storage capacitor Cst overlapping with the channel T30 of the driving transistor T3 is multiplexed as the gate G3 of the driving transistor T3.

[0081] Optionally, the first conductive layer M1 can include an alloy composed of one or more materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and can be formed as a single layer or a multi-layer structure.

[0082] In combination with FIG. 4 and FIG. 8, FIG. 8 is a top view of a second metal layer according to an embodiment of the present application, which shows the area where two pixel driving circuit rows and four pixel driving circuit columns are located, the pixel driving circuit row includes a plurality of pixel driving circuits 21 arranged along a first direction h21, the pixel driving circuit column includes a plurality of pixel driving circuits 21 arranged along a second direction h22, and the second metal layer MC includes a second plate C2 of a storage capacitor Cst. The second plate C2 and the first plate C1 described above at least partially overlap along a direction h1 perpendicular to the plane where the substrate 1 is located.

[0083] For example, the second metal layer MC can include an alloy composed of one or more materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and can be formed as a single layer or a multi-layer structure.

[0084] For example, the first reset transistor T5 can include an oxide transistor according to an embodiment of the present application. When the first reset transistor T5 includes an oxide transistor, the first reset transistor T5 can be optionally configured as a top-bottom double-gate transistor according to an embodiment of the present application. In the embodiment of the present application, as shown in FIG. 5, the conductive film layer further includes a second semiconductor layer SC2 on the side of the second metal layer MC away from the substrate 1, and a third metal layer MG on the side of the second semiconductor layer SC2 away from the substrate 1. For example, in combination with FIG. 4, FIG. 5, FIG. 9, and FIG. 10, FIG. 9 is a top view of a second semiconductor layer according to an embodiment of the present application, and FIG. 10 is a top view of a third metal layer according to an embodiment of the present application, which shows the area where two pixel driving circuit rows and four pixel driving circuit columns are located, the pixel driving circuit row includes a plurality of pixel driving circuits 21 arranged along a first direction h21, the pixel driving circuit column includes a plurality of pixel driving circuits 21 arranged along a second direction h22, and the second semiconductor layer SC2 includes a channel T50 of the first reset transistor T5.

[0085] Optionally, the second semiconductor layer SC2 includes an oxide semiconductor such as IGZO.

[0086] For example, as shown in FIG. 8, the bottom gate G51 of the first reset transistor T5 can also be provided in the second metal layer MC according to an embodiment of the present application.

[0087] As shown in FIG. 10, the embodiment of the present application can arrange the top gate G52 of the first reset transistor T5 in the third metal layer MG, and the channel T50 of the first reset transistor T5 at least partially overlaps the bottom gate G51 and the top gate G52 of the first reset transistor T5 in the direction h1 perpendicular to the plane where the substrate 1 is located.

[0088] As shown in FIG. 4, the display panel 100 further includes a second scan control signal line S1N, the second scan control signal line S1N includes a fourth part S1N1 and a fifth part S1N2, the fourth part S1N1 overlaps the channel T50 of the first reset transistor T5 in the direction h1 perpendicular to the plane where the substrate 1 is located, and the fifth part S1N2 does not overlap the channel T50 of the first reset transistor T5; in the embodiment of the present application, the fourth part S1N1 includes a third sub-part S1N11 and a fourth sub-part S1N12 which are arranged in layers and electrically connected to each other, wherein the third sub-part S1N11 is located on the side of the second semiconductor layer SC2 close to the substrate 1, and the fourth sub-part S1N12 is located on the side of the second semiconductor layer SC2 away from the substrate 1. The third sub-part S1N11 can be reused as the bottom gate G51 of the first reset transistor T5, and the fourth sub-part S1N12 can be reused as the top gate G52 of the first reset transistor T5, based on the arrangement, the control effect of the turn-on and turn-off of the first reset transistor T5 can be more stable.

[0089] For example, as shown in FIG. 4 and FIG. 8, the embodiment of the present application can arrange the third sub-part S1N11 in the second metal layer MC. As shown in FIG. 4 and FIG. 10, the embodiment of the present application can arrange the fourth sub-part S1N12 in the third metal layer MG.

[0090] Optionally, the embodiment of the present application can arrange the fifth part S1N2 and the fourth sub-part S1N12 in the same layer, and FIG. 10 takes the arrangement of the two in the third metal layer MG as an example.

[0091] For example, the third metal layer MG can include an alloy composed of one or more materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), vanadium (V), and can be formed as a single layer or a multi-layer structure.

[0092] Optionally, the embodiment of the present application can also arrange the threshold compensation transistor T4 to include an oxide transistor. When the threshold compensation transistor T4 includes an oxide transistor, optionally, the embodiment of the present application can arrange the threshold compensation transistor T4 as a top-bottom double-gate transistor.

[0093] As shown in Fig. 9, the second semiconductor layer SC2 includes a channel T40 of the threshold compensation transistor T4.

[0094] As shown in Fig. 8, the second metal layer MC can be used to set a bottom gate G41 of the threshold compensation transistor T4. As shown in Fig. 10, the third metal layer MG can be used to set a top gate G42 of the threshold compensation transistor T4. The channel T40 of the threshold compensation transistor T4 at least partially overlaps the bottom gate G41 and the top gate G42 of the threshold compensation transistor T4 along a direction h1 perpendicular to a plane in which the substrate 1 is located.

[0095] As shown in Fig. 4, the display panel 100 further includes a third scan control signal line S2N. The third scan control signal line S2N includes a sixth portion S2N1 and a seventh portion S2N2. The sixth portion S2N1 overlaps the channel T40 of the threshold compensation transistor T4 along the direction h1 perpendicular to the plane in which the substrate 1 is located, and the seventh portion S2N2 does not overlap the channel T40 of the threshold compensation transistor T4. The sixth portion S2N1 includes a fifth sub-portion S2N11 and a sixth sub-portion S2N12 which are stacked and electrically connected to each other. The fifth sub-portion S2N11 is located on a side of the second semiconductor layer SC2 close to the substrate 1, and the sixth sub-portion S2N12 is located on a side of the second semiconductor layer SC2 away from the substrate 1. The fifth sub-portion S2N11 can be used as the bottom gate G41 of the threshold compensation transistor T4, and the sixth sub-portion S2N12 can be used as the top gate G42 of the threshold compensation transistor T4. In this way, the control effect of turning on and turning off the threshold compensation transistor T4 can be more stable.

[0096] As shown in Fig. 4 and Fig. 8, the fifth sub-portion S2N11 can be located on the second metal layer MC. As shown in Fig. 4 and Fig. 10, the sixth sub-portion S2N12 can be located on the third metal layer MG.

[0097] Optionally, the sixth sub-portion S2N12 and the seventh portion S2N2 can be located on the same layer. As shown in Fig. 10, the sixth sub-portion S2N12 and the seventh portion S2N2 are located on the third metal layer MG.

[0098] Optionally, as shown in Fig. 9, the channel T50 of the first reset transistor T5 and the channel T40 of the threshold compensation transistor T4 are arranged along the second direction h22, and both of them extend along the second direction h22.

[0099] As shown in Fig. 5, the display panel further includes a first source-drain layer M2. The first source-drain layer M2 is located on a side of the second metal layer MC away from the substrate 1. As shown in Fig. 5, when the display panel includes a third metal layer MG, the first source-drain layer M2 is located on a side of the third metal layer MG away from the substrate 1.

[0100] For example, the first source-drain layer M2 can be formed of an alloy including one or more of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and can be formed as a single layer or a multi-layer structure. For example, the first source-drain layer M2 can be formed as a three-layer structure including Ti / Al / Ti to reduce the resistance of the trace provided on the first source-drain layer M2.

[0101] Optionally, as shown in FIG. 5, the display panel 100 further includes a second source-drain layer M3 located on the side of the first source-drain layer M2 away from the substrate 1. In combination with FIG. 5 and FIG. 12, which is a top view of the second source-drain layer according to an embodiment of the present application, the data line DATA can be provided on the second source-drain layer M3 according to an embodiment of the present application.

[0102] For example, the second source-drain layer M3 can be formed of an alloy including one or more of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and can be formed as a single layer or a multi-layer structure. For example, the second source-drain layer M3 can be formed as a three-layer structure including Ti / Al / Ti to reduce the resistance of the trace provided on the second source-drain layer M3.

[0103] In an embodiment of the present application, the first connecting component 30 is located on the side of the second metal layer MC close to the substrate 1, and the data line DATA is located on the side of the second metal layer MC away from the substrate 1. For example, as shown in FIG. 6, the first connecting component 30 can be provided on the first semiconductor layer SC1 according to an embodiment of the present application, and as shown in FIG. 12, the data line DATA can be provided on the second source-drain layer M3 according to an embodiment of the present application.

[0104] When the charging of the first node N1 is completed and the data voltage provided by the data line DATA changes, if the coupling capacitance between the data line DATA and the first connecting component 30 is large, the voltage change on the data line DATA will affect the potential on the first connecting component 30 through coupling. Since the first connecting component 30 is electrically connected to the second node N2, the signal change on the first connecting component 30 will affect the potential of the second node N2.

[0105] When the pixel driving circuit 21 is working, as shown in FIG. 3, after the fourth scan control signal line SP switches from the enable level to the non-enable level, since the threshold compensation transistor T4 is still in the on state under the action of the third scan control signal line S2N, if the potential of the second node N2 changes, the potential change of the second node N2 will be written into the first node N1 through the driving transistor T3 and the threshold compensation transistor T4, and affect the on state of the driving transistor T3. For example, in the light emitting stage, when the first light emitting control transistor T1 and the second light emitting control transistor T6 are in the on state, the potential change of the first node N1 may cause the driving transistor T3, which should be in the off state, to open, causing the light emitting element 22, which should not emit light, to emit light, and unnecessary light emitting phenomenon occurs. For example, when writing black to a local area of the display panel, there will be bright lines or dark lines at the edge of the area, affecting the display effect of the display panel.

[0106] In the embodiment of the present application, by locating the first connecting component 30 in the first semiconductor layer SC1, the data line DATA can be arranged on the side of the second metal layer MC far from the substrate 1, for example, as shown in FIG. 5, the data line DATA is arranged in the second source-drain layer M3 which has a large distance from the first semiconductor layer SC1, the distance between the first connecting component 30 and the data line DATA in the direction h1 perpendicular to the plane where the substrate 1 is located can be increased, so that the coupling capacitance between the first connecting component 30 and the data line DATA can be reduced. When the data voltage transmitted by the data line DATA changes, the signal change amount of the second node N2 can be reduced, so that the potential change of the second node N2 can not affect the potential change of the first node N1 through the driving transistor T3 and the threshold compensation transistor T4, and further affect the light emitting brightness of the light emitting element 22, thereby improving the brightness uniformity of the display panel.

[0107] It should be noted that FIG. 2 is only an example of the pixel driving circuit 21 arranged in the "8T1C" structure including 8 transistors and 1 storage capacitor, wherein "T" represents a transistor and "C" represents a storage capacitor. Those skilled in the art can also arrange the pixel driving circuit 21 in other structures according to different design requirements, and the specific design method of the pixel driving circuit 21 is not limited in the embodiment of the present application.

[0108] Optionally, as shown in FIG. 4, in the embodiment of the present application, the light emitting control signal line EM is arranged on the connection path of the bias adjustment transistor T8 and the driving transistor T3, that is, along the direction h1 perpendicular to the plane where the substrate 1 is located, the first connecting component 30 will overlap the light emitting control signal line EM, based on this arrangement, the area of the pixel driving circuit 21 can be compressed, which is beneficial to improve the resolution of the display panel 100.

[0109] As shown in FIG. 4 and FIG. 13, FIG. 13 is an enlarged schematic view of the light emitting control signal line EM according to an embodiment of the present application. The light emitting control signal line EM extends along a first direction h21, and includes a first portion EM1 and a second portion EM2 electrically connected. Along a direction h1 perpendicular to the plane on which the substrate 1 lies, the first portion EM1 and the channel T10 (not shown in FIG. 13) of the first light emitting control transistor T1 overlap, and the second portion EM2 and the first connecting component 30 (not shown in FIG. 13) overlap. Moreover, the first portion EM1 and the first connecting component 30 (not shown in FIG. 13) do not overlap, and the second portion EM2 and the channel T10 (not shown in FIG. 13) of the first light emitting control transistor T1 do not overlap. In the embodiment of the present application, the first portion EM1 is multiplexed as the gate G1 of the first light emitting control transistor T1.

[0110] As shown in FIG. 13, the first portion EM1 includes a first sub-portion EM11 and a second sub-portion EM12 stacked. Along the direction h1 perpendicular to the plane on which the substrate 1 lies, both the first sub-portion EM11 and the second sub-portion EM12 overlap the channel T10 of the first light emitting control transistor T1. The first sub-portion EM11 and the second sub-portion EM12 are electrically connected. For example, the first sub-portion EM11 and the second sub-portion EM12 are electrically connected through a via K penetrating an insulating layer between them.

[0111] In the embodiment of the present application, as shown in FIG. 7 and FIG. 13, the first sub-portion EM11 can be disposed on the first metal layer M1, and the second portion EM2 can be disposed on the side of the first metal layer M1 away from the substrate 1.

[0112] In the embodiment of the present application, by disposing the second portion EM2 on the side of the first metal layer M1 away from the substrate 1, compared with disposing the second portion EM2 on the side of the first metal layer M1 close to the first semiconductor layer SC1, the distance between the second portion EM2 and the first connecting component 30 can be increased. On the one hand, the second portion EM2 and the first connecting component 30 on the first semiconductor layer SC1 do not overlap to form a thin film transistor device. On the other hand, the coupling capacitance between the first connecting component 30 and the second portion EM2 can be reduced, so that the high-frequency varying signal on the light emitting control signal line EM can not interfere with the potential on the first connecting component 30 electrically connected to the second node N2.

[0113] As shown in FIG. 10 and FIG. 13, the second portion EM2 can be located in the third metal layer MG in the embodiment of the present application, so as to increase the distance between the second portion EM2 and the first connecting component 30, avoid the second portion EM2 and the first connecting component 30 from overlapping to form a thin film transistor device, and reduce the interference of the high frequency changed signal on the light emitting control signal line EM to the potential on the first connecting component 30 electrically connected to the second node N2.

[0114] Alternatively, as shown in FIG. 14, which is another enlarged schematic view of the light emitting control signal line provided by the embodiment of the present application, the second portion EM2 can be located in the second metal layer MC in the embodiment of the present application.

[0115] In the embodiment of the present application, the second sub-portion EM12 can serve as a connecting component for connecting the first sub-portion EM11 and the second portion EM2 located in different film layers. As an example, the second sub-portion EM12 and the second portion EM2 can be arranged in the same layer in the embodiment of the present application, i.e., the whole including the second sub-portion EM12 and the second portion EM2 is arranged as a line segment extending along the first direction h21, so as to reduce the number of film layers of the light emitting control signal line EM and thin the thickness of the display panel 100. As an example, as shown in FIG. 10 and FIG. 13, the second sub-portion EM12 and the second portion EM2 are arranged in the same layer in the third metal layer MG as an example. FIG. 14 takes the second sub-portion EM12 and the second portion EM2 arranged in the same layer in the second metal layer MC as an example.

[0116] As shown in FIG. 10, FIG. 13 and FIG. 14, the light emitting control signal line EM further includes a third portion EM3, which does not overlap with the channel T10 of the first light emitting control transistor T1 and the first connecting component 30 along the direction h1 perpendicular to the plane where the substrate 1 is located. In the embodiment of the present application, the third portion EM3 is arranged in the same layer or different layer with the second portion EM2.

[0117] FIG. 10 and FIG. 13 take the third portion EM3 and the second portion EM2 arranged in the same layer in the third metal layer MG as an example. FIG. 14 takes the third portion EM3 and the second portion EM2 arranged in the same layer in the second metal layer MC as an example. The third portion EM3 and the second portion EM2 arranged in the same layer can be formed by using the same material in the same patterning process, so as to simplify the manufacturing process of the display panel. As shown in FIG. 10, FIG. 13 and FIG. 14, the third portion EM3 and the second portion EM2 can be connected to each other, and when they are arranged in the same layer, no interface can exist between them, i.e., they can be regarded as an integral structure.

[0118] As shown in FIG. 10, FIG. 13 and FIG. 14, the light emitting control signal line EM further comprises a fourth portion EM4, which overlaps with the channel T60 of the second light emitting control transistor T6 in the direction h1 perpendicular to the plane where the substrate 1 is located, and the fourth portion EM4 is multiplexed as the gate G6 of the second light emitting control transistor T6. As shown in FIG. 7, FIG. 10, FIG. 13 and FIG. 14, the fourth portion EM4 comprises two portions which are arranged in a stack, and the two portions are electrically connected through a via K passing through the insulating layer between the two portions. Optionally, as shown in FIG. 10, one of the portions EM42 in the fourth portion EM4 can be arranged in the same layer as the second portion EM2 and the second sub-portion EM12, and as shown in FIG. 7, the other portion EM41 in the fourth portion EM4 can be arranged in the same layer as the first sub-portion EM11. The third portion EM3 described above can be used to electrically connect the fourth portion EM4 and the second portion EM2.

[0119] When the first semiconductor layer SC1 is arranged, as shown in FIG. 6, the pixel driving circuit 21 comprises a connection node N4 which is electrically connected with the bias adjustment transistor T8, the first light emitting control transistor T1 and the driving transistor T3; specifically, the connection node N4 is electrically connected with the channel T80 of the bias adjustment transistor T8, the channel T10 of the first light emitting control transistor T1 and the channel T30 of the driving transistor T3.

[0120] As shown in FIG. 6, the channel T80 of the bias adjustment transistor T8 and the channel T10 of the first light emitting control transistor T1 are respectively located on the two sides of the connection node N4. Among them, the channel T80 of the bias adjustment transistor T8 and the channel T10 of the first light emitting control transistor T1 are respectively located on the two sides of the connection node N4, which can be understood as that the channel T80 of the bias adjustment transistor T8 and the channel T10 of the first light emitting control transistor T1 are located on the two sides of the first reference line passing through the connection node N4, and the first reference line passes through the connection node N4 and extends in the first direction h21. Optionally, as shown in FIG. 6, the first semiconductor layer SC1 comprises a first sub-semiconductor portion X1 extending in the second direction h22, and the first sub-semiconductor portion X1 comprises the channel T80 of the bias adjustment transistor T8, the channel T10 of the first light emitting control transistor T1 and the connection node N4. The first connecting component 30 comprises a first line segment 301 extending in the first direction h21 and a second line segment 302 extending in the second direction h22, the first line segment 301 is electrically connected with the connection node N4 and the second line segment 302, and the second line segment 302 is electrically connected with the first line segment 301 and the channel T30 of the driving transistor T3.

[0121] Alternatively, as shown in FIG. 15, which is a top view of a first semiconductor layer according to another embodiment of the present application, the channel T80 of the bias adjustment transistor T8 and the channel T10 of the first light emitting control transistor T1 are located on the same side of the connection node N4. It should be understood that the channel T80 of the bias adjustment transistor T8 and the channel T10 of the first light emitting control transistor T1 are located on the same side of the first reference line, which extends along the first direction h21 and passes through the connection node N4.

[0122] As shown in FIG. 15, the channel T80 of the bias adjustment transistor T8 is electrically connected to the connection node N4 through the first connection component 30, and the connection node N4 is electrically connected to the channel T30 of the driving transistor T3.

[0123] Optionally, as shown in FIG. 15, the first semiconductor layer SC1 includes a second sub-semiconductor part X2, a third sub-semiconductor part X3 and a fourth sub-semiconductor part X4. The second sub-semiconductor part X2 includes the channel T80 of the bias adjustment transistor T8; the third sub-semiconductor part X3 includes the channel T10 of the first light emitting control transistor T1; and the fourth sub-semiconductor part X4 includes the first connection component 30.

[0124] For example, as shown in FIG. 15, the second sub-semiconductor part X2 and the third sub-semiconductor part X3 are parallel to each other, and both intersect and connect with the first connection component 30. In FIG. 15, it is shown that both extend along the second direction h22.

[0125] Optionally, as shown in FIG. 15, part of the first connection component 30 extends along the third direction h23, which intersects with the first direction h21 and the second direction h22.

[0126] For example, as shown in FIG. 6 and FIG. 15, the channel T70 of the second reset transistor T7 and the channel T80 of the bias adjustment transistor T8 can be arranged along the first direction h21 according to the embodiments of the present application, and the channel T60 of the second light emitting control transistor T6 and the channel T10 of the first light emitting control transistor T1 can be arranged along the first direction h21.

[0127] Optionally, as shown in FIG. 6 and FIG. 15, along the first direction h21, the channel T60 of the second light emitting control transistor T6 and the channel T10 of the first light emitting control transistor T1 are respectively located on the two sides of the channel T30 of the driving transistor T3. Along the second direction h22, the channel T20 of the data write transistor T2 and the channel T80 of the bias adjustment transistor T8 are located on the two sides of the channel T30 of the driving transistor T3.

[0128] As shown in FIG. 4, the first power voltage line PVDD includes a first sub power voltage line PVDD1 extending along a first direction h21.

[0129] As shown in FIG. 11, the first sub power voltage line PVDD1 includes a first sub part PVDD11 and a second sub part PVDD12 which are stacked and electrically connected to reduce the resistance of the first sub power voltage line PVDD1. As shown in FIG. 8, the first sub part PVDD11 is located in the second metal layer MC and electrically connected to the second plate C2 of the storage capacitor Cst to provide the first sub power voltage Vpvdd to the second plate C2 of the storage capacitor Cst. As shown in FIG. 11, the second sub part PVDD12 of the first sub power voltage line PVDD1 is located in the first source-drain layer M2.

[0130] As shown in FIG. 11, the second sub part PVDD12 and the first sub part PVDD11 at least partially overlap in a direction h1 perpendicular to the plane of the substrate 1.

[0131] As shown in FIG. 11, the first source-drain layer M2 further includes a first connecting part L1 electrically connecting the second sub part PVDD12 and the first sub part PVDD11.

[0132] As shown in FIG. 11, the first connecting part L1 extends from the second sub part PVDD12 along a second direction h22 away from the second sub part PVDD12. The orthographic projection of the first connecting part L1 on the plane of the substrate 1 is located between two adjacent pixel circuits 21.

[0133] As shown in FIG. 4, the first power voltage line PVDD further includes a second sub power voltage line PVDD2 extending along the second direction h22, and the second sub power voltage line PVDD2 is electrically connected to the first sub power voltage line PVDD1. The arrangement of the second sub power voltage line PVDD2 and the first sub power voltage line PVDD1 can form the first power voltage line PVDD into a grid structure, which can reduce the voltage drop of the first power voltage signal Vpvdd during transmission and improve the display uniformity of the sub-pixels at different positions.

[0134] As shown in FIG. 12, the second sub power voltage line PVDD2 is located in the second source-drain layer M3.

[0135] As shown in FIG. 4, the first scan control signal line SP* overlaps with the channel T80 of the bias adjustment transistor T8 in the direction h1 perpendicular to the plane where the substrate 1 is located. The portion of the first scan control signal line SP* overlapping with the channel T80 of the bias adjustment transistor T8 is multiplexed as the gate G8 of the bias adjustment transistor T8. FIG. 4 and FIG. 7 take the first scan control signal line SP* being located in the first metal layer M1 as an example.

[0136] For example, as shown in FIG. 4, the first scan control signal line SP* at least partially overlaps with the bias adjustment signal line DVH in the direction h1 perpendicular to the plane where the substrate 1 is located, so as to reduce the area of the pixel driving circuit 21 and improve the resolution of the display panel 100.

[0137] FIG. 4 and FIG. 7 take the first scan control signal line SP* being located in the first metal layer M1, and FIG. 4 and FIG. 10 take the bias adjustment signal line DVH including a second sub-bias adjustment signal line DVH2 extending in the first direction h21, the second sub-bias adjustment signal line DVH2 being located in the third metal layer MG, and the first scan control signal line SP* at least partially overlaps with the second sub-bias adjustment signal line DVH2 in the direction h1 perpendicular to the plane where the substrate 1 is located as an example.

[0138] For example, as shown in FIG. 16, FIG. 16 is a simplified schematic diagram of another display panel provided by an embodiment of the present application,

[0139] The display area AA includes a first display area AA1 and a second display area AA2, and the first display area AA1 is located at least one side of the second display area AA2 in the first direction h21. As shown in FIG. 16, the display area AA includes two first display areas AA1, and the two first display areas AA1 are located at two sides of the second display area AA2 in the first direction h21, in other words, the first display area AA1 is closer to the edge E of the display panel 100 than the second display area AA2.

[0140] In the embodiment of the present application, the data line DATA includes a first data line DATA1 located in the first display area AA1 and a second data line DATA2 located in the second display area AA2.

[0141] As shown in FIG. 16, the display panel 100 further includes a non-display area NA at least partially surrounding the display area AA; the non-display area NA includes a fan-out area FA located at one side of the display area AA in the second direction h22, and the fan-out area FA includes a plurality of fan-out wires 6, and the data line DATA is connected with the fan-out wire 6.

[0142] As shown in FIG. 16, the display area AA further includes the connection line 5. Exemplarily, the fanout wire 6 includes a first fanout wire 61 and a second fanout wire 62, the first data line DATA1 is connected with the first fanout wire 61 through the connection line 5; the second data line DATA2 can be directly electrically connected with the second fanout wire 62. The first fanout wire 61 and the second fanout wire 62 are electrically connected with the pin 63.

[0143] As shown in FIG. 16, the connection line 5 includes a first connection line 51 and a second connection line 52 which are electrically connected, the first connection line 51 is electrically connected with the first data line DATA1, the first connection line 51 extends along a first direction h21, and the second connection line 52 extends along a second direction h22.

[0144] In the embodiment of the present application, the first data line DATA1 in the first display area AA1 can be electrically connected with the first fanout wire 61 through the connection line 5, and the second data line DATA2 in the second display area AA2 can be directly electrically connected with the second fanout wire 62. With this arrangement, part of the fanout wire is arranged in the display area (Fanout in AA, referred to as FIAA), which can reduce the occupied space of the fanout wire 6, and further reduce the area of the fanout area FA, so as to reduce the area ratio of the non-display area NA in the display panel, and increase the area ratio of the display area AA in the display panel, that is, to improve the screen-to-body ratio of the display panel, and improve the user experience.

[0145] Moreover, as shown in FIG. 16, the second connection line 52 is located on the side of the first data line DATA1 connected therewith close to the second display area AA2. Based on this arrangement, the first fanout wire 61 which needs to be connected with the first data line DATA1 can be led out from the position close to the middle area of the display area AA, avoiding the first fanout wire 61 connected with the first data line DATA1 in the first display area AA1 being led out from the area close to the corner of the frame of the display panel 100, which is conducive to reducing the frame width at the corner of the display panel 100, and optimizing the visual effect of the display panel.

[0146] The embodiment of the present application can adjust the film layer positions of the first connection line 51 and the second connection line 52 according to the arrangement of different film layers in the display panel 100. For example, the first connection line 51 and the second connection line 52 can be arranged in different layers, and electrically connected through a via. Alternatively, the first connection line 51 and the second connection line 52 can be arranged in the same layer.

[0147] In the case that the first connection line 51 and the second connection line 52 are arranged in different layers, the embodiment of the present application can arrange the second connection line 52 and the first connection line 51 in two adjacent conductive layers, so as to reduce the difficulty of arranging the via hole for electrically connecting the first connection line 51 and the second connection line 52. The two adjacent conductive layers refer to the two closest conductive layers in the display panel 100. For example, the first source-drain layer M2 and the second source-drain layer M3 in FIG. 5 are the two adjacent conductive layers.

[0148] In the case that the first connection line 51 and the second connection line 52 are arranged in different layers, the embodiment of the present application can arrange the second connection line 52 on the side of the first connection line 51 away from the substrate.

[0149] For example, referring to FIG. 17 and FIG. 18, FIG. 17 is a wiring diagram of another display panel provided by the embodiment of the present application, and FIG. 18 is a top view of another first source-drain layer provided by the embodiment of the present application. The embodiment of the present application can arrange the first connection line 51 on the first source-drain layer M2.

[0150] For example, referring to FIG. 17 and FIG. 19, FIG. 19 is a top view of another second source-drain layer provided by the embodiment of the present application. The second connection line 52 can be arranged on the second source-drain layer M3.

[0151] In the embodiment of the present application, the second connection line 52 is arranged on the side of the first connection component 30 away from the substrate 1.

[0152] For example, the embodiment of the present application can arrange the second connection line 52 on the side of the second metal layer MC away from the substrate 1. For example, as shown in FIG. 19, arranging the second connection line 52 on the second source-drain layer M3 which is far away from the first connection component 30 can increase the distance between the first connection component 30 and the second connection line 52 in the direction h1 perpendicular to the plane of the substrate 1, so as to reduce the coupling capacitance between the first connection component 30 and the second connection line 52. When the data voltage transmitted by the second connection line 52 changes, the signal change of the second node N2 can be weakened, so as to avoid the influence of the potential change of the second node N2 on the potential change of the first node N1 through the driving transistor T3 and the threshold compensation transistor T4, and further avoid the influence on the luminous brightness of the light emitting element 22, and improve the brightness uniformity of the display panel.

[0153] Exemplarily, in the embodiment of the present application, one of the data line DATA and the second connection line 52 and the first connection component 30 at least partially overlap in the direction h1 perpendicular to the plane where the substrate 1 is located. Based on this arrangement, the area of the pixel driving circuit 21 can be compressed, which is beneficial to improve the resolution of the display panel 100. FIG. 17 schematically shows that the data line DATA and the first connection component 30 overlap in the direction h1 perpendicular to the plane where the substrate 1 is located. In other arrangements, the relative positions of the data line DATA and the second connection line 52 can be adjusted, and the second connection line 52 is arranged to at least partially overlap with the first connection component 30, which is not schematically shown herein.

[0154] Exemplarily, in the embodiment of the present application, the fixed signal line and the second connection line 52 are located between two adjacent data lines DATA in the first direction h21; wherein the fixed signal line is used to transmit one of the first reset voltage Vref1, the second reset voltage Vref2 and the bias adjustment voltage Vdvh. For example, as shown in FIG. 19, two fixed signal lines 8 are shown, one of which transmits the second reset voltage Vref2, and the other transmits the bias adjustment voltage Vdvh, i.e., one of the fixed signal lines 8 is the second reset signal line REF2, and the other fixed signal line 8 is the bias adjustment signal line DVH as an example.

[0155] Exemplarily, as shown in FIG. 20, which is a simplified schematic diagram of another display panel provided by the embodiment of the present application, the first reset signal line REF1 includes a first sub-reset signal line REF11 extending in the second direction h22; the second reset signal line REF2 includes a second sub-reset signal line REF21 extending in the second direction h22; the bias adjustment signal line DVH includes a first sub-bias adjustment signal line DVH1 extending in the second direction h22; and the above-mentioned fixed signal line includes any one or more of the first sub-reset signal line REF11, the second sub-reset signal line REF21 and the first sub-bias adjustment signal line DVH1.

[0156] In the embodiment of the present application, any two or three of the first sub-reset signal line REF11, the second sub-reset signal line REF21 and the first sub-bias adjustment signal line DVH1 are arranged alternately in the first direction h21.

[0157] As shown in FIG. 20, where the three are arranged in turn in the order of the second sub-reset signal line REF21, the first sub-reset signal line REF11 and the first sub-bias adjustment signal line DVH1 as an example. Of course, other arrangement orders such as the first sub-reset signal line REF11, the first sub-bias adjustment signal line DVH and the second sub-reset signal line REF21 can also be alternately arranged, which will not be illustrated one by one here. Based on this arrangement mode, the fixed signal lines transmitting different signals can be dispersed as evenly as possible in the display panel, and in the limited space, the voltage drop of multiple fixed signals can be reduced.

[0158] As shown in FIG. 21, FIG. 21 is a simplified schematic diagram of another display panel provided by an embodiment of the present application, where the first sub-reset signal line REF11 and the second sub-reset signal line REF21 are arranged in turn along the first direction h21 as an example.

[0159] As shown in FIG. 22, FIG. 22 is a simplified schematic diagram of another display panel provided by an embodiment of the present application, where the first sub-reset signal line REF11 and the first sub-bias adjustment signal line DVH1 are arranged in turn along the first direction h21 as an example.

[0160] As shown in FIG. 23, FIG. 23 is a simplified schematic diagram of another display panel provided by an embodiment of the present application, where the second sub-reset signal line REF21 and the first sub-bias adjustment signal line DVH1 are arranged in turn along the first direction h21 as an example.

[0161] As shown in FIG. 4 and FIG. 17, the first reset signal line REF1 further includes a third sub-reset signal line REF12 electrically connected with the first sub-reset signal line REF11, and the third sub-reset signal line REF12 extends along the first direction h21 as an example. Based on this arrangement mode, the first reset signal line REF1 can be formed into a grid structure, the transmission path of the first reset voltage Vref1 can be increased, the voltage drop of the first reset voltage Vref1 in the transmission process can be reduced, the consistency of the potential of the first reset voltage Vref1 received by the pixel driving circuit 21 at different positions can be improved, and then the display effect of the light emitting element 22 at different positions tends to be consistent.

[0162] As shown in FIG. 4 and FIG. 17, the second reset signal line REF2 further comprises a fourth sub-reset signal line REF22 electrically connected with the second sub-reset signal line REF21, and the fourth sub-reset signal line REF22 extends along the first direction h21. Based on this arrangement, the second reset signal line REF2 can be formed as a grid structure, the transmission path of the second reset voltage Vref2 is increased, the voltage drop of the second reset voltage Vref2 during transmission can be reduced, the consistency of the second reset voltage Vref2 received by the pixel driving circuit at different positions is improved, and thus the display effect of the light emitting element 22 at different positions tends to be consistent.

[0163] As shown in FIG. 4 and FIG. 17, the bias adjustment signal line DVH comprises a second sub-bias adjustment signal line DVH2 electrically connected with the first sub-bias adjustment signal line DVH1, and the second sub-bias adjustment signal line DVH2 extends along the first direction h21. Based on this arrangement, the bias adjustment signal line DVH can be formed as a grid structure, the transmission path of the bias adjustment voltage Vdvh is increased, the voltage drop of the bias adjustment voltage Vdvh during transmission can be reduced, the consistency of the corresponding fixed signals received by the pixel driving circuit 21 at different positions, such as the first reset voltage Vref1, the second reset voltage Vref2 and the bias adjustment voltage Vdvh, is improved, and thus the display effect of the light emitting element 22 at different positions tends to be consistent.

[0164] For example, in the embodiment of the present application, the third sub-reset signal line REF12 and the first sub-reset signal line REF11 are arranged in different layers. The fourth sub-reset signal line REF22 and the second sub-reset signal line REF21 are arranged in different layers. The second sub-bias adjustment signal line DVH2 and the first sub-bias adjustment signal line DVH1 are arranged in different layers.

[0165] Optionally, at least two of the first sub-reset signal line REF11, the second sub-reset signal line REF21 and the first sub-bias adjustment signal line DVH1 can be arranged in the same layer in the embodiment of the present application.

[0166] Optionally, as shown in FIG. 7, the third sub-reset signal line REF12 can be located in the first metal layer M1, and the first sub-reset signal line REF11 can be located in the second source-drain layer M3, and the two are electrically connected through a via hole.

[0167] For example, as shown in FIG. 8, the fourth sub-reset signal line REF22 can be located in the second metal layer MC, and as shown in FIG. 12 and FIG. 19, the second sub-reset signal line REF21 can be located in the second source-drain layer M3, and the fourth sub-reset signal line REF22 and the second sub-reset signal line REF21 are electrically connected through a via hole.

[0168] Optionally, as shown in FIG. 10, the second sub bias adjustment signal line DVH2 can be located on the third metal layer MG, and as shown in FIG. 12 and FIG. 19, the first sub bias adjustment signal line DVH1 can be located on the second source-drain layer M3, and the second sub bias adjustment signal line DVH2 and the first sub bias adjustment signal line DVH1 are electrically connected through a via.

[0169] In the embodiment of the present application, at least two of the data line DATA, the second connection line 52, the first sub reset signal line REF11, the second sub reset signal line REF21 and the first sub bias adjustment signal line DVH1 are arranged on the same layer. Based on this arrangement, the number of films in the display panel can be reduced, the manufacturing process of the display panel can be simplified, and the thickness of the display panel can be thinned. As an example, as shown in FIG. 19, the second sub power voltage line PVDD2, the data line DATA, the second connection line 52, the second sub reset signal line REF21 and the first sub bias adjustment signal line DVH1 are all arranged on the second source-drain layer M3.

[0170] As an example, as shown in FIG. 19, along the first direction h21, the second connection line 52 is located between two adjacent data lines DATA.

[0171] Alternatively, as shown in FIG. 24, which is a simplified schematic diagram of another display panel provided by the embodiment of the present application, the relative position relationship between the data line DATA and the second connection line 52 can be adjusted, so that along the first direction h21, the data line DATA is located between two adjacent second connection lines 52. The second sub power voltage line PVDD2 is located on the side of the second connection line 52 away from the data line DATA. As an example, as shown in FIG. 24, along the direction perpendicular to the plane on which the substrate lies, the second connection line 52 at least partially overlaps the pixel driving circuit 21.

[0172] As an example, as shown in FIG. 25 and FIG. 26, which are a wiring schematic diagram of another pixel driving circuit provided by the embodiment of the present application and a schematic diagram of the second plate and the shielding component, the display panel further comprises a shielding component 7, which receives a constant signal.

[0173] In the embodiment of the present application, as shown in FIG. 25, along the direction perpendicular to the plane on which the substrate 1 lies, the shielding component 7 is located between the data line DATA and the first connection component 30, and the shielding component 7 at least partially overlaps the data line DATA and the first connection component 30. In the embodiment of the present application, the arrangement of the shielding component 7 can further weaken the coupling capacitance between the data line DATA and the first connection component 30, thereby reducing the interference of the signal change on the data line DATA on the signal on the first connection component 30, which is conducive to improving the potential stability of the second node N2, and further improving the potential stability of the first node N1, and improving the display uniformity of the display panel.

[0174] Alternatively, when adjusting the relative positional relationship between the data line DATA and the second connection line 52, the embodiment of the present application can also make the shielding component be located between the second connection line and the first connection component, and make the shielding component at least partially overlap with the second connection line and the first connection component in the direction perpendicular to the plane where the substrate is located. Based on this arrangement, the shielding component can weaken the coupling capacitance between the second connection line and the first connection component, thereby reducing the interference of the signal change on the second connection line on the signal on the first connection component, and being beneficial to improving the potential stability of the second node N2, and further improving the potential stability of the first node N1, and improving the display uniformity of the display panel.

[0175] Optionally, the constant signal transmitted by the shielding component 7 includes any one of the first power supply voltage Vpvdd, the first reset voltage Vref1, the second reset voltage Vref2, and the bias adjustment voltage Vdvh.

[0176] For example, as shown in FIGS. 25 and 26, the shielding component 7 is electrically connected with the second plate C2, so that the shielding component 7 receives the first power supply voltage Vpvdd through the second plate C2.

[0177] For example, as shown in FIGS. 25 and 26, the shielding component 7 is arranged in the same layer as the second plate C2 in the second metal layer MC. The shielding component 7 protrudes from the second plate C2 to the side away from the second plate C2 along the second direction h22.

[0178] Alternatively, as shown in FIGS. 27 and 28, FIG. 27 is a wiring schematic diagram of another pixel driving circuit provided by the embodiment of the present application, and FIG. 28 is a schematic diagram of the shielding component and the second sub-bias adjustment signal line in FIG. 27. The shielding component 7 is electrically connected with the bias adjustment signal line DVH, so that the shielding component 7 receives the bias adjustment voltage Vdvh. In FIG. 27, the shielding component 7 is arranged in the same layer as the second sub-bias adjustment signal line in the third metal layer MG, and the second sub-part and the second part of the light-emitting control signal line EM are located in the second metal layer MC as an example.

[0179] Alternatively, the embodiment of the present application can also make the shielding component 7 be electrically connected with the first reset signal line REF1 or the second reset signal line REF2. As shown in FIGS. 29 and 30, FIG. 29 is a wiring schematic diagram of another pixel driving circuit provided by the embodiment of the present application, and FIG. 30 is a schematic diagram of the shielding component and the fourth sub-reset signal line in FIG. 29. The shielding component 7 is electrically connected with the fourth sub-reset signal line REF22 in the second reset signal line REF2, so that the shielding component 7 receives the second reset voltage Vref2.

[0180] For example, as shown in FIG. 4, FIG. 17, FIG. 25 and FIG. 27, the two pixel drive circuits 21 adjacent in the first direction h21 can be symmetrically arranged, and the symmetry line extends along the second direction h22. Specifically, each transistor in the two pixel drive circuits 21 adjacent in the first direction h21 is symmetrically arranged about the symmetry line, for example, the first light emitting control transistor T1 in the two pixel drive circuits 21 adjacent in the first direction h21 is symmetric about the symmetry line. Based on the arrangement, some transistors in the two pixel drive circuits 21 adjacent can share a via to electrically connect with a corresponding signal line, which can simplify the structure of the pixel drive circuit and facilitate reducing the area of the pixel drive circuit. For example, as shown in FIG. 4, the bias adjustment transistor T8 in the two pixel drive circuits 21 adjacent in the first direction h21 can be electrically connected with the bias adjustment signal line DVH through the same via.

[0181] For example, as shown in FIG. 4, FIG. 17, FIG. 25 and FIG. 27, the fourth sub-reset signal line REF22, the first scan control signal line SP*, the light emitting control signal line EM, the first sub-power voltage line PVDD1, the fourth scan control signal line SP, the third scan control signal line S2N, the second scan control signal line S1N and the third sub-reset signal line REF12 in the substrate 1 are arranged along the second direction h22 in sequence.

[0182] Based on the same inventive concept, the embodiment of the present application further provides a display device. As shown in FIG. 31, FIG. 31 is a schematic diagram of a display device provided by an embodiment of the present application, and the display device comprises the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiments, and will not be repeated here. Of course, the display device shown in FIG. 31 is only for illustrative purposes, and the display device can be any electronic device with display function, such as a mobile phone, a vehicle display screen, a tablet computer, a notebook computer, an electronic paper or a television.

[0183] The above only describes preferred embodiments of the present application and should not be used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0184] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a data line and a pixel driving circuit located on one side of the substrate; the pixel driving circuit comprises a driving transistor, a bias adjusting transistor and a first connecting component, a gate of the driving transistor is electrically connected with a first node, a first pole of the driving transistor is electrically connected with a second node, and a second pole of the driving transistor is electrically connected with a third node; the first connecting component electrically connects the bias adjusting transistor and the second node; the display panel further comprises a first semiconductor layer and a first metal layer, which are sequentially stacked in a direction away from the substrate; the first semiconductor layer comprises a channel of the driving transistor and a channel of the bias adjusting transistor, and the first metal layer comprises a gate of the driving transistor and a gate of the bias adjusting transistor; the first connecting component is located in the first semiconductor layer.

2. The display panel of claim 1, wherein, The pixel driving circuit further comprises a first light-emitting control transistor, and the first semiconductor layer further comprises a channel of the first light-emitting control transistor; the display panel further comprises a light-emitting control signal line, which extends in a first direction; the light-emitting control signal line comprises a first part and a second part which are electrically connected; in a direction perpendicular to a plane where the substrate is located, the first part overlaps with the channel of the first light-emitting control transistor, and the second part overlaps with the first connecting component; the first part comprises a first subpart and a second subpart which are stacked; the first subpart and the second subpart are electrically connected; the first subpart is located in the first metal layer, and the second subpart and the second part are located on a side of the first metal layer away from the substrate.

3. The display panel of claim 2, wherein: the pixel driving circuit comprises a connecting node which electrically connects the bias adjusting transistor, the first light-emitting control transistor and the driving transistor; the channel of the bias adjusting transistor and the channel of the first light-emitting control transistor are respectively located on two sides of the connecting node; or the channel of the bias adjusting transistor and the channel of the first light-emitting control transistor are located on the same side of the connecting node.

4. The display panel of claim 2, wherein: the light-emitting control signal line further comprises a third part which does not overlap with the channel of the first light-emitting control transistor and the first connecting component in a direction perpendicular to a plane where the substrate is located; and the third part is arranged in the same layer or different layers with the second part; a second metal layer is further included, and the second metal layer is located on a side of the first metal layer away from the substrate; 5. The display panel of claim 2, wherein, the second part is located in the second metal layer. a first scanning control signal line and a bias adjusting signal line are further included; 6. The display panel of claim 1, wherein, the bias adjusting transistor is electrically connected with the bias adjusting signal line and the second node; in a direction perpendicular to a plane where the substrate is located, the first scanning control signal line overlaps with the channel of the bias adjusting transistor.

7. The display panel of claim 6, wherein: ​ The first scan control signal line and the bias adjustment signal line at least partially overlap in a direction perpendicular to a plane in which the substrate is located.

8. The display panel of claim 2, wherein, The pixel driving circuit further comprises a first reset transistor; the first reset transistor is electrically connected with a first reset signal line and the first node; and the first reset transistor comprises an oxide transistor. The display panel further comprises a second semiconductor layer, a second metal layer and a third metal layer; the second metal layer is located on a side of the first metal layer away from the substrate; and The second semiconductor layer is located between the second metal layer and the third metal layer; and the second semiconductor layer comprises a channel of the first reset transistor. The second part is located on the third metal layer.

9. The display panel of claim 8, wherein, The display panel further comprises a second scan control signal line, 10. The display panel of claim 8, wherein, The second scan control signal line comprises a fourth part and a fifth part; the fourth part overlaps with the channel of the first reset transistor in a direction perpendicular to a plane in which the substrate is located; and the fifth part does not overlap with the channel of the first reset transistor. The fourth part comprises a third sub-part and a fourth sub-part which are arranged in a stack; the third sub-part is located on the second metal layer; and the fourth sub-part and the fifth part are located on the third metal layer.

11. The display panel of claim 8, wherein, The pixel driving circuit further comprises a threshold compensation transistor; the threshold compensation transistor is electrically connected with the third node and the first node; and the threshold compensation transistor comprises an oxide transistor. The second semiconductor layer comprises a channel of the threshold compensation transistor. The display panel further comprises a third scan control signal line; the third scan control signal line comprises a sixth part and a seventh part; the sixth part overlaps with the channel of the threshold compensation transistor in a direction perpendicular to a plane in which the substrate is located; and the seventh part does not overlap with the channel of the threshold compensation transistor.

12. The display panel of claim 11, wherein, The sixth part comprises a fifth sub-part and a sixth sub-part which are arranged in a stack; the fifth sub-part is located on the second metal layer; and the sixth sub-part and the seventh part are located on the third metal layer. The display panel further comprises a first power voltage line; the first power voltage line is electrically connected with the first light-emitting control transistor.

13. The display panel of claim 2, wherein, The display panel further comprises a second metal layer and a first source-drain layer; the second metal layer is located on a side of the first metal layer away from the substrate; and the first source-drain layer is located on a side of the second metal layer away from the substrate. The first power voltage line comprises a first sub-power voltage line extending in the first direction; the first sub-power voltage line comprises a first sub-part and a second sub-part which are arranged in a stack; the first sub-part is located on the second metal layer; the second sub-part is located on the first source-drain layer; and the first sub-part and the second sub-part are electrically connected.

14. The display panel of claim 1, wherein, The data line comprises a first data line; and ​ The display panel further comprises a connection line, the connection line comprises a first connection line and a second connection line electrically connected, the first connection line is electrically connected with the first data line, the first connection line extends along a first direction, the second connection line extends along a second direction, the first direction intersects with the second direction; The second connection line is located on the side of the first connection component away from the substrate.

15. The display panel of claim 14, wherein, The display panel comprises a first source-drain layer and a second source-drain layer, the first source-drain layer is located on the side of the first metal layer away from the substrate, the second source-drain layer is located on the side of the first source-drain layer away from the first metal layer, the first connection line is located on the first source-drain layer, and the second connection line is located on the second source-drain layer.

16. The display panel of claim 14, wherein, In a direction perpendicular to the plane on which the substrate is located, one of the second connection line and the data line at least partially overlaps with the first connection component.

17. The display panel of claim 14, wherein, Further comprising a light emitting element electrically connected with the pixel driving circuit; the pixel driving circuit further comprises a first reset transistor and a second reset transistor; The first reset transistor is electrically connected with a first reset signal line and the first node, and the first reset signal line transmits a first reset voltage; The second reset transistor is electrically connected with a second reset signal line and the light emitting element, and the second reset signal line transmits a second reset voltage; The bias adjustment transistor is electrically connected with a bias adjustment signal line and the second node, and the bias adjustment signal line transmits a bias adjustment voltage; In the first direction, a fixed signal line and the second connection line are located between two adjacent data lines; wherein the fixed signal line is used to transmit one of the first reset voltage, the second reset voltage and the bias adjustment voltage.

18. The display panel of claim 17, wherein, The first reset signal line comprises a first sub-reset signal line extending along the second direction; The second reset signal line comprises a second sub-reset signal line extending along the second direction; The bias adjustment signal line comprises a first sub-bias adjustment signal line extending along the second direction; Any two or three of the first sub-reset signal line, the second sub-reset signal line and the first sub-bias adjustment signal line are alternately arranged in the first direction.

19. The display panel of claim 18, wherein, The first reset signal line further comprises a third sub-reset signal line electrically connected with the first sub-reset signal line, and the third sub-reset signal line extends along the first direction; The second reset signal line further comprises a fourth sub-reset signal line electrically connected with the second sub-reset signal line, and the fourth sub-reset signal line extends along the first direction; The bias adjustment signal line comprises a second sub-bias adjustment signal line electrically connected with the first sub-bias adjustment signal line, and the second sub-bias adjustment signal line extends along the first direction.

20. The display panel of claim 18, wherein, at least two of the data line, the second connection line, the first sub-reset signal line, the second sub-reset signal line, and the first sub-bias adjustment signal line are arranged in the same layer.

21. The display panel of claim 14, wherein, in the first direction, the data line is located between two adjacent second connection lines.

22. The display panel of claim 21, wherein, the display panel comprises a first source-drain layer and a second source-drain layer, the first source-drain layer is located on a side of the first metal layer away from the substrate, the second source-drain layer is located on a side of the first source-drain layer away from the first metal layer, the first connection line is located in the first source-drain layer, and the second connection line is located in the second source-drain layer.

23. The display panel of claim 14, wherein, further comprising a shielding component, the shielding component receives a constant signal; in a direction perpendicular to a plane in which the substrate is located, the shielding component is located between the second connection line and the first connection component, and the shielding component at least partially overlaps the second connection line and the first connection component; or, in a direction perpendicular to a plane in which the substrate is located, the shielding component is located between the data line and the first connection component, and the shielding component at least partially overlaps the data line and the first connection component.

24. The display panel of claim 23, wherein, the pixel driving circuit further comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate, in a direction perpendicular to a plane in which the substrate is located, the first plate overlaps a channel of the driving transistor; the first plate is located between the substrate and the second plate; the shielding component is electrically connected to the second plate.

25. The display panel of claim 23, wherein, the bias adjustment transistor is electrically connected to a bias adjustment signal line and the second node; the shielding component is electrically connected to the bias adjustment signal line.

26. The display panel of claim 23, wherein, further comprising a light emitting element electrically connected to the pixel driving circuit; the pixel driving circuit comprises a first reset transistor and a second reset transistor, the first reset transistor is electrically connected to a first reset signal line and the first node, and the second reset transistor is electrically connected to a second reset signal line and the light emitting element; the shielding component is electrically connected to the first reset signal line or the second reset signal line.

27. A display device comprising: a display panel as claimed in any one of claims 1 to 26.

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